Power control circuit and server

Abstract

The embodiment of the application provides a power supply control circuit and a server, the circuit comprises a general control circuit and at least one detection circuit, the detection circuit comprises a controller and at least two filters, the at least two filters are connected in series with the controller, and the controller is connected with the general control circuit; wherein the at least two filters are used for acquiring an initial power supply signal of a detected power supply module, and performing filtering processing on the initial power supply signal to obtain a target power supply signal; the controller is used for determining a power supply state of the detected power supply module according to the target power supply signal, and sending the power supply state to the general control circuit; and the general control circuit is used for controlling a working state of the at least one detection circuit according to the received power supply state, and the working state comprises a running state or a pause state. The reliability of the power supply control circuit for controlling multiple power supply modules is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit, and particularly relates to a power control circuit and a server. BACKGROUND

[0002] The power control circuit can control a plurality of power modules to ensure stable operation of the plurality of power modules.

[0003] In the related art, the power control circuit can determine the power state through the voltage output by each power module, and control each power module according to the power state. However, in the above process, the voltage is usually affected by other signals in the circuit and fluctuates, resulting in low accuracy of determining the power state, and further resulting in low reliability of the power control circuit in controlling the plurality of power modules. SUMMARY

[0004] Aspects of the present application provide a power control circuit and a server to improve the reliability of the power control circuit in controlling the plurality of power modules.

[0005] In a first aspect, an embodiment of the present application provides a power control circuit, comprising a master control circuit and at least one detection circuit, the detection circuit comprising a controller and at least two filters, the at least two filters being connected in series with the controller, and the controller being connected with the master control circuit; wherein,

[0006] The at least two filters are configured to obtain an initial power signal of a detected power module, and perform filtering processing on the initial power signal to obtain a target power signal.

[0007] The controller is configured to determine a power state of the detected power module according to the target power signal, and send the power state to the master control circuit.

[0008] The master control circuit is configured to control a working state of the at least one detection circuit according to the received power state, the working state comprising a running state or a pause state.

[0009] In a possible implementation, the at least two filters comprise a first filter and a second filter, wherein,

[0010] The input end of the first filter is configured to be connected with the detected power module, and the output end of the first filter is connected with the input end of the second filter.

[0011] The output end of the second filter is connected with the controller.

[0012] In a possible implementation,

[0013] The first filter is configured to filter the initial power supply signal based on a system clock frequency to obtain a first power supply signal.

[0014] The second filter is configured to filter the first power supply signal based on a preset clock frequency to obtain the target power supply signal.

[0015] In a possible implementation, the first filter is specifically configured to:

[0016] sample the initial power supply signal based on the system clock frequency to obtain a first sample signal;

[0017] if there is a first abrupt signal in the first sample signal, filter the first abrupt signal in the first sample signal to obtain the first power supply signal, a duration of the first abrupt signal being less than or equal to a duration of M system clocks, and the M being an integer greater than or equal to 1.

[0018] In a possible implementation, the second filter is specifically configured to:

[0019] sample the first power supply signal based on the preset clock frequency to obtain a second sample signal;

[0020] if there is a second abrupt signal in the second sample signal, filter the second abrupt signal in the second sample signal to obtain the target power supply signal, a duration of the second abrupt signal being less than or equal to a duration of N preset clocks, and the N being an integer greater than or equal to 1.

[0021] In a possible implementation, the controller is specifically configured to:

[0022] determine that the power supply state is an abnormal state when it is determined that the target power supply signal includes K preset signals, and the K being an integer greater than or equal to 1.

[0023] In a possible implementation, the total control circuit is specifically configured to:

[0024] if the received power supply state is the abnormal state, send a lock signal to the at least one detection circuit, the lock signal being configured to instruct the at least one detection circuit to switch a working state to the pause state.

[0025] In a possible implementation, the power supply control circuit is located in a sub-card circuit, and the total control circuit is further configured to:

[0026] receive a first electrical control signal sent by a power supply control circuit in a mainboard circuit through an up-down point interface and a second electrical control signal sent by the power supply control circuit through a bus interface.

[0027] According to the first electric control signal and the second electric control signal, power modules in the sub-card circuit are controlled to be powered on or powered off.

[0028] In a possible implementation, the master control circuit is specifically configured to:

[0029] When the first electric control signal and / or the second electric control signal indicates powering on, the power modules in the sub-card circuit are controlled to be powered on.

[0030] When the first electric control signal and the second electric control signal respectively indicate powering off, the power modules in the sub-card circuit are controlled to be powered off.

[0031] In a second aspect, an embodiment of the present application provides a mainboard circuit, including the power control circuit in any one of the first aspect, and at least one power module, wherein the at least one detection circuit in the power control circuit is connected with the corresponding power module respectively.

[0032] In a third aspect, an embodiment of the present application provides a sub-card circuit, including the power control circuit in any one of the first aspect, and at least one power module, wherein the at least one detection circuit in the power control circuit is connected with the corresponding power module respectively.

[0033] In a fourth aspect, an embodiment of the present application provides a server, including the mainboard circuit in the second aspect, and at least one sub-card circuit in the third aspect, wherein the power control circuit in the mainboard circuit and the power control circuit in the sub-card circuit are connected.

[0034] The embodiments of the present application provide a power control circuit and a server. The power control circuit can include a master control circuit and at least one detection circuit. The detection circuit can include a controller and at least two filters. The at least two filters can obtain an initial power signal of a detected power module, and perform filtering processing on the initial power signal to obtain a target power signal. The controller can determine a power state of the detected power module according to the target power signal, and send the power state to the master control circuit. The master control circuit can control a working state of the at least one detection circuit according to the received power state. Since the initial power signal of the power module can be filtered by the at least two filters, and then the power state is determined by the controller, compared with determining the power state by the voltage output by each power module, the accuracy of determining the power state is improved, and then the reliability of the power control circuit in controlling the plurality of power modules is improved. BRIEF DESCRIPTION OF DRAWINGS

[0035] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

[0036] Figure 1 A schematic diagram of an application scenario provided for an exemplary embodiment of the present application;

[0037] Figure 2 A structural schematic diagram of a power supply control circuit provided for an exemplary embodiment of the present application;

[0038] Figure 3 A structural schematic diagram of another power supply control circuit provided for an exemplary embodiment of the present application;

[0039] Figure 4 A structural schematic diagram of a mainboard circuit provided for an exemplary embodiment of the present application;

[0040] Figure 5 A structural schematic diagram of a daughter card circuit provided for an exemplary embodiment of the present application;

[0041] Figure 6 A structural schematic diagram of a server provided for an exemplary embodiment of the present application;

[0042] Figure 7 A flowchart of a power-on method provided for an exemplary embodiment of the present application;

[0043] Figure 8 A flowchart of a power-off method provided for an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0044] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be described below in conjunction with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0045] Figure 1 A schematic diagram of an application scenario provided for an exemplary embodiment of the present application. Please refer to Figure 1 , the server can include a plurality of power supply modules and a plurality of components. For example, the plurality of power supply modules can be power supply module 1, power supply module 2, power supply module 3, …, and power supply module i; the plurality of components can be component 1, component 2, component 3, …, and component j.

[0046] For any one component, the component can be powered by the corresponding power module. For example, the power module 1 can power the component 1, the power module 2 can power the component 2, …, and the power module i can power the component j.

[0047] In the related art, the power control circuit can determine the power state according to the voltage output by each power module, and control each power module according to the power state. However, in the above process, the voltage is usually affected by other signals in the circuit and fluctuates, resulting in low accuracy of determining the power state, and thus low reliability of the power control circuit in controlling multiple power modules.

[0048] In the embodiments of the present application, the power control circuit can include a master control circuit and at least one detection circuit, and the detection circuit can include a controller and at least two filters. Since the initial power signal of the power module can be filtered by at least two filters, and the power state is determined by the controller, compared with determining the power state by the voltage output by each power module, the accuracy of determining the power state is improved, and thus the reliability of the power control circuit in controlling multiple power modules is improved.

[0049] In the following, the technical solutions shown in the present application are described in detail through specific embodiments. It should be noted that the following embodiments can exist independently, or can be combined with each other. For the same or similar content, it is not repeated in different embodiments.

[0050] Figure 2 A structure diagram of a power control circuit provided for the exemplary embodiments of the present application is shown. Please refer to Figure 2 The power control circuit can include a master control circuit and at least one detection circuit.

[0051] The power control circuit can be a complex programmable logic device (CPLD), which is a digital integrated circuit that users can construct logic functions according to their needs.

[0052] Optionally, the at least one detection circuit can be detection circuit 1, detection circuit 2, …, and detection circuit Q. Q is an integer greater than or equal to 1.

[0053] For any one detection circuit, the detection circuit can include a controller and at least two filters, the at least two filters are connected in series with the controller, and the controller is connected with the master control circuit.

[0054] As Figure 2In an example, the detection circuit 1 can include a filter 11, a filter 12 and a controller 13. The filter 11 can be connected in series with the filter 12, the filter 12 can be connected with the controller 13, and the controller 13 can be connected with the master control circuit.

[0055] In an example, at least two filters can be used to obtain an initial power signal of the power module to be detected and filter the initial power signal to obtain a target power signal.

[0056] The initial power signal can include a power good (PG) signal and / or a power fail signal. The PG signal can be used to indicate that the power supply is normal, and the power fail signal can be used to indicate that the power supply is abnormal.

[0057] Optionally, the PG signal can be represented by "1", and the power fail signal can be represented by "0".

[0058] The target power signal can be a signal obtained by filtering the initial power signal.

[0059] For example, as shown in Figure 2 In an example, if the power module to be detected is the power module 1, and the initial power signal 1 is "1110011110", the filter 11 in the detection circuit 1 can obtain the initial power signal 1, and filter the initial power signal 1 through the filter 11 and the filter 12 to obtain the target power signal 1. The target power signal 1 can be represented as "1111111111".

[0060] In an example, the controller can be configured to determine the power state of the power module to be detected according to the target power signal, and send the power state to the master control circuit.

[0061] Optionally, the power state can include a normal state or an abnormal state.

[0062] For example, if the target power signal 1 corresponding to the power module 1 is "1111111111", the controller can determine that the power state of the power module 1 is normal according to the target power signal 1, and send the power state to the master control circuit; if the target power signal 1 is "1111100000", the controller can determine that the power state of the power module 1 is abnormal according to the target power signal 1, and send the power state to the master control circuit.

[0063] In an example, the master control circuit can be configured to control the working state of at least one detection circuit according to the received power state.

[0064] Optionally, the working state can include a running state or a pause state.

[0065] For example, as shown in Figure 2 For example, as shown in

[0066] In the embodiment of the present application, the power control circuit can include a general control circuit and at least one detection circuit, and the detection circuit can include a controller and at least two filters. The at least two filters can obtain an initial power signal of the detected power module and perform filtering processing on the initial power signal to obtain a target power signal. The controller can determine the power state of the detected power module according to the target power signal and send the power state to the general control circuit. The general control circuit can control the working state of the at least one detection circuit according to the received power state. Since the initial power signal of the power module can be filtered by the at least two filters, and then the power state is determined by the controller, compared with determining the power state by the voltage output by each power module, the accuracy of determining the power state is improved, and thus the reliability of the power control circuit in controlling multiple power modules is improved.

[0067] In the following, based on the embodiment shown in Figure 2 , the power control circuit will be further described in detail. Figure 3

[0068] Figure 3 Another structure schematic diagram of a power control circuit provided by an exemplary embodiment of the present application is shown in Figure 3 , which can include at least one power module and a power control circuit.

[0069] As shown in Figure 3 , the at least one power module can be power module 1, power module 2, …, and power module Q respectively.

[0070] The power control circuit can include a general control circuit and at least one detection circuit. Any one detection circuit can include at least two filters and a controller. The at least two filters can include a first filter and a second filter, wherein the input end of the first filter is connected with the detected power module, the output end of the first filter is connected with the input end of the second filter, and the output end of the second filter is connected with the controller.

[0071] As shown in Figure 3 ​In the detection circuit 1, a first filter 11, a second filter 12 and a controller 13 can be included. An input end of the first filter 11 can be connected with the power module 1, an output end of the first filter 11 can be connected with an input end of the second filter 12, and an output end of the second filter 12 can be connected with the controller 13.

[0072] Optionally, the first filter can be configured to filter the initial power signal based on a system clock frequency to obtain a first power signal. The second filter can be configured to filter the first power signal based on a preset clock frequency to obtain a target power signal.

[0073] The system clock frequency can be a man-made preset frequency. For example, the system clock frequency can be 50MHz.

[0074] The preset clock frequency can be a man-made preset frequency. For example, the preset clock frequency can be 2KHz.

[0075] In an optional embodiment, the first power signal can be obtained by: sampling the initial power signal through the first filter based on the system clock frequency to obtain a first sampling signal; and filtering out a first mutation signal from the first sampling signal to obtain the first power signal, if the first mutation signal exists in the first sampling signal, a duration of the first mutation signal being less than or equal to a duration of M system clocks, M being an integer greater than or equal to 1.

[0076] The first sampling signal can include a plurality of initial power signals. For example, if the initial power signal can be represented by "0" and / or "1", if sampling is performed continuously for 5 times, the first sampling signal can be "11101".

[0077] For example, if the power module to be detected is the power module 1, and the system clock frequency is 50MHz, the first filter 11 can sample the initial power signal 1 every 50MHz to obtain a first sampling signal. Assuming that sampling is performed for 5 times, the first sampling signal obtained is "11101".

[0078] The first mutation signal can be a Power Fail signal, and the first mutation signal can be represented by "0".

[0079] Optionally, obtaining the first power signal can include the following three cases:

[0080] Case 1: the first sampling signal does not include the first mutation signal.

[0081] In this case, the first sampling signal is the first power signal without filtering out the first mutation signal from the first sampling signal.

[0082] For example, if the sampling is continuously performed 5 times, the first sampling signal is "11111", and there is no first mutation signal "0", the first mutation signal "0" does not need to be filtered out in the first sampling signal, and the first power supply signal is "11111".

[0083] Case 2: There is a first mutation signal in the first sampling signal, and the duration of the first mutation signal is less than or equal to the duration of M system clocks.

[0084] In this case, since the duration of the first mutation signal is less than or equal to the duration of M system clocks, the first mutation signal is likely to be caused by the high frequency influence of pulse width modulation (PWM) in the circuit, and not caused by the abnormality of the detected power module. Therefore, the first mutation signal can be filtered out in the first sampling signal to remove the influence of the high frequency pulse signal, and the first power supply signal is obtained.

[0085] For example, if M is 3, the system clock frequency can be 50MHz, and the duration of 3 system clocks can be 60ns (nanoseconds). If the sampling is continuously performed 5 times, the first sampling signal is "11001", and the duration of 2 first mutation signals "0" is 40ns. Since the duration of 2 first mutation signals "0" is 40ns, which is less than the duration of 3 system clocks 60ns, the first sampling signal can be filtered to obtain the first power supply signal "11111".

[0086] Case 3: There is a first mutation signal in the first sampling signal, and the duration of the first mutation signal is greater than the duration of M system clocks.

[0087] In this case, since the duration of the first mutation signal is greater than the duration of M system clocks, the first mutation signal is likely to be caused by the abnormality of the detected power module. Therefore, the first mutation signal can not be filtered out in the first sampling signal, and the first power supply signal is obtained.

[0088] For example, if M is 3, the system clock frequency can be 50MHz, and the duration of 3 system clocks can be 60ns. If the sampling is continuously performed 5 times, the first sampling signal is "10000", and the duration of 4 first mutation signals "0" is 80ns. Since the duration of 4 first mutation signals "0" is 80ns, which is greater than the duration of 3 system clocks 60ns, the first mutation signal can not be filtered out in the first sampling signal, and the first power supply signal is "10000".

[0089] After the first filter obtains the first power supply signal, the first filter can output the first power supply signal to the second filter, so that the second filter obtains the target power supply signal from the first power supply signal.

[0090] In an optional embodiment, the target power supply signal can be obtained by: sampling the first power supply signal based on the preset clock frequency through the second filter to obtain a second sampling signal; and filtering out a second mutation signal from the second sampling signal to obtain the target power supply signal, if the second mutation signal exists in the second sampling signal, a duration of the second mutation signal being less than or equal to a duration of N preset clocks, N being an integer greater than or equal to 1.

[0091] For example, if the detected power supply module is the power supply module 1, the preset clock frequency can be 2KHz, and if the first power supply signal 1 is "10000", the second filter 12 can sample the first power supply signal 1 every 2KHz to obtain a second sampling signal. Assuming that 4 samplings are performed, the obtained second sampling signal can be "1000".

[0092] The second mutation signal can be a Power Fail signal, and the second mutation signal can be represented by "0".

[0093] Optionally, obtaining the target power supply signal can include the following three cases:

[0094] Case 1: the second sampling signal does not contain the second mutation signal.

[0095] In this case, it is not necessary to filter out the second mutation signal from the second sampling signal, and the second sampling signal is the target power supply signal.

[0096] For example, if 4 samplings are continuously performed, the second sampling signal is "1111", and there is no second mutation signal "0", it is not necessary to filter out the second mutation signal "0" from the second sampling signal, and the target power supply signal is "1111".

[0097] Case 2: the second sampling signal contains the second mutation signal, and a duration of the second mutation signal is less than or equal to a duration of N preset clocks.

[0098] In this case, since the duration of the second mutation signal is less than or equal to the duration of N preset clocks, the second mutation signal can be caused by interference of a high driving capability signal in the circuit and / or interference of some low-speed signal interface, and the second mutation signal can be filtered out from the second sampling signal to obtain the target power supply signal.

[0099] For example, if N is 2, the preset clock frequency is 20 KHz, the duration of 2 preset clocks can be 100 us (microsecond), if 4 samplings are performed, the second sampling signal is "1101", and the duration of the second mutation signal "0" is 50 us, since the duration of the second mutation signal "0" is less than the duration of 2 preset clocks, the second sampling signal can be filtered to obtain the target power signal "1111".

[0100] Case 3: The second sampling signal contains a second mutation signal, and the duration of the second mutation signal is greater than the duration of N preset clocks.

[0101] In this case, since the duration of the second mutation signal is greater than the duration of N preset clocks, the second mutation signal is likely to be caused by the abnormality of the first power signal, and the second mutation signal can not be filtered out in the second sampling signal to obtain the target power signal.

[0102] For example, if N is 2, the preset clock frequency is 20 KHz, the duration of 2 preset clocks can be 100 us (microsecond), if 4 samplings are performed, the second sampling signal is "1000", and the duration of the second mutation signal "0" is 150 us, since the duration of the second mutation signal "0" is greater than the duration of 2 preset clocks, the second mutation signal can not be filtered out in the second sampling signal to obtain the target power signal "1000".

[0103] Optionally, the filtering processing of the first filter and the second filter can make the target power signal more accurately reflect the power state of the detected power module.

[0104] After obtaining the target power signal, the second filter can output the target power signal to the controller, so that the controller determines the power state of the detected power module according to the target power signal.

[0105] Optionally, the controller determining the power state can include the following two cases:

[0106] Case 1: The target power signal does not contain a K-bit preset signal.

[0107] Optionally, the preset signal can be represented by "0". K can be an integer greater than or equal to 1.

[0108] In this case, the controller can determine the power state of the detected power module as a normal state according to the target power signal.

[0109] For example, if K is 1, the detected power module is power module 1, and the corresponding target power signal 1 is "1111", since there is no preset signal "0" in the target power signal 1, the controller 13 can determine that the power state of the power module 1 is a normal state.

[0110] Case 2: It is determined that there are K-bit preset signals in the target power signal.

[0111] In this case, the controller can determine, according to the target power signal, that the power state of the detected power module is an abnormal state.

[0112] For example, if K is 1, the detected power module is power module 1, and the corresponding target power signal 1 is "1000", since there are 3 preset signals "0" in the target power signal 1, the controller 13 can determine that the power state of the power module 1 is an abnormal state.

[0113] After the controller determines the power state of the power module, the controller can output the power state to the master control circuit, and the master control circuit can control the working state of at least one detection circuit according to the power state.

[0114] Optionally, for any one detection circuit, different time windows can be set for the detection circuit, and the first filter, the second filter and the controller in the detection circuit are normally operated within the time window. For example, the time length of the time window of the detection circuit can be the time length between the start and the shutdown of the device in which the detection circuit is located.

[0115] Optionally, the master control circuit can control the working state of at least one detection circuit according to the power state, which can be divided into the following two cases:

[0116] Case 1: The received power state is a normal state.

[0117] In this case, the master control circuit can control the working state of at least one detection circuit to be a running state.

[0118] For example, as shown in Figure 3 If the power state 1 output by the controller 13 to the master control circuit is a normal state, after the master control circuit receives the power state 1, since the power state 1 is a normal state, it means that there is no abnormality, and at least one detection circuit can continue to operate normally.

[0119] Case 2: The received power state is an abnormal state.

[0120] In this situation, it indicates that at least one power module is malfunctioning. Since multiple power modules may influence each other, causing other power modules to malfunction, their corresponding detection circuits may determine the power status as abnormal. Ultimately, this prevents the main control circuit from identifying the first malfunctioning power module. Therefore, when the main control circuit receives at least one abnormal power status, it can send a lock signal to at least one detection circuit to instruct it to switch its operating state to a paused state. This prevents the detection circuit from sending power status information to the main control circuit, facilitating the main control circuit's identification of the first malfunctioning power module.

[0121] Optionally, the lock signal can be represented by "lock".

[0122] For example, such as Figure 3 If the power state 1 transmitted by the controller 13 to the main control circuit is an abnormal state, the main control circuit can send a lock signal to the Q detection circuits after receiving the power state 1, so as to instruct the Q detection circuits to switch their working state to the pause state, so that the Q detection circuits will no longer send the power state to the main control circuit, making it easier for the main control circuit to determine that the first power module that has an abnormality is power module 1.

[0123] Optionally, if multiple controllers simultaneously send multiple power states to the central control circuit, all of which are abnormal states, the central control circuit can also synthesize fault information based on the priority of the power states sent by each controller, and send the fault information to the read / write module so that the read / write module records the power states of multiple power modules.

[0124] Alternatively, the control process of the power supply control circuit can be implemented through code.

[0125] In this embodiment, the power control circuit may include a central control circuit and at least one detection circuit. The detection circuit may include a controller, a first filter, and a second filter. The first filter filters the initial power signal to obtain a first power signal, and the second filter filters the first power signal to obtain a target power signal. The controller can determine the power state of the power module based on the target power signal and send the power state to the central control circuit. The central control circuit can control the operating state of at least one detection circuit based on the received power state. Since the initial power signal of the power module can be filtered by at least two filters, and the power state can be determined by the controller, the accuracy of determining the power state is improved compared to determining the power state based on the voltage output of each power module. This improves the reliability of the power control circuit in controlling multiple power modules.

[0126] Below, based on any of the above embodiments, combined withFigure 4 , provide a schematic diagram of a mainboard circuit.

[0127] Figure 4 A schematic diagram of a mainboard circuit is provided for the exemplary embodiments of the present application. Please refer to Figure 4 , the mainboard circuit can include a power supply control circuit and at least one power module.

[0128] As Figure 4 , the at least one power module can be power module 1, power module 2, …, power module Q respectively. For any one power module, the power supply can generate an initial power signal. For example, power module 1 can generate initial power signal 1.

[0129] Optionally, the initial power signal can include a PG signal and a Power Fail signal. If the voltage of the power module is low, the Power Fail signal "0" can be generated; if the voltage of the power module is high, the PG signal "1" can be generated. For example, if the voltage of power module 1 is "high high low low high", the corresponding initial power signal 1 can be "11001".

[0130] The power supply control circuit can include a master control circuit and at least one detection circuit.

[0131] For any one detection circuit, the detection circuit can be connected with the corresponding power module. As Figure 4 , detection circuit 1 can be connected with power module 1, detection circuit 2 can be connected with power module 2, …, detection circuit Q can be connected with power module Q.

[0132] For any one detection circuit, the detection circuit can include a first filter, a second filter and a controller. The input end of the first filter is connected with the detected power module, the output end of the first filter is connected with the input end of the second filter; the output end of the second filter is connected with the controller.

[0133] The first filter can be used to filter the initial power signal based on the system clock frequency to obtain a first power signal.

[0134] The second filter can be used to filter the first power signal based on a preset clock frequency to obtain a target power signal.

[0135] It should be noted that the specific execution process of obtaining the first power signal and the target power signal can refer to the specific execution process of obtaining the first power signal and the target power signal in Figure 3 , which will not be described here.

[0136] After the second filter determines the target power supply signal, the target power supply signal can be output to the controller. The controller can determine the power supply state of the detected power supply module according to the target power supply signal. The power supply state can be divided into a normal state and an abnormal state.

[0137] It should be noted that the specific implementation process of the controller determining the power supply state of the detected power supply module can refer to the specific implementation process of the controller determining the power supply state of the detected power supply module in Figure 3 , which will not be described here in detail.

[0138] After the controller determines the power supply state of the detected power supply module, the power supply state can be output to the master control circuit. The master control circuit can control the working state of at least one detection circuit according to the power supply state. The working state can be divided into a running state or a suspended state.

[0139] Optionally, if the power supply state received by the master control circuit is an abnormal state, the master control circuit can send a locking signal to at least one detection circuit according to the power supply state, instructing at least one detection circuit to switch the working state to a suspended state, so that at least one detection circuit no longer sends the power supply state to the master control circuit, facilitating the master control circuit to determine the first detected power supply module that has an abnormality.

[0140] In the embodiments of the present application, the mainboard circuit can include a power supply control circuit and at least one power supply module. The power supply control circuit can include a master control circuit and at least one detection circuit, and the detection circuit can include a controller, a first filter and a second filter. The first filter can filter the initial power supply signal to obtain a first power supply signal, and the second filter can filter the first power supply signal to obtain a target power supply signal. The controller can determine the power supply state of the detected power supply module according to the target power supply signal and send the power supply state to the master control circuit. The master control circuit can control the working state of at least one detection circuit according to the received power supply state. Since the initial power supply signal of the power supply module can be filtered by at least two filters, and then the power supply state is determined by the controller, compared with determining the power supply state by the voltage output by each power supply module, the accuracy of determining the power supply state is improved, and the reliability of the power supply control circuit in controlling multiple power supply modules is improved.

[0141] Figure 5 A structure diagram of a sub-card circuit is provided for the exemplary embodiments of the present application. Please refer to Figure 5 , the sub-card circuit can include a power supply control circuit and at least one power supply module.

[0142] As Figure 5The at least one power module can be power module 1, power module 2, …, and power module P respectively. For any one power module, the power module can generate an initial power signal. For example, power module 1 can generate initial power signal 1.

[0143] The power control circuit can include a master control circuit and at least one detection circuit.

[0144] For any one detection circuit, the detection circuit can be connected to the corresponding power module. For example, Figure 5 detection circuit 1 can be connected to power module 1, detection circuit 2 can be connected to power module 2, …, and detection circuit P can be connected to power module P.

[0145] For any one detection circuit, the detection circuit can include a first filter, a second filter, and a controller. The input end of the first filter is connected to the detected power module, the output end of the first filter is connected to the input end of the second filter, and the output end of the second filter is connected to the controller.

[0146] The first filter can be used to filter the initial power signal based on the system clock frequency to obtain a first power signal.

[0147] The second filter can be used to filter the first power signal based on a preset clock frequency to obtain a target power signal.

[0148] It should be noted that the specific execution process of obtaining the first power signal and the target power signal can be referred to Figure 3 the specific execution process of obtaining the first power signal and the target power signal, which will not be described here.

[0149] After the second filter determines the target power signal, the second filter can output the target power signal to the controller. The controller can determine the power state of the detected power module according to the target power signal. The power state can be divided into a normal state and an abnormal state.

[0150] It should be noted that the specific execution process of the controller determining the power state of the detected power module can be referred to Figure 3 the specific execution process of the controller determining the power state of the detected power module, which will not be described here.

[0151] After the controller determines the power state of the detected power module, the controller can output the power state to the master control circuit, and the master control circuit can control the working state of the at least one detection circuit according to the power state. The working state can be divided into a running state or a suspended state.

[0152] Optionally, if the power state received by the general control circuit is an abnormal state, the general control circuit can send a locking signal to the at least one detection circuit according to the power state, instructing the at least one detection circuit to switch the working state to a suspended state, so that the at least one detection circuit no longer sends the power state to the general control circuit, facilitating the general control circuit to determine the first detected power module that is abnormal.

[0153] In the embodiments of the present application, the sub-card circuit can include a power control circuit and at least one power module. The power control circuit can include a general control circuit and at least one detection circuit, and the detection circuit can include a controller, a first filter and a second filter. The first filter can filter the initial power signal to obtain a first power signal, and the second filter can filter the first power signal to obtain a target power signal. The controller can determine the power state of the detected power module according to the target power signal and send the power state to the general control circuit. The general control circuit can control the working state of the at least one detection circuit according to the received power state. Since the initial power signal of the power module can be filtered by at least two filters, and then the power state is determined by the controller, compared with determining the power state by the voltage output by each power module, the accuracy of determining the power state is improved, and the reliability of the power control circuit in controlling multiple power modules is improved.

[0154] In the following, on the basis of any of the above embodiments, combined with Figure 6 , a structural diagram of a server is provided.

[0155] Figure 6 A structural diagram of a server is provided for the exemplary embodiments of the present application. Please refer to Figure 6 The server can include a mainboard circuit and at least one sub-card circuit.

[0156] The mainboard circuit can include a power control circuit and at least one power module. The power control circuit can include at least one detection circuit and a general control circuit.

[0157] The at least one sub-card circuit can be sub-card circuit 1, …, sub-card circuit S respectively. S is an integer greater than or equal to 1.

[0158] For any one sub-card circuit, the sub-card circuit can include a power control circuit and at least one power module. The power control circuit can include at least one detection circuit and a general control circuit.

[0159] Optionally, the power control circuit in the mainboard circuit and the power control circuit in the sub-card circuit are connected. For example, as shown in Figure 6 , the power control circuit 1 in the mainboard circuit can be connected with the power control circuit 2 in the sub-card circuit 1.

[0160] For any one of the power control circuits in the mainboard circuit or the sub-card circuit, the power control circuit can include a master control circuit and at least one detection circuit, the detection circuit can include a controller, a first filter and a second filter. The first filter can filter the initial power signal to obtain a first power signal, and the second filter can filter the first power signal to obtain a target power signal. The controller can determine the power state of the detected power module according to the target power signal, and send the power state to the master control circuit. The master control circuit can control the working state of the at least one detection circuit according to the received power state.

[0161] It should be noted that the specific roles of the controller, the first filter and the second filter, and the master control circuit can be referred to the contents shown in any of the above embodiments, which will not be described here.

[0162] When the power control circuit is located in the sub-card circuit, the master control circuit can be used to receive the first electrical control signal sent by the power control circuit in the mainboard circuit through the up-down point interface, and the second electrical control signal sent through the bus interface; according to the first electrical control signal and the second electrical control signal, control the power module in the sub-card circuit to power on or power off.

[0163] The up-down point interface refers to the communication interface between the mainboard circuit and the sub-card circuit. For example, the up-down point interface can be a serial general purpose input / output (Serial General Purpose Input / Output, SGPIO) interface.

[0164] The first electrical control signal can be a communication signal between the mainboard circuit and the sub-card circuit.

[0165] The bus interface refers to the physical bus interface between the mainboard circuit and the sub-card circuit.

[0166] The second electrical control signal can be a power-on signal or a power-off signal.

[0167] As Figure 6 In the above, the master control circuit 1 in the mainboard circuit can send the first electrical control signal to the master control circuit 2 in the sub-card circuit through the up-down point interface, and send the second electrical control signal to the master control circuit 2 through the bus interface, then the master control circuit 2 in the sub-card circuit can control the power module in the sub-card circuit to power on or power off according to the first electrical control signal and the second electrical control signal.

[0168] Alternatively, if the first electrical control signal and / or the second electrical control signal indicates power on, the power module in the sub-card circuit can be controlled to power on; if the first electrical control signal and the second electrical control signal respectively indicate power off, the power module in the sub-card circuit can be controlled to power off.

[0169] The following describes the process of powering on the power module in the control sub-card circuit. Figure 7 The following describes the process of powering on the power module in the control sub-card circuit.

[0170] Figure 7 A flowchart of a power-on method provided by an exemplary embodiment of the present application is shown in FIG. 7. The method can include the following steps. Figure 7 The method can include the following steps.

[0171] S701, determining an initial state of the power module.

[0172] The master control circuit in the sub-card circuit can determine the initial state of the power module in the sub-card circuit. The initial state can be divided into a power-off state and a power-on state.

[0173] If the initial state of the power module is the power-off state, steps S702-S704 can be performed.

[0174] S702, determining whether the first electrical control signal indicates power-on.

[0175] The master control circuit in the sub-card circuit can determine whether the first electrical control signal indicates power-on. If not, step S703 can be performed; if yes, step S704 can be performed.

[0176] S703, determining whether the second electrical control signal indicates power-on.

[0177] The master control circuit in the sub-card circuit can determine whether the second electrical control signal indicates power-on. If yes, step S704 can be performed; if not, it means that neither the first electrical control signal nor the second electrical control signal indicates power-on, and the initial state of the power module, i.e., the power-off state, can be maintained.

[0178] S704, controlling the power module to power on.

[0179] If either the first electrical control signal indicates power-on in step S702 or the second electrical control signal indicates power-on in step S703, the master control circuit in the sub-card circuit can control the power module in the sub-card circuit to power on.

[0180] The following describes the process of powering on the power module in the control sub-card circuit. Figure 8 The following describes the process of powering on the power module in the control sub-card circuit.

[0181] Figure 8 A flowchart of a power-off method provided by an exemplary embodiment of the present application is shown in FIG. 8. The method can include the following steps. Figure 8 The method can include the following steps.

[0182] S801, determining an initial state of the power module.

[0183] The master control circuit in the daughter card circuit can determine the initial state of the power module in the daughter card circuit. The initial state can be divided into the power-down state and the power-on state.

[0184] If the initial state of the power module is power-on, then S802 to S804 can be executed.

[0185] S802. Determine whether the first electrical control signal indicates power-off.

[0186] The master control circuit in the daughter card circuit can determine whether the first power control signal indicates power-off. If yes, it can execute S803; otherwise, it maintains the initial state of the power module, i.e., the power-on state.

[0187] S803. Determine whether the second electrical control signal indicates power-off.

[0188] The master control circuit in the daughter card circuit can determine whether the second power control signal indicates power-off. If yes, it can execute S804; if no, it can maintain the initial state of the power module, i.e., the power-on state.

[0189] S804, power off the control power module.

[0190] If in step S802 it is determined that the first electrical control signal indicates power-off, and in step S803 it is determined that the second electrical control signal indicates power-off, and both conditions are met, then the master control circuit in the sub-card circuit can control the power supply module in the sub-card circuit to power off.

[0191] pass Figure 8 As shown in the process, the master control circuit in the daughter card circuit can determine whether to power down the power module based on the first electrical control signal and the second electrical control signal, thereby improving the reliability of controlling the power module.

[0192] Optionally, if the master control circuit in the daughter card circuit receives a power status message from the controller indicating an abnormal state, the master control circuit in the daughter card circuit can send fault information to the master control circuit in the motherboard circuit. This fault information may include the power status message. The motherboard circuit can then perform appropriate processing based on the system strategy and the fault information.

[0193] In the embodiment of the present application, the server can include a mainboard circuit and at least one daughterboard circuit. The mainboard circuit and the daughterboard circuit can each include a power control circuit and at least one power module. Any one of the power control circuits can include a master control circuit and at least one detection circuit, and the detection circuit can include a controller, a first filter and a second filter. The first filter can perform filtering processing on the initial power supply signal to obtain a first power supply signal, and the second filter can perform filtering processing on the first power supply signal to obtain a target power supply signal. The controller can determine the power supply state of the detected power module according to the target power supply signal, and send the power supply state to the master control circuit. The master control circuit can control the working state of the at least one detection circuit according to the received power supply state. The master control circuit in the daughterboard circuit can also control the power-on and power-off of the power module in the daughterboard circuit according to the first and second electrical control signals. Since the initial power supply signal of the power module can be filtered by at least two filters, and then the power supply state is determined by the controller, compared with determining the power supply state according to the voltage output by each power module, the accuracy of determining the power supply state is improved. Moreover, the master control circuit in the daughterboard circuit can double-check whether the power module is powered off according to the first and second electrical control signals, thereby improving the reliability of the power control circuit in the server for controlling multiple power modules.

[0194] Those skilled in the art will understand that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage, etc.) containing computer-usable program code.

[0195] The present application is described with reference to flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing apparatus to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing apparatus produce a device that implements the functions specified in the flowcharts and / or block diagrams. Figure 1 The functions specified in a flow or multiple flows and / or blocks Figure 1 The functions specified in a flow or multiple flows and / or blocks

[0196] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the Figure 1 function specified in the flow or flows and / or blocks Figure 1 of the block or blocks.

[0197] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the Figure 1 function specified in the flow or flows and / or blocks Figure 1 of the block or blocks.

[0198] In one typical configuration, the computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory.

[0199] The memory can include non-persistent memory and / or volatile memory, such as random access memory (RAM) about which the computer stores information about an operating system, application software, and / or the like. Memory is an example of computer readable media.

[0200] Computer readable media includes permanent and non-permanent, moveable and non- moveable media that can be implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital versatile disks (DVDs) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that is accessible to a computing device. According to the definition provided herein, a computer readable medium excludes transitory computer readable media, such as modulated data signals and carrier waves.

[0201] It is also to be noted that the terms "comprising", "including", and any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises a... " does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0202] The above description is merely illustrative of the application, and not restrictive. Various modifications and changes can become apparent to those skilled in the art. Incorporating any modification, equivalent substitution, improvement, etc. within the spirit and principle of the application, shall be included in the scope of the claims of the application.

Claims

1. A power supply control circuit, characterized in that, The system includes a master control circuit and at least one detection circuit. The detection circuit includes a controller and at least two filters, including a first filter and a second filter. The input terminal of the first filter is connected to the power module under test, and the output terminal of the first filter is connected to the input terminal of the second filter. The output terminal of the second filter is connected to the controller, and the controller is connected to the master control circuit. The first filter is used to acquire the initial power signal of the power module under test, and to sample the initial power signal based on the system clock frequency to obtain the first sampled signal; If a first abrupt change signal exists in the first sampled signal, the first abrupt change signal is filtered out from the first sampled signal to obtain a first power supply signal; the duration of the first abrupt change signal is less than or equal to the duration of M system clock cycles, where M is an integer greater than or equal to 1. The second filter is used to sample the first power signal based on a preset clock frequency to obtain a second sampled signal; If a second abrupt change signal exists in the second sampled signal, the second abrupt change signal is filtered out from the second sampled signal to obtain the target power signal. The duration of the second abrupt change signal is less than or equal to the duration of N preset clock cycles, where N is an integer greater than or equal to 1. The controller is used to determine the power status of the detected power module based on the target power signal, and send the power status to the main control circuit; the power status includes a normal state or an abnormal state; The main control circuit is used to control the operating state of the at least one detection circuit according to the received power status, the operating state including running state or paused state.

2. The circuit according to claim 1, characterized in that, The controller is specifically used for: When it is determined that there is a K-bit preset signal in the target power signal, the power state is determined to be an abnormal state, where K is an integer greater than or equal to 1.

3. The circuit according to claim 1 or 2, characterized in that, The main control circuit is specifically used for: If the received power state is an abnormal state, a lock signal is sent to the at least one detection circuit, the lock signal being used to instruct the at least one detection circuit to switch its operating state to the paused state.

4. The circuit according to claim 1 or 2, characterized in that, The power control circuit is located in the sub-card circuit; the main control circuit is also used for: It receives the first electrical control signal sent by the power control circuit in the motherboard circuit through the up and down point interfaces, and the second electrical control signal sent through the bus interface; Based on the first electrical control signal and the second electrical control signal, the power module in the sub-card circuit is controlled to be powered on or off.

5. The circuit according to claim 4, characterized in that, The main control circuit is specifically used for: When the first electrical control signal and / or the second electrical control signal indicate power-on, the power module in the sub-card circuit is powered on. When the first electrical control signal and the second electrical control signal respectively indicate power-off, the power module in the sub-card circuit is powered off.

6. A motherboard circuit, characterized in that, It includes the power control circuit as described in any one of claims 1-5 and at least one power module, wherein at least one detection circuit in the power control circuit is connected to the corresponding power module.

7. A daughter card circuit, characterized in that, It includes the power control circuit as described in any one of claims 1-5 and at least one power module, wherein at least one detection circuit in the power control circuit is connected to the corresponding power module.

8. A server, characterized in that, It includes the motherboard circuit of claim 6 and at least one daughter card circuit of claim 7, wherein the power control circuit in the motherboard circuit and the power control circuit in the daughter card circuit are connected.

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