Method and device for automatically generating logic circuit, electronic equipment and storage medium

Abstract

Embodiments of the present application provide a method and device for automatically generating a logic circuit, electronic equipment and a storage medium. The method comprises obtaining a plurality of sets of input values and an output value corresponding to each set of input values; obtaining an initial logic relationship between the output value and the input values according to the plurality of sets of input values and the output value corresponding to each set of input values; performing combination and simplification processing on the initial logic relationship between the output value and the input values, determining the same items in the initial logic relationship between the output value and the input values, using preset identification information to identify the same items, and using the identification information to update the initial logic relationship to obtain a target logic relationship between the output value and the input values; and generating a logic circuit according to the target logic relationship between the output value and the input values. This method automatically generates a logic circuit, especially for a complex logic circuit, without the need for a user to use an iterative approximation algorithm to design a logic circuit capable of performing mathematical calculations on a given input value, thereby reducing the design time of the logic circuit and improving efficiency.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more specifically to a method, apparatus, electronic device, and storage medium for automatically generating logic circuits. Background Technology

[0002] With the rapid development of computers, the demand for high-speed execution of certain functions in hardware is increasing. For example, integrated circuits used for computer image processing and digital signal processing may often need to calculate the value of logarithms, gamma functions, or other mathematical functions for a given input value. In some technologies, when performing complex mathematical calculations in circuits, they are often not performed directly, but rather using iterative approximation algorithms. For example, in trigonometric function calculations, the Cordic algorithm is commonly used to iteratively approximate the true result to obtain the calculated value.

[0003] The above approach requires developers to be familiar with iterative approximation algorithms, such as the Cordic algorithm, and to design logic circuits capable of performing mathematical calculations on a given input value using these algorithms. This is especially true for logic circuits involving complex mathematical calculations, which are time-consuming and demand highly skilled developers, resulting in low project development efficiency and long development cycles. Summary of the Invention

[0004] In view of this, this application provides a method, apparatus, electronic device and storage medium for automatically generating logic circuits, so as to solve the problem that the logic circuit design for implementing mathematical calculations in the prior art is time-consuming and inefficient.

[0005] In a first aspect, embodiments of this application provide a method for automatically generating logic circuits, comprising:

[0006] Obtain multiple sets of input values ​​and the corresponding output value for each set of input values;

[0007] Based on the multiple sets of input values ​​and the output value corresponding to each set of input values, obtain the initial logical relationship between the output value and the input value;

[0008] The initial logical relationship between the output value and the input value is combined and simplified to determine the common items in the initial logical relationship between the output value and the input value. The common items are identified using preset identification information, and the initial logical relationship is updated using the identification information to obtain the target logical relationship between the output value and the input value.

[0009] A logic circuit is generated based on the target logical relationship between the output value and the input value.

[0010] Preferably, obtaining the initial logical relationship between the input values ​​and the output values ​​based on the multiple sets of input values ​​and the output value corresponding to each set of input values ​​includes:

[0011] Get the preset number of bits for the preset data format of each input value in any set of input values, and the preset number of bits for the preset data format of the output value;

[0012] Based on the preset number of bits of the preset data format of each input value in any set of input values ​​and the preset number of bits of the preset data format of the output value, each set of input values ​​and the corresponding output value are converted according to the preset data format to obtain the truth table information between the input values ​​and the output values; wherein, the input value of the preset data format contains its corresponding preset number of data bits; the output value of the preset data format contains its corresponding preset number of data bits;

[0013] Based on the truth table information, the initial logical relationship between the output value and the input value is obtained; wherein, the initial logical relationship between the data bits of different output values ​​and the data bits of the input values ​​is not completely the same.

[0014] Preferably, the step of combining and simplifying the initial logical relationship between the output value and the input value, determining the common items in the initial logical relationship between the output value and the input value, identifying the common items using preset identification information, and updating the initial logical relationship using the identification information to obtain the target logical relationship between the output value and the input value includes:

[0015] Obtain a preset simplification algorithm, and perform logical simplification on the logical relationship between each data bit of the output value and each data bit of the input value according to the preset simplification algorithm to obtain the simplified logical relationship between each data bit of the output value and each data bit of the input value;

[0016] The simplified logical relationship between each data bit of the output value and each data bit of the input value is combined and simplified to determine the same items in the simplified logical relationship between the output value and the input value. The same items are identified using preset identification information, and the logical relationship is updated using the identification information to obtain the target logical relationship between the output value and the input value.

[0017] Preferably, the step of combining and simplifying the simplified logical relationship between each data bit of the output value and each data bit of the input value, determining the common items in the simplified logical relationship between the output value and the input value, identifying the common items using preset identification information, and updating the logical relationship using the identification information to obtain the target logical relationship between the output value and the input value includes:

[0018] Based on the preset number of bits of the preset data format of each input value in any set of input values, obtain the comparison logic item;

[0019] Based on the comparison logic term, it is detected whether there is a common term in the simplified logical relationship between different data bits of the output value and each data bit of the input value; if so, the common term is identified using preset identification information, and the simplified logical relationship is updated using the identification information to obtain the target logical relationship between the output value and the input value.

[0020] Preferably, obtaining the comparison logic item based on the preset number of bits of the preset data format of each input value in the set of input values ​​includes:

[0021] Based on the preset number of bits of the preset data format of each input value in any set of input values, determine m logical input groups; each logical input group contains two logical input values ​​with opposite values; where m is an integer greater than 1;

[0022] Set n to a preset initial value; the preset initial value is an integer greater than 1 and not greater than m;

[0023] From the logical input values ​​contained in the m logical input groups, a comparison logical term is formed according to the n logical input values ​​from different logical input groups, resulting in... One comparison logic item;

[0024] Check if n is equal to m;

[0025] If they are not equal, then n is updated to n+1, and the step described above is repeated: among the logical input values ​​contained in the m logical input groups, a comparison logical term is formed according to the n logical input values ​​from different logical input groups, resulting in... Each comparison logic term is used to check whether n is equal to m, until n is equal to m.

[0026] Preferably, the step of detecting whether there is a common term in the simplified logical relationship between different data bits of the output value and each data bit in at least one set of input values, based on the comparison logic term; if so, identifying the common term using identification information and updating the simplified logical relationship using the identification information to obtain the target logical relationship between the output value and the input value includes:

[0027] All acquired comparison logic items are identified as unmarked comparison logic items;

[0028] Among the unlabeled comparison logic items, a target comparison logic item is determined; the target logic item is the comparison logic item with the most logical input values ​​contained in the unlabeled comparison logic items.

[0029] Update the marked comparison logic item according to the target comparison logic item, and update the unmarked comparison logic item;

[0030] Based on the marked comparison logic term, check whether the simplified logical relationship between different data bits of the output value and each data bit of the input value contains at least two items that are the same as the marked comparison logic term;

[0031] If so, at least two items that are the same as the marked comparison logical item are marked using the identification information, and the simplified logical relationship is updated using the identification information.

[0032] Check for the presence of unlabeled comparison logic items;

[0033] If it exists, the step of determining the target comparison logic item in the unlabeled comparison logic item is repeated until the step of checking whether there is an unlabeled comparison logic item is found, until there is no unlabeled comparison logic item.

[0034] Preferably, the preset simplification algorithm includes: Quinn-McLusky QM simplification.

[0035] Preferably, generating the logic circuit based on the target logical relationship between the output value and the input value includes:

[0036] Based on the target logical relationship between the output and input values, register transfer level RTL code is generated.

[0037] Secondly, embodiments of this application provide an automatic logic circuit generation apparatus, comprising:

[0038] The acquisition unit is used to acquire multiple sets of input values ​​and the corresponding output value for each set of input values;

[0039] The acquisition unit is further configured to acquire the initial logical relationship between the output value and the input value based on the multiple sets of input values ​​and the output value corresponding to each set of input values;

[0040] The processing unit is used to perform combination and simplification processing on the initial logical relationship between the output value and the input value, determine the same items in the initial logical relationship between the output value and the input value, identify the same items using preset identification information, and update the initial logical relationship using the identification information to obtain the target logical relationship between the output value and the input value.

[0041] The processing unit is also configured to generate logic circuits based on the target logical relationship between the output value and the input value.

[0042] Thirdly, embodiments of this application provide an electronic device, including a memory for storing computer program instructions and a processor for executing the program instructions, wherein when the computer program instructions are executed by the processor, the electronic device is triggered to execute the method described in any of the first aspects above.

[0043] Fourthly, embodiments of this application provide a computer-readable storage medium including a stored program, wherein, when the program is executed, it controls the device where the computer-readable storage medium is located to perform the method described in any of the first aspects above.

[0044] The scheme provided in this application embodiment obtains multiple sets of input values ​​and the corresponding output values ​​for each set of input values; based on the multiple sets of input values ​​and the corresponding output values ​​for each set of input values, an initial logical relationship between the output values ​​and input values ​​is obtained; the initial logical relationship between the output values ​​and input values ​​is combined and simplified to determine the common items in the initial logical relationship between the output values ​​and input values, and the common items are identified using preset identification information, and the initial logical relationship is updated using the identification information to obtain the target logical relationship between the output values ​​and input values; based on the target logical relationship between the output values ​​and input values, a logic circuit corresponding to the target mathematical function is generated. In other words, in this application embodiment, when implementing the operation of a mathematical function, the input values ​​of the mathematical function can be obtained and its output values ​​can be calculated. Based on the input values ​​and output values, an initial logical relationship between the output values ​​and input values ​​is obtained; the initial logical relationship between the output values ​​and input values ​​is combined and simplified to determine the common items in the initial logical relationship, and the common items are identified using preset identification information; the initial logical relationship is updated using the preset identification information to obtain the target logical relationship between the output values ​​and input values. Based on the target logical relationship between the output values ​​and input values, a logic circuit is generated. In other words, in this embodiment of the application, logic circuits can be automatically generated directly based on the input and output values ​​calculated from the data. Users do not need to use iterative approximation algorithms to design logic circuits that can perform mathematical calculations on fixed input values, which reduces the design time of logic circuits, especially complex mathematical logic circuits, and improves efficiency. Attached Figure Description

[0045] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 A flowchart illustrating an automatic logic circuit generation method provided in an embodiment of this application;

[0047] Figure 2 A flowchart illustrating an automatic logic circuit generation method provided in an embodiment of this application;

[0048] Figure 3 A schematic diagram of the structure of an automatic logic circuit generation device provided in an embodiment of this application;

[0049] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0050] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0051] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0052] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0053] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0054] Before providing a detailed description of the embodiments of this application, the terms used or possibly used in the embodiments of this application will first be explained.

[0055] RTL (Register Transfer Level) is an abstract description of a real circuit.

[0056] QM method: Quinn-McLoughlinsky simplification is a logical expression simplification method that overcomes the limitations of Karnaugh map simplification and is suitable for computer-aided simplification.

[0057] In related technologies, when performing complex mathematical calculations in circuits, the methods are often not direct computation, but rather iterative approximation algorithms. For example, in trigonometric function calculations, the Cordic algorithm is typically used to iteratively approximate the actual result to obtain the calculated value.

[0058] The above approach requires developers to be familiar with iterative approximation algorithms, such as the Cordic algorithm, and to design their own logic circuits capable of performing mathematical calculations on a given input value. In other words, the logic circuits for mathematical calculations need to be designed manually by the user, which is time-consuming, increases the developer's workload, and is inefficient.

[0059] To address the aforementioned problems, this application provides an automatic logic circuit generation method, apparatus, electronic device, and storage medium. The method involves acquiring multiple sets of input values ​​and corresponding output values ​​for each set of input values; obtaining an initial logical relationship between the output values ​​and input values ​​based on the multiple sets of input values ​​and their corresponding output values; performing a combination and simplification process on the initial logical relationship between the output values ​​and input values ​​to identify common items in the initial logical relationship; using preset identification information to identify common items; and updating the initial logical relationship using the identification information to obtain a target logical relationship between the output values ​​and input values; and generating a logic circuit corresponding to a target mathematical function based on the target logical relationship between the output values ​​and input values. In other words, in this application embodiment, when implementing the operation of a mathematical function, the input values ​​of the mathematical function can be acquired and its output values ​​calculated. Based on the input values ​​and output values, the initial logical relationship between the output values ​​and input values ​​is acquired; the initial logical relationship between the output values ​​and input values ​​is performed through combination and simplification to identify common items in the initial logical relationship; using preset identification information to identify common items; and updating the initial logical relationship based on the preset identification information to obtain the target logical relationship between the output values ​​and input values. A logic circuit is generated based on the target logical relationship between the output value and the input value. In other words, in this embodiment, a logic circuit can be automatically generated directly from the input and output values ​​calculated from the data. This eliminates the need for users to design logic circuits capable of mathematical calculations on fixed input values ​​using iterative approximation algorithms, reducing the design time for logic circuits, especially complex mathematical logic circuits, and improving efficiency. A detailed explanation follows.

[0060] See Figure 1 This is a flowchart illustrating an automatic logic circuit generation method provided in an embodiment of this application. Figure 1 As shown, the method includes:

[0061] Step S101: Obtain multiple sets of input values ​​and the corresponding output values ​​for each set of input values.

[0062] The output value for each group is calculated using a preset mathematical function based on the input values ​​for that group. Each input group contains at least one input value.

[0063] In this embodiment, to automatically generate the logic circuit of the mathematical function, all possible input values ​​can be preset for the mathematical function. Each preset possible input value is treated as a group of input values, resulting in multiple groups of input values. This allows for the acquisition of multiple preset input values, and each group of input values ​​is calculated using a preset data function to obtain the corresponding output value.

[0064] It should be understood that mathematical calculations are usually performed on given input values. That is, input values ​​and mathematical functions are typically set during mathematical calculations. The output value is then calculated based on the set input values ​​and mathematical functions. Of course, when setting input values, specific numerical values ​​can be directly specified. This means specifying how many input values ​​are included in each group, the specific value of each input value, and the total number of input groups. The range of values ​​for each input value and the rules for obtaining them can also be set. The rules for obtaining them specify how to obtain the input value within the specified range. For example, each group of input values ​​contains two input values, 'a' and 'b'. The specific values ​​of 'a' and 'b' differ between groups. Assuming the rules specify that 'a' and 'b' are both integers, and their range is [0, 9], then according to the rules, integers within that range will be used as input values. Thus, by determining the range and rules for each input value, each group of input values ​​can be determined, resulting in 100 values.

[0065] As one possible implementation, to generate the logic circuit more accurately, it is necessary to exhaustively enumerate all possible output values. Therefore, when obtaining multiple sets of input values, all possible input values ​​for which mathematical function calculations are required should be obtained. In this way, given that the mathematical function is known, all possible output values ​​can be exhaustively enumerated. That is, to obtain all sets of input values ​​for performing the preset mathematical function calculation and the corresponding output value for each set of input values.

[0066] As shown in the example above, when the input value is 100, the value 100 can be obtained. A preset mathematical function is applied to each set of input values ​​to calculate and obtain the value 100. Let's assume the preset mathematical function is... The calculated output values ​​are shown in Table 1 below.

[0067] Table 1

[0068]

[0069]

[0070] Step S102: Based on multiple sets of input values ​​and the output value corresponding to each set of input values, obtain the initial logical relationship between the output value and the input value.

[0071] The initial logical relationship between the data bits of different output values ​​and the data bits of the input values ​​is not exactly the same.

[0072] In this embodiment of the application, after obtaining multiple sets of input values ​​and the output values ​​corresponding to each set of input values, the numerical relationship between each set of input values ​​and the output values ​​corresponding to each set of input values ​​can be converted into a logical relationship between the output values ​​and the input values, which is to obtain the initial logical relationship between the output values ​​and the input values.

[0073] As one possible implementation, obtaining the initial logical relationship between input values ​​and output values ​​based on multiple sets of input values ​​and the corresponding output value for each set of input values ​​includes:

[0074] Obtain the preset number of bits for the preset data format of each input value in any set of input values, and the preset number of bits for the preset data format of the output value. Based on the preset number of bits for the preset data format of each input value in any set of input values, and the preset number of bits for the preset data format of the output value, perform preset data format conversion processing on each set of input values ​​and the corresponding output value to obtain truth table information between input values ​​and output values. Based on the truth table information, obtain the initial logical relationship between output values ​​and input values.

[0075] The input value in the preset data format contains a preset number of data bits; the output value in the preset data format also contains a preset number of data bits. Furthermore, each data bit in both the input and output values ​​has a value of either 0 or 1.

[0076] To more quickly and accurately obtain the initial logical relationship between input and output values, the input and output values ​​can first be converted into a preset data format. The initial logical relationship is then determined based on the relationship between the input and output values ​​in the preset data format. For example, if the preset data format is binary, the initial logical relationship between the output and input values ​​can be obtained based on the numerical relationship between the input and output values ​​after conversion to binary. At this point, the preset bit length of the preset data format for each input value and the preset bit length of the preset data format for the output value can be obtained. That is, how many bits of binary digits represent each input and output value. After obtaining the preset bit length of the preset data format for each input value and the preset bit length of the preset data format for each output value, each input value in each group can be converted into its own preset data format with its own preset bit length. Finally, each output value is converted into its preset data format with its own preset bit length, thus obtaining the truth table information between the input and output values. For example, when the preset data format is binary, after obtaining the preset number of bits for the binary data formats of each input value and the output value, each input value in each group is converted into a binary number of the preset number of bits according to its corresponding binary data format. Similarly, the output value is converted into a binary number of the preset number of bits according to its corresponding binary data format. Truth table information is formed by each input value and its corresponding output value in each group of input values ​​in binary data format, thus obtaining the truth table information between the input and output values. Based on the truth table information between the input and output values, the numerical relationship between the input and output values ​​is converted into a logical relationship, obtaining the initial logical relationship between the output and input values. That is, based on the truth table information between the input and output values, the logical relationship between each data bit of the output value and each data bit in at least one group of input values ​​can be determined. This logical relationship can be used as the initial logical relationship between the output and input values, obtaining the preset number of initial logical relationships for the output value.

[0077] The initial logical relationship between the output value and the input value refers to how each data bit of the output value is represented by the data bits in the input value.

[0078] It should be understood that after converting the input and output values ​​into data of a preset data format according to the corresponding preset number of bits, the initial logical relationship can be obtained based on the data relationship between each data bit of the output value and each data bit of the input value, and the preset number of initial logical relationships of the output value can be obtained.

[0079] That is, after converting the input and output values ​​into data of a preset data format, the input value of the preset data format contains a preset number of data bits. The output value of the preset data format contains a preset number of data bits. For example, when the preset data format is binary data format, after each input value is converted into binary data format, each input value contains its corresponding preset number of data bits. After the output value is converted into binary data format, the output value contains its corresponding preset number of data bits. For example, if the preset number of bits for the output value is c, after converting the output value into a binary number, the output value contains c data bits, namely x[0], x[1], ..., x[c-1]. The value of each data bit is 0 or 1. For example, if the output value x is 4 and the preset number of bits is 4, then the value of the output value x after being converted to binary data format is: 0100; at this time, the output value contains 4 data bits, the value of the first data bit x[0] is 0, the value of the second data bit x[1] is 0, the value of the third data bit x[2] is 1, and the value of the fourth data bit x[3] is 0. At this time, it is necessary to obtain the initial logical relationship between each data bit of the output value and each data bit of the input value according to the numerical relationship between each data bit of the output value and each data bit of the input value, and c initial logical relationships can be obtained.

[0080] The preset bit depth for input and output values ​​is set based on the actual accuracy requirements of the logic circuit design, specifying the number of bits in the preset data format for each input and output value. That is, how many bits of a preset data format are used to represent the input and output values. The preset bit depth for at least two input values ​​within the same group can be the same or different, depending on the actual needs. In the example above, each group of input values ​​contains input value 'a' and input value 'b'. The preset bit depth for input value 'a' and input value 'b' can be the same or different. Since different groups of input values ​​only change the numerical values ​​of the individual input values ​​within them, without changing the number of input values ​​within a group, the number of input values ​​contained in different groups is the same. In other words, different groups of input values ​​all contain two input values, input value 'a' and input value 'b', and the values ​​of input value 'a' and / or input value 'b' are different in different groups. Therefore, the preset bit depth for input value 'a' is the same across different groups, and similarly, the preset bit depth for input value 'b' is also the same across different groups.

[0081] It should be noted that the preset data format can be a binary data format, or other data formats that can represent the logical relationship between input and output values. This application does not impose any restrictions on this.

[0082] For example, assume that the preset bit length of each input value and output value is 8 bits. As shown in the example above, after obtaining Table 1, each input value and output value in Table 1 can be converted into binary data format to obtain the truth table information between the input values ​​and output values, as shown in Table 2 below. That is to say, according to Table 1 above, each value of a, b, and x in Table 1 is converted into an 8-bit binary number representation (for ease of explanation, x in the example only retains the integer part, and the decimal part is directly discarded), as shown in Table 2 below.

[0083] Table 2

[0084]

[0085] After obtaining the truth table information between the input and output values, the numerical relationship between the input and output values ​​in the truth table can be converted into a logical relationship to obtain the target logical relationship between the output and input values. For example, the relationship between the input and output values ​​in Table 2 above can be converted into a logical relationship by the following logical function expression. Since the expression is too long, F1() is used to summarize it below: X=F1(a[7],a[6],…,a[1],a[0],b[7],b[6],…,b[1],b[0]).

[0086] Furthermore, the initial logical relationship can be obtained based on the truth table information in the following manner. Since the truth table information in Table 2 is quite large, the simplified truth table information in Table 3 will be used in the following embodiment description.

[0087] Table 3

[0088]

[0089] The truth table information shown in Table 3 reveals the initial logical relationship between each data bit of the output value and each data bit in at least one set of input values. Specifically, the truth table information in Table 3 shows that the output value has two data bits: x[1] and x[0]. When the data bit x[1] of the output value is 1, it is related to the first set of input values ​​a and b, the fourth set of input values ​​a and b, the sixth set of input values ​​a and b, and the seventh set of input values ​​a and b. At this time, each set of input values ​​a and b in the four sets of input values ​​a and b can be used as a relational term in the logical relationship between x[1] and the input value. Therefore, x[1] can be represented by each data bit in the four sets of input values ​​a and b.

[0090] x[1]=a[1]'&a[0]'&b[0]'+a[1]'&a[0]&b[0]+a[1]&a[0]'&b[0]+a[1]&a[0]'&b[0]'; where a[1]' represents the inversion of a[1], a[0]' represents the inversion of a[0], and b[0]' represents the inversion of b[0].

[0091] Similarly, the expression for the data bit x[0] of the output value can be obtained as follows:

[0092] x[0]=a[1]&a[0]'&b[0]+a[1]&a[0]&b[0]'+a[1]&a[0]&b[0].

[0093] For ease of representation, we can use X = F1(a[1],a[0],b[0]) to uniformly express these two expressions.

[0094] After obtaining X = F1(a[1],a[0],b[0]), the logical relationship between the obtained output value and the input value can be directly determined as the initial logical relationship between the output value and the input value.

[0095] Step S103: Perform combination and simplification processing on the initial logical relationship between the output value and the input value, determine the common items in the initial logical relationship between the output value and the input value, identify the common items using preset identification information, and update the initial logical relationship using the identification information to obtain the target logical relationship between the output value and the input value.

[0096] In this embodiment, in the initial logical relationship between the output value and the input value obtained above, each data bit of the output value is represented by each data bit of each input value in at least one set of input values, and at least some different output values ​​are represented by each data bit of each input value in different sets of input values. Therefore, the initial logical relationship between each data bit of the output value is relatively complex. If a logic circuit is generated based on this initial logical relationship, the generated logic circuit will be relatively complex. To reduce the complexity of the logical relationship, the initial logical relationship between each data bit of the output value and the input value can be simplified by combining the data bits. This involves finding the common items in each initial logical relationship of the output value, marking the common items with preset identification information, updating the initial logical relationship using the preset identification information, representing the common items in the initial logical relationship with the corresponding preset identification information, and using the updated initial logical relationship as the target logical relationship between the output value and the input value.

[0097] As one possible implementation, the initial logical relationship between the output and input values ​​is simplified by combining different elements. This identifies the common elements in the initial logical relationship, identifies these common elements using pre-defined identifiers, and updates the initial logical relationship using these identifiers. The resulting target logical relationship between the output and input values ​​includes:

[0098] A preset simplification algorithm is obtained. Based on this algorithm, the initial logical relationship between each data bit of the output value and each data bit of the input value is simplified to obtain the simplified logical relationship between each data bit of the output value and each data bit of the input value. This simplified logical relationship between each data bit of the output value and each data bit of the input value is then combined and simplified to identify common terms in the simplified logical relationship. These common terms are then identified using preset identification information, and the logical relationship is updated using this information to obtain the target logical relationship between the output value and the input value.

[0099] In other words, based on the truth table information, we can first obtain the initial logical relationship between each data bit of the output value and each data bit of the input value. That is, based on the truth table information, we first obtain the representation of different data bits in the output value through the data bits of different input values. The initial logical relationship is quite complex and needs simplification. At this point, a preset simplification algorithm can be obtained, which can simplify the logical relationship. After obtaining the preset simplification algorithm, we can use it to simplify the logical relationship between each data bit of the output value and the input value, obtaining the simplified logical relationship.

[0100] It should be understood that the preset simplification algorithm is an algorithm that simplifies logical relationships in advance according to actual needs. As one possible implementation, the preset simplification algorithm includes QM simplification. That is, QM simplification is used to simplify the initial logical relationship between each data bit of the output value and the input value to obtain the simplified logical relationship. The preset simplification algorithm can also be other logical relationship simplification algorithms, such as Karnaugh map simplification, which is not limited in this application.

[0101] The initial logical relationship between the output and input values ​​obtained above is simplified using a preset simplification algorithm to obtain a simplified logical relationship, which is the simplified logical relationship between different data bits of the output value and the input value. The simplified logical relationships between different data bits of the output value and the input value are not entirely identical. There may be identical terms in the simplified logical relationships between different data bits of the output value and the input value, and these identical terms can be implemented using a single circuit when generating the logic circuit. Therefore, to reduce the complexity of the logic circuit, all identical terms can be found in the simplified logical relationships between different data bits of the output value and the input value. For example, simplifying the logical relationship between each data bit of the output value and the input value in Table 2 above yields the simplified logical relationship as follows:

[0102] x[7]=a[1]&a[3]&b[7]&b[2]'+a[5]&a[2]'&b[0];

[0103] x[6]=a[4]&a[3]&b[7]+a[5]&a[2]'&b[0]+a[6]&a[3]';

[0104] …

[0105] x[0]=a[1]&a[3]+a[5]&a[2]'&b[0]. Among them, a[1]&a[3] in the logical relationship between x[7] and the input value is the same as a[1]&a[3] in the logical relationship between x[0] and the input value. Therefore, when implementing the logic circuit, a[1]&a[3] in x[7] and x[0] can be implemented by the same circuit. Based on this, the simplified logical relationship between each data bit of the output value and each data bit in the input value can be combined and simplified to determine the same items in the simplified logical relationship between the output value and the input value. The same items are identified by the preset identification information, and the logical relationship is updated by the identification information to obtain the target logical relationship between the output value and the input value.

[0106] As one possible implementation, the simplified logical relationship between each data bit of the output value and each data bit of the input value is combined and simplified to determine the common items in the simplified logical relationship between the output value and the input value. These common items are then identified using preset identification information, and the logical relationship is updated using this identification information. The resulting target logical relationship between the output value and the input value includes:

[0107] Based on the preset number of bits of the preset data format of each input value in any set of input values, obtain the comparison logic term; based on the comparison logic term, detect whether there is a common term in the simplified logical relationship between different data bits of the output value and each data bit in the input value; if so, use the identification information to identify the common term, and use the identification information to update the simplified logical relationship to obtain the target logical relationship between the output value and the input value.

[0108] In this embodiment, since each data bit of the output value is represented by the data bits of the input value, comparison logic terms can be obtained by combining all possible combinations of the data bits of all input values ​​in each group. By comparing each comparison logic term with each item of each logical relation, it is possible to find out whether there are any identical items in each logical relation. Therefore, comparison logic terms can be obtained by combining all possible combinations of the data bits of the input value according to the truth table information. For each comparison logic term, it is detected whether there are at least two identical items in the logical relation between each data bit of the output value and the input value. If so, it is determined that there are identical items in the simplified logical relation between each data bit of the output value and each data bit of the input value. At this time, the identical items can be identified using preset identification information, and the identical items in the simplified logical relation between each data bit of the output value and each data bit of the input value can be replaced with the preset identification information to update the simplified logical relation.

[0109] The updated simplified logical relationship is used as the target logical relationship between the output value and the input value.

[0110] As one possible implementation, the comparison logic terms can be determined in the following way, i.e., as follows: Figure 2 As shown, based on the truth table information, the comparison logic items include:

[0111] Step S201: Determine m logic input groups based on the preset number of bits of the preset data format of each input value in any set of input values.

[0112] Each logical input group contains two logical input values ​​with opposite values. m is an integer greater than 1.

[0113] In this embodiment, to identify all identical items in the simplified logical relation, all possible combinations of each data bit of all input values ​​in each group of input values ​​can be obtained. Since the number of input values ​​contained in different groups of input values ​​and the number of data bits contained in each input value are the same, all possible combinations of each data bit of all input values ​​in different groups of input values ​​are the same. Therefore, it is only necessary to determine all possible combinations of each data bit of all input values ​​within a single group of input values.

[0114] To obtain all possible combinations of data bits in the input values, it is necessary to first determine the total number of data bits in any set of input values. This can be done by obtaining the preset bit length of the preset data format for each input value in the set. Based on the preset bit length of the preset data format for each input value, the total number of data bits in any set of input values ​​can be calculated. This means the sum of the preset bit lengths of the preset data format for each input value is defined as m. Each data bit in a set of input values ​​is defined as a logical input group, with different data bits belonging to different logical input groups, resulting in m logical input groups. In other words, m represents the total number of data bits in a set of input values.

[0115] Since each data bit can take either a value of 1 or 0, obtaining all possible combinations of different data bits for a set of input values ​​essentially means determining all possible combinations of different values ​​for each data bit within that set of input values. In this case, a data bit can be defined as a logical input group, and the different values ​​of a data bit can be used as the logical input values ​​for that group. Therefore, when m logical input groups are obtained, each logical input group contains two logical input values ​​with opposite values. That is, each logical input group contains two logical input values, one of which is 1, and the other is 0.

[0116] Step S202: Set n to a preset initial value.

[0117] The initial value is a integer greater than 1 and not greater than m.

[0118] It should be noted that the preset initial value is a pre-set minimum number of data bits that should be included in the comparison logic item.

[0119] As one possible implementation, the initial value is preset to 2.

[0120] Step S203: From the logic input values ​​contained in the m logic input groups, form a comparison logic term according to the n logic input values ​​from different logic input groups, and obtain... A comparison logic item.

[0121] In this embodiment, since it is necessary to obtain all possible combinations of different values ​​between the data bits of each input value in a set of input values, the comparison logic terms formed by n logical input values ​​from different logical input groups are obtained from the logical input values ​​contained in the m logical input groups. There are several comparison logic terms. Among them, This means selecting n data bits from m data bits, where each data bit has two possible values.

[0122] Step S204: Check if n is equal to m.

[0123] Since we need to obtain all possible combinations of different values ​​between each data bit of each input value in a set of input values, we check whether n is equal to m. If they are equal, it means that all possible combinations of different values ​​between each data bit of each input value in a set of input values ​​have been obtained. If they are not equal, it means that only all possible combinations of different values ​​between n data bits of each input value in a set of input values ​​have been obtained, and there are still all possible combinations of different values ​​between mn data bits that have not been obtained, so we need to continue to obtain them.

[0124] It should be noted that when n and m are found to be equal, it means that all comparison logic terms have been obtained, and the step of obtaining comparison logic terms can be ended. When n and m are found to be unequal, the following step S205 is executed.

[0125] Step S205: If they are not equal, update n to n+1 and re-execute the step. From the logical input values ​​contained in the m logical input groups, form a comparison logical term according to the n logical input values ​​from different logical input groups, and obtain... Each comparison logic term is used to check whether n is equal to m, until n is equal to m.

[0126] In this embodiment of the application, when it is detected that n and m are not equal, it means that not all possible combinations of different values ​​between the data bits of each input value in a set of input values ​​have been obtained. At this time, n is updated to n+1, and step S204 is re-executed until n and m are equal.

[0127] Through the above steps, with a preset initial value of 2, we can obtain all the data bits of all input values ​​contained in a set of input values, all comparison logic terms consisting of 2 data bits, all comparison logic terms consisting of 3 data bits, ..., all comparison logic terms consisting of m data bits. In other words, by changing the value of n, we can obtain all possible combinations of m data bits.

[0128] After obtaining all the comparison logic terms, we can check whether there are any identical terms in the simplified logical relationship between the different data bits of the output value and each data bit of the input value. If there are, we can use the identification information to identify the identical terms and update the simplified logical relationship to obtain the target logical relationship between the output value and the input value.

[0129] As one possible implementation, the specific detection can be achieved in the following way: based on the comparison logic terms, it is detected whether there are any identical terms in the simplified logical relationship between different data bits of the output value and each data bit in at least one set of input values; if so, the identical terms are identified using identification information, and the simplified logical relationship is updated using the identification information, resulting in the target logical relationship between the output value and the input value, including:

[0130] All acquired comparison logic items are identified as unlabeled comparison logic items. Among the unlabeled comparison logic items, the target comparison logic item is determined. The labeled comparison logic items are updated based on the target comparison logic item, and the unlabeled comparison logic items are also updated. Based on the labeled comparison logic items, it is checked whether the simplified logical relationships between different data bits of the output value and each data bit of the input value contain at least two items identical to the labeled comparison logic item. If so, the at least two items identical to the labeled comparison logic item are marked using identification information, and the simplified logical relationships are updated using the identification information. It is then checked whether unlabeled comparison logic items exist. If so, the steps to determine the target comparison logic item among the unlabeled comparison logic items are repeated until no unlabeled comparison logic items exist.

[0131] Among them, the target logic item is the comparison logic item with the most logical input values ​​contained in the unlabeled comparison logic item.

[0132] In other words, to obtain the simplest logic circuit, when checking whether there are identical terms in the simplified logical relationships between different data bits of the output value and each data bit of the input value based on the comparison logic terms, it is necessary to search in order of the number of data bits contained, from most to least. Therefore, among the comparison logic terms obtained above, it is necessary to first obtain the comparison logic term containing the most data bits. At this time, all the comparison logic terms obtained above can be identified as unlabeled comparison logic terms. Among the unlabeled comparison logic terms, the comparison logic term containing the most logical input values ​​is identified as the target comparison logic term. If there are multiple comparison logic terms containing the most data bits, one of them can be selected as the target comparison logic term. The target comparison logic term is then updated to a labeled comparison logic term, that is, among the unlabeled comparison logic terms, the comparison logic term containing the most data bits is updated to a labeled comparison logic term, and the labeled comparison logic term is deleted from the unlabeled comparison logic terms, and the unlabeled comparison logic terms are updated. After updating the marked comparison logic item, the marked logic comparison item can be used to search for at least two items that are identical to the marked logic comparison item in the simplified logical relationship between different data bits of the output value and each data bit of the input value. That is, it searches for at least two items whose contained data bits are the same as those contained in the marked comparison logic item. If so, it means that there are identical items in the simplified logical relationship between different data bits of the output value and each data bit of the input value. At this time, the at least two items that are identical to the marked comparison logic item can be regarded as identical items in the simplified logical relationship. The at least two items can be marked with identification information, and the identical items in the simplified logical relationship can be replaced with identification information to update the simplified logical relationship. If not, the comparison logic item is deleted. In this way, at least two items that are identical to the marked comparison logic item in the simplified logical relationship can be found. Check if there are still unmarked comparison logic items. If so, it means that there are still comparison logic items that have not been checked for identical items in the simplified logical relationship. At this time, the above steps are repeated to determine the target comparison logic item in the unmarked comparison logic items, until the step of checking if there are any unmarked comparison logic items, until there are no unmarked logic items. At this point, all identical items in the simplified logical relation can be identified, and then identified using the identification information. The simplified logical relation can then be updated to obtain the target logical relation.

[0133] For example, suppose the different simplified logical relations obtained are x[7]=a[1]&a[3]&b[7]&b[2]'+a[5]&a[2]'&b[0];

[0134] x[6]=a[4]&a[3]&b[7]+a[5]&a[2]'&b[0]+a[6]&a[3]';…x[0]=a[1]&a[3]+a[5]&a[2]'&b[0]. Assuming the marked logical comparison term is determined to be a[1]&a[3], we search for at least two terms that are the same as the marked logical term in different simplified logical relations. At this time, we can determine that there are two terms that are the same as the marked logical term in different simplified logical relations, that is, a[1]&a[3] appears twice in different simplified logical relations. At this point, the identifier information temp1 can be used to identify the same item, that is, temp1 = a[1] & a[3]. The identifier information is used to replace the same item in the simplified logical relation to obtain the target logical relation. At this point, the target logical relation is x[7] = temp1 & b[7] & b[2]' + a[5] & a[2]' & b[0]; x[6] = a[4] & a[3] & b[7] + a[5] & a[2]' & b[0] + a[6] & a[3]'; ... x[0] = temp1 + a[5] & a[2]' & b[0]; temp1 = a[1] & a[3].

[0135] The above steps can be used to obtain the target logical relationship between the output value and the input value.

[0136] Step S104: Generate a logic circuit based on the target logical relationship between the output value and the input value.

[0137] In this embodiment of the application, after obtaining the target logical relationship between the output value and the input value, the target logical relationship is the relationship between each device in the logic circuit. At this time, the logic circuit can be directly generated according to the target logical relationship between the output value and the input value.

[0138] As one possible implementation, generating logic circuits based on the target logical relationship between output and input values ​​includes: generating RTL code based on the target logical relationship between output and input values.

[0139] In other words, the logic circuit is described using RTL code, so RTL code can be generated based on the target logic relationship. At this point, the RTL code can be generated line by line, based on the target logic relationship between the output and input values, resulting in an RTL file. The logic circuit is then generated from the RTL file.

[0140] In this embodiment, when implementing the mathematical function operation, the input value of the mathematical function can be obtained and its output value can be calculated. Based on the input and output values, the initial logical relationship between the output and input values ​​is obtained. This initial logical relationship is then simplified by combination, identifying common terms within the initial logical relationship. These common terms are then identified using preset identification information. The initial logical relationship is updated based on the preset identification information to obtain the target logical relationship between the output and input values. Based on this target logical relationship, a logic circuit is generated. In other words, in this embodiment, a logic circuit can be automatically generated directly from the input and output values ​​calculated from the data. This eliminates the need for users to design logic circuits capable of mathematical calculations on fixed input values ​​using iterative approximation algorithms, reducing the design time for logic circuits, especially complex mathematical logic circuits, and improving efficiency.

[0141] See Figure 3 This application provides an automatic logic circuit generation device. For example... Figure 3 As shown, the automatic generation device includes:

[0142] The acquisition unit 301 is used to acquire multiple sets of input values ​​and the corresponding output value for each set of input values.

[0143] Each set of input values ​​includes at least one input value. The output value is calculated based on the input values ​​using a preset mathematical function.

[0144] The acquisition unit 301 is also used to acquire the initial logical relationship between the output value and the input value based on multiple sets of input values ​​and the output value corresponding to each set of input values.

[0145] The processing unit 302 is used to perform combination simplification processing on the initial logical relationship between the output value and the input value, determine the same items in the initial logical relationship between the output value and the input value, identify the same items using preset identification information, and update the initial logical relationship using the identification information to obtain the target logical relationship between the output value and the input value.

[0146] As one possible implementation, processing unit 302 is specifically used to obtain the preset number of bits of the preset data format for each input value in any set of input values, and the preset number of bits of the preset data format for the output value. Based on the preset number of bits of the preset data format for each input value in any set of input values, and the preset number of bits of the preset data format for the output value, each set of input values ​​and the corresponding output value are converted according to the preset data format to obtain truth table information between the input and output values. Based on the truth table information, the initial logical relationship between the output and input values ​​is obtained.

[0147] The input value in the preset data format contains a preset number of data bits; the output value in the preset data format also contains a preset number of data bits. The initial logical relationship between the data bits of different output values ​​and the data bits of the input values ​​is not entirely the same.

[0148] As one possible implementation, the processing unit 302 is specifically used to obtain a preset simplification algorithm, and to perform logical simplification on the logical relationship between each data bit of the output value and each data bit of the input value according to the preset simplification algorithm, so as to obtain the simplified logical relationship between each data bit of the output value and each data bit of the input value; to perform combined simplification processing on the simplified logical relationship between each data bit of the output value and each data bit of the input value, to determine the same items in the simplified logical relationship between the output value and the input value, to identify the same items using preset identification information, and to update the logical relationship using the identification information, so as to obtain the target logical relationship between the output value and the input value.

[0149] As one possible implementation, the processing unit 302 is specifically used to obtain a comparison logic term based on the preset number of bits of the preset data format of each input value in any set of input values; based on the comparison logic term, detect whether there is a common term in the simplified logical relationship between different data bits of the output value and each data bit in the input value; if so, use preset identification information to identify the common term, and use the identification information to update the simplified logical relationship to obtain the target logical relationship between the output value and the input value.

[0150] As one possible implementation, processing unit 302 is specifically used to determine m logical input groups based on the preset number of bits of the preset data format of each input value in any set of input values. n is set to a preset initial value. Among the logical input values ​​contained in the m logical input groups, a comparison logical term is formed according to the n logical input values ​​from different logical input groups, resulting in... A comparison logic term is generated; it checks if n is equal to m; if not, n is updated to n+1, and the comparison logic term is generated again from the logic input values ​​contained in the m logic input groups, according to the n logic input values ​​from different logic input groups. Each comparison logic term is used to check whether n is equal to m, until n is equal to m.

[0151] Each logical input group contains two logical input values ​​with opposite values; m is an integer greater than 1; the default initial value is an integer greater than 1 and not greater than m.

[0152] As one possible implementation, processing unit 302 is specifically configured to: determine all acquired comparison logic items as unmarked comparison logic items; determine the target comparison logic item among the unmarked comparison logic items; update the marked comparison logic items and update the unmarked comparison logic items according to the target comparison logic item; search, according to the marked comparison logic item, whether there are at least two items in the simplified logical relationship between different data bits of the output value and each data bit of the input value that are the same as the marked comparison logic item; if so, mark the at least two items that are the same as the marked comparison logic item using identification information, and update the simplified logical relationship using the identification information; detect whether there are unmarked comparison logic items; if so, repeat the step of determining the target comparison logic item among the unmarked comparison logic items until the step of detecting whether there are unmarked comparison logic items is no longer present.

[0153] Among them, the target logic item is the comparison logic item with the most logical input values ​​contained in the unlabeled comparison logic item.

[0154] As one possible implementation, the pre-defined simplification algorithm includes: Quine-McLusky QM simplification.

[0155] The processing unit 302 is also used to generate logic circuits based on the target logical relationship between the output value and the input value.

[0156] As one possible implementation, the processing unit 302 is specifically used to generate register transfer level RTL code based on the target logical relationship between the output value and the input value.

[0157] Corresponding to the above embodiments, this application also provides an electronic device. Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. The electronic device 400 may include a processor 401, a memory 402, and a communication unit 403. These components communicate through one or more buses. Those skilled in the art will understand that the structure of the server shown in the figure does not constitute a limitation on the embodiment of the present invention. It may be a bus topology or a star topology, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0158] The communication unit 403 is used to establish a communication channel, enabling the storage device to communicate with other devices. It can receive user data sent by other devices or send user data to other devices.

[0159] The processor 401 serves as the control center of the storage device, connecting various parts of the electronic device via various interfaces and lines. It executes software programs and / or modules stored in the memory 402, and calls data stored in the memory to perform various functions of the electronic device and / or process data. The processor can be composed of integrated circuits (ICs), such as a single packaged IC or multiple packaged ICs with the same or different functions connected together. For example, the processor 401 may consist only of a central processing unit (CPU). In this embodiment of the invention, the CPU may have a single processing core or include multiple processing cores.

[0160] The memory 402 is used to store the execution instructions of the processor 401. The memory 402 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk.

[0161] When the execution instructions in memory 402 are executed by processor 401, the electronic device 400 is able to perform operations. Figure 1 Some or all of the steps in the illustrated embodiments.

[0162] In a specific implementation, the present invention also provides a computer storage medium, wherein the computer storage medium may store a program, which, when executed, may include some or all of the steps of the various embodiments of the automatic generation method of logic circuits provided by the present invention. The storage medium may be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0163] Those skilled in the art will clearly understand that the techniques in the embodiments of the present invention can be implemented using software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solutions in the embodiments of the present invention, or the parts that contribute to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments or certain parts of the embodiments of the present invention.

[0164] The same or similar parts between the various embodiments in this specification can be referred to mutually. In particular, the device embodiments and terminal embodiments are basically similar to the method embodiments, so the description is relatively simple, and the relevant parts can be referred to the description in the method embodiments.

Claims

1. A method for automatically generating logic circuits, characterized in that, include: Obtain multiple sets of input values ​​and the corresponding output value for each set of input values; Based on the multiple sets of input values ​​and the output value corresponding to each set of input values, obtain the initial logical relationship between the output value and the input value; The initial logical relationship between the output value and the input value is combined and simplified to determine the common items in the initial logical relationship between the output value and the input value. The common items are identified using preset identification information, and the initial logical relationship is updated using the identification information to obtain the target logical relationship between the output value and the input value. Based on the target logical relationship between the output value and the input value, generate the logic circuit; The process of combining and simplifying the initial logical relationship between the output and input values, identifying the common items in the initial logical relationship, identifying the common items using preset identification information, and updating the initial logical relationship using the identification information to obtain the target logical relationship between the output and input values ​​includes: A comparison logic term is obtained based on the preset number of bits of the preset data format of each input value in any set of input values; wherein, the comparison logic term is obtained by performing all possible combinations of the data bits of all input values ​​in each set; Based on the comparison logic term, it is detected whether there is a common term in the simplified logical relationship between different data bits of the output value and each data bit of the input value; if so, the common term is identified using preset identification information, and the simplified logical relationship is updated using the identification information to obtain the target logical relationship between the output value and the input value; wherein, the simplified logical relationship between each data bit of the output value and each data bit of the input value is obtained by logically simplifying the logical relationship between each data bit of the output value and each data bit of the input value according to a preset simplification algorithm.

2. The method according to claim 1, characterized in that, The step of obtaining the initial logical relationship between the input values ​​and the output values ​​based on the multiple sets of input values ​​and the corresponding output values ​​of each set of input values ​​includes: Get the preset number of bits for the preset data format of each input value in any set of input values, and the preset number of bits for the preset data format of the output value; Based on the preset number of bits of the preset data format of each input value in any set of input values ​​and the preset number of bits of the preset data format of the output value, each set of input values ​​and the corresponding output value are converted according to the preset data format to obtain the truth table information between the input values ​​and the output values; wherein, the input value of the preset data format contains its corresponding preset number of data bits; the output value of the preset data format contains its corresponding preset number of data bits; Based on the truth table information, the initial logical relationship between the output value and the input value is obtained; wherein, the initial logical relationship between the data bits of different output values ​​and the data bits of the input values ​​is not exactly the same.

3. The method according to claim 1, characterized in that, The step of obtaining the comparison logic item based on the preset number of bits of the preset data format of each input value in any set of input values ​​includes: Based on the preset number of bits of the preset data format of each input value in any set of input values, determine m logical input groups; each logical input group contains two logical input values ​​with opposite values; where m is an integer greater than 1; Set n to a preset initial value; the preset initial value is an integer greater than 1 and not greater than m; From the logical input values ​​contained in the m logical input groups, a comparison logical term is formed according to the n logical input values ​​from different logical input groups, resulting in... One comparison logic item; Check if n is equal to m; If they are not equal, then n is updated to n+1, and the step described above is repeated: among the logical input values ​​contained in the m logical input groups, a comparison logical term is formed according to the n logical input values ​​from different logical input groups, resulting in... Each comparison logic term is used to check whether n is equal to m, until n is equal to m.

4. The method according to claim 1, characterized in that, Based on the comparison logic term, detect whether there is a common term in the simplified logical relationship between different data bits of the output value and each data bit in at least one set of input values; If they exist, the identical items are identified using the identification information, and the simplified logical relationship is updated using the identification information. The target logical relationship between the output value and the input value includes: All acquired comparison logic items are identified as unmarked comparison logic items; Among the unlabeled comparison logic items, a target comparison logic item is determined; the target comparison logic item is the comparison logic item with the most logical input values ​​contained in the unlabeled comparison logic items. Update the marked comparison logic item according to the target comparison logic item, and update the unmarked comparison logic item; Based on the marked comparison logic term, check whether the simplified logical relationship between different data bits of the output value and each data bit of the input value contains at least two items that are the same as the marked comparison logic term; If so, at least two items that are the same as the marked comparison logical item are marked using the identification information, and the simplified logical relationship is updated using the identification information. Check for the presence of unlabeled comparison logic items; If it exists, the step of determining the target comparison logic item in the unlabeled comparison logic item is repeated until the step of checking whether there is an unlabeled comparison logic item is found, until there is no unlabeled comparison logic item.

5. The method according to claim 1, characterized in that, The preset simplification algorithm includes: Quinn-McLusky QM simplification.

6. The method according to any one of claims 1-5, characterized in that, The step of generating the logic circuit based on the target logical relationship between the output value and the input value includes: Based on the target logical relationship between the output and input values, register transfer level RTL code is generated.

7. An automatic logic circuit generation device, characterized in that, include: The acquisition unit is used to acquire multiple sets of input values ​​and the corresponding output value for each set of input values; The acquisition unit is further configured to acquire the initial logical relationship between the output value and the input value based on the multiple sets of input values ​​and the output value corresponding to each set of input values; The processing unit is used to perform combination and simplification processing on the initial logical relationship between the output value and the input value, determine the same items in the initial logical relationship between the output value and the input value, identify the same items using preset identification information, and update the initial logical relationship using the identification information to obtain the target logical relationship between the output value and the input value. The processing unit is also configured to generate a logic circuit based on the target logical relationship between the output value and the input value; The processing unit is specifically configured to obtain a comparison logic term based on the preset number of bits of the preset data format of each input value in any set of input values; wherein, the comparison logic term is obtained by performing all possible combinations of the data bits of all input values ​​in each set; Based on the comparison logic term, it is detected whether there is a common term in the simplified logical relationship between different data bits of the output value and each data bit of the input value; if so, the common term is identified using preset identification information, and the simplified logical relationship is updated using the identification information to obtain the target logical relationship between the output value and the input value; wherein, the simplified logical relationship between each data bit of the output value and each data bit of the input value is obtained by logically simplifying the logical relationship between each data bit of the output value and each data bit of the input value according to a preset simplification algorithm.

8. An electronic device, characterized in that, It includes a memory for storing computer program instructions and a processor for executing the program instructions, wherein when the computer program instructions are executed by the processor, the electronic device is triggered to perform the method according to any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored program, wherein, when the program is executed, it controls the device on which the computer-readable storage medium is located to perform the method according to any one of claims 1-6.

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