Display panel and display device

Abstract

The embodiment of the present application provides a display panel and a display device, wherein the display panel includes a first type of pixel circuit, in which the first electrode of the first transistor is electrically connected to the second electrode of the driving transistor, the first electrode of the second transistor is electrically connected to the gate of the driving transistor, and the second electrode of the first transistor and the second electrode of the second transistor include a first node between them; the first end of the first sub-selection module is electrically connected to the gate of the driving transistor, the second end is electrically connected to the first end of the second sub-selection module, and the second end of the second sub-selection module is electrically connected to the first node; the time period during which the first sub-selection module is turned on is before the time period during which the second sub-selection module is turned on. The present application can help reduce the potential difference between the first node and the gate of the driving transistor while avoiding the first node from affecting the gate potential of the driving transistor through the first sub-selection module and the second sub-selection module, thereby improving the problem of leakage from the first node to the gate of the driving transistor.

Description

[Technical field]

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. [Background technology]

[0002] Organic light-emitting diode (OLED) display panels have the advantages of low power consumption, self-luminescence, wide viewing angle, wide temperature characteristics and fast response speed, and are widely used in the market. Among them, the pixel circuit used to control the light emission of the light-emitting device is the core technology content of the OLED display panel and has important research significance.

[0003] The pixel circuit generally includes a driving transistor, which can generate a driving current for driving the light-emitting device according to the voltage of its gate. However, in the prior art, the gate voltage of the driving transistor has a leakage problem, which causes the gate voltage of the driving transistor to be unstable, affecting the brightness of the light-emitting device and further affecting the display effect.

[0004]

Application Contents

[0005] In view of this, embodiments of the present application provide a display panel and a display device to solve the above problems.

[0006] In a first aspect, an embodiment of the present application provides a display panel, which includes a plurality of pixel circuits and a plurality of light-emitting modules, wherein the pixel circuit includes a driving transistor, a first transistor, and a second transistor, wherein the driving transistor is used to provide a light-emitting driving current for the light-emitting module; a first electrode of the first transistor is electrically connected to a second electrode of the driving transistor, and a first electrode of the second transistor is electrically connected to a gate electrode of the driving transistor; a first node is included between the second electrode of the first transistor and the second electrode of the second transistor; the plurality of pixel circuits include a first type of pixel circuit, wherein the first type of pixel circuit includes a first selection module, wherein the first selection module includes a first sub-selection module and a second sub-selection module, wherein a first end of the first sub-selection module is electrically connected to a gate electrode of the driving transistor, and a second end is electrically connected to a second node, and a first end of the second sub-selection module is electrically connected to a second node, and a second end is electrically connected to the first node; the first selection module is used to adjust the potential of the first node; wherein a period during which the first sub-selection module is turned on is before a period during which the second sub-selection module is turned on.

[0007] In an implementation of the first aspect, the first sub-selection module includes a third transistor, a first electrode of the third transistor is electrically connected to the gate of the driving transistor, and a second electrode is electrically connected to the second node; the second sub-selection module includes a fourth transistor, a first electrode of the fourth transistor is electrically connected to the first node, and a second electrode is electrically connected to the second node.

[0008] In an implementation manner of the first aspect, the first type of pixel circuit includes a first capacitor, one plate of the first capacitor is electrically connected to the second node, and the other plate of the first capacitor is electrically connected to the fixed potential signal line.

[0009] In an implementation manner of the first aspect, the fixed potential signal line is electrically connected to the first power supply voltage signal line, and the first power supply voltage signal line is electrically connected to the light emitting module.

[0010] In an implementation of the first aspect, the first type of pixel circuit also includes a data voltage writing module, an input end of the data voltage writing module is electrically connected to the data signal line, and an output end is electrically connected to the first electrode of the driving transistor; the working process of the first type of pixel circuit includes a data writing stage, in which the data voltage writing module and the first transistor and the second transistor are turned on; the first selection module is turned on after the data writing stage.

[0011] In an implementation of the first aspect, the operation process of the first type of pixel circuit further includes a light emitting phase performed after the data writing phase; and the first gating module is turned on during the light emitting phase.

[0012] In an implementation of the first aspect, the operation process of the first type of pixel circuit further includes an adjustment phase and a light emitting phase which are sequentially performed after the data writing phase; and the first gating module is turned on in the adjustment phase.

[0013] In an implementation of the first aspect, the data voltage writing module includes a fifth transistor, a first electrode of the fifth transistor is electrically connected to the data signal line, a second electrode is electrically connected to the first electrode of the driving transistor, and a gate is electrically connected to the first scan line; the gate of the first transistor and the gate of the second transistor are electrically connected to the first scan line; the signal transmitted by the first scan line controls the switching states of the first transistor, the second transistor and the fifth transistor to be the same.

[0014] In an implementation manner of the first aspect, a gate of the third transistor is electrically connected to the second scan line, and a gate of the fourth transistor is electrically connected to the third scan line.

[0015] In an implementation of the first aspect, the first type of pixel circuit also includes a power supply voltage writing module and a light-emitting control module; the input end of the power supply voltage writing module is electrically connected to the second power supply voltage signal line, the output end is electrically connected to the first pole of the driving transistor, and the control end is electrically connected to the light-emitting control signal line; the input end of the light-emitting control module is electrically connected to the second pole of the driving transistor, the output end is electrically connected to the first pole of the light-emitting module, and the control end is electrically connected to the light-emitting control signal line; the third scanning line is electrically connected to the light-emitting control signal line, and the signal transmitted by the light-emitting control signal line controls the switching states of the power supply voltage writing module, the light-emitting control module and the fourth transistor to be the same.

[0016] In an implementation of the first aspect, the display panel includes multiple rows of first-class pixel circuits, the second scan line electrically connected to the first-class pixel circuit in the i-th row is electrically connected to the first scan line electrically connected to the first-class pixel circuit in the i+1-th row, and the third scan line electrically connected to the first-class pixel circuit in the i-th row is electrically connected to the first scan line electrically connected to the first-class pixel circuit in the i+2-th row, i≥1.

[0017] In an implementation of the first aspect, the first sub-selection module is turned on for a duration not less than the data voltage writing module is turned on, and the second sub-selection module is turned on for a duration not less than the data voltage writing module is turned on.

[0018] In an implementation of the first aspect, a duration during which the first sub-gating module is turned on is not less than a duration during which the second sub-gating module is turned on.

[0019] In an implementation of the first aspect, a plurality of pixel circuits include a second type of pixel circuit, the second type of pixel circuit includes a second selection module, a first end of the second selection module is electrically connected to the first node, and a second end is electrically connected to the second node in the first type of pixel circuit; wherein a switching state of the second selection module is the same as a switching state of a second sub-selection module in the first type of pixel circuit.

[0020] In a second aspect, an embodiment of the present application provides a display device, comprising a display panel provided in the first aspect.

[0021] In the embodiment of the present application, by setting a first selection module between the first node and the gate of the driving transistor and adjusting the potential of the first node by using the gate potential of the driving transistor, the potential difference between the first node and the gate of the driving transistor can be reduced, which is beneficial to improve the problem of leakage from the first node to the gate of the driving transistor, stabilize the gate potential of the driving transistor, and further help avoid large changes in the brightness of the display frame and improve the display effect of the display panel.

[0022] In addition, in the first selection module, the time period in which the first sub-selection module is turned on is set before the time period in which the second sub-selection module is turned on, so that the gate potential of the driving transistor can be first written into the second node through the first sub-selection module, and then written into the first node through the second sub-selection module to adjust the potential of the first node, which can prevent the potential of the first node from affecting the gate potential of the driving transistor through the first selection module, thereby facilitating further ensuring the stability and accuracy of the gate potential of the driving transistor and further improving the display effect of the display panel.

Brief Description of the Drawings

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 A schematic diagram of a display panel provided in an embodiment of the present application;

[0025] Figure 2 A schematic diagram of a first type of pixel circuit provided in an embodiment of the present application;

[0026] Figure 3 for Figure 2 A schematic diagram of a first type of pixel circuit is shown;

[0027] Figure 4 for Figure 3 A timing diagram of the first type of pixel circuit shown;

[0028] Figure 5 A schematic diagram of another first-type pixel circuit provided in an embodiment of the present application;

[0029] Figure 6 for Figure 3 Another timing diagram of the first type of pixel circuit shown;

[0030] Figure 7 for Figure 3 Another timing diagram of the first type of pixel circuit shown;

[0031] Figure 8 for Figure 3 Another timing diagram of the first type of pixel circuit shown;

[0032] Fig. 9 for Figure 3 Another timing diagram of the first type of pixel circuit shown;

[0033] Fig.10 A schematic diagram of another first-type pixel circuit provided in an embodiment of the present application;

[0034] Fig.11 for Figure 1 A connection diagram of the first type of pixel circuits in three adjacent rows;

[0035] Fig.12 A schematic diagram of another display panel provided in an embodiment of the present application;

[0036] Fig.13 A schematic diagram of connecting a second type pixel circuit and a first type pixel circuit provided in an embodiment of the present application;

[0037] Fig.14 A schematic diagram of a display device provided in an embodiment of the present application. [Specific implementation method]

[0038] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0039] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0040] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0041] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0042] In the description of this specification, it is necessary to understand that the words such as "substantially", "approximately", "approximately", "about", "roughly", "substantially" and the like described in the claims and embodiments of the present application refer to what can be generally recognized within a reasonable process operation range or tolerance range, rather than an exact value.

[0043] It should be understood that, although the terms first, second, etc. may be used to describe transistors, nodes, directions, etc. in the embodiments of the present application, these transistors, nodes, directions, etc. should not be limited to these terms. These terms are only used to distinguish transistors, nodes, directions, etc. from each other. For example, without departing from the scope of the embodiments of the present application, the first node may also be referred to as the second node, and similarly, the second node may also be referred to as the first node.

[0044] The applicant in this case has provided a solution to the problems existing in the prior art through careful and in-depth research.

[0045] Figure 1 A schematic diagram of a display panel provided in an embodiment of the present application, Figure 2 A schematic diagram of a first type of pixel circuit provided in an embodiment of the present application, Figure 3for Figure 2 A schematic diagram of a first type of pixel circuit is shown.

[0046] The present application embodiment provides a display panel 01, such as Figure 1 As shown, the display panel 01 includes a plurality of pixel circuits 11 and a light emitting module 12. The pixel circuits 11 are electrically connected to the light emitting module 12 to drive the light emitting module 12 to emit light. In the display panel 01, the pixel circuits 11 may be arranged in an array along a first direction X and a second direction Y. The first direction X may be a row direction of the display panel 01, and the second direction Y may be a column direction of the display panel 01.

[0047] like Figure 2 As shown, the pixel circuit 11 includes a driving transistor Td, a first transistor T1 and a second transistor T2. The driving transistor Td is used to provide a light-emitting driving current for the light-emitting module 12. The first electrode of the first transistor T1 is electrically connected to the second electrode of the driving transistor Td. The first electrode of the second transistor T2 is electrically connected to the gate of the driving transistor Td. The second electrode of the first transistor T1 and the second electrode of the second transistor T2 include a first node N1. The first transistor T1 and the second transistor T2 are used to compensate the threshold voltage of the driving transistor Td to the gate of the driving transistor Td.

[0048] Specifically, Figure 2 and Figure 3 As shown, the second electrode of the first transistor T1 and the second electrode of the second transistor T2 are electrically connected at the first node N1. The gate of the first transistor T1 and the gate of the second transistor T2 are both electrically connected to the first scan line S1, and the signal transmitted by the first scan line S1 controls the switching states of the first transistor T1 and the second transistor T2 to be the same.

[0049] When the first scan line S1 transmits a valid signal to control the first transistor T1 and the second transistor T2 to turn on, the threshold voltage of the driving transistor Td can be compensated to the gate of the driving transistor Td through the turned-on first transistor T1 and the second transistor T2.

[0050] Please combine Figure 1 and Figure 2 The multiple pixel circuits 11 include a first type pixel circuit 111, the first type pixel circuit 111 includes the driving transistor Td, the first transistor T1 and the second transistor T2 included in the above-mentioned pixel circuit 11, and the first type pixel circuit 111 also includes a first selection module 20, that is, the pixel circuit 11 including the first selection module 20 can be the first type pixel circuit 111.

[0051] The first selection module 20 includes a first sub-selection module 21 and a second sub-selection module 22. The first end of the first sub-selection module 21 is electrically connected to the gate of the driving transistor Td, and the second end is electrically connected to the second node N2. The first end of the second sub-selection module 22 is electrically connected to the second node N2, and the second end is electrically connected to the first node N1. The first selection module 20 is used to adjust the potential of the first node N1.

[0052] Specifically, when the first gating module 20 is turned on, the first node N1 is connected to the gate of the driving transistor Td, and the first gating module 20 can use the gate potential of the driving transistor Td to adjust the potential of the first node N1, thereby reducing the potential difference between the first node N1 and the gate of the driving transistor Td. The first end of the first sub-gating module 21 and the gate of the driving transistor Td can be electrically connected at the third node N3, and the potential of the third node N3 is the same as the gate potential of the driving transistor Td.

[0053] In the first gating module 20 , the period during which the first sub-gating module 21 is turned on is before the period during which the second sub-gating module 22 is turned on.

[0054] That is, the periods during which the first sub-gating module 21 and the second sub-gating module 22 are turned on do not overlap, and the first sub-gating module 21 is turned on first and the second sub-gating module 22 is turned on later.

[0055] It should be noted that, in the embodiment of the present application, the non-overlapping time periods of the first sub-gating module 21 and the second sub-gating module 22 include the situation where the closing time of the first sub-gating module 21 is the same as the opening time of the second sub-gating module 22.

[0056] It is understandable that, due to the working characteristics of the transistor, even though the transistor is in the off state, when there is a potential difference between the first electrode and the second electrode of the transistor, the transistor will have leakage, and the greater the potential difference between the first electrode and the second electrode of the transistor, the more obvious the leakage of the transistor. The first electrode and the second electrode of the transistor may be the source and the drain of the transistor.

[0057] In the prior art, after the first transistor T1 and the second transistor T2 capture the threshold voltage of the driving transistor Td to the gate of the driving transistor Td, due to the coupling effect of the signal transmitted by the first scan line S1, the potential of the first node N1 is usually greater than the gate potential of the driving transistor Td, that is, the second electrode potential of the second transistor T2 is greater than its first electrode potential. Although the first transistor T1 and the second transistor T2 are both in the off state at this time, the first node N1 will still leak to the gate of the driving transistor Td, which causes the gate potential of the driving transistor Td to be unstable when generating the light-emitting driving current, thereby causing the light-emitting driving current generated according to its gate potential to be unstable, affecting the brightness of the light-emitting module 12. Especially when the display panel 01 is displayed at a low frequency, the screen flickers very obviously.

[0058] In the embodiment of the present application, by setting a first selection module 20 between the first node N1 and the gate of the driving transistor Td, and using the gate potential of the driving transistor Td to adjust the potential of the first node N1, the potential difference between the first node N1 and the gate of the driving transistor Td can be reduced, which is beneficial to improve the problem of leakage from the first node N1 to the gate of the driving transistor Td, stabilize the gate potential of the driving transistor Td, and further help avoid large changes in the brightness of the display frame, thereby improving the display effect of the display panel 01.

[0059] In addition, in the first selection module 20, the time period in which the first sub-selection module 21 is turned on is set before the time period in which the second sub-selection module 22 is turned on, so that the gate potential of the driving transistor Td can be first written into the second node N2 through the first sub-selection module 21, and then written into the first node N1 through the second sub-selection module 22 to adjust the potential of the first node N1, which can avoid the potential of the first node N1 from affecting the gate potential of the driving transistor Td through the first selection module 20, thereby facilitating further ensuring the stability and accuracy of the gate potential of the driving transistor Td, and further improving the display effect of the display panel 01.

[0060] Figure 4 for Figure 3 A timing diagram of the first type of pixel circuit is shown.

[0061] In one embodiment of the present application, Figure 3 As shown, the first sub-selection module 21 includes a third transistor T3, a first electrode of the third transistor T3 is electrically connected to the gate of the driving transistor Td, and a second electrode is electrically connected to the second node N2. The second sub-selection module 22 includes a fourth transistor T4, a first electrode of the fourth transistor T4 is electrically connected to the first node N1, and a second electrode is electrically connected to the second node N2.

[0062] That is, each of the first sub-selection module 21 and the second sub-selection module 22 may include only one transistor to simplify the structure of the first type pixel circuit 111 .

[0063] Furthermore, please combine Figure 3 and Figure 4 , the gate of the third transistor T3 is electrically connected to the second scan line S2, and the gate of the fourth transistor T4 is electrically connected to the third scan line S3. The period during which the second scan line S2 transmits a valid signal (such as a low level) to control the third transistor T3 to turn on is before the period during which the third scan line S3 transmits a valid signal (such as a low level) to control the fourth transistor T4 to turn on.

[0064] Figure 5 A schematic diagram of another first-type pixel circuit provided in an embodiment of the present application.

[0065] The inventors of the present application consider that after the gate potential of the driving transistor Td is written into the second node N2, as time passes, the potential of the second node N2 will usually be lower than the gate potential of the driving transistor Td. In the process of connecting the second node N2 to the first node N1 to adjust the potential of the first node N1, there may still be a large potential difference between the first node N1 and the gate potential of the driving transistor Td. The first node N1 may still leak to the gate of the driving transistor Td, affecting the stability of the gate potential of the driving transistor Td. Therefore, the inventors of the present application provide a solution that can further reduce the potential difference between the first node N1 and the gate potential of the driving transistor Td without affecting the gate potential of the driving transistor Td through the first selection module 20.

[0066] In one embodiment of the present application, Figure 5 As shown, the first type pixel circuit 111 includes a first capacitor C1, one plate of the first capacitor C1 is electrically connected to the second node N2, and the other plate of the first capacitor C1 is electrically connected to the fixed potential signal line CL1.

[0067] Alternatively, if Figure 5 As shown, the fixed potential signal line CL1 is electrically connected to the first power voltage signal line PVEE, and the first power voltage signal line PVEE is electrically connected to the light emitting module 12. Of course, in some other embodiments, the fixed potential signal line CL1 may also be electrically connected to the second power voltage signal line PVDD.

[0068] In the embodiment of the present application, the first capacitor C1 can effectively stabilize the potential of the second node N2, which is beneficial to completely preserve the gate potential of the driving transistor Td in the second node N2, that is, it is beneficial to achieve that the potential of the second node N2 is similar to the gate potential of the driving transistor Td, so that after the second node N2 and the first node N1 are turned on, it is beneficial to further reduce the potential between the first node N1 and the gate of the driving transistor Td, thereby ensuring that the gate potential of the driving transistor Td remains stable, which is beneficial to improving the display effect of the display panel 01.

[0069] Please continue to refer to Figure 2 , Figure 3 In one embodiment of the present application, the first type pixel circuit 111 also includes a data voltage writing module 30, the input end of the data voltage writing module 30 is electrically connected to the data signal line DL1, and the output end is electrically connected to the first electrode of the driving transistor Td. The data voltage writing module 30 is used to transmit the data voltage Vdata transmitted by the data signal line DL1 to the first electrode of the driving transistor Td.

[0070] The working process of the first type pixel circuit 111 includes a data writing phase E1. In the data writing phase E1, the data voltage writing module 30 and the first transistor T1 and the second transistor T2 are turned on.

[0071] The first gating module 20 is turned on after the data writing phase E1.

[0072] Specifically, Figure 3 As shown, the control end of the data voltage writing module 30 is electrically connected to the first scan line S1, and the signal transmitted by the first scan line S1 controls the data voltage writing module 30 and the switching states of the first transistor T1 and the second transistor T2 to be the same.

[0073] Further, the data voltage writing module 30 includes a fifth transistor T5, a first electrode of the fifth transistor T5 is electrically connected to the data signal line DL1, a second electrode is electrically connected to the first electrode of the driving transistor Td, and a gate is electrically connected to the first scanning line S1. The gate of the first transistor T1 and the gate of the second transistor T2 are both electrically connected to the first scanning line S1, and the signal transmitted by the first scanning line S1 controls the switching states of the first transistor T1, the second transistor T2 and the fifth transistor T5 to be the same.

[0074] In the data writing phase E1 , the fifth transistor T5 , the first transistor T1 , and the second transistor T2 are turned on, the data voltage Vdata is transmitted to the gate of the driving transistor Td, and the threshold voltage of the driving transistor Td is compensated to the gate of the driving transistor Td.

[0075] like Figure 2As shown, the first type pixel circuit 111 also includes a first reset module 40, the input end of the first reset module 40 is electrically connected to the first reset signal line SL1, and the output end is electrically connected to the gate of the driving transistor Td. The first reset module 40 is used to transmit the first reset voltage Vref1 transmitted by the first reset signal line SL1 to the gate of the driving transistor Td.

[0076] Alternatively, if Figure 3 As shown, the first reset module 40 includes a sixth transistor T6 and a seventh transistor T7, a first electrode of the sixth transistor T6 is electrically connected to the first reset signal line SL1, a second electrode is electrically connected to the first electrode of the seventh transistor T7, and a second electrode of the seventh transistor T7 is electrically connected to the gate of the driving transistor Td; the gate of the sixth transistor T6 and the gate of the seventh transistor T7 are both electrically connected to the fourth scan line S4, and the signal transmitted by the fourth scan line S4 controls the switching states of the sixth transistor T6 and the seventh transistor T7 to be the same.

[0077] Combination Figure 4 As shown, the working process of the first type pixel circuit 111 also includes a reset phase E0 performed before the data writing phase E1. In the reset phase E0, the fourth scan line S4 transmits a valid signal to control the sixth transistor T6 and the seventh transistor T7 to turn on. At this time, the first reset voltage Vref1 transmitted by the first reset signal line SL1 is transmitted to the gate of the driving transistor Td through the turned-on sixth transistor T6 and the seventh transistor T7, and the gate of the driving transistor Td is reset.

[0078] It can be understood that the gate potential of the driving transistor Td when generating the light-emitting driving current is the potential after the data writing stage E1.

[0079] In the embodiment of the present application, the first selection module 20 is turned on after the data writing stage E1, which can ensure that the potential of the first node N1 is adjusted by the gate potential of the driving transistor Td when generating the light-emitting driving current, thereby reducing the potential difference between the first node N1 and the gate potential of the driving transistor Td when the display panel 01 emits light, which is beneficial to stabilize the gate potential of the driving transistor Td, avoid large changes in the brightness of the display frame, and improve the display effect of the display panel 01.

[0080] In addition, the embodiment of the present application sets the first selection module 20 to be turned on after the data writing stage E1, which can also avoid the first selection module 20 from affecting the reset stage E0 and the data writing stage E1 of the first type of pixel circuit 111, which is beneficial to ensure the normal operation of the first type of pixel circuit 111.

[0081] In one embodiment of the present application, please continue to refer to Figure 4The working process of the first type pixel circuit 111 also includes a light emitting stage E2 performed after the data writing stage E1.

[0082] The first gating module 20 is turned on in the light emitting stage E2.

[0083] It is understandable that in the light emitting stage E2, the first transistor T1, the second transistor T2, the sixth transistor T6 and the seventh transistor T7 are all turned off. At this time, the driving transistor Td generates a light emitting driving current for driving the light emitting module 12 according to its gate potential.

[0084] In the embodiment of the present application, the first selection module 20 is set to be turned on in the light-emitting stage E2, so that the potential of the first node N1 in the light-emitting stage E2 can be adjusted to improve the problem of leakage of the first node N1 to the gate of the driving transistor Td in the light-emitting stage E2, thereby improving the display effect of the display panel 01.

[0085] Figure 6 for Figure 3 Another timing diagram of the first type of pixel circuit shown, Figure 7 for Figure 3 Another timing diagram of the first type of pixel circuit is shown.

[0086] like Figure 6 As shown, in one embodiment of the present application, the working process of the first type pixel circuit 111 also includes an adjustment phase E3 and a light emitting phase E2 which are sequentially performed after the data writing phase E1.

[0087] The first gating module 20 is turned on in the regulation phase E3 .

[0088] Figure 6 The timing shown is similar to Figure 4 The difference between the timings shown mainly lies in that an adjustment phase E3 is set between the data writing phase E1 and the light emitting phase E2, and the second scanning line S2 and the third scanning line S3 transmit valid signals in the adjustment phase E3 to control the first transistor T1 and the second transistor T2 to turn on.

[0089] The embodiment of the present application can neutralize the potential of the first node N1 before the light-emitting stage E2, thereby facilitating that the gate potential of the driving transistor Td remains stable at the start of the light-emitting stage E2, and facilitating further ensuring the brightness stability of the display frame.

[0090] It should be noted that if Figure 7As shown, in some other embodiments, the second scan line S2 can also be set to transmit a valid signal in the adjustment stage E3 to control the first transistor T1 to turn on, and the third scan line S3 can be set to transmit a valid signal in the light-emitting stage E2 to control the second transistor T2 to turn on. That is, the gate potential of the driving transistor Td is first written into the second node N2 in the adjustment stage E3, and then the second node N2 is connected to the first node N1 in the light-emitting stage E2, so as to neutralize the potential of the first node N1, realize the adjustment of the first node N1, and then reduce the leakage problem from the first node N1 to the gate of the driving transistor Td.

[0091] Figure 8 for Figure 3 Another timing diagram of the first type of pixel circuit is shown.

[0092] In one embodiment of the present application, the duration of the first sub-selection module 21 being turned on is not less than the duration of the second sub-selection module 22 being turned on. That is, the period of time during which the second scan line S2 transmits a valid signal (such as a low level) is not less than the period of time during which the third scan line S3 transmits a valid signal (such as a low level).

[0093] Alternatively, if Figure 6 As shown, the duration t1 during which the first sub-gating module 21 is turned on is equal to the duration t2 during which the second sub-gating module 22 is turned on.

[0094] Alternatively, if Figure 8 As shown, the duration t1 during which the first sub-gating module 21 is turned on is greater than the duration t2 during which the second sub-gating module 22 is turned on.

[0095] In the embodiment of the present application, when the duration of the first sub-enabling module 21 being turned on is longer than the duration of the second sub-enabling module 22 being turned on, the time for writing the gate potential of the driving transistor Td into the second node N2 can be increased, which is beneficial for more completely preserving the gate potential of the driving transistor Td in the second node N2, thereby facilitating that after the first node N1 and the second node N2 are turned on, the potential of the first node N1 is further approached to the gate potential of the driving transistor Td, thereby further helping to further reduce the problem of leakage from the first node N1 to the gate of the driving transistor Td.

[0096] When the duration of the first sub-enabling module 21 being turned on is equal to the duration of the second sub-enabling module 22 being turned on, it becomes possible for the second scan line S2 and the third scan line S3 to be provided by the same peripheral circuit, which is beneficial to reducing the number of peripheral driving circuits and reducing the design and manufacturing difficulty of the display panel 01.

[0097] Fig. 9 for Figure 3 Another timing diagram of the first type of pixel circuit is shown.

[0098] In one embodiment of the present application, during the operation of the first type pixel circuit 111, the duration of the first sub-selection module 21 being turned on is not less than the duration of the data voltage writing module 30 being turned on, and the duration of the second sub-selection module 22 being turned on is not less than the duration of the data voltage writing module 30 being turned on.

[0099] That is to say, during the operation of the first type of pixel circuit 111, the duration of the second scan line S2 transmitting a valid signal (such as a low level) is not less than the duration of the first scan line S1 transmitting a valid signal (such as a low level), and the duration of the third scan line S3 transmitting a valid signal (such as a low level) is not less than the duration of the first scan line S1 transmitting a valid signal (such as a low level).

[0100] Alternatively, if Figure 6 As shown, the time length t1 during which the first sub-selection module 21 is turned on is equal to the time length t3 during which the data voltage writing module 30 is turned on, and the time length t2 during which the second sub-selection module 22 is turned on is equal to the time length t3 during which the data voltage writing module 30 is turned on.

[0101] Alternatively, if Fig. 9 As shown, the first sub-gating module 21 is turned on for a duration t1 greater than the data voltage writing module 30 is turned on for a duration t3, and the second sub-gating module 22 is turned on for a duration t2 greater than the data voltage writing module 30 is turned on for a duration t3.

[0102] Of course, it is also possible to set the first sub-selection module 21 and the second sub-selection module 22 so that one is turned on for a duration equal to the duration when the data voltage writing module 30 is turned on, and the other is turned on for a duration greater than the duration when the data voltage writing module 30 is turned on.

[0103] In the embodiment of the present application, when the duration for which the first sub-selection module 21 and the duration for which the second sub-selection module 22 are turned on are both greater than the duration for which the data voltage writing module 30 is turned on, the time for writing the gate potential of the driving transistor Td to the second node N2 can be increased, and the time for neutralizing the potential of the second node N2 with the potential of the first node N1 can be increased, which is beneficial for more fully writing the gate potential of the driving transistor Td to the second node N2 and fully neutralizing it with the potential of the first node N1, so that after the data writing stage E1, the potential of the first node N1 is closer to the gate potential of the driving transistor Td, thereby helping to further reduce the problem of leakage from the first node N1 to the gate of the driving transistor Td, and further helping to further improve the display effect of the display panel 01.

[0104] When the duration for which the first sub-selection module 21 and the duration for which the second sub-selection module 22 are turned on are both equal to the duration for which the data voltage writing module 30 is turned on, while ensuring that the gate potential of the driving transistor Td can be used to adjust the potential of the first node N1, it becomes possible for the second scan line S2, the third scan line S3 and the first scan line S1 to be provided by the same peripheral driving circuit, which is beneficial to further reduce the number of peripheral driving circuits and reduce the design difficulty and preparation difficulty of the display panel 01.

[0105] Fig.10 A schematic diagram of another first-type pixel circuit provided in an embodiment of the present application.

[0106] In one embodiment of the present application, Figure 2 , Figure 3 , Figure 5 and Fig.10 As shown, the first type of pixel circuit 111 also includes a power supply voltage writing module 50 and a light emitting control module 60, wherein the input end of the power supply voltage writing module 50 is electrically connected to the second power supply voltage signal line PVDD, the output end is electrically connected to the first pole of the driving transistor Td, and the control end is electrically connected to the light emitting control signal line EM; the input end of the light emitting control module 60 is electrically connected to the second pole of the driving transistor Td, the output end is electrically connected to the first pole of the light emitting module 12, and the control end is electrically connected to the light emitting control signal line EM.

[0107] Specifically, Figure 3 , Figure 5 and Fig.10 As shown, the power supply voltage writing module 50 includes an eighth transistor T8, and the light-emitting control module 60 includes a ninth transistor T9. The first electrode of the eighth transistor T8 is electrically connected to the second power supply voltage signal line PVDD, the second electrode is electrically connected to the first electrode of the driving transistor Td, and the gate is electrically connected to the light-emitting control signal line EM; the first electrode of the ninth transistor T9 is electrically connected to the second electrode of the driving transistor Td, the second electrode is electrically connected to the first electrode of the light-emitting module 12, and the gate is electrically connected to the light-emitting control signal line EM; the second electrode of the light-emitting module 12 is electrically connected to the first power supply voltage signal line PVEE.

[0108] In the light emitting stage E2, the light emitting control signal line EM transmits a valid signal to control the eighth transistor T8 and the ninth transistor T9 to turn on, and the driving transistor Td generates a light emitting driving current according to its gate potential and transmits it to the first electrode of the light emitting module 12, driving the light emitting module 12 to emit light. The light emitting module 12 may include an organic light emitting diode, the first electrode of the light emitting module 12 may be an anode of the organic light emitting diode, and the second electrode of the light emitting module 12 may be a cathode of the organic light emitting diode.

[0109] Among them, Fig.10As shown, the third scan line S3 is electrically connected to the light emitting control signal line EM, and the signal transmitted by the light emitting control signal line EM controls the switching states of the power supply voltage writing module 50, the light emitting control module 60 and the fourth transistor T4 to be the same. That is, the channel types of the eighth transistor T8, the ninth transistor T9 and the fourth transistor T4 are the same.

[0110] In the embodiment of the present application, the third scan line S3 is electrically connected to the light-emitting control signal line EM, that is, the signal transmitted by the light-emitting control signal line EM is reused to control the switching state of the fourth transistor T4. While ensuring that the potential of the first node N1 can be adjusted in the light-emitting stage E2, there is no need to additionally set the control signal of the fourth transistor T4, which is beneficial to simplifying the design of the peripheral driving circuit in the display panel 01 and reducing the difficulty of preparing the display panel 01.

[0111] Please continue to refer to Figure 2 In one embodiment of the present application, the first type pixel circuit 111 also includes a second reset module 70, an input end of the second reset module 70 is electrically connected to the first reset signal line SL1, and an output end is electrically connected to the first pole of the light-emitting module 12, and the second reset module 70 is used to transmit the first reset voltage Vref1 transmitted by the first reset signal line SL1 to the first pole of the light-emitting module 12 to reset the first pole of the light-emitting module 12.

[0112] Specifically, Figure 3 , Figure 5 and Fig.10 As shown, the second reset module 70 includes a tenth transistor T10, a first electrode of the tenth transistor T10 is electrically connected to the first reset signal line SL1, a second electrode is electrically connected to the first electrode of the light emitting module 12, and a gate is electrically connected to the first scan line S1. The channel type of the tenth transistor T10 is the same as the channel type of the first transistor T1 and the second transistor T2.

[0113] In the data writing phase E1 , the tenth transistor T10 is turned on, and the first reset voltage Vref1 transmitted by the first reset signal line SL1 is transmitted to the first electrode of the light emitting module 12 through the turned-on tenth transistor T10 , thereby completing the resetting of the light emitting module 12 .

[0114] In order to explain the technical solution of the embodiment of the present application more clearly, Figure 3 and Figure 4 right Figure 3 The working process of the first type pixel circuit 111 is described below.

[0115] It should be noted that the following description is made by taking the first transistor T1 , the second transistor T2 , the third transistor T3 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 , the seventh transistor T7 , the eighth transistor T8 , the ninth transistor T9 and the tenth transistor T10 as P-type transistors as an example.

[0116] The working process of the first type pixel circuit 111 includes a reset phase E0, a data writing phase E1 and a light emitting phase E2 which are performed in sequence.

[0117] In the reset phase E0, the fourth scan line S4 transmits an on signal, i.e., a low-level signal, and the sixth transistor T6 and the seventh transistor T7 are turned on; the first scan line S1, the second scan line S2, the third scan line S3 and the light-emitting control signal line EM transmit an off signal, i.e., a high-level signal, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 are turned off. At the same time, the first reset signal line SL1 transmits the first reset voltage Vref1, and the first reset voltage Vref1 is transmitted to the gate of the driving transistor Td through the turned-on sixth transistor T6 and the seventh transistor T7, completing the resetting of the gate of the driving transistor Td.

[0118] In the data writing phase E1, the first scan line S1 transmits a start signal, i.e., a low level signal, and the first transistor T1, the second transistor T2, the fifth transistor T5, and the tenth transistor T10 are turned on; the second scan line S2, the third scan line S3, the fourth scan line S4, and the light emitting control signal line EM transmit a shutdown signal, i.e., a high level signal, and the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned off. At the same time, the data signal line DL1 transmits the data voltage Vdata. At the starting point of the data writing phase E1, the gate potential of the driving transistor Td is the first reset voltage Vref1, the source potential of the driving transistor Td is the data voltage signal Vdata, and the potential difference between the source and the gate of the driving transistor Td is (Vdata-Vref1), and the potential difference between the two is greater than 0. Therefore, the driving transistor Td is turned on, and the data voltage Vdata is transmitted to the gate of the driving transistor Td through the turned-on driving transistor Td and the turned-on first transistor T1 and second transistor T2, so that the gate potential of the driving transistor Td gradually increases. When the gate potential of the driving transistor Td is equal to (Vdata-|Vth|), the driving transistor Td is turned off, where Vth is the threshold voltage of the driving transistor Td.

[0119] Meanwhile, the first reset voltage Vref1 resets the first electrode of the light emitting module 12 through the turned-on tenth transistor T10. Optionally, the light emitting module 12 includes an organic light emitting diode, and the first reset voltage Vref1 resets the anode of the organic light emitting diode through the turned-on tenth transistor T10.

[0120] In the light-emitting stage E2, the first scan line S1 and the fourth scan line S4 transmit a shutdown signal, i.e., a high-level signal, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the tenth transistor T10 are turned off; the second scan line S2, the third scan line S3, and the light-emitting control signal line EM transmit an open signal, i.e., a low-level signal, and the third transistor T3, the fourth transistor T4, the eighth transistor T8, and the ninth transistor T9 are turned on. At the same time, the second power supply voltage signal line PVDD transmits the second power supply voltage VDD, i.e., the potential of the source of the driving transistor Td is the second power supply voltage VDD. Since the potential of the second power supply voltage VDD is greater than the potential of the data voltage Vdata, the driving transistor Td generates a light-emitting driving current and transmits it to the light-emitting module 12 through the ninth transistor T9, thereby controlling the light-emitting module 12 to emit light.

[0121] At the same time, the third transistor T3 and the fourth transistor T4 are turned on in sequence, so that the gate potential of the driving transistor Td can be first written into the second node N2 through the third transistor T3, and then written into the first node N1 through the fourth transistor T4 to adjust the potential of the first node N1. While avoiding the potential of the first node N1 from affecting the gate potential of the driving transistor Td through the third transistor T3 and the fourth transistor T4, the potential difference between the first node N1 and the gate of the driving transistor Td can be reduced, which is beneficial to improving the problem of leakage from the first node N1 to the gate of the driving transistor Td, stabilizing the gate potential of the driving transistor Td, and further beneficial to avoiding large changes in the brightness of the display frame, thereby improving the display effect of the display panel 01.

[0122] Fig.11 for Figure 1 A connection diagram of three adjacent rows of first-type pixel circuits.

[0123] In one embodiment of the present application, Figure 1 and Fig.11 As shown, the display panel 01 includes a plurality of rows of first-type pixel circuits 111, the second scan line S2 electrically connected to the first-type pixel circuit 111 in the i-th row is electrically connected to the first scan line S1 electrically connected to the first-type pixel circuit 111 in the i+1-th row, and the third scan line S3 electrically connected to the first-type pixel circuit 111 in the i-th row is electrically connected to the first scan line S1 electrically connected to the first-type pixel circuit 111 in the i+2-th row. Wherein, i≥1.

[0124] That is to say, the gate of the third transistor T3 in the first-type pixel circuit 111 in the i-th row is electrically connected to the gate of the fifth transistor T5 in the first-type pixel circuit 111 in the i+1-th row, and the gate of the fourth transistor T3 in the first-type pixel circuit 111 in the i-th row is electrically connected to the gate of the fifth transistor T5 in the first-type pixel circuit 111 in the i+2-th row.

[0125] In the embodiment of the present application, the second scan line S2 , the third scan line S3 and the first scan line S1 may be provided by the same peripheral driving circuit, which is beneficial to reducing the number of peripheral driving circuits and lowering the design difficulty and manufacturing difficulty of the display panel 01 .

[0126] For further information, please refer to Fig.11 The first scan line S1 electrically connected to the first type pixel circuit 111 in the i-th row can also be electrically connected to the fourth scan line S4 electrically connected to the first type pixel circuit 111 in the (i+1)-th row, so that the first scan line S1, the second scan line S2, the third scan line S3 and the fourth scan line S4 can all be provided by the same peripheral driving circuit, which is beneficial to further reduce the number of peripheral driving circuits and reduce the design difficulty and preparation difficulty of the display panel 01.

[0127] Fig.12 A schematic diagram of another display panel provided in an embodiment of the present application, Fig.13 A schematic diagram of the connection between a second type of pixel circuit and a first type of pixel circuit provided in an embodiment of the present application.

[0128] In one embodiment of the present application, Fig.12 and Fig.13 As shown, the plurality of pixel circuits 11 further include a second type of pixel circuit 112 , and the second type of pixel circuit 112 may be arranged in the same row as the first type of pixel circuit 111 .

[0129] The second type pixel circuit 112 includes a second gating module 80 , a first end of the second gating module 80 is electrically connected to the first node N1 , and a second end of the second gating module 80 is electrically connected to the second node N2 in the first type pixel circuit 111 .

[0130] The switch state of the second selection module 80 is the same as the switch state of the second sub-selection module 22 in the first type pixel circuit 111 .

[0131] Specifically, in the second type pixel circuit 112, the second gating module 80 includes a fourth transistor T4, a first electrode of the fourth transistor T4 is electrically connected to the first node N1, a second electrode is electrically connected to the second node N2 in the first type pixel circuit 111, and a gate is electrically connected to the third scan line S3 electrically connected to the first type pixel circuit 111. The second type pixel circuit 112 and the first type pixel circuit 111 are located in the same row.

[0132] Fig.13 The difference between the second type pixel circuit 112 and the first type pixel circuit 111 is that the second type pixel circuit 112 does not include the third transistor T3 and the first capacitor C1 .

[0133] In the embodiment of the present application, after the first sub-selection module 21 in the first-type pixel circuit 111 writes the gate potential of the driving transistor Td in the first-type pixel circuit 111 into the second node N2, the second selection module 80 in the second-type pixel circuit 112 is turned on, so that the first node N1 in the second-type pixel circuit 112 is turned on with the second node N2 in the first-type pixel circuit 111, thereby utilizing the potential of the second node N2 in the first-type pixel circuit 111 to neutralize the potential of the first node N1 in the second-type pixel circuit 112, and similarly can reduce the potential difference between the first node N1 in the second-type pixel circuit 112 and the gate of the driving transistor Td in the second-type pixel circuit 112, thereby facilitating improving the stability of the brightness of the light-emitting module 12 driven by the second-type pixel circuit 112, thereby ensuring the display quality of the display panel 01.

[0134] The embodiment of the present application can reduce the number of transistors in the display panel 01 while improving the display quality of the display panel 01 , thereby facilitating reducing the cost of the display panel 01 .

[0135] Fig.14 A schematic diagram of a display device provided in an embodiment of the present application.

[0136] The present application embodiment provides a display device 02, such as Fig.14 As shown, the display device 02 includes the display panel 01 provided in the above embodiment. The display device 02 provided in the embodiment of the present application may be a mobile phone, in addition, the display device 02 may also be an electronic device such as a computer or a television.

[0137] In the display device 02, by setting a first selection module 20 between the first node N1 and the gate of the driving transistor Td, and using the gate potential of the driving transistor Td to adjust the potential of the first node N1, the potential difference between the first node N1 and the gate of the driving transistor Td can be reduced, which is beneficial to improve the problem of leakage from the first node N1 to the gate of the driving transistor Td, stabilize the gate potential of the driving transistor Td, and further help avoid large changes in the brightness of the display frame, thereby improving the display effect of the display device 02.

[0138] In addition, in the first selection module 20, the time period in which the first sub-selection module 21 is turned on is set before the time period in which the second sub-selection module 22 is turned on, so that the gate potential of the driving transistor Td can be first written into the second node N2 through the first sub-selection module 21, and then written into the first node N1 through the second sub-selection module 22 to adjust the potential of the first node N1, which can avoid the potential of the first node N1 from affecting the gate potential of the driving transistor Td through the first selection module 20, thereby facilitating further ensuring the stability and accuracy of the gate potential of the driving transistor Td, and further improving the display effect of the display device 02.

[0139] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: The device comprises a plurality of pixel circuits and a plurality of light-emitting modules, wherein the pixel circuit comprises: A driving transistor, the driving transistor is used to provide a light-emitting driving current for the light-emitting module; a first transistor and a second transistor, wherein a first electrode of the first transistor is electrically connected to a second electrode of the driving transistor, and a first electrode of the second transistor is electrically connected to a gate of the driving transistor; and a first node is included between the second electrode of the first transistor and the second electrode of the second transistor; The plurality of pixel circuits include a first type of pixel circuit, and the first type of pixel circuit includes: a first gating module, the first gating module comprising a first sub-gating module and a second sub-gating module, the first end of the first sub-gating module being electrically connected to the gate of the driving transistor and the second end being electrically connected to the second node, the first end of the second sub-gating module being electrically connected to the second node and the second end being electrically connected to the first node; the first gating module being used to adjust the potential of the first node; Wherein, the period during which the first sub-gating module is turned on is before the period during which the second sub-gating module is turned on; The duration during which the first sub-enabling module is turned on is not less than the duration during which the second sub-enabling module is turned on.

2. The display panel according to claim 1, characterized in that: The first sub-selection module includes a third transistor, a first electrode of the third transistor is electrically connected to the gate of the driving transistor, and a second electrode of the third transistor is electrically connected to the second node; The second sub-selection module includes a fourth transistor, a first electrode of the fourth transistor is electrically connected to the first node, and a second electrode of the fourth transistor is electrically connected to the second node.

3. The display panel according to claim 1, characterized in that: The first type of pixel circuit includes a first capacitor, one plate of the first capacitor is electrically connected to the second node, and the other plate of the first capacitor is electrically connected to the fixed potential signal line.

4. The display panel according to claim 3, characterized in that: The fixed potential signal line is electrically connected to a first power supply voltage signal line, and the first power supply voltage signal line is electrically connected to the light emitting module.

5. The display panel according to claim 2, characterized in that: The first type of pixel circuit further includes a data voltage writing module, wherein an input end of the data voltage writing module is electrically connected to the data signal line, and an output end of the data voltage writing module is electrically connected to the first electrode of the driving transistor; The working process of the first type of pixel circuit includes a data writing stage, during which the data voltage writing module and the first transistor and the second transistor are turned on; The first gating module is turned on after the data writing phase.

6. The display panel according to claim 5, characterized in that: The working process of the first type of pixel circuit also includes a light emitting stage performed after the data writing stage; The first gating module is turned on during the light emitting phase.

7. The display panel according to claim 5, characterized in that: The working process of the first type of pixel circuit also includes an adjustment phase and a light emitting phase which are sequentially performed after the data writing phase; The first gating module is turned on during the adjustment phase.

8. The display panel according to claim 5, characterized in that: The data voltage writing module comprises a fifth transistor, a first electrode of the fifth transistor is electrically connected to the data signal line, a second electrode of the fifth transistor is electrically connected to the first electrode of the driving transistor, and a gate of the fifth transistor is electrically connected to the first scanning line; The gate of the first transistor and the gate of the second transistor are electrically connected to the first scan line; the signal transmitted by the first scan line controls the switching states of the first transistor, the second transistor and the fifth transistor to be the same.

9. The display panel according to claim 8, characterized in that: A gate of the third transistor is electrically connected to the second scan line, and a gate of the fourth transistor is electrically connected to the third scan line.

10. The display panel according to claim 9, characterized in that: The first type of pixel circuit further includes a power supply voltage writing module and a light emitting control module; the input end of the power supply voltage writing module is electrically connected to the second power supply voltage signal line, the output end is electrically connected to the first electrode of the driving transistor, and the control end is electrically connected to the light emitting control signal line; the input end of the light emitting control module is electrically connected to the second electrode of the driving transistor, the output end is electrically connected to the first electrode of the light emitting module, and the control end is electrically connected to the light emitting control signal line; The third scan line is electrically connected to the light emitting control signal line, and the signal transmitted by the light emitting control signal line controls the switching states of the power supply voltage writing module, the light emitting control module and the fourth transistor to be the same.

11. The display panel according to claim 9, characterized in that: The display panel includes multiple rows of the first-type pixel circuits, the second scan line electrically connected to the first-type pixel circuits in the i-th row is electrically connected to the first scan line electrically connected to the first-type pixel circuits in the i+1-th row, and the third scan line electrically connected to the first-type pixel circuits in the i-th row is electrically connected to the first scan line electrically connected to the first-type pixel circuits in the i+2-th row, i≥1.

12. The display panel according to claim 5, characterized in that: The first sub-selection module is turned on for a duration not less than the data voltage writing module is turned on, and the second sub-selection module is turned on for a duration not less than the data voltage writing module is turned on.

13. The display panel according to claim 1, characterized in that: The plurality of pixel circuits include a second type of pixel circuit, and the second type of pixel circuit includes: a second gating module, wherein a first end of the second gating module is electrically connected to the first node, and a second end of the second gating module is electrically connected to a second node in the first type of pixel circuit; The switching state of the second gating module is the same as the switching state of the second sub-gating module in the first type of pixel circuit.

14. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-13.

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