A high surge capability planar diode and a method of manufacturing the same

Abstract

A planar diode with high surge capacity and a preparation method thereof. Relate to a semiconductor device. It comprises a substrate, a P+ substrate region diffused from the top of the substrate, located in the substrate, the top of the substrate is provided with an annular notch near the edge, an arc-shaped shoulder is provided between the annular notch and the top surface of the P+ substrate region, and an oxide passivation film is provided on the arc-shaped shoulder and connected with the substrate and the P+ substrate region respectively, the top surface and the bottom surface of the planar diode are respectively provided with a metal layer. The metal layer comprises an upper metal layer provided on the oxide passivation film and connected with the P+ substrate region in the middle, and a lower metal layer provided at the bottom of the substrate. The application effectively avoids avalanche at the edge of the planar diode chip first, improves the surge capacity and reliability of the diode, and improves the product quality.

Description

Technical Field

[0001] This invention relates to a semiconductor device, and more particularly to a planar diode with high surge capability and a method for fabricating the same. Background Technology

[0002] Currently, planar diodes are generally manufactured using planar junction technology. Because the base region has a uniform concentration on the upper surface but a shallower depth beneath the edge junction, the breakdown voltage is weaker. When a large surge current flows into the product, the current rapidly expands laterally along the high-concentration base region below the passivation layer and flows to the weaker area beneath the junction. Since the edge breakdown voltage is lower than the central region, the edge junction is the first to break down and fail. Therefore, in reverse operation, the edge junction is prone to avalanche breakdown, ultimately affecting the overall breakdown voltage and reliability of the diode, leading to a decline in product quality. Summary of the Invention

[0003] To address the above problems, this invention provides a planar diode with high surge capability and its fabrication method, which effectively avoids edge avalanche in planar diode chips and improves the surge resistance and reliability of the diode.

[0004] The technical solution of this invention is: a planar diode with high surge capability, comprising:

[0005] Substrate;

[0006] A P+ substrate region, the P+ substrate region extending downwards from the top of the substrate and located within the substrate; an annular notch is provided at the top of the substrate near its edge; an arc-shaped shoulder is provided between the annular notch and the top surface of the P+ substrate region; and

[0007] An oxide passivation film is disposed on the arc-shaped shoulder and connected to the substrate and the P+ substrate region respectively. The top and bottom surfaces of the planar diode are respectively provided with metal layers.

[0008] Specifically, the metal layer includes: an upper metal layer disposed on an oxide passivation film and connected to the P+ substrate region in the middle; and a lower metal layer disposed at the bottom of the substrate.

[0009] Specifically, the oxide passivation film is placed on the annular notch.

[0010] Specifically, the inner line of the annular notch is located on the upper side of the base region at a distance of 50-100 μm from the boundary between the substrate and the base region, and the outer line extends to the outer edge of the substrate. The depth of the annular notch is 3-15 μm.

[0011] Specifically, the width of the annular oxide passivation film is 200-250 μm, mainly covering the annular notch and the main junction at the junction of the substrate and the base region.

[0012] A method for fabricating a planar diode with high surge capability includes the following steps:

[0013] S001: Substrate selection;

[0014] Select a substrate silicon wafer with appropriate resistivity based on the product's voltage withstand requirements;

[0015] S002: Primary oxidation;

[0016] An oxide film is grown on the substrate surface;

[0017] S003: Selective photolithography of the front-side diffusion area;

[0018] A base region to be diffused is reserved on the upper surface of the substrate, and the rest is protected with photoresist;

[0019] S004: Oxide film removal;

[0020] Remove the oxide film above the base region to be diffused to expose the front area to be diffused;

[0021] S005: High-temperature propulsion in the base region;

[0022] Boron impurities are deposited on the exposed substrate surface and diffused at high temperature to form a P+ substrate region;

[0023] S006: Secondary front-side selective lithography;

[0024] The oxide film grown at high temperature on the surface during high-temperature diffusion above the P+ substrate region is covered with photoresist, while the remaining annular area to be etched is exposed.

[0025] S007: Oxide film removal;

[0026] Remove the oxide film from the surface of the annular region to be etched to expose the silicon at the etched location;

[0027] S008: Silicon removal from the high-concentration doped region at the base edge;

[0028] The silicon exposed at the edge of the base region is etched using mixed acid to remove the highly doped silicon from the surface of the base region edge.

[0029] S009: Removal of photoresist and oxide film

[0030] Remove the photoresist and attached oxide layer from the surface;

[0031] S010: Multilayer oxide film passivation:

[0032] A SIPOS passivation film and a low-temperature oxide film are deposited on the wafer surface to protect the exposed PN junction;

[0033] S011: Three-stage selective front-side lithography;

[0034] The non-oxide passivation film preparation area is exposed, and the oxide passivation film preparation area is covered with photoresist;

[0035] S0012: Removal of oxide film on electrode surface;

[0036] Remove the surface oxide film from the upper surface region of the base area;

[0037] S013: Metal evaporation: Double-sided evaporation of Ag metal;

[0038] S014: Quadruple yellow light-electrode selective photolithography:

[0039] Selective photolithography to remove metal from the surface of the dicing track; S015: Metal etching and photoresist removal:

[0040] Metal etching solution is used to etch away the exposed metal on the wafer surface.

[0041] This invention discloses a planar diode structure with high surge capability. By etching away the highly concentrated diffused silicon in the planar junction region at the base edge, forming an annular notch, the surface concentration of the base region beneath the oxide passivation film decreases, increasing lateral resistance and lateral electric field strength, and enhancing the withstand voltage of the weak region beneath the junction. Under large surge currents, the current flows from the central main junction region, effectively preventing avalanche at the edge of the planar diode chip, improving the diode's surge resistance and reliability, and enhancing product quality. Attached Figure Description

[0042] Figure 1 This is a structural schematic diagram of step S001 of the present invention.

[0043] Figure 2 This is a structural schematic diagram of step S002 of the present invention.

[0044] Figure 3 This is a structural schematic diagram of step S003 of the present invention.

[0045] Figure 4 This is a structural schematic diagram of step S004 of the present invention.

[0046] Figure 5 This is a structural schematic diagram of step S005 of the present invention.

[0047] Figure 6 This is a structural schematic diagram of step S006 of the present invention.

[0048] Figure 7 This is a structural schematic diagram of step S007 of the present invention.

[0049] Figure 8 This is a structural schematic diagram of step S008 of the present invention.

[0050] Figure 9This is a structural schematic diagram of step S009 of the present invention.

[0051] Figure 10 This is a structural schematic diagram of step S010 of the present invention.

[0052] Figure 11 This is a structural schematic diagram of step S011 of the present invention.

[0053] Figure 12 This is a structural schematic diagram of step S012 of the present invention.

[0054] Figure 13 This is a structural schematic diagram of step S013 of the present invention.

[0055] Figure 14 This is a structural schematic diagram of step S014 of the present invention.

[0056] Figure 15 This is a structural schematic diagram of step S015 of the present invention;

[0057] In the figure, 100 is the substrate, 200 is the P+ substrate region, 300 is the oxide passivation film, and 400 is the metal layer. Detailed Implementation

[0058] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0059] In the description of this invention, it should be understood that the terms "upper," "lower," "left," "right," "vertical," and "horizontal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0060] The present invention is as follows Figure 1-15 As shown; a planar diode with high surge capability, comprising:

[0061] Substrate 100;

[0062] P+ substrate region 200, the P+ substrate region 200 diffuses downward from the top of substrate 100 and is located within substrate 100; the top of substrate 100 near the edge has an annular notch for etching with mixed acid; an arc-shaped shoulder is provided between the annular notch and the top surface of P+ substrate region 200; and

[0063] An oxide passivation film 300 is disposed on the arc-shaped shoulder and is connected to the substrate 100 and the P+ substrate region 200 respectively. Metal layers 400 are respectively provided on the top and bottom surfaces of the planar diode.

[0064] Further defining the metal layer 400, the metal layer 400 includes: an upper metal layer disposed on the oxide passivation film 300 and connected to the P+ substrate region 200 in the middle; and a lower metal layer disposed at the bottom of the substrate.

[0065] Further specified, the oxide passivation film 300 is disposed on the annular notch.

[0066] Further defined, the inner line of the annular notch is located on the upper side of the base region at a distance of 50-100 μm from the boundary between the substrate and the base region, and the outer line extends to the outer edge of the substrate, with a depth of 3-15 μm for the annular notch.

[0067] Further specified, the width of the annular oxide passivation film 300 is 200-250 μm, mainly covering the annular notch and the main junction at the junction of the substrate and the base region.

[0068] A method for fabricating a planar diode with high surge capability, taking an N-type substrate as an example, is characterized by comprising the following steps:

[0069] S001: N-type substrate selection;

[0070] Reference Figure 1 As shown, based on the product's voltage withstand requirements, select an N-type substrate silicon wafer with the appropriate resistivity, typically 0.0001-0.5Ω;

[0071] S002: Primary oxidation;

[0072] Reference Figure 2 As shown, an oxide film is grown on the substrate surface, and the oxide film thickness is required to be 15,000-30,000 angstroms;

[0073] S003: Selective photolithography of the front-side diffusion area;

[0074] Reference Figure 3 As shown, a base region to be diffused is reserved on the upper surface of the substrate, and the rest is protected with photoresist;

[0075] S004: Oxide film removal;

[0076] Reference Figure 4 As shown, the oxide film above the base region to be diffused is removed to expose the front area to be diffused;

[0077] S005: Base region boron pre-deposition (or ion implantation) and high-temperature propulsion;

[0078] Reference Figure 5 As shown, a certain concentration of boron impurities (typically 5E18~6E20) is deposited on the exposed N-type silicon substrate surface, and then diffused at high temperature to form a P+ substrate region 200.

[0079] S006: Secondary front-side selective lithography;

[0080] Reference Figure 6 As shown, the oxide film grown at high temperature on the surface during high-temperature diffusion in the P+ substrate region 200 (a square area within 50-100 μm from the edge of the base region on the upper surface) is covered with photoresist, while the remaining annular area to be etched is exposed.

[0081] S007: Oxide film removal;

[0082] Reference Figure 7 As shown, the oxide film on the surface of the annular region to be etched is removed to expose the silicon at the etched area;

[0083] S008: Silicon removal from the high-concentration doped region at the base edge;

[0084] Reference Figure 8 As shown, mixed acid is used to etch the silicon exposed at the edge of the base region to remove the highly doped silicon on the surface of the base region edge. The etching depth is determined by the doping concentration and junction depth, and is generally 3-15 μm.

[0085] The main components of mixed acid are generally a mixture of HF, HNO3 and glacial acetic acid. The corrosion rate varies depending on the acid temperature and corrosion time. Generally, the corrosion solution temperature is -6℃ to 5℃ and the corrosion time is 150-300 seconds.

[0086] S009: Removal of photoresist and oxide film

[0087] Reference Figure 9 As shown, the photoresist and attached oxide layer on the wafer surface are removed;

[0088] S010: Multilayer oxide film passivation:

[0089] Reference Figure 10 As shown, an SIPOS passivation film and a low-temperature oxide film are deposited on the wafer surface using the LPCVD method to protect the exposed PN junction;

[0090] S011: Three-stage selective front-side lithography;

[0091] Reference Figure 11 As shown, the non-oxide passivation film 300 preparation area is exposed, and the oxide passivation film 300 preparation area is covered with photoresist;

[0092] S0012: Removal of oxide film on electrode surface;

[0093] Reference Figure 12 As shown, the surface oxide film on the upper surface of the base region is removed;

[0094] S013: Metal Evaporation: Double-sided Evaporation of Ag Metal; Reference Figure 13 As shown,

[0095] S014: Quadruple yellow light-electrode selective photolithography:

[0096] Reference Figure 14 As shown, selective photolithography removes metal from the surface of the dicing track; S015: Metal etching and photoresist removal:

[0097] Metal etching solution is used to etch away the exposed metal on the wafer surface.

[0098] Regarding the information disclosed in this case, the following points need to be clarified:

[0099] (1) The accompanying drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case; other structures can refer to the general design.

[0100] (2) Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments;

[0101] The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.

Claims

1. A planar diode with high surge capability, characterized in that, include: Substrate; The P+ substrate region diffuses downward from the top of the substrate and is located within the substrate; The substrate has an annular notch near its top edge. The inner line of the annular notch is located on the upper side of the base region, 50-100 μm away from the boundary between the substrate and the base region, and the outer line extends to the outer edge of the substrate. The depth of the annular notch is 3-15 μm. An arc-shaped shoulder is provided between the annular notch and the top surface of the P+ substrate region. The arc-shaped shoulder reduces the surface concentration of the base region below the oxide passivation film, increases the lateral resistance and lateral electric field, and thus enhances the breakdown voltage capability of the weak region below the junction. and An oxide passivation film, the width of which is 200-250um, covers the annular notch and the main junction at the junction of the substrate and the base region. The oxide passivation film is disposed on the arc-shaped shoulder and is connected to the substrate and the P+ substrate region respectively, for strengthening the voltage withstand protection of the base region edge. The top and bottom surfaces of the planar diode are respectively provided with metal layers.

2. The planar diode with high surge capability according to claim 1, characterized in that, The metal layer includes: an upper metal layer disposed on an oxide passivation film and connected to the P+ substrate region in the middle; and a lower metal layer disposed at the bottom of the substrate.

3. A planar diode with high surge capability according to claim 1, characterized in that, The oxide passivation film is placed on the annular notch.

4. A method for fabricating a planar diode with high surge capability, as described in any one of claims 1 to 3, characterized in that, Includes the following steps: S001: Substrate selection; Select a substrate silicon wafer with appropriate resistivity based on the product's voltage withstand requirements; S002: Primary oxidation; An oxide film is grown on the substrate surface; S003: Selective photolithography of the front-side diffusion area; A base region to be diffused is reserved on the upper surface of the substrate, and the rest is protected with photoresist; S004: Oxide film removal; Remove the oxide film above the base region to be diffused to expose the front area to be diffused; S005: High-temperature propulsion in the base region; Boron impurities are deposited on the exposed substrate surface and diffused at high temperature to form a P+ substrate region; S006: Secondary front-side selective lithography; The oxide film grown at high temperature on the surface during high-temperature diffusion above the P+ substrate region is covered with a photoresist, and the remaining annular area to be etched is exposed. The range of the annular area to be etched corresponds to the inner and outer line positions of the annular notch. S007: Oxide film removal; Remove the oxide film from the surface of the annular region to be etched to expose the silicon at the etched location; S008: Silicon removal from the high-concentration doped region at the base edge; The silicon exposed at the edge of the base region is etched using mixed acid to remove the highly concentrated doped silicon on the surface of the base region edge; the temperature of the etching solution is controlled at -6℃ to 5℃, the etching time is 150-300s, and the etching depth is controlled at 3-15um. S009: Removal of photoresist and oxide film Remove the photoresist and attached oxide layer from the surface; S010: Multilayer oxide film passivation: A SIPOS passivation film and a low-temperature oxide film are deposited on the wafer surface to protect the exposed PN junction; The deposition temperature for preparing SIPOS passivation films is 600-650℃, and the deposition temperature for low-temperature oxide films is 300-400℃. S011: Three-stage selective front-side lithography; The non-oxide passivation film preparation area is exposed, and the oxide passivation film preparation area is covered with photoresist; S0012: Removal of oxide film on electrode surface; Remove the surface oxide film from the upper surface region of the base area; S013: Metal evaporation: Double-sided evaporation of Ag metal; S014: Quadruple yellow light-electrode selective photolithography: Selective lithography removes metal from the surface of the cut track; S015: Metal corrosion and photoresist removal: Metal etching solution is used to etch away the exposed metal on the wafer surface.

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