A high-precision relaxation oscillator for ADC

Abstract

This invention proposes a high-precision relaxation oscillator for an ADC. The oscillator includes current sources I1 and I2, capacitor CRES, a comparator, inverters INV1 and INV2, an oscillator transistor group, and a voltage selection switch TG. The comparator is connected to the inverter INV1 and capacitor CRES, and also to the oscillator transistors M1 and M2. The comparator is connected to bias power supplies VB1, VB2, and VB3, and calibration signal ports Caln1~CalnN and Calp1~CalpN. By connecting calibration signals Vn1~VnN and Vp1~VpN, mismatch problems existing in the comparison process are calibrated. The oscillator achieves high precision by calibrating the comparator mismatch. The voltage selection switch selects the corresponding standard voltage according to the comparator output to achieve oscillation output. The circuit structure of this invention is simple, easy to integrate, highly operable, and has low power consumption, achieving high precision and suitable for application in ADC systems.

Description

Technical Field

[0001] This invention relates to the field of circuit design technology, and in particular to a high-precision relaxation oscillator for ADCs. Background Technology

[0002] With the rise of the Internet of Things (IoT) industry, sensors, as devices that can convert non-electrical signals in nature into electrical signals, are the source of information for the entire IoT system. Signals in nature are continuous analog signals. With current technology, processing analog signals is difficult, while processing digital signals is much easier. Therefore, information often needs to be converted from the analog domain to the digital domain through an analog-to-digital converter (ADC).

[0003] In an ADC system, an oscillator is needed to provide the clock frequency. Different oscillator circuit structures have their own advantages and disadvantages in terms of power consumption, frequency stability, and area. Commonly used oscillator circuits for clocking include crystal oscillators, ring oscillators, LC oscillators, and RC oscillators.

[0004] (1) Crystal oscillator circuits have advantages such as high precision and strong anti-interference. However, crystal oscillators require an external quartz crystal, which is not conducive to the internal integration of chips.

[0005] (2) Ring oscillators have advantages such as simple circuit structure and convenient use. However, the output frequency of ring oscillators is easily affected by the environment and has weak anti-interference ability, resulting in low frequency stability.

[0006] (3) LC oscillators have good temperature and voltage characteristics. However, they require a large number of capacitors C and inductors L, which takes up too much chip area and are not easy to integrate.

[0007] (4) RC oscillators are highly operable and can be integrated into chips, with a small area and low cost. However, the frequency stability of RC oscillators is not high, and the output frequency is easily affected by temperature, device mismatch and power supply voltage.

[0008] For highly integrated systems like ADCs, ring oscillators and RC oscillators are commonly used. Compared to ring oscillators, RC oscillators have a smaller temperature coefficient and a more stable output frequency. Therefore, RC oscillators are widely used. However, RC oscillators are susceptible to the effects of temperature, component mismatch, and voltage, resulting in unstable oscillation frequencies. Therefore, researching high-precision oscillators is currently a hot research topic. Relaxation oscillators are also a type of RC oscillator. This invention relates to a high-precision relaxation oscillator for ADCs. Summary of the Invention

[0009] This invention proposes a high-precision relaxation oscillator for ADCs, which has a simple circuit structure, is easy to integrate, is highly operable, and has low power consumption.

[0010] The present invention adopts the following technical solution.

[0011] A high-precision relaxation oscillator for an ADC, the oscillator comprising current sources I1 and I2, capacitor CRES, comparator, inverters INV1 and INV2, oscillator transistor group, and voltage selection switch TG; the comparator is connected to inverter INV1 and capacitor CRES, and also to oscillator transistors M1 and M2;

[0012] The comparator is connected to bias power supplies VB1, VB2, and VB3, as well as calibration signal ports Caln1~CalnN and Calp1~CalpN. By connecting calibration signals Vn1~VnN and Vp1~VpN, the mismatch problem that exists during the comparison process can be calibrated.

[0013] The oscillator achieves high precision by calibrating the comparator mismatch, and the voltage selection switch selects the corresponding standard voltage according to the comparator output to achieve oscillation output.

[0014] The lower end of the current source I1 is connected to the source of the oscillator transistor M1, and the upper end is connected to the power supply; the upper end of the current source I2 is connected to the source of the oscillator transistor M2, and the lower end is grounded.

[0015] The drains of oscillator transistors M1 and M2 are connected to the comparator input port VIP and the upper plate of capacitor CRES, and their gates are connected to the comparator output port Vout.

[0016] The upper plate of capacitor CRES is connected to the comparator input terminal VIP; the lower plate is grounded.

[0017] The input terminal VIP is connected to the upper plate of capacitor CRES; the input terminal VIN is connected to the right end of the selector switch TG.

[0018] The left end of inverter INV1 is connected to the comparator output port Vout; the right end is connected to the left end of inverter INV2 and serves as the input signal terminal VOSC_B of the selector switch TG.

[0019] The right end of inverter INV2 is connected to the input signal terminal VOSC of selector switch TG and serves as the output terminal of the overall circuit.

[0020] The voltage selection switch TG is connected to the selected reference voltages VRES1 and VRES2; the right end is connected to the comparator input VIN.

[0021] The oscillator oscillates the output signal during operation, using the following method:

[0022] Step S1: If Vout is low, transistor M1 is turned on, M2 is turned off, CRES is charged, and VIP is pulled high; while the voltage selection switch TG selects the low reference voltage VRES2 according to the comparator output Vout, so VIN is low. The system output VOSC is low.

[0023] Step S2: Subsequently, since VIP>VIN, the comparator output Voutp is at a high level. At this time, transistor M2 is turned on, M1 is turned off, and CRES discharges to ground, pulling VIP to a low level. The voltage selection switch TG selects the high reference voltage VRES1 according to the comparator output Vout, so VIN is at a high level, making the system output VOSC high.

[0024] Steps S1 and S2 are repeated cyclically.

[0025] The comparator consists of current sources Ic0~IcN+1 and comparator transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, Mn1~MnN and Mp1~MpN;

[0026] The gates of comparator transistors M1 and M2 are connected to the bias power supply VB1, and their sources are grounded. The drain of M1 is connected to the source of M3; the drain of M2 is connected to the source of M4.

[0027] The gates of comparator transistors M3 and M4 are connected to the bias power supply VB2. The drain of M3 is connected to the drain of M5; the drain of M4 is connected to the drain of M6.

[0028] The gates of comparator transistors M5 and M6 are connected to the bias power supply VB3. The source of M5 is connected to the drain of M7; the source of M6 is connected to the drain of M8.

[0029] The gates of comparator transistors M7 and M8 are shorted and connected to the drains of M3 and M5, respectively, while their sources are connected to the power supply potential. The sources of transistors M9 and M10 are both connected to the lower end of the current source Ic1. The gate of M9 is connected to the VIN signal, and its drain is connected to the drain of M1. The gate of M10 is connected to the VIP signal, and its drain is connected to the drain of M2. The remaining comparator transistors Mn1~MnN and Mp1~MpN are arranged in pairs according to their serial numbers 1~N.

[0030] The sources of comparator transistors Mn1 and Mp1 are both connected to the lower end of current source Ic2. The gate of Mn1 is connected to the Caln1 signal, and its drain is connected to the drain of M1. The gate of Mp1 is connected to the Calp1 signal, and its drain is connected to the drain of M2.

[0031] The sources of comparator transistors MnN and MpN are both connected to the lower end of current source IcN+1. The gate of MnN is connected to the CalnN signal, and its drain is connected to the drain of M1. The gate of MpN is connected to the CalpN signal, and its drain is connected to the drain of M2.

[0032] The gates of comparator transistor M11 and the drains of M4 and M6 are connected together, the source is grounded, and the drain is connected to the lower end of the current source Ic0, serving as the comparator output Vout.

[0033] When VIP > VIN, the current flowing through comparator transistor M2 decreases, the drain potential of comparator transistor M2 decreases, and the drain potential of comparator transistor M1 increases; the gate potential of comparator transistor M11 decreases, and the drain potential of comparator transistor M11 increases. The input signal VIP-VIN is then amplified by the multi-stage operational amplifier structure and finally outputs a high level.

[0034] The voltage selective switch TG includes voltage selective switch transistors M1, M2, M3, and M4;

[0035] The gates of voltage selection switch transistors M1 and M4 are connected to the signal VOSC. The source of M1 is connected to the drain of M2 and connected to the reference potential VRES2. The drain of M1 is connected to the source of M2. The gate of M2 is connected to the gate of M3 and connected to the signal VOSC_B. The source of M3 is connected to the drain of M4 and connected to the reference potential VRES1. The drain of M3 is connected to the source of M4 and connected to the drain of M1 and the source of M2 as the output port OUT.

[0036] When signal VOSC is high and VOSC_B is low, voltage selection switch transistors M1 and M2 are turned off; M3 and M4 are turned on, and the output voltage OUT of output port OUT is VRES1; when signal VOSC is low and VOSC_B is high, voltage selection switch transistors M1 and M2 are turned on; voltage selection switch transistors M3 and M4 are turned off, and the output voltage OUT of output port OUT is VRES2.

[0037] The calibration signals Vn1~VnN and Vp1~VpN are calibration signals generated by external FPGA input or internal DAC.

[0038] The comparator has a multi-stage operational amplifier structure, which is a high-gain two-stage operational amplifier structure.

[0039] The oscillator proposed in this invention has a precise calibration function. Compared with traditional oscillator circuits, calibration signals Vn1~VnN and Vp1~VpN are added (calibration signals are input from an external FPGA or generated by an internal DAC). The circuit structure is simple, easy to integrate, highly operable, and has low power consumption.

[0040] This invention achieves high precision with a simple circuit structure, making it suitable for application in ADC systems. Attached Figure Description

[0041] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0042] Appendix Figure 1 This is a schematic diagram of the overall circuit of the oscillator described in this invention;

[0043] Appendix Figure 2 This is a circuit diagram of the comparator of the present invention;

[0044] Appendix Figure 3 This is a circuit diagram of the voltage selective switch TG. Detailed Implementation

[0045] As shown in the figure, a high-precision relaxation oscillator for an ADC includes current sources I1 and I2, a capacitor CRES, a comparator, inverters INV1 and INV2, an oscillator transistor group, and a voltage selection switch TG; the comparator is connected to the inverter INV1 and the capacitor CRES, and is also connected to the oscillator transistors M1 and M2.

[0046] The comparator is connected to bias power supplies VB1, VB2, and VB3, as well as calibration signal ports Caln1~CalnN and Calp1~CalpN. By connecting calibration signals Vn1~VnN and Vp1~VpN, the mismatch problem that exists during the comparison process can be calibrated.

[0047] The oscillator achieves high precision by calibrating the comparator mismatch, and the voltage selection switch selects the corresponding standard voltage according to the comparator output to achieve oscillation output.

[0048] The lower end of the current source I1 is connected to the source of the oscillator transistor M1, and the upper end is connected to the power supply; the upper end of the current source I2 is connected to the source of the oscillator transistor M2, and the lower end is grounded.

[0049] The drains of oscillator transistors M1 and M2 are connected to the comparator input port VIP and the upper plate of capacitor CRES, and their gates are connected to the comparator output port Vout.

[0050] The upper plate of capacitor CRES is connected to the comparator input terminal VIP; the lower plate is grounded.

[0051] The input terminal VIP is connected to the upper plate of capacitor CRES; the input terminal VIN is connected to the right end of the selector switch TG.

[0052] The left end of inverter INV1 is connected to the comparator output port Vout; the right end is connected to the left end of inverter INV2 and serves as the input signal terminal VOSC_B of the selector switch TG.

[0053] The right end of inverter INV2 is connected to the input signal terminal VOSC of selector switch TG and serves as the output terminal of the overall circuit.

[0054] The voltage selection switch TG is connected to the selected reference voltages VRES1 and VRES2; the right end is connected to the comparator input VIN.

[0055] The oscillator oscillates the output signal during operation, using the following method:

[0056] Step S1: If Vout is low, transistor M1 is turned on, M2 is turned off, CRES is charged, and VIP is pulled high; while the voltage selection switch TG selects the low reference voltage VRES2 according to the comparator output Vout, so VIN is low. The system output VOSC is low.

[0057] Step S2: Subsequently, since VIP>VIN, the comparator output Voutp is at a high level. At this time, transistor M2 is turned on, M1 is turned off, and CRES discharges to ground, pulling VIP to a low level. The voltage selection switch TG selects the high reference voltage VRES1 according to the comparator output Vout, so VIN is at a high level, making the system output VOSC high.

[0058] Steps S1 and S2 are repeated cyclically.

[0059] like Figure 2 As shown, the comparator consists of current sources Ic0~IcN+1 and comparator transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, Mn1~MnN and Mp1~MpN;

[0060] The gates of comparator transistors M1 and M2 are connected to the bias power supply VB1, and their sources are grounded. The drain of M1 is connected to the source of M3; the drain of M2 is connected to the source of M4.

[0061] The gates of comparator transistors M3 and M4 are connected to the bias power supply VB2. The drain of M3 is connected to the drain of M5; the drain of M4 is connected to the drain of M6.

[0062] The gates of comparator transistors M5 and M6 are connected to the bias power supply VB3. The source of M5 is connected to the drain of M7; the source of M6 is connected to the drain of M8.

[0063] The gates of comparator transistors M7 and M8 are shorted and connected to the drains of M3 and M5, respectively, while their sources are connected to the power supply potential. The sources of transistors M9 and M10 are both connected to the lower end of the current source Ic1. The gate of M9 is connected to the VIN signal, and its drain is connected to the drain of M1. The gate of M10 is connected to the VIP signal, and its drain is connected to the drain of M2. The remaining comparator transistors Mn1~MnN and Mp1~MpN are arranged in pairs according to their serial numbers 1~N.

[0064] The sources of comparator transistors Mn1 and Mp1 are both connected to the lower end of current source Ic2. The gate of Mn1 is connected to the Caln1 signal, and its drain is connected to the drain of M1. The gate of Mp1 is connected to the Calp1 signal, and its drain is connected to the drain of M2.

[0065] The sources of comparator transistors MnN and MpN are both connected to the lower end of current source IcN+1. The gate of MnN is connected to the CalnN signal, and its drain is connected to the drain of M1. The gate of MpN is connected to the CalpN signal, and its drain is connected to the drain of M2.

[0066] The gates of comparator transistor M11 and the drains of M4 and M6 are connected together, the source is grounded, and the drain is connected to the lower end of the current source Ic0, serving as the comparator output Vout.

[0067] When VIP > VIN, the current flowing through comparator transistor M2 decreases, the drain potential of comparator transistor M2 decreases, and the drain potential of comparator transistor M1 increases; the gate potential of comparator transistor M11 decreases, and the drain potential of comparator transistor M11 increases. The input signal VIP-VIN is then amplified by the multi-stage operational amplifier structure and finally outputs a high level.

[0068] like Figure 3 As shown, the voltage selection switch TG includes voltage selection switch transistors M1, M2, M3, and M4;

[0069] The gates of voltage selection switch transistors M1 and M4 are connected to the signal VOSC. The source of M1 is connected to the drain of M2 and connected to the reference potential VRES2. The drain of M1 is connected to the source of M2. The gate of M2 is connected to the gate of M3 and connected to the signal VOSC_B. The source of M3 is connected to the drain of M4 and connected to the reference potential VRES1. The drain of M3 is connected to the source of M4 and connected to the drain of M1 and the source of M2 as the output port OUT.

[0070] When signal VOSC is high and VOSC_B is low, voltage selection switch transistors M1 and M2 are turned off; M3 and M4 are turned on, and the output voltage OUT of output port OUT is VRES1; when signal VOSC is low and VOSC_B is high, voltage selection switch transistors M1 and M2 are turned on; voltage selection switch transistors M3 and M4 are turned off, and the output voltage OUT of output port OUT is VRES2.

[0071] The calibration signals Vn1~VnN and Vp1~VpN are calibration signals generated by external FPGA input or internal DAC.

[0072] The comparator has a multi-stage operational amplifier structure, which is a high-gain two-stage operational amplifier structure.

[0073] Example:

[0074] When the oscillator is operating, if Vout is low, transistor M1 is turned on, M2 is turned off, CRES is charged, and VIP is pulled high. Meanwhile, the voltage selection switch TG selects the low reference voltage VRES2 based on the comparator's output Vout, so VIN is low. The system output VOSC is low.

[0075] When the comparator is operating, if VIP > VIN, the current flowing through M2 decreases, the drain potential of M2 decreases, and the drain potential of M1 increases; conversely, the gate potential of M11 decreases, and the drain potential of M11 increases. Because the comparator uses a two-stage operational amplifier structure, it has a high gain, ultimately outputting a high level. The mismatch problem during comparison is addressed by connecting calibration signals Vn1~VnN and Vp1~VpN to the external terminals. Appropriate current sources are selected to calibrate the input current.

[0076] Subsequently, since VIP>VIN, the comparator output Voutp is at a high level. At this time, transistor M2 is turned on, M1 is turned off, and CRES discharges to ground, pulling VIP to a low level.

[0077] The voltage selection switch TG is selected based on the comparator output Vout. If the high reference voltage VRES1 is selected, then VIN will be at a high level.

[0078] The system outputs a high level VOSC signal. The relaxation oscillator then generates an oscillating output signal, repeating this cycle to achieve its function.

Claims

1. A high-precision relaxation oscillator for ADC, characterized in that: The oscillator includes current sources I1 and I2, capacitor CRES, comparator, inverters INV1 and INV2, oscillator transistor group, and voltage selection switch TG; the comparator is connected to inverter INV1 and capacitor CRES, and is also connected to transistors M1 and M2 in the oscillator transistor group. The comparator is connected to bias power supplies VB1, VB2, and VB3, as well as calibration signal ports Caln1~CalnN and Calp1~CalpN. By connecting calibration signals Vn1~VnN and Vp1~VpN, the mismatch problem that exists during the comparison process can be calibrated. The oscillator achieves high precision by calibrating the comparator mismatch, and the voltage selection switch selects the corresponding standard voltage according to the comparator output to achieve oscillation output. The lower end of the current source I1 is connected to the source of transistor M1, and the upper end is connected to the power supply; the upper end of the current source I2 is connected to the source of M2 in the oscillator transistor group, and the lower end is grounded. The drains of M1 and M2 in the oscillator transistor group are connected to the comparator input port VIP and the upper plate of capacitor CRES, and the gates are connected to the comparator output port Vout. The upper plate of capacitor CRES is connected to the comparator input terminal VIP; the lower plate is grounded. The input terminal VIP is connected to the upper plate of capacitor CRES; the input terminal VIN is connected to the right end of the selector switch TG. The left end of inverter INV1 is connected to the comparator output port Vout; the right end is connected to the left end of inverter INV2 and serves as the input signal terminal VOSC_B of the selector switch TG. The right end of inverter INV2 is connected to the input signal terminal VOSC of selector switch TG and serves as the output terminal of the overall circuit. The voltage selection switch TG is connected to the selected reference voltages VRES1 and VRES2; the right end is connected to the comparator input VIN. The voltage selection switch TG includes a voltage selection switch and transistors M1, M2, M3, and M4 of the oscillator transistor group; The gates of transistors M1 and M4 are connected to the signal VOSC. The source of M1 is connected to the drain of M2 and connected to the reference potential VRES2. The drain of M1 is connected to the source of M2. The gate of M2 is connected to the gate of M3 and connected to the signal VOSC_B. The source of M3 is connected to the drain of M4 and connected to the reference potential VRES1. The drain of M3 is connected to the source of M4 and connected to the drain of M1 and the source of M2 as the output port OUT. When signal VOSC is high and VOSC_B is low, transistors M1 and M2 are turned off; M3 and M4 are turned on, and the output voltage OUT at output port OUT is VRES1; when signal VOSC is low and VOSC_B is high, transistors M1 and M2 are turned on; transistors M3 and M4 are turned off, and the output voltage OUT at output port OUT is VRES2.

2. A high-precision relaxation oscillator for an ADC according to claim 1, characterized in that: The oscillator oscillates the output signal during operation, using the following method: Step S1: If Vout is low, transistor M1 is turned on, M2 is turned off, CRES is charged and pulls VIP high; while voltage selection switch TG selects the low reference voltage VRES2 according to the comparator output Vout, so VIN is low. The system outputs VOSC at a low level; Step S2: Subsequently, since VIP>VIN, the comparator output Voutp is at a high level. At this time, transistor M2 is turned on, M1 is turned off, and CRES discharges to ground, pulling VIP to a low level. Meanwhile, the voltage selection switch TG selects the high reference voltage VRES1 according to the comparator output Vout, so VIN is at a high level, making the system output VOSC high. Steps S1 and S2 are repeated cyclically.

3. A high-precision relaxation oscillator for an ADC according to claim 2, characterized in that: The comparator consists of current sources Ic0~IcN+1 and transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, Mn1~MnN and Mp1~MpN in the oscillator transistor group; Transistors M1 and M2 have their gates connected to the bias power supply VB1 and their sources grounded. The drain of M1 is connected to the source of M3, and the drain of M2 is connected to the source of M4. The gates of transistors M3 and M4 are connected to the bias power supply VB2, and the drain of M3 is connected to the drain of M5; the drain of M4 is connected to the drain of M6. The gates of transistors M5 and M6 are connected to the bias power supply VB3. The source of M5 is connected to the drain of M7; the source of M6 is connected to the drain of M8. Transistors M7 and M8 have their gates shorted and connected to the drains of M3 and M5, respectively, and their sources connected to the power supply potential. The sources of transistors M9 and M10 are both connected to the lower end of the current source Ic1. The gate of M9 is connected to the VIN signal, and its drain is connected to the drain of M1. The gate of M10 is connected to the VIP signal, and its drain is connected to the drain of M2. The remaining transistors Mn1~MnN and Mp1~MpN are arranged in pairs according to their serial numbers 1~N. The sources of transistors Mn1 and Mp1 are both connected to the lower end of current source Ic2. The gate of Mn1 is connected to the Caln1 signal, and its drain is connected to the drain of M1. The gate of Mp1 is connected to the Calp1 signal, and its drain is connected to the drain of M2. The sources of transistors MnN and MpN are both connected to the lower end of current source IcN+1. The gate of MnN is connected to the CalnN signal, and its drain is connected to the drain of M1. The gate of MpN is connected to the CalpN signal, and its drain is connected to the drain of M2. The gate of transistor M11 is connected to the drain of M4 and M6, the source is grounded, and the drain is connected to the lower end of the current source Ic0, serving as the comparator output Vout. When VIP > VIN, the current flowing through transistor M2 decreases, the drain potential of transistor M2 decreases, and the drain potential of transistor M1 increases. When the gate potential of transistor M11 decreases, the drain potential of transistor M11 increases, and the input signal VIP-VIN is amplified by the multi-stage operational amplifier structure and finally outputs a high level.

4. A high-precision relaxation oscillator for an ADC according to claim 1, characterized in that: The calibration signals Vn1~VnN and Vp1~VpN are calibration signals generated by external FPGA input or internal DAC.

5. A high-precision relaxation oscillator for an ADC according to claim 3, characterized in that: The comparator has a multi-stage operational amplifier structure, which is a high-gain two-stage operational amplifier structure.

Images