A current comparator circuit

Abstract

The application belongs to the technical field of circuits and relates to a current comparator circuit, which comprises a current-voltage conversion circuit, a pre-amplification circuit, a latch circuit and at least one set of gain adjustment circuits; the output end of the pre-amplification circuit is provided with a first control switch in parallel; the latch circuit is provided with a second control switch; and each set of gain adjustment circuits is provided with a third control switch. The comparator circuit realizes three working modes of an error pre-amplification circuit, a latch amplification circuit and a clear circuit through multiplexing of devices in combination with the working states of the first control switch, the second control switch and the third control switch, which is beneficial to maximizing the utilization of the area of the comparator; the gain of the current comparator is adjusted by changing the number of the closed third control switches, so as to adapt to high-precision comparison of different input currents and greatly improve the robustness of the current comparator.

Description

A current comparator circuit Technical Field

[0001] This invention belongs to the field of circuit technology, and more specifically, relates to a current comparator circuit. Background Technology

[0002] With the rapid development of integrated circuit design technology, especially after the design of high-speed and high-precision current-driven digital-to-analog converters entered the submicron and deep submicron levels, the area of ​​the current source array is constantly being compressed as the operating frequency continues to increase. However, the linearity requirement has not been reduced, making the calibration of the current source one of the important factors affecting the performance of the current source.

[0003] In circuit design, achieving high-precision current source calibration requires highly accurate current comparators for detecting errors. Existing current comparators tend to be high-speed, but their accuracy is usually either measured by external devices, which is inconvenient to use, or by sacrificing low-order calibration accuracy, thus reducing the calibration effect.

[0004] Traditional switching current comparators tend to eliminate comparator offset and improve comparison speed, but they cannot meet the accuracy requirements for calibration of current-mode DACs. Summary of the Invention

[0005] To solve the above-mentioned technical problems, the present invention provides a current comparator circuit, including a current-to-voltage conversion circuit, a pre-amplification circuit, a latching circuit, and at least one set of gain adjustment circuits.

[0006] The output terminal of the pre-amplification circuit is provided with a first control switch in parallel; the latch circuit is provided with a second control switch; and the gain adjustment circuits of each group are provided with a third control switch.

[0007] The input terminal of the current-to-voltage conversion circuit is used for differential current signal input; the output terminal of the current-to-voltage conversion circuit is electrically connected to the input terminal of the pre-amplifier circuit.

[0008] The output terminal of the pre-amplifier circuit is electrically connected to the input terminal of the latch circuit and the input terminal of the gain adjustment circuit.

[0009] When the first control switch, the second control switch, and all the third control switches are closed, the pre-amplification circuit, the first control switch, the latch circuit, and the gain adjustment circuit constitute a clearing circuit; when the clearing circuit is in operation, the comparison result output after inputting the differential current signal is zero.

[0010] When the first control switch is open, the second control switch and all the third control switches are closed, and the pre-amplification circuit, the latching circuit, and the gain adjustment circuit constitute an error pre-amplification circuit; the gain of the error pre-amplification circuit is adjusted by adjusting the number of closed third control switches.

[0011] When the first control switch is disconnected from all the third control switches, the second control switch is closed, and the pre-amplification circuit and the latch circuit constitute a latch-up amplifier circuit.

[0012] The beneficial effects of this invention are as follows: By reusing components and combining the working states of the first, second, and third control switches, this invention realizes three working modes: error pre-amplification circuit, latch storage circuit, and clearing circuit, which is beneficial to maximizing the utilization of the current comparator area; by changing the number of closed third control switches, the gain of the current comparator is adjusted to adapt to high-precision comparison of different input currents, which greatly improves the robustness of the current comparator.

[0013] Based on the above technical solution, the present invention can be further improved as follows.

[0014] Furthermore, the current-to-voltage conversion circuit includes a first MOSFET and a second MOSFET; the drain and gate of the first MOSFET are connected to the first input terminal of the current-to-voltage conversion circuit and the first input terminal of the pre-amplifier circuit; the drain and gate of the second MOSFET are connected to the second input terminal of the current-to-voltage conversion circuit and the second input terminal of the pre-amplifier circuit; the source of the first MOSFET and the source of the second MOSFET are grounded.

[0015] Furthermore, the pre-amplification circuit includes a third MOSFET and a fourth MOSFET; the latching circuit includes a fifth MOSFET and a sixth MOSFET;

[0016] The gate of the third MOS transistor is electrically connected to the first output terminal of the current-to-voltage conversion circuit; the gate of the fourth MOS transistor is electrically connected to the second output terminal of the current-to-voltage conversion circuit.

[0017] The drain of the third MOS transistor is electrically connected to the drain of the fifth MOS transistor, the gate of the sixth MOS transistor, the first terminal of the first control switch, and the first input terminal of the gain adjustment circuit; the drain of the fourth MOS transistor is electrically connected to the drain of the sixth MOS transistor, the gate of the fifth MOS transistor, the second terminal of the first control switch, and the second input terminal of the gain adjustment circuit.

[0018] The source of the third MOS transistor is grounded, as is the source of the fourth MOS transistor.

[0019] The latching circuit is equipped with a power supply; the power supply is connected to the source of the fifth MOS transistor and the source of the sixth MOS transistor via the second control switch.

[0020] Furthermore, the gain adjustment circuit includes a seventh MOSFET and an eighth MOSFET;

[0021] The gate and drain of the seventh MOS transistor are electrically connected to the first input terminal of the gain adjustment circuit and the first output terminal of the current comparator; the gate and drain of the eighth MOS transistor are electrically connected to the second input terminal of the gain adjustment circuit and the second output terminal of the current comparator.

[0022] The source of the seventh MOS transistor and the source of the eighth MOS transistor are electrically connected to the third control switch, respectively.

[0023] Furthermore, the current-to-voltage conversion circuit includes a first MOSFET, a second MOSFET, a ninth MOSFET, and a tenth MOSFET;

[0024] The gate of the ninth MOS transistor is electrically connected to the gate of the tenth MOS transistor.

[0025] The drain of the ninth MOS transistor is connected to the first input terminal of the current-to-voltage conversion circuit, the gate of the first MOS transistor, the first output terminal of the current-to-voltage conversion circuit, and the second input terminal of the pre-amplifier circuit; the drain of the tenth MOS transistor is connected to the second input terminal of the current-to-voltage conversion circuit, the gate of the second MOS transistor, the second output terminal of the current-to-voltage conversion circuit, and the first input terminal of the pre-amplifier circuit.

[0026] The source of the ninth MOS transistor is electrically connected to the drain of the first MOS transistor; the source of the tenth MOS transistor is electrically connected to the drain of the second MOS transistor.

[0027] The source of the first MOSFET and the source of the second MOSFET are grounded.

[0028] Furthermore, the pre-amplification circuit includes a third MOSFET, a fourth MOSFET, an eleventh MOSFET, and a twelfth MOSFET; the latching circuit includes a fifth MOSFET and a sixth MOSFET;

[0029] The gate of the eleventh MOS transistor is connected to the gate of the twelfth MOS transistor;

[0030] The second output terminal of the current-to-voltage conversion circuit is connected to the gate of the third MOS transistor; the first output terminal of the current-to-voltage conversion circuit is connected to the gate of the fourth MOS transistor.

[0031] The drain of the eleventh MOSFET is electrically connected to the drain of the fifth MOSFET, the gate of the sixth MOSFET, the first terminal of the first control switch, the first input terminal of the gain adjustment circuit, and the first output terminal of the current comparator; the drain of the fourth MOSFET is electrically connected to the drain of the sixth MOSFET, the gate of the fifth MOSFET, the second terminal of the first control switch, the second input terminal of the gain adjustment circuit, and the second output terminal of the current comparator.

[0032] The source of the eleventh MOS transistor is electrically connected to the drain of the third MOS transistor; the source of the twelfth MOS transistor is electrically connected to the drain of the fourth MOS transistor.

[0033] The source of the third MOS transistor is grounded, as is the source of the fourth MOS transistor.

[0034] The latching circuit is equipped with a power supply; the power supply is connected to the source of the fifth MOS transistor and the source of the sixth MOS transistor through the second control switch.

[0035] Furthermore, both the first MOS transistor and the second MOS transistor are NMOS transistors.

[0036] Furthermore, the input terminal of the current-to-voltage conversion circuit is also connected to a DC bias power supply.

[0037] Furthermore, the third MOS transistor and the fourth MOS transistor are both NMOS transistors; the fifth MOS transistor and the sixth MOS transistor are both PMOS transistors.

[0038] Furthermore, the first control switch, the second control switch, and the third control switch are all PMOS transistors. Attached Figure Description

[0039] Figure 1 is a circuit diagram of the current comparator circuit provided in Embodiment 1 of the present invention;

[0040] Figure 2 is the control timing diagram of the current comparator circuit;

[0041] Figure 3 is an extended application circuit diagram of the current comparator circuit provided in Embodiment 2 of the present invention;

[0042] Figure 4 is a circuit diagram of the current comparator circuit with DC bias power supply in Embodiment 2 of the present invention.

[0043] Icons: N1 - First MOSFET; N2 - Second MOSFET; N3 - Third MOSFET; N4 - Fourth MOSFET; P5 - Fifth MOSFET; P6 - Sixth MOSFET; N7 - Seventh MOSFET; N8 - Eighth MOSFET; N9 - Ninth MOSFET; N10 - Tenth MOSFET; P11 - Eleventh MOSFET; P12 - Twelfth MOSFET; S1 - First control switch; S2 - Second control switch; GS - DC bias power supply. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0045] Example 1

[0046] As an example, to solve the above-mentioned technical problems, this embodiment provides a current comparator circuit, including a current-to-voltage conversion circuit, a pre-amplification circuit, a latching circuit, and at least one set of gain adjustment circuits;

[0047] A first control switch is connected in parallel at the output of the pre-amplifier circuit; a second control switch is provided in the latch circuit; and a third control switch is provided in each group of gain adjustment circuits.

[0048] The input terminal of the current-to-voltage conversion circuit is used for differential current signal input; the output terminal of the current-to-voltage conversion circuit is electrically connected to the input terminal of the pre-amplifier circuit.

[0049] The output of the pre-amplifier circuit is electrically connected to the input of the latch circuit and the input of the gain adjustment circuit.

[0050] When the first control switch, the second control switch, and all the third control switches are closed, the pre-amplifier circuit, the first control switch, the latch circuit, and the gain adjustment circuit constitute the clearing circuit; when the clearing circuit is in operation, the comparison result after inputting the differential current signal is zero.

[0051] When the first control switch is open, the second control switch and all the third control switches are closed. The pre-amplifier circuit, latch circuit, and gain adjustment circuit constitute the error pre-amplifier circuit. The gain of the error pre-amplifier circuit is adjusted by adjusting the number of closed third control switches.

[0052] When the first control switch is disconnected from all the third control switches and the second control switch is closed, the pre-amplifier circuit and the latch circuit constitute the latch-up amplifier circuit.

[0053] The gain adjustment circuit can effectively improve the gain of the current comparator. Furthermore, by changing the number of closed switches in the parallel third control switch, the number of conducting gain adjustment circuits can be adjusted, thereby adjusting the current comparator gain to adapt to high-precision current comparison under different process angles and working environments.

[0054] Optionally, as shown in Figure 1, the current-to-voltage conversion circuit includes a first MOSFET N1 and a second MOSFET N2; the drain and gate of the first MOSFET N1 are connected to the first input terminal I1 of the current-to-voltage conversion circuit and the first input terminal of the pre-amplifier circuit; the drain and gate of the second MOSFET N2 are connected to the second input terminal I2 of the current-to-voltage conversion circuit and the second input terminal of the pre-amplifier circuit; the source of the first MOSFET N1 and the source of the second MOSFET N2 are grounded.

[0055] Optionally, as shown in Figure 1, the pre-amplifier circuit includes a third MOSFET N3 and a fourth MOSFET N4; the latch circuit includes a fifth MOSFET P5 and a sixth MOSFET P6.

[0056] The gate of the third MOSFET N3 is electrically connected to the first output terminal of the current-to-voltage conversion circuit; the gate of the fourth MOSFET N4 is electrically connected to the second output terminal of the current-to-voltage conversion circuit.

[0057] The drain of the third MOSFET N3 is electrically connected to the drain of the fifth MOSFET P5, the gate of the sixth MOSFET P6, the first terminal of the first control switch S1, and the first input terminal of the gain adjustment circuit; the drain of the fourth MOSFET N4 is electrically connected to the drain of the sixth MOSFET P6, the gate of the fifth MOSFET N5, the second terminal of the first control switch S1, and the second input terminal of the gain adjustment circuit.

[0058] The source of the third MOSFET N3 and the source of the fourth MOSFET N4 are grounded;

[0059] The latching circuit is equipped with a power supply; the power supply is connected to the source of the fifth MOSFET P5 and the source of the sixth MOSFET P6 through the second control switch S2.

[0060] The output terminals of the current comparator are OUTP and OUTN.

[0061] Optionally, as shown in Figure 1, the gain adjustment circuit includes a seventh MOSFET P7 and an eighth MOSFET P8.

[0062] The gate and drain of the seventh MOSFET P7 are electrically connected to the first input terminal of the gain adjustment circuit and the first output terminal OUTP of the current comparator; the gate and drain of the eighth MOSFET P8 are electrically connected to the second input terminal of the gain adjustment circuit and the second output terminal OUTN of the current comparator circuit.

[0063] The source of the seventh MOSFET P7 and the source of the eighth MOSFET P8 are electrically connected to the third control switch S3, respectively.

[0064] The gain adjustment circuit also includes a DC power supply; the DC power supply is connected to the source of the seventh MOSFET P7 and the source of the eighth MOSFET P8 via a third control switch S3. The connection state of the sources of the seventh MOSFET P7 and the eighth MOSFET P8 is controlled by the third control switch S3, thereby controlling the operating state of the gain adjustment circuit.

[0065] In practical applications, by changing the number of closed third control switches S3, the number of conducting gain adjustment circuits is adjusted, thereby adjusting the current comparator gain to adapt to high-precision current comparison under different process angles and working environments.

[0066] The working principle of this current comparator circuit is as follows:

[0067] The first MOSFET N1 and the second MOSFET N2 realize the differential current signal input and current-voltage signal conversion; after the differential current signal is converted into a current difference, it is sent to the pre-amplifier circuit for amplification; the circuit state is changed by various control switches to realize the comparison output.

[0068] When the first control switch S1 is open, and the second control switch S2 and all the third control switches S31-S3N are closed, the pre-amplifier circuit, the latch circuit, and the gain adjustment circuit constitute the latch-up amplifier circuit. That is, the error pre-amplifier circuit composed of the third MOSFET N3, the fourth MOSFET N4, the fifth MOSFET P5, the sixth MOSFET P6, and the gain adjustment circuit is turned on. When the first control switch S1 is open, the second control switch S2 is closed, and all the third control switches S31-S3N are open, the pre-amplifier circuit and the latch circuit constitute the latch-up amplifier circuit. That is, the third MOSFET N3, the fourth MOSFET N4, the fifth MOSFET P5, and the sixth MOSFET P6 constitute the latch-up amplifier circuit. When the first control switch S1, the second control switch S2, and all the third control switches S31-S3N are closed, the pre-amplifier circuit, the first control switch S1, the latch circuit, and the gain adjustment circuit constitute the clear circuit. At this time, the output of the current comparator circuit is zero.

[0069] Optionally, both the first control switch S1 and the second control switch S2 are PMOS transistors.

[0070] Optionally, both the first MOSFET N1 and the second MOSFET N2 are NMOS transistors.

[0071] Specifically, this structure requires strict adherence to corresponding timing controls to complete the comparison function. The timing controls are as follows:

[0072] When a differential current signal is input, closing the first control switch S1, the second control switch S2, and the third control switch S3 clears the output to zero and waits until the output stabilizes. Opening the first control switch S1 and closing the second and third control switches S2 activates the error pre-amplifier circuit, which waits until the output stabilizes before entering the pre-amplifier state. Opening the first and third control switches S1 and closing the second control switch S2 activates the latch-up amplification state, waiting for the output signal to stabilize before obtaining the target output signal. Repeating this timing control allows for complex comparison of the differential input signal. Only when the first control switch S1 is closed does the entire current comparator shut down and stop working. The specific control timing diagram is shown in Figure 2.

[0073] This comparator circuit, through the multiplexing of components and the combined operating states of the first, second, and third control switches, realizes three operating modes: error pre-amplification circuit, latch-up circuit, and clear circuit. This is beneficial for maximizing the area utilization of the current comparator. By changing the number of closed third control switches, the gain of the current comparator can be adjusted to adapt to high-precision comparison of different input currents, greatly improving the robustness of the current comparator.

[0074] Example 2

[0075] Based on the working principle shown in Embodiment 1 of the present invention, an embodiment of the present invention also provides a current comparator circuit, including a current-to-voltage conversion circuit, a pre-amplification circuit, a latching circuit, and at least one set of gain adjustment circuits.

[0076] A first control switch is connected in parallel at the output of the pre-amplifier circuit; a second control switch is provided in the latch circuit; and a third control switch is provided in each group of gain adjustment circuits.

[0077] The input terminal of the current-to-voltage conversion circuit is used for differential current signal input; the output terminal of the current-to-voltage conversion circuit is electrically connected to the input terminal of the pre-amplifier circuit.

[0078] The output of the pre-amplifier circuit is electrically connected to the input of the latch circuit and the input of the gain adjustment circuit.

[0079] When the first control switch, the second control switch, and all the third control switches are closed, the pre-amplifier circuit, the first control switch, the latch circuit, and the gain adjustment circuit constitute the clearing circuit; when the clearing circuit is in operation, the comparison result after inputting the differential current signal is zero.

[0080] When the first control switch is open, the second control switch and all the third control switches are closed. The pre-amplifier circuit, latch circuit, and gain adjustment circuit constitute the error pre-amplifier circuit. The gain of the gain adjustment circuit is adjusted by adjusting the number of closed third control switches.

[0081] When the first control switch is disconnected from all the third control switches and the second control switch is closed, the pre-amplifier circuit and the latch circuit constitute the latch-up amplifier circuit.

[0082] Optionally, in practical applications, compared to embodiment 1, the current-to-voltage conversion circuit can be expanded into the circuit shown in Figure 3, which includes a first MOSFET N1, a second MOSFET N2, a ninth MOSFET N9, and a tenth MOSFET N10.

[0083] The gate of the ninth MOSFET N9 is electrically connected to the gate of the tenth MOSFET N10;

[0084] The drain of the ninth MOSFET N9 is connected to the first input terminal I1 of the current-to-voltage conversion circuit, the gate of the first MOSFET N1, the first output terminal of the current-to-voltage conversion circuit, and the second input terminal of the pre-amplifier circuit; the drain of the tenth MOSFET N10 is connected to the second input terminal I2 of the current-to-voltage conversion circuit, the gate of the second MOSFET N2, the second output terminal of the current-to-voltage conversion circuit, and the first input terminal of the pre-amplifier circuit.

[0085] The source of the ninth MOSFET N9 is electrically connected to the drain of the first MOSFET N1; the source of the tenth MOSFET N10 is electrically connected to the drain of the second MOSFET N2.

[0086] The source of the first MOSFET N1 and the source of the second MOSFET N2 are grounded. The output terminals of the current comparator are OUTP and OUTN.

[0087] Optionally, in practical applications, compared to Embodiment 1, the latching and amplification circuit can be expanded into the circuit shown in Figure 3. The pre-amplification circuit includes a third MOS transistor N3, a fourth MOS transistor N4, an eleventh MOS transistor N11, and a twelfth MOS transistor N12; the latching circuit includes a fifth MOS transistor P5 and a sixth MOS transistor P6.

[0088] The gate of the eleventh MOSFET N11 is connected to the gate of the twelfth MOSFET N12;

[0089] The second output terminal of the current-to-voltage conversion circuit is connected to the gate of the third MOSFET N3; the first output terminal of the current-to-voltage conversion circuit is connected to the gate of the fourth MOSFET N4.

[0090] The drain of the eleventh MOSFET N11 is electrically connected to the drain of the fifth MOSFET P5, the gate of the sixth MOSFET P6, the first terminal of the first control switch S1, the first input terminal of the gain adjustment circuit, and the first output terminal OUTP of the current comparator circuit; the drain of the twelfth MOSFET N12 is electrically connected to the drain of the sixth MOSFET P6, the gate of the fifth MOSFET P5, the second terminal of the first control switch S1, the second input terminal of the gain adjustment circuit, and the second output terminal OUTN of the current comparator circuit.

[0091] The source of the eleventh MOSFET N11 is electrically connected to the drain of the third MOSFET N3; the source of the twelfth MOSFET N12 is electrically connected to the drain of the fourth MOSFET N4.

[0092] The source of the third MOSFET N3 and the source of the fourth MOSFET N4 are grounded;

[0093] The latching circuit is equipped with a power supply; the power supply is connected to the source of the fifth MOSFET P5 and the source of the sixth MOSFET P6 through the second control switch S2.

[0094] Optionally, the first MOSFET N1 and the second MOSFET N2 are both NMOS transistors. Optionally, the third MOSFET N3 and the fourth MOSFET N4 are both NMOS transistors; the fifth MOSFET P5 and the sixth MOSFET P6 are both PMOS transistors.

[0095] The gain adjustment circuit also includes a DC power supply; the DC power supply is connected to the source of the seventh MOSFET P7 and the source of the eighth MOSFET P8 via a third control switch S3. The connection state of the sources of the seventh MOSFET P7 and the eighth MOSFET P8 is controlled by the third control switch S3, thereby controlling the operating state of the gain adjustment circuit.

[0096] In practical applications, by changing the number of closed third control switches S3, the number of conducting gain adjustment circuits is adjusted, thereby adjusting the gain of the comparator circuit to adapt to high-precision comparison under different input currents.

[0097] The working principle of this current comparator circuit is as follows:

[0098] The first MOSFET N1, the ninth MOSFET N9, the second MOSFET N2, and the tenth MOSFET N10 realize the differential current signal input and current-voltage signal conversion; after the differential current signal is converted into a current-voltage signal, the current difference is converted into a voltage difference and sent to the pre-amplifier circuit for amplification; the circuit state is changed by various control switches to realize the comparison output.

[0099] When the first control switch S1 is open and the second control switch S2 and all the third control switches S31-S3N are closed, the pre-amplifier circuit, latch circuit, and gain adjustment circuit constitute the latch-up amplifier circuit, that is, the error pre-amplifier circuit composed of the third MOSFET N3, the fourth MOSFET N4, the eleventh MOSFET N11, the twelfth MOSFET N12, the fifth MOSFET P5, the sixth MOSFET P6, and the gain adjustment circuit is turned on; when the first control switch S1 is open, the second control switch S2 is closed, and all the third control switches S31-S3N are closed, the error pre-amplifier circuit is turned on. When all switches S1-S3N are open, the pre-amplifier circuit and the latch circuit form a latch-up circuit, i.e., the third MOSFET N3, the fourth MOSFET N4, the eleventh MOSFET N11, the twelfth MOSFET N12, the fifth MOSFET P5, and the sixth MOSFET P6 form a latch-up circuit. When the first control switch S1, the second control switch S2, and all the third control switches S31-S3N are closed, the pre-amplifier circuit, the first control switch S1, the latch circuit, and the gain adjustment circuit form a clearing circuit. At this time, the output of the current comparator circuit is zero.

[0100] Optionally, the first control switch S1, the second control switch S2, and the third control switch S3 are all PMOS transistors.

[0101] Optionally, as shown in Figure 4, the input terminal of the current-to-voltage conversion circuit is also connected to a DC bias power supply GS.

[0102] In practical applications, adding a DC bias power supply GS to the input terminal of the current-to-voltage conversion circuit allows the circuit to output comparison results even when the input signal is very small.

[0103] This comparator circuit, through the multiplexing of components and the combined operating states of the first, second, and third control switches, realizes three operating modes: error pre-amplification circuit, latch-up circuit, and clear circuit. This is beneficial for maximizing the area utilization of the current comparator. By changing the number of closed third control switches, the gain of the current comparator can be adjusted to adapt to high-precision comparison of different input currents, greatly improving the robustness of the current comparator.

[0104] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A current comparator circuit, characterized in that, The circuit includes a current-to-voltage conversion circuit, a pre-amplifier circuit, a latch circuit, and at least one set of gain adjustment circuits. A first control switch is connected in parallel to the output of the pre-amplifier circuit. A second control switch is provided in the latch circuit. Each set of gain adjustment circuits is equipped with a third control switch. The input of the current-to-voltage conversion circuit is used for differential current signal input. The output of the current-to-voltage conversion circuit is electrically connected to the input of the pre-amplifier circuit. The current-to-voltage conversion circuit includes a first MOSFET and a second MOSFET. The drain and gate of the first MOSFET are connected to the first input of the current-to-voltage conversion circuit and the first input of the pre-amplifier circuit. The drain and gate of the second MOSFET are connected to the second input of the current-to-voltage conversion circuit. The pre-amplification circuit has a second input terminal; the source of the first MOS transistor and the source of the second MOS transistor are grounded; the output terminal of the pre-amplification circuit is electrically connected to the input terminal of the latch circuit and the input terminal of the gain adjustment circuit; the gain adjustment circuit includes a seventh MOS transistor and an eighth MOS transistor; the gate and drain of the seventh MOS transistor are electrically connected to the first input terminal of the gain adjustment circuit and the first output terminal of the current comparator; the gate and drain of the eighth MOS transistor are electrically connected to the second input terminal of the gain adjustment circuit and the second output terminal of the current comparator; the source of the seventh MOS transistor and the source of the eighth MOS transistor are respectively electrically connected to the third control switch; the gain adjustment circuit is also provided with a DC power supply. The DC power supply is connected to the source of the seventh MOSFET P7 and the source of the eighth MOSFET P8 via the third control switch S3. The number of closed third control switches S3 is adjusted to control the number of conducting gain adjustment circuits, thus adjusting the current comparator gain. When the first control switch, the second control switch, and all the third control switches are closed, the pre-amplifier circuit, the first control switch, the latch circuit, and the gain adjustment circuit constitute a clearing circuit. In the clearing circuit's operating state, the comparison result output after inputting the differential current signal is zero. When the first control switch is open and the second control switch and all the third control switches are closed, the pre-amplifier circuit, the latch circuit, and the gain adjustment circuit constitute an error pre-amplifier circuit. The gain of the error pre-amplifier circuit is adjusted by regulating the number of closed third control switches. When the first control switch and all the third control switches are open and the second control switch is closed, the pre-amplifier circuit and the latch circuit constitute a latch-up amplifier circuit.

2. The current comparator circuit according to claim 1, characterized in that, The pre-amplification circuit includes a third MOSFET and a fourth MOSFET; the latch circuit includes a fifth MOSFET and a sixth MOSFET; the gate of the third MOSFET is electrically connected to the first output terminal of the current-to-voltage conversion circuit; the gate of the fourth MOSFET is electrically connected to the second output terminal of the current-to-voltage conversion circuit; the drain of the third MOSFET is electrically connected to the drain of the fifth MOSFET, the gate of the sixth MOSFET, the first terminal of the first control switch, and the first input terminal of the gain adjustment circuit; the drain of the fourth MOSFET is electrically connected to the drain of the sixth MOSFET, the gate of the fifth MOSFET, the second terminal of the first control switch, and the second input terminal of the gain adjustment circuit; the source of the third MOSFET is grounded to the source of the fourth MOSFET; the latch circuit is provided with a power supply; the power supply is connected to the source of the fifth MOSFET and the source of the sixth MOSFET through the second control switch.

3. The current comparator circuit according to claim 1, characterized in that, The current-to-voltage conversion circuit includes a first MOSFET, a second MOSFET, a ninth MOSFET, and a tenth MOSFET; the gate of the ninth MOSFET is electrically connected to the gate of the tenth MOSFET; the drain of the ninth MOSFET is connected to the first input terminal of the current-to-voltage conversion circuit, the gate of the first MOSFET, the first output terminal of the current-to-voltage conversion circuit, and the second input terminal of the pre-amplifier circuit; the drain of the tenth MOSFET is connected to the second input terminal of the current-to-voltage conversion circuit, the gate of the second MOSFET, the second output terminal of the current-to-voltage conversion circuit, and the first input terminal of the pre-amplifier circuit; the source of the ninth MOSFET is electrically connected to the drain of the first MOSFET; the source of the tenth MOSFET is electrically connected to the drain of the second MOSFET; the sources of the first MOSFET and the second MOSFET are grounded.

4. The current comparator circuit according to claim 1, characterized in that, The pre-amplification circuit includes a third MOSFET, a fourth MOSFET, an eleventh MOSFET, and a twelfth MOSFET; the latching circuit includes a fifth MOSFET and a sixth MOSFET; the gate of the eleventh MOSFET is electrically connected to the gate of the twelfth MOSFET; the second output terminal of the current-to-voltage conversion circuit is connected to the gate of the third MOSFET; the first output terminal of the current-to-voltage conversion circuit is connected to the gate of the fourth MOSFET; the drain of the eleventh MOSFET is connected to the drain of the fifth MOSFET, the gate of the sixth MOSFET, the first terminal of the first control switch, the first input terminal of the gain adjustment circuit, and the first output terminal of the current comparator. The output terminals are electrically connected; the drain of the twelfth MOS transistor is electrically connected to the drain of the sixth MOS transistor, the gate of the fifth MOS transistor, the second terminal of the first control switch, the second input terminal of the gain adjustment circuit, and the second output terminal of the current comparator; the source of the eleventh MOS transistor is electrically connected to the drain of the third MOS transistor; the source of the twelfth MOS transistor is electrically connected to the drain of the fourth MOS transistor; the source of the third MOS transistor and the source of the fourth MOS transistor are grounded; the latch circuit is provided with a power supply; the power supply is connected to the source of the fifth MOS transistor and the source of the sixth MOS transistor through the second control switch.

5. A current comparator circuit according to any one of claims 1 or 3, characterized in that, Both the first MOS transistor and the second MOS transistor are NMOS transistors.

6. A current comparator circuit according to any one of claims 1-4, characterized in that, The input terminal of the current-to-voltage conversion circuit is also connected to a DC bias power supply.

7. A current comparator circuit according to claim 2 or 4, characterized in that, The third and fourth MOS transistors are both NMOS transistors; the fifth and sixth MOS transistors are both PMOS transistors.

8. A current comparator circuit according to any one of claims 1-4, characterized in that, The first control switch, the second control switch, and the third control switch are all PMOS transistors.

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