An ISFET sensor chip and an ISFET sensor

Abstract

The present invention discloses an ISFET sensor chip and an ISFET sensor, which are applied to the technical field of sensor chips, and include a substrate, an ISFET transistor, a sensitive film and a sensor chip integrated circuit arranged on the substrate; the substrate includes a top layer and an intermediate layer below the top layer; the sensitive film is located on the top layer, the ISFET transistor is arranged on the intermediate layer, and the sensitive film is connected to the gate of the ISFET transistor through a via; the sensor chip integrated circuit is arranged on the intermediate layer, and the sensitive film covers at least a part of the sensor chip integrated circuit. By arranging the sensitive film on the top layer of the substrate and arranging the ISFET transistor and the sensor chip integrated circuit on the intermediate layer of the substrate, the sensitive film and the sensor chip integrated circuit are distributed along the thickness direction in the substrate, so that the area of the ISFET sensor chip can be effectively reduced in the horizontal direction, and the miniaturization of the ISFET sensor chip is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of sensor chips, and particularly to an ISFET sensor chip and an ISFET sensor. Background Art

[0002] Biochemical sensors based on Ion Sensitive Field Effect Transistors (ISFETs) have attracted the attention and research of many scientific researchers. Currently, ISFET sensors can be used to detect parameters such as pH, detect specific ions by modifying a specific sensitive membrane sensitive to specific charged ions on the surface of the floating gate, then detect specific ions, perform gene sequencing and single nucleotide polymorphism detection through DNA polymerization reactions, etc., modify enzymes, antigens, antibodies, etc. on the sensitive membrane to promote the reaction of the sample to be measured to generate H+ so as to detect blood glucose, lactic acid, proteins, etc. The working principle of ISFET is to use surface modification technology to enable its sensitive membrane to adsorb specific charged ions, and these charged ions will change the channel conductivity of the ISFET device, thereby affecting the device threshold voltage. Therefore, the concentration of the sample to be measured can be indirectly reflected by detecting the drain-source current of the device. ISFETs have the characteristics of small size, fast response, low output impedance, easy integration, and convenient application.

[0003] However, at the present stage, the area of ISFET sensor chips is usually large and the chip cost is high. Therefore, how to miniaturize ISFET sensor chips is an urgent problem to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of the present invention is to provide an ISFET sensor chip with a smaller area; another purpose of the present invention is to provide an ISFET sensor with a smaller area.

[0005] To solve the above technical problems, the present invention provides an ISFET sensor chip, including a substrate, an ISFET transistor, a sensitive membrane, and a sensor chip integrated circuit disposed on the substrate; the substrate includes a top layer and an intermediate layer below the top layer;

[0006] The sensitive membrane is located on the top layer, the ISFET transistor is disposed on the intermediate layer, and the sensitive membrane is connected to the gate of the ISFET transistor through a via; the sensor chip integrated circuit is disposed on the intermediate layer, and the sensitive membrane covers at least a part of the sensor chip integrated circuit.

[0007] Optionally, the metal structure connected to the gate in the ISFET transistor is disposed in the sub-top metal layer closest to the top layer in the intermediate layer;

[0008] The sensitive film is connected to the metal structure in the secondary top metal layer through the via hole.

[0009] Optionally, the sensitive film includes a plurality of sensitive units, and the plurality of sensitive units are arranged in an array on the top layer.

[0010] Optionally, a plurality of the ISFET transistors are included, and the plurality of ISFET transistors are arranged in an array on the intermediate layer. The sensitive unit is connected to the corresponding ISFET transistor through the via hole.

[0011] Optionally, the plurality of sensitive units form a sensitive unit array, and the plurality of ISFET transistors form an ISFET array. The ISFET array is arranged in the central area of the sensitive unit array.

[0012] Optionally, the gates of the ISFET transistors located at the edge of the ISFET array are connected to an external voltage.

[0013] Optionally, the sensor chip integrated circuit includes any one or any combination of the following:

[0014] Row selection circuit, column selection circuit, signal reading circuit, bias circuit.

[0015] Optionally, the sensor chip integrated circuit and the ISFET transistor are arranged in parallel in the intermediate layer.

[0016] Optionally, the sensitive film covers all of the sensor chip integrated circuit.

[0017] The present invention also provides an ISFET sensor, including the ISFET sensor chip as described in any one of the above.

[0018] An ISFET sensor chip provided by the present invention includes a substrate, an ISFET transistor, a sensitive film, and a sensor chip integrated circuit disposed on the substrate; the substrate includes a top layer and an intermediate layer below the top layer; the sensitive film is located on the top layer, the ISFET transistor is disposed on the intermediate layer, and the sensitive film is connected to the gate of the ISFET transistor through a via hole; the sensor chip integrated circuit is disposed on the intermediate layer, and the sensitive film covers at least a part of the sensor chip integrated circuit.

[0019] By disposing the sensitive film on the top layer of the substrate and disposing the ISFET transistor and the sensor chip integrated circuit on the intermediate layer of the substrate, the sensitive film and the sensor chip integrated circuit are distributed in the thickness direction of the substrate, and the sensitive film covers at least a part of the sensor chip integrated circuit, which can effectively reduce the area of the ISFET sensor chip in the horizontal direction, increase the space utilization rate in the substrate, and realize the miniaturization of the ISFET sensor chip.

[0020] The present invention also provides an ISFET sensor, which also has the above beneficial effects and will not be elaborated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0022] Figure 1 It is a schematic structural diagram of an ISFET sensor chip provided by an embodiment of the present invention;

[0023] Figure 2 It is a schematic structural diagram of a specific ISFET sensor chip provided by an embodiment of the present invention;

[0024] Figure 3 For Figure 2 the distribution schematic diagram of the ISFET array and the sensitive unit array in

[0025] Figure 4 It is a performance diagram of an ISFET sensor chip provided by an embodiment of the present invention.

[0026] In the figure: 1. Sensitive film, 11. Sensitive unit, 2. ISFET transistor, 21. ISFET array, 3. Sensor chip integrated circuit. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0027] The core of the present invention is to provide an ISFET sensor chip. In the prior art, since the ISFET sensor needs to use surface modification technology to modify the sensitive film, and due to limited precision during surface modification, it is necessary to ensure that the area of the ISFET sensitive region is large enough. The required sensitive region area is about dozens of times the layout area of a common ISFET device. In the ISFET chips in the prior art, generally, the ISFET array is placed in the middle of the chip, and the signal output circuit, row and column selection circuit, bias circuit, etc. are surrounded around it. Therefore, the circuit part occupies a part of the chip area, which results in a relatively high chip cost.

[0028] An ISFET sensor chip provided by the present invention includes a substrate, an ISFET transistor, a sensitive film, and a sensor chip integrated circuit disposed on the substrate; the substrate includes a top layer and an intermediate layer below the top layer; the sensitive film is located on the top layer, the ISFET transistor is disposed on the intermediate layer, and the sensitive film is connected to the gate of the ISFET transistor through a via; the sensor chip integrated circuit is disposed on the intermediate layer, and the sensitive film covers at least a part of the sensor chip integrated circuit.

[0029] By disposing the sensitive film on the top layer of the substrate and disposing the ISFET transistor and the sensor chip integrated circuit on the intermediate layer of the substrate, the sensitive film and the sensor chip integrated circuit are distributed in the thickness direction in the substrate, and the sensitive film covers at least a part of the sensor chip integrated circuit, which can effectively reduce the area of the ISFET sensor chip in the horizontal direction, increase the space utilization rate in the substrate, and realize the miniaturization of the ISFET sensor chip.

[0030] To enable those skilled in the art to better understand the solution of the present invention, the present invention will be further described in detail below with reference to the drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0031] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of an ISFET sensor chip provided by an embodiment of the present invention.

[0032] See Figure 1 In the embodiment of the present invention, the ISFET sensor chip includes a substrate, an ISFET transistor 2, a sensitive film 1, and a sensor chip integrated circuit 3 disposed on the substrate; the substrate includes a top layer and an intermediate layer below the top layer; the sensitive film 1 is located on the top layer, the ISFET transistor 2 is disposed on the intermediate layer, the sensitive film 1 is connected to the gate of the ISFET transistor 2 through a via; the sensor chip integrated circuit 3 is disposed on the intermediate layer, and the sensitive film 1 covers at least a part of the sensor chip integrated circuit 3.

[0033] The above-mentioned substrate is usually divided into a multi-layer composite structure, which specifically includes a top layer and an intermediate layer below the top layer. Usually, a metal layer is provided between the layers of the substrate for setting the structure and wiring of the ISFET sensor chip. The specific structure and material of the substrate can refer to the prior art and will not be elaborated here.

[0034] The top layer of the above-mentioned substrate is usually provided with a sensitive film 1. In the embodiments of the present invention, the sensitive film 1 can be modified. According to the different functions of the ISFET sensor chip, the modification of the sensitive film 1 can also be different. For example, to achieve the detection of pH, a specific sensitive film sensitive to specific charged ions is modified on the surface of the floating gate, and then specific ions are detected; gene sequencing and single nucleotide polymorphism detection are carried out through DNA polymerization reaction, etc.; enzymes, antigen-antibodies, etc. are modified on the sensitive film to promote the reaction of the sample to be measured to generate H+ so as to detect blood glucose, lactic acid, proteins, etc. The specific content can be set according to the actual situation and will not be specifically limited here. The above-mentioned sensitive film 1 is located on the top layer of the substrate and usually needs to be in contact with the external solution to achieve its measurement function.

[0035] The above-mentioned intermediate layer is the other layer structure of the substrate except the top layer. Usually, the intermediate layer is composed of multiple layers stacked along the thickness direction, and the metal layer therein is used to set up various circuits, traces, devices, etc. In the embodiments of the present invention, an ISFET transistor 2 and a sensor chip integrated circuit 3 need to be set in the intermediate layer. The structure of the above-mentioned ISFET transistor 2 usually includes structures such as a source electrode, a gate electrode, and a drain electrode. The specific structure of the ISFET transistor 2 can refer to the prior art and will not be elaborated here.

[0036] Since the above-mentioned sensitive film 1 is set on the top layer and the ISFET transistor 2 is set in the intermediate layer, it means that the sensitive film 1 and the ISFET transistor 2 are set in different layers of the substrate. Usually, the ISFET transistor 2 is set below the sensitive film 1. In the embodiments of the present invention, the sensitive film 1 needs to be connected to the gate electrode of the ISFET transistor 2 through a via hole, so as to realize the measurement of the external solution by the ISFET transistor 2 based on the sensitive film 1. The above-mentioned via hole can be a through hole or other structures, and will not be specifically limited here.

[0037] The above-mentioned sensor chip integrated circuit 3 is the corresponding supporting circuit that needs to be set in the ISFET sensor chip. The sensor chip integrated circuit 3 needs to be connected to the ISFET transistor 2 to achieve the corresponding functions. In the embodiments of the present invention, the sensor chip integrated circuit 3 usually includes any one or any combination of the following: a row selection circuit, a column selection circuit, a signal reading circuit, and a bias circuit. The specific circuits and functional modules included in the sensor chip integrated circuit 3 can be set according to the actual situation and will not be specifically limited here.

[0038] The above-mentioned sensor chip integrated circuit 3 is specifically arranged in the middle layer of the substrate, that is, the sensor chip integrated circuit 3 is also specifically arranged on a different layer of the substrate from the sensitive film 1. Specifically, the sensitive film 1 is arranged on the upper layer of the substrate, while the sensor chip integrated circuit 3 is arranged on the lower layer of the sensitive film 1. Therefore, in the embodiment of the present invention, the sensitive film 1 can cover the sensor chip integrated circuit 3, thereby reducing the area occupied by the sensor chip integrated circuit 3 in the horizontal direction. Specifically, in the embodiment of the present invention, the sensitive film 1 covers at least part of the sensor chip integrated circuit 3 to reduce the area of the ISFET sensor chip. Usually, the sensitive film 1 covers the entire sensor chip integrated circuit 3, that is, the sensor chip integrated circuit 3 is arranged entirely under the sensitive film 1, so as to minimize the area required for the ISFET sensor chip as much as possible.

[0039] It should be noted that since the area occupied by the sensitive film 1 is usually much larger than the area occupied by the ISFET transistor 2, there is enough space under the sensitive film 1 for arranging the sensor chip integrated circuit 3.

[0040] Specifically, in the embodiment of the present invention, the metal structure connected to the gate in the ISFET transistor 2 is arranged in the sub-top metal layer closest to the top layer in the middle layer; the sensitive film 1 is connected to the metal structure in the sub-top metal layer through the via hole. The sub-top metal layer closest to the top layer in the above-mentioned middle layer is the N top metal -1 layer, that is, in the embodiment of the present invention, a metal structure will be specifically arranged in the N top metal -1 layer. The above-mentioned metal structure is connected to the gate of the ISFET transistor 2, which is equivalent to extending the gate of the ISFET transistor 2 to the N top metal -1 layer. And the above-mentioned sensitive film 1 is connected to the metal structure in the sub-top metal layer through the via hole, so as to realize the connection between the sensitive film 1 and the gate of the ISFET transistor 2.

[0041] An ISFET sensor chip provided by an embodiment of the present invention, by arranging the sensitive film 1 on the top layer of the substrate, and arranging the ISFET transistor 2 and the sensor chip integrated circuit 3 on the middle layer of the substrate, enables the sensitive film 1 and the sensor chip integrated circuit 3 to be distributed in the thickness direction of the substrate, and enables the sensitive film 1 to cover at least part of the sensor chip integrated circuit 3, which can effectively reduce the area of the ISFET sensor chip in the horizontal direction, increase the space utilization rate in the substrate, and realize the miniaturization of the ISFET sensor chip.

[0042] The specific structure of an ISFET sensor chip provided by the present invention will be introduced in detail in the following embodiments of the invention.

[0043] Please refer to Figure 2 and Figure 3 , Figure 2 which is a schematic structural diagram of a specific ISFET sensor chip provided by an embodiment of the present invention; Figure 3 is Figure 2 a schematic diagram of the distribution of the ISFET array and the sensitive unit array in

[0044] Different from the above-mentioned embodiment of the invention, the embodiment of the present invention further defines the structure of the ISFET sensor chip on the basis of the above-mentioned embodiment of the invention. The rest of the content has been introduced in detail in the above-mentioned embodiment of the invention and will not be repeated here.

[0045] Refer to Figure 2 , in the embodiment of the present invention, the sensitive film 1 includes a plurality of sensitive units 11, and the plurality of sensitive units 11 are arranged in an array on the top layer. The above-mentioned sensitive unit 11 generally includes a metal layer on the surface of the top layer and a passivation layer on the surface of the metal layer. In the embodiment of the present invention, the above-mentioned structure is determined as the sensitive unit 11, and the plurality of sensitive units 11 are arranged in an array to form the sensitive film 1. The above-mentioned via hole specifically connects the metal layer on the top layer of the substrate to the gate of the corresponding ISFET transistor 2, which is equivalent to extending the gate of the ISFET transistor 2 to the top layer for measurement based on the sensitive film 1.

[0046] In the embodiment of the present invention, it generally includes a plurality of the ISFET transistors 2, and the plurality of the ISFET transistors 2 are arranged in an array on the intermediate layer, and the sensitive unit 11 is connected to the corresponding ISFET transistor 2 through the via hole. The above-mentioned ISFET transistor 2 and the sensitive unit 11 are generally in a one-to-one correspondence relationship, and the corresponding sensitive unit 11 and the ISFET transistor 2 are connected through a via hole.

[0047] Since the size of the above-mentioned ISFET transistor 2 is generally smaller than the size of the sensitive film 1, the size of the ISFET array 21 formed by the plurality of ISFET transistors 2 is generally smaller than the sensitive unit array formed by the plurality of the sensitive units 11. In order to generally reduce the required lines for connecting between the sensitive film 1 and the corresponding ISFET transistor 2, the above-mentioned ISFET array 21 is arranged in the central area of the sensitive unit array to reduce the distance between the ISFET transistor 2 and the corresponding sensitive film 1. As Figure 3 shown, taking the column vector of m×1 as an example, where the solid line frame is the sensitive unit 11, the dotted line frame is the ISFET transistor 2, and the m×1 ISFET array 21 is distributed in the center of the m×1 sensitive unit array, and the distribution direction of the ISFET array 21 is the same as the distribution direction of the sensitive unit array.

[0048] Specifically, in the embodiment of the present invention, the gates of the ISFET transistors 2 located at the edge of the ISFET array 21 are connected to an external voltage. For the convenience of chip packaging and testing after tape-out, the gates of the ISFET transistors 2 at the edge of the ISFET array 21, such as the gates of the outermost two rings of ISFET transistors 2, can be connected to an external voltage for electrical test to verify the chip performance.

[0049] Specifically, in the embodiment of the present invention, the sensor chip integrated circuit 3 and the ISFET transistor 2 are arranged in parallel in the intermediate layer. That is, in the intermediate layer, the above-mentioned sensor chip integrated circuit 3 can be arranged in parallel with the ISFET transistor 2, so as to avoid the ISFET sensor chip from being too thick. The specific structure of the above-mentioned sensor chip integrated circuit 3 can be arranged in the metal layers 1 to N top metal -1 of the entire substrate. At this time, there will also be enough space in the ISFET sensor chip to arrange the sensor chip integrated circuit 3.

[0050] In the ISFET sensor chip provided by the embodiment of the present invention, by arranging the sensitive film 1 on the top layer of the substrate and arranging the ISFET transistor 2 and the sensor chip integrated circuit 3 on the intermediate layer of the substrate, the sensitive film 1 and the sensor chip integrated circuit 3 are distributed along the thickness direction in the substrate, and the sensitive film 1 covers at least part of the sensor chip integrated circuit 3, which can effectively reduce the area of the ISFET sensor chip in the horizontal direction, increase the space utilization rate in the substrate, and realize the miniaturization of the ISFET sensor chip.

[0051] Please refer to Figure 4 , Figure 4 , which is the performance diagram of an ISFET sensor chip provided by the embodiment of the present invention.

[0052] Next, the drawing method of the ISFET sensor chip layout and the testing process of the ISFET sensor chip will be described.

[0053] S1: Draw the layout of a single ISFET transistor with a normal size. When drawing the gate, the metal structure connected to it is drawn to the Nth top metal -1 layer.

[0054] S2: Call the layouts of m ISFET transistors and splice them into an m×1 transistor array. Place the top metal symmetrically up and down above it according to the area requirement of the sensitive film 1 as the sensitive unit 11, and connect it through vias and the Nth top metal -1 layer of metal to form an m×1 ISFET array 21.

[0055] S3: Call n m×1 ISFET arrays 21 and splice them into an m×n ISFET array layout.

[0056] S4: Place the sensor chip integrated circuit 3 in the idle area under the ISFET array layout, that is, the area of the substrate intermediate layer where the ISFET transistors 2 are not set. The sensor chip integrated circuit 3 includes a row selection circuit, a column selection circuit, a signal reading circuit, a bias circuit, etc. Part of the sensor chip integrated circuit 3 is drawn using the 1st to N - 1 layer of metal. top metal -1 layer metal drawing.

[0057] S5: Add ESD (electrostatic protection), Pad (pad), etc. to complete the ISFET sensor chip layout drawing, and then detect the design rules and simulate and adjust to obtain a layout that meets the performance.

[0058] The above design rules include the basic properties of each layer of metal in the integrated circuit, such as the minimum pitch, the minimum width, the maximum width, etc. The parameters are usually provided by the foundry.

[0059] The above simulation refers to simulating the effects of the pre - placed circuit layout through a simulation tool, including the layout power consumption, the voltage drop of pixels at different positions inside the layout, the isolation degree between analog signals and digital signals, whether the traces are passable, etc.

[0060] The above layout power consumption means ensuring that the overall power consumption of the chip after the circuit is pre - placed is in the lowest state; the voltage drop of pixels at different positions inside the layout is determined by the equivalent resistance between the power Pad and the calculated pixels. It is necessary to ensure that the voltage drop is not much different from the previous circuit simulation results, and the voltage drops of two symmetric pixels above and below are equal.

[0061] The above isolation degree between analog signals and digital signals means that the analog signal unit and the digital signal unit in the ISFET sensor chip are placed separately according to a certain area range to ensure that the analog signals and digital signals do not interfere with each other and work properly.

[0062] The above whether the traces are passable means that after the circuit layout is placed, each unit can be normally connected to the outside, and it is necessary to ensure that the connection lines between units are as short as possible and there is no situation such as wire - winding blockage.

[0063] Adopting the above ISFET sensor chip layout structure of the embodiment of the present invention, an ISFET sensor chip is fabricated using a 180nm CMOS process, and its structure is as Figure 3 shown. Connect the gates of the outermost two rings of ISFET devices of the chip to an external voltage for electrical test to verify the chip performance. After building a test system and configuring a test environment, the test results are as Figure 4As shown. Obviously, the above structure can ensure that the ISFET sensor chip has good performance.

[0064] The present invention also provides an ISFET sensor, which needs to include the ISFET sensor chip as described in any of the above embodiments.

[0065] Specifically, in the embodiments of the present invention, the ISFET sensor chip included in the ISFET sensor generally includes a substrate, an ISFET transistor, a sensitive film, and a sensor chip integrated circuit disposed on the substrate; the substrate includes a top layer and an intermediate layer below the top layer;

[0066] The sensitive film is located on the top layer, the ISFET transistor is disposed on the intermediate layer, and the sensitive film is connected to the gate of the ISFET transistor through a via; the sensor chip integrated circuit is disposed on the intermediate layer, and the sensitive film covers at least a part of the sensor chip integrated circuit.

[0067] The above substrate is generally divided into a multi-layer composite structure, which specifically includes a top layer and an intermediate layer below the top layer. Usually, a metal layer is provided between the layers of the substrate for arranging the structure and wiring of the ISFET sensor chip.

[0068] The top layer of the above substrate is usually provided with a sensitive film 1. In the embodiments of the present invention, the sensitive film 1 can be modified. According to the different functions of the ISFET sensor chip, the modification of the above sensitive film 1 can also be different. The above sensitive film 1 is located on the top layer of the substrate and usually needs to be in contact with the external solution to achieve its measurement function.

[0069] The above intermediate layer is the other layer structure of the substrate except the top layer. Usually, the intermediate layer is composed of multiple layers stacked along the thickness direction, and the metal layer therein is used for arranging various circuits, wirings, devices, etc. In the embodiments of the present invention, an ISFET transistor 2 and a sensor chip integrated circuit 3 need to be provided in the intermediate layer. The structure of the above ISFET transistor 2 usually includes structures such as a source electrode, a gate electrode, and a drain electrode.

[0070] Since the above sensitive film 1 is disposed on the top layer and the ISFET transistor 2 is disposed on the intermediate layer, it means that the sensitive film 1 and the ISFET transistor 2 are disposed on different layers in the substrate. Usually, the ISFET transistor 2 is disposed below the sensitive film 1. In the embodiments of the present invention, the sensitive film 1 needs to be connected to the gate of the ISFET transistor 2 through a via, so as to realize the measurement of the external solution by the ISFET transistor 2 based on the sensitive film 1. The above via can be a through hole or other structures.

[0071] The above-mentioned sensor chip integrated circuit 3 is a corresponding supporting circuit required in the ISFET sensor chip. This sensor chip integrated circuit 3 needs to be connected to the ISFET transistor 2 to achieve corresponding functions. In the embodiments of the present invention, the sensor chip integrated circuit 3 generally includes any one or any combination of the following: a row selection circuit, a column selection circuit, a signal reading circuit, and a bias circuit.

[0072] The above-mentioned sensor chip integrated circuit 3 is specifically arranged in the middle layer of the substrate, that is, the sensor chip integrated circuit 3 is also specifically arranged on a different layer of the substrate from the sensitive film 1. Specifically, the sensitive film 1 is arranged on the upper layer of the substrate, while the sensor chip integrated circuit 3 is arranged on the lower layer of the sensitive film 1. Therefore, in the embodiments of the present invention, the sensitive film 1 can cover the sensor chip integrated circuit 3, thereby reducing the area occupied by the sensor chip integrated circuit 3 in the horizontal direction. Specifically, in the embodiments of the present invention, the sensitive film 1 covers at least a part of the sensor chip integrated circuit 3 to reduce the area of the ISFET sensor chip. Usually, the sensitive film 1 covers all of the sensor chip integrated circuit 3, that is, the sensor chip integrated circuit 3 is entirely arranged below the sensitive film 1, so as to minimize the area required for the ISFET sensor chip as much as possible.

[0073] It should be noted that since the area occupied by the sensitive film 1 is usually much larger than the area occupied by the ISFET transistor 2, there is sufficient space below the sensitive film 1 for arranging the sensor chip integrated circuit 3.

[0074] Specifically, in the embodiments of the present invention, the metal structure connected to the gate in the ISFET transistor 2 is arranged in the sub-top metal layer closest to the top layer in the middle layer; the sensitive film 1 is connected to the metal structure in the sub-top metal layer through the via hole. The sub-top metal layer closest to the top layer in the above-mentioned middle layer is the N top metal -1 layer, that is, in the embodiments of the present invention, a metal structure will specifically be arranged in the N top metal -1 layer. The above metal structure is connected to the gate of the ISFET transistor 2, which is equivalent to extending the gate of the ISFET transistor 2 to the N top metal -1 layer. And the above sensitive film 1 is connected to the metal structure in the sub-top metal layer through the via hole, thereby realizing the connection between the sensitive film 1 and the gate of the ISFET transistor 2.

[0075] In an embodiment of the present invention, the sensitive film 1 includes a plurality of sensitive units 11, and the plurality of sensitive units 11 are arranged in an array on the top layer. The above-mentioned sensitive unit 11 generally includes a metal layer located on the surface of the top layer and a passivation layer located on the surface of the metal layer. In the embodiment of the present invention, the above structure is determined as the sensitive unit 11, and the plurality of sensitive units 11 are arranged in an array to form the sensitive film 1. The above-mentioned via hole specifically connects the metal layer on the top layer of the substrate to the gate of the corresponding ISFET transistor 2, which is equivalent to extending the gate of the ISFET transistor 2 to the top layer for measurement based on the sensitive film 1.

[0076] In an embodiment of the present invention, there are generally a plurality of the ISFET transistors 2, and the plurality of ISFET transistors 2 are arranged in an array on the intermediate layer. The sensitive unit 11 is connected to the corresponding ISFET transistor 2 through the via hole. The above-mentioned ISFET transistor 2 and the sensitive unit 11 are generally in a one-to-one correspondence relationship, and the corresponding sensitive unit 11 and the ISFET transistor 2 are connected through the via hole.

[0077] Since the size of the above-mentioned ISFET transistor 2 is generally smaller than the size of the sensitive film 1, the size of the ISFET array 21 formed by a plurality of ISFET transistors 2 is generally smaller than the sensitive unit array formed by a plurality of the sensitive units 11. In order to generally reduce the lines required for the connection between the sensitive film 1 and the corresponding ISFET transistor 2, the above-mentioned ISFET array 21 is arranged in the central area of the sensitive unit array to reduce the distance between the ISFET transistor 2 and the corresponding sensitive film 1.

[0078] Specifically, in an embodiment of the present invention, the gate of the ISFET transistor 2 located at the edge of the ISFET array 21 is connected to an external voltage. For the convenience of chip packaging and testing after wafering, the gate of the ISFET transistor 2 located at the edge of the ISFET array 21, such as the outermost two rings of ISFET transistors 2, can be connected to an external voltage for electrical test to verify the chip performance.

[0079] Specifically, in an embodiment of the present invention, the sensor chip integrated circuit 3 and the ISFET transistor 2 are arranged in parallel in the intermediate layer. That is, in the intermediate layer, the above-mentioned sensor chip integrated circuit 3 can be arranged in parallel with the ISFET transistor 2 to avoid the ISFET sensor chip from being too thick. The specific structure of the above-mentioned sensor chip integrated circuit 3 can be set in the metal layers 1 to N top metal -1 of the entire substrate. At this time, there will also be enough space in the ISFET sensor chip to set the sensor chip integrated circuit 3.

[0080] Since an ISFET sensor chip provided by an embodiment of the present invention arranges a sensitive film 1 on the top layer of a substrate, and arranges an ISFET transistor 2 and a sensor chip integrated circuit 3 on the middle layer of the substrate, the sensitive film 1 and the sensor chip integrated circuit 3 are distributed along the thickness direction in the substrate, and the sensitive film 1 covers at least a part of the sensor chip integrated circuit 3, which can effectively reduce the area of the ISFET sensor chip in the horizontal direction, increase the space utilization rate in the substrate, realize the miniaturization of the ISFET sensor chip, and correspondingly, the ISFET sensor in the embodiment of the present invention can have a higher utilization rate and realize miniaturization.

[0081] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other.

[0082] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0083] The steps of the method or algorithm described in combination with the embodiments disclosed herein can be directly implemented by hardware, a software module executed by a processor, or a combination of the two. The software module can be placed in a random access memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, or any other form of storage medium well-known in the technical field.

[0084] Finally, it should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

[0085] The above has introduced in detail an ISFET sensor chip and an ISFET sensor provided by the present invention. Specific examples are used in this text to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims

1. An ISFET sensor chip, characterized in that, It includes a substrate, an ISFET transistor, a sensitive film, and a sensor chip integrated circuit disposed on the substrate; the substrate is a multi-layer composite structure, the substrate includes a top layer and an intermediate layer below the top layer, and a metal layer is provided between the layers of the substrate, and the metal layer is used to arrange the structure and wiring of the ISFET sensor chip; The sensitive film is located on the top layer, the ISFET transistor is disposed on the intermediate layer, and the sensitive film is connected to the gate of the ISFET transistor through a via hole to enable the ISFET transistor to measure the external solution based on the sensitive film; the sensor chip integrated circuit is disposed on the intermediate layer, and the sensitive film at least covers part of the sensor chip integrated circuit; the sensor chip integrated circuit is connected to the ISFET transistor; the sensor chip integrated circuit and the ISFET transistor are arranged in parallel in the intermediate layer.

2. The ISFET sensor chip according to claim 1, characterized in that, The metal structure connected to the gate in the ISFET transistor is disposed in the sub-top metal layer closest to the top layer in the intermediate layer; The sensitive film is connected to the metal structure in the sub-top metal layer through the via hole.

3. The ISFET sensor chip according to claim 1, characterized in that, The sensitive film includes a plurality of sensitive units, and the plurality of sensitive units are arranged in an array on the top layer.

4. The ISFET sensor chip according to claim 3, wherein It includes a plurality of the ISFET transistors, and the plurality of ISFET transistors are arranged in an array in the intermediate layer, and the sensitive unit is connected to the corresponding ISFET transistor through the via hole.

5. The ISFET sensor chip according to claim 4, characterized in that, The plurality of sensitive units form a sensitive unit array, the plurality of ISFET transistors form an ISFET array, and the ISFET array is disposed in the central area of the sensitive unit array.

6. The ISFET sensor chip according to claim 5, wherein, The gates of the ISFET transistors located at the edge of the ISFET array are connected to an external voltage.

7. The ISFET sensor chip according to claim 1, characterized in that, The sensor chip integrated circuit includes any one or any combination of the following: A row selection circuit, a column selection circuit, a signal reading circuit, and a bias circuit.

8. The ISFET sensor chip according to claim 1, characterized in that, The sensitive film covers all of the sensor chip integrated circuit.

9. An ISFET sensor, characterized in that, It includes the ISFET sensor chip according to any one of claims 1 to 8.

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