Memory failure prediction method, system, central processing unit and computing device

Abstract

The application discloses a memory fault prediction method and system, a central processing unit and a computing device, relates to the technical field of computers, and improves the timeliness and accuracy of memory fault prediction. The method comprises the following steps: determining at least one second storage unit in the memory based on the fault type of a first storage unit in the memory; the first storage unit is any storage unit in the memory that triggers a correctable error CE of the memory after the processor accesses the memory based on the executed service when executing the service; the fault type comprises the address of the first storage unit, and the at least one second storage unit is determined based on the address of the first storage unit; testing the at least one second storage unit to obtain fault information of the at least one second storage unit; and obtaining risk information of uncorrectable errors UCE of the memory according to the fault information of the at least one second storage unit.

Description

TECHNICAL FIELD

[0001] The present application relates to the computer technical field, and particularly relates to a memory fault prediction method and system, a central processing unit and a computing device. BACKGROUND

[0002] With the evolution of memory architecture, in order to put more storage units in the same area of silicon chip and perform faster read and write operations, the process of dynamic random access memory (DRAM) is getting smaller and smaller, and the working frequency is getting higher and higher. In order to control the heat, the working voltage is forced to be continuously reduced, which reduces the reliability of the memory medium itself, thereby making the memory system based on DRAM more and more fragile, so that the memory fault has become one of the most common fault sources in the server field. Memory faults can be divided into correctable errors (CE) and uncorrectable errors (UCE). The CE fault of the memory can be corrected by the central processing unit (CPU), and will not affect the normal operation of the system. However, the UCE fault of the memory is a fault that cannot be corrected by the CPU, which will cause the server to restart abnormally or go down. Therefore, it is necessary to predict the fault of the memory system in advance to replace the memory before the UCE fault occurs.

[0003] At present, in order to collect memory fault information, it is necessary to rely on the random access of the business system to trigger the memory fault, which leads to uncertainty in the accuracy and real-time performance of the memory fault information collection, thereby reducing the timeliness of the memory fault prediction, and making it impossible to predict the memory fault in time. SUMMARY

[0004] The embodiments of the present application provide a memory fault prediction method and system, a central processing unit and a computing device, which improve the fault information collection speed of the memory, improve the comprehensiveness of the fault information collection of the memory, and further improve the timeliness and accuracy of the memory fault prediction.

[0005] To achieve the above technical purposes, the present application adopts the following technical solutions:

[0006] In a first aspect, a memory fault prediction method is provided, which is applied to a processor. The method comprises: determining at least one second storage unit in the memory based on a fault type of a first storage unit in the memory; the first storage unit being any storage unit in the memory that triggers a correctable error (CE) of the memory when the processor accesses the memory based on a service being executed; the fault type comprising an address of the first storage unit, and the at least one second storage unit being determined based on the address of the first storage unit; testing the at least one second storage unit to obtain fault information of the at least one second storage unit; and obtaining risk information of an uncorrectable error (UCE) of the memory based on the fault information of the at least one second storage unit.

[0007] In the technical solution, when the processor passively accesses the first storage unit in the memory while executing a service, and after detecting that the first storage unit in the memory has a fault and obtaining the fault type of the fault, one or more second storage units (i.e., storage units affected by the CE of the first storage unit) can be actively determined based on the fault type, and the one or more second storage units can be actively accessed and triggered to actively test the second storage units, obtain fault information of the second storage units obtained through the testing, and obtain risk information of a UCE of the memory based on the fault information of the second storage units. When a fault of a storage unit is detected during the execution of a service, the storage units affected by the fault can be actively tested, without waiting for random access of the memory by a service system to trigger a memory fault, so that fault information of the storage units affected by the fault can be collected, a potential memory fault is actively triggered, the speed of collecting fault information of the memory is improved, the comprehensiveness of collecting fault information of the memory is improved by actively determining that the second storage units can be affected by the fault, and the timeliness and accuracy of memory fault prediction are improved.

[0008] In a possible implementation, when the fault type is a preset granularity fault, the at least one second storage unit is a storage unit in a preset granularity range in which the first storage unit is located; the preset granularity fault is a fault type divided according to a preset granularity; the preset granularity is a refinement degree of the memory involved in the CE of the first storage unit in the memory; and the preset granularity range is a range of memory addresses determined according to the preset granularity.

[0009] The possible implementation manner provides that when the fault type is a preset granularity fault, in the process of determining the second storage unit, the storage units in the preset granularity range in which the first storage unit is located can be determined as the second storage unit. Different preset granularity faults correspond to different preset granularity ranges, which improves the comprehensiveness of determining the second storage unit according to the fault type, and makes the second storage unit as much as possible to be all the storage units possibly involved in the fault of the first storage unit.

[0010] In a possible implementation manner, the at least one second storage unit is specifically in the preset granularity range in which the first storage unit is located, and is not triggered by the access when the first storage unit is triggered by the access.

[0011] In the possible implementation manner, since there may be some storage units that have been triggered by the access in the second storage unit determined according to the fault type, if the storage units that have been triggered by the access do not have faults, there is no need to test them again, and if the storage units that have been triggered by the access have faults, the fault information corresponding to the storage units has been collected, so the storage units that have been triggered by the access in the second storage unit determined according to the fault type need to be removed to avoid unnecessary testing process and reduce the computing pressure of the system.

[0012] In a possible implementation manner, the fault information of the at least one second storage unit includes: a memory address of the at least one second storage unit; position information of the at least one second storage unit in the memory; and a fault type of the at least one second storage unit when the at least one second storage unit causes the memory to generate a CE after being triggered.

[0013] In the possible implementation manner, the fault information of the second storage unit can include the memory address, the position information and the fault type, and the comprehensiveness of collecting information can be improved by obtaining the fault information, thereby improving the accuracy of predicting the memory fault.

[0014] In a possible implementation manner, the testing on the at least one second storage unit and the obtaining of the fault information of the at least one second storage unit include: testing the at least one second storage unit according to a target test algorithm to obtain the fault information of the at least one second storage unit; wherein the target test algorithm includes at least one of a frequency of read-write operation on the at least one second storage unit and a program code used for the read-write operation on the at least one second storage unit; and the target test algorithm is used to determine the second storage unit on which the read-write operation is performed from the at least one second storage unit according to a preset density; wherein the preset density is used to represent the positional relationship of each second storage unit on which the read-write operation is performed from the at least one second storage unit.

[0015] In the possible implementation, the target test algorithm for testing the second storage unit can complete the test by specifying the program code used for the read-write operation, the frequency of the read-write operation, and the density of the storage unit selected from the second storage unit for testing, and the read-write operation is performed in multiple ways to test the second storage unit, thereby improving the accuracy of the test.

[0016] In a possible implementation, before testing the at least one second storage unit according to the target test algorithm and obtaining the fault information of the at least one second storage unit, the method further includes: determining a test algorithm corresponding to the fault type of the first storage unit as the target test algorithm; or combining at least two test algorithms corresponding to the fault type of the first storage unit to generate the target test algorithm.

[0017] In the possible implementation, two ways of determining the target test algorithm are provided. Since the test algorithms corresponding to different fault types are different, and the test algorithms are pre-set, the test effect that can be achieved is unknown, and therefore, the target test algorithm is determined in multiple ways, which can improve the accuracy of the test to a certain extent.

[0018] In a possible implementation, before testing the at least one second storage unit and obtaining the fault information of the at least one second storage unit, the method further includes: transferring the memory data in the at least one second storage unit to a third storage unit, and the third storage unit is an idle storage unit in the memory except the first storage unit and the second storage unit.

[0019] In the possible implementation, in order not to affect the data already stored in the second storage unit and not to affect the subsequent system operation during the test, the memory data in the second storage unit is transferred before the test on the second storage unit is determined, so as to avoid errors caused by the change of the memory data in the system.

[0020] In a possible implementation, the testing and obtaining the fault information of the at least one second storage unit include: testing the at least one second storage unit after marking, and obtaining the fault information of the at least one second storage unit; and the marking is used to represent the change of the attribute of the second storage unit and indicates that the second storage unit does not contain the memory data.

[0021] In the possible implementation, each second storage unit can be isolated by marking the second storage unit, so as to realize the separate test on each second storage unit.

[0022] In a possible implementation, before obtaining the failure information of the at least one second storage unit, the method further includes: stopping allocation and use of the at least one second storage unit.

[0023] In the possible implementation, the second storage unit is stopped from being allocated and used before the test is completed, so as not to affect the test effect and accuracy.

[0024] In a possible implementation, after obtaining the risk information of the memory generating the uncorrectable error (UCE) according to the failure information of the at least one second storage unit, the method further includes: resuming allocation and use of the at least one second storage unit in a case where the risk information indicates that the risk of the memory generating the UCE is less than or equal to a first specified risk.

[0025] In the possible implementation, after the memory failure prediction is completed and the determination result indicates that the memory is less likely to generate the UCE, the second storage unit can continue to be normally read and written by resuming allocation and use of the second storage unit, and the normal use of the subsequent memory is avoided from being affected.

[0026] In a possible implementation, after obtaining the risk information of the memory generating the uncorrectable error (UCE) according to the failure information of the at least one second storage unit, the method further includes: generating a risk prompt in a case where the risk information indicates that the risk of the memory generating the UCE is greater than a second specified risk.

[0027] In the possible implementation, after the memory failure prediction is completed and the determination result indicates that the memory is more likely to generate the UCE, the user can be reminded by generating the risk prompt, and the impact of the UCE of the subsequent memory on the business is avoided.

[0028] In a possible implementation, before determining the at least one second storage unit in the memory based on the failure type of the first storage unit in the memory, the method further includes: receiving failure information of the first storage unit reported by a basic input output system (BIOS); the failure information of the first storage unit is information collected when the first storage unit generates the CE; and determining the failure type of the first storage unit based on the failure information of the first storage unit.

[0029] In the possible implementation, the failure information of the first storage unit can be reported to the OS by the BIOS, so that the OS can perform the test and predict the failure risk according to a subsequent algorithm.

[0030] In a possible implementation, the risk information of the memory generating the uncorrectable error (UCE) is obtained according to the failure information of the at least one second storage unit, including: inputting the failure information of the at least one second storage unit into a memory failure prediction model, and obtaining the risk information of the memory generating the uncorrectable error (UCE) output by the memory failure prediction model, the memory failure prediction model being a neural network model used for memory failure prediction.

[0031] In the possible implementation, after obtaining the respective failure information of the second storage units, the memory failure prediction model can be used to process the failure information to obtain the risk information output by the memory failure prediction model. The risk of the memory generating the UCE is predicted according to the risk information, and the timeliness of the memory failure prediction is improved.

[0032] In a second aspect, a memory failure prediction apparatus is provided. The memory failure prediction apparatus is configured to perform any of the memory failure prediction methods provided in the first aspect.

[0033] In a possible implementation, the memory failure prediction apparatus can be divided into functional modules according to the method provided in the first aspect. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. For example, the memory failure prediction apparatus can be divided into a processing module and a prediction module according to functions. The possible technical solutions and beneficial effects of each functional module described above can be referred to the technical solutions provided in the first aspect or the corresponding possible implementation of the first aspect, which will not be described herein.

[0034] In a third aspect, a central processing unit (CPU) is provided, including an interface and a logic circuit, the logic circuit being configured to implement the memory failure prediction method provided in the first aspect.

[0035] In a fourth aspect, a computing device is provided, including a processor and a memory, the memory storing at least one computer program, the at least one computer program being loaded and executed by the processor to implement the memory failure prediction method provided in the first aspect.

[0036] In a fifth aspect, a chip system is provided. The chip system includes an interface circuit and a processor. The interface circuit and the processor are interconnected by a circuit. The processor receives and executes computer instructions from the memory through the interface circuit, so that the processor implements any of the memory failure prediction methods provided in the first aspect and any of the possible implementation of the first aspect.

[0037] In a sixth aspect, an embodiment of the present application provides a computer readable storage medium, and at least one computer program is stored in the computer readable storage medium. The computer program is loaded and executed by a processor to implement the memory failure prediction method in the first aspect.

[0038] In a seventh aspect, an embodiment of the present application provides a computer program product or a computer program, which includes computer instructions stored in a computer readable storage medium. A processor of a terminal reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions to enable the terminal to perform the memory failure prediction method provided in various optional implementation manners of the first aspect.

[0039] The detailed description of the second aspect to the seventh aspect and various implementation manners thereof in the present application can refer to the detailed description in the first aspect and various implementation manners thereof, and the beneficial effects of the second aspect to the seventh aspect and various implementation manners thereof can refer to the beneficial effect analysis in the first aspect and various implementation manners thereof, which will not be described herein again.

[0040] These aspects or other aspects of the present application will be more apparent in the following description. BRIEF DESCRIPTION OF DRAWINGS

[0041] Figure 1 is a structural schematic diagram of a server according to an exemplary embodiment;

[0042] Figure 2 is a hardware structural schematic diagram of a server according to an exemplary embodiment;

[0043] Figure 3 is a structural schematic diagram of a memory according to an exemplary embodiment;

[0044] Figure 4 is a flow schematic diagram of a memory failure prediction method according to an exemplary embodiment;

[0045] Figure 5 is Figure 4 is a flow schematic diagram of a memory test and failure prediction in the embodiment shown;

[0046] Figure 6 is Figure 4 is a flowchart of a memory failure prediction process in the embodiment shown;

[0047] Figure 7 is a structural schematic diagram of a memory failure prediction device provided by an exemplary embodiment of the present application;

[0048] Figure 8Fig. 1 is a schematic diagram of a chip system according to an example embodiment of the present application. DETAILED DESCRIPTION

[0049] First, some concepts involved in the memory failure prediction method, system, central processing unit and computing device provided by the embodiments of the present application are explained:

[0050] Row failure: a failure of a corrected error (CE) or an uncorrected error (UCE) occurring in a row of the memory. The physical granularity of the memory, from large to small, is: dimm, rank, device, bank, row / column, cell, bit. The relationship between the multiple physical granularities is: each computer device can include multiple memory sticks (dimm), each memory stick has two memory columns (rank) on two sides of the memory, for example, two memory columns are rank0 and rank1. Each memory column can be configured with multiple memory chips (Chip) for storing data, and the memory chip can also be referred to as a memory particle (device). The memory chip can be a dynamic random access memory (DRAM), a static random access memory (SRAM), etc. Each memory chip can be divided into multiple storage arrays (bank). When the memory chip stores data, the data is written into a storage array in units of bits. In addition, multiple storage arrays can be grouped into a storage array group (bank group). The number of storage arrays in each storage array group can be the same or different. A storage array is composed of a large number of storage units (cell). The large number of storage units are arranged in a two-dimensional matrix form. As long as the row and column on the storage array are specified, a storage unit on the storage array can be located. The smallest unit of memory failure is a storage unit on the storage array. That is, the memory failure includes at least one of the following: dimm failure, rank failure, device failure, bank failure, row failure / column failure, cell failure, and bit failure.

[0051] The scheme shown in the embodiments of the present application can be executed by a computing device, which can be a server including a hardware layer and a software layer, and the software layer is program code running on the hardware layer. The software layer can be further divided into several layers, and the layers communicate with each other through a software interface. The software layer includes, from top to bottom, an application layer, an operating system (OS) and a basic input output system (BIOS), a driver layer, and a hardware layer. Figure 1

[0052] The application layer includes a series of program codes running application programs.

[0053] The OS is a system running in the CPU. The OS system can be Linux, Windows, or vxWorks, etc.

[0054] The BIOS can be stored in a separate Flash memory chip (hereinafter referred to as a BIOS chip), and the CPU runs the BIOS by calling the program code of the BIOS stored in the Flash chip. The BIOS is used to set the hardware and prepare for the OS to run. The main functions of the BIOS are power-on, self-test, CPU initialization, memory initialization, detection of input and output devices, and booting of the OS.

[0055] The driver layer includes a board machine support package and a driver, which is used to provide device interfaces in the hardware layer for the application layer, the OS and the BIOS; that is, the driver layer is the connection layer of the application layer, the OS and the BIOS with the hardware layer.

[0056] The hardware layer includes computer hardware such as a central processing unit (CPU) 201, a memory 202, a BIOS chip 205, and a baseboard management controller (BMC) 206. The BMC 206, also known as an out-of-band controller, is an out-of-band processor independent of the central processor CPU 201. The out-of-band controller can include a monitoring and management unit outside the computer device, a management system in a management chip outside the processor, a computer device baseboard management unit, a system management module (SMM), etc. The connection relationship among these hardware is as shown in Figure 2

[0057] Figure 2 ​​Fig. 1 is a schematic diagram of a hardware structure of a server provided by an embodiment of the present application. The server can be an X86 architecture server, and can be a blade server, a high-density server, a rack server, a high-performance server, or the like. The server includes a processor 201, a memory 202, a network interface 203, a bus 204, a BIOS chip 205, and a BMC 206.

[0058] The processor 201 can include one or more processing units. For example, the processor 201 can include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, a neural-network processing unit (NPU), or the like. Different processing units can be independent devices or integrated into one or more processors.

[0059] The memory 202 is configured to store data. The memory 202 can include, but is not limited to, a random access memory (RAM), a read-only memory (ROM), a flash memory, an optical memory, or the like.

[0060] The memory 202 is configured to interact with the processor 201, and send fault information generated in the interaction process to the BIOS chip 205. The memory 202 includes at least one memory. The memory can include a plurality of memory banks, and the structure of memory columns, memory particles, memory arrays, and memory cells in the memory bank is as shown in Fig. 2. Figure 3

[0061] The network interface 203 is a wired interface (port), such as a FDDI, GE interface. Alternatively, the network interface 203 is a wireless interface. It should be understood that the network interface 203 includes a plurality of physical ports.

[0062] The bus 204 connects the processor 201, the memory 202, the network interface 203, the BIOS chip 205, and the BMC 206, or connects them in other ways.

[0063] ​The processor 201 can be configured to detect the memory fault, and the processor 201 can include a fault register and a memory controller. The fault register can be configured to record fault information, and the memory controller can be configured to detect whether a fault occurs in the memory. The processor 201 can obtain the fault information of the memory when a correctable error occurs, and record the fault information in the fault register through the memory controller. It should be noted that the specific content of the memory fault detected by the processor 201 is not limited in the embodiments of the present application. It should be noted that each fault in the memory is caused by a plurality of Bit faults and / or Cell faults.

[0064] The BMC 206 can be configured to remotely maintain and manage the server through a dedicated data channel. The BMC is completely independent of the OS of the server, and can communicate with the BIOS and the OS through an out-of-band management interface of the server.

[0065] Figure 4 FIG. 1 is a flow diagram of a memory fault prediction method provided by the embodiments of the present application. As shown in FIG. 1, the method comprises the following steps: Figure 4

[0066] S101, in a case where the memory controller in the CPU detects that a first storage unit has a fault, the memory controller records fault information of the first storage unit.

[0067] In the embodiments of the present application, when the memory data is subjected to a data read / write operation, and the access triggers to the first storage unit, if the CPU detects that the first storage unit has a fault, the CPU can record the fault information of the first storage unit having the fault.

[0068] In the embodiments of the present application, when the memory data is subjected to a data read / write operation, and the access triggers to the first storage unit, if the CPU detects that the first storage unit has a fault, the CPU can record the fault information of the first storage unit having the fault.

[0069] That is, in a case where the CPU detects that the first storage unit has a fault through the memory controller, the fault information of the first storage unit can be recorded in the fault register.

[0070] In a possible implementation, the data read / write operation of the memory data by the OS can be an operation of storing or reading out the memory data of each storage unit in the memory in a process in which the processor executes a certain service.

[0071] ​The first storage unit can be any storage unit that triggers the memory to generate a correctable error (CE) after the memory is accessed based on the executed service when the processor executes the service. The failure information of the first storage unit is information collected by the CPU when the first storage unit triggers the generation of the CE. The failure information of the first storage unit can include the memory address of the failed first storage unit, the location information of the first storage unit in the memory, the failure level of the failed first storage unit, the failure identification corresponding to the failure of the first storage unit, and the like.

[0072] For example, the location information of the first storage unit in the memory can include at least one of a memory rank to which the first storage unit belongs, a memory device to which the first storage unit belongs, a storage array group (bank group) to which the first storage unit belongs, a storage array (bank) to which the first storage unit belongs, a row and a column to which the first storage unit belongs.

[0073] Optionally, the failure level of the failed first storage unit can be used to indicate the degree of the failure of the first storage unit. The failure level can be used to determine the range of the subsequent first storage unit affected after the generation of the CE. The failure identification corresponding to the failure of the first storage unit can be an error code of the memory. The failure identification corresponding to the failure of the first storage unit can be used to indicate the type of the failure according to the form of the memory after the failure. It can be understood that the type of the failure includes the address of the first storage unit.

[0074] In a possible implementation, in a case where the CPU detects that the first storage unit fails, the CPU can obtain the failure information of the first storage unit and store the failure information of the first storage unit in a failure register. The failure register is a register in the CPU for storing the failure information.

[0075] That is, after the CPU detects that the first storage unit fails, the CPU can record the memory address corresponding to the first storage unit, which can include the location information of the first storage unit in the memory at different granularities, and store the memory address in the failure register in the CPU. As shown in Figure 3 The granularities of the memory from large to small can include a memory rank, a memory device, a storage array group (bank group), a storage array (bank), and a row and a column.

[0076] The embodiments of the present application do not limit the cause of the failure of the first storage unit. For example, the first storage unit can be a storage unit that fails when data is written, or a storage unit that fails when data is read.

[0077] S102, the BIOS chip acquires the fault information of the first storage unit.

[0078] In the embodiment of the present application, after acquiring the fault information of the first storage unit, the CPU can send an interrupt instruction to the BIOS chip, the interrupt instruction can be an instruction for controlling the BIOS chip to acquire the fault information from the fault register, and the BIOS starts an interrupt service program in response to the interrupt instruction, through which the fault information of the first storage unit recorded in the fault register can be collected.

[0079] In a possible implementation, after acquiring the fault information of the first storage unit, the CPU can trigger an interrupt, and then the BIOS can respond to the triggered interrupt and collect all the memory-related fault information recorded in the fault register in the interrupt service program and report it to the OS.

[0080] S103, the OS in the CPU receives the fault information of the first storage unit reported by the BIOS.

[0081] In the embodiment of the present application, after collecting the fault information of the first storage unit from the CPU, the BIOS can send the fault information of the first storage unit to the OS, because the BIOS does not have the function of analyzing the fault information, so that the OS can analyze the received fault information of the first storage unit.

[0082] S104, the OS in the CPU determines the fault type of the first storage unit based on the fault information of the first storage unit.

[0083] In the embodiment of the present application, after the OS receives the fault information of the first storage unit, the fault type of the first storage unit is determined by analyzing the fault information of the first storage unit.

[0084] In a possible implementation, the fault type of the first storage unit can include at least one of single-bit fault, multi-bit fault, row fault, column fault, storage array fault, memory device fault, memory rank fault, and memory dimm fault.

[0085] The OS can determine the fault type corresponding to the fault of the first storage unit in the fault information of the first storage unit based on the fault identifier corresponding to the fault, that is, the corresponding relationship between the fault identifier and the fault type can be stored in advance, and when the fault identifier included in the fault information of the first storage unit is acquired, the fault type corresponding to the fault identifier can be determined according to the above corresponding relationship.

[0086] Alternatively, the OS can determine the corresponding fault type based on the fault identification corresponding to the fault of the first storage unit in the fault information of the first storage unit and the fault level, that is, the pre-stored fault identification can have a corresponding relationship with multiple fault types, when the fault identification included in the fault information of the first storage unit is obtained, the corresponding relationship can be used to determine part of the fault types from the multiple fault types as possible fault types, and then the fault type that meets the fault level in the fault information is selected from the possible fault types as the determined fault type of the first storage unit according to the fault level.

[0087] In a possible implementation, the pre-stored fault identification can have a corresponding relationship with one or more fault types.

[0088] For example, the fault identification "001" can have a corresponding relationship with column fault and rank fault; the fault identification "002" can have a corresponding relationship with bank fault.

[0089] In a possible implementation, if the OS obtains the fault identification in the fault information of the first storage unit, one or more fault types corresponding to the fault identification are determined according to the corresponding relationship between the pre-stored fault identification and the fault type, if it is determined that the fault identification only has a corresponding relationship with one fault type, the fault type can be directly determined as the fault type of the first storage unit; if it is determined that the fault identification can have a corresponding relationship with at least two fault types, the OS determines one fault type that meets the fault level in the at least two fault types as the fault type of the first storage unit according to the fault level in the fault information.

[0090] The fault level is used to indicate the influence range of the CE generated by the first storage unit on the memory, and the higher the fault level, the corresponding determined fault type can be a fault type divided according to a preset granularity with a larger granularity. Each fault level can correspond to at least one fault type, for example, if the fault level is divided into high-level fault, medium-level fault and low-level fault, the high-level fault can correspond to at least one fault type with a granularity greater than or equal to a device, that is, rank fault and device fault; the medium-level fault can correspond to at least one fault type with a granularity greater than or equal to a bank and less than a device, that is, bank group fault and bank fault; and the low-level fault can correspond to at least one fault type with a granularity less than a bank, that is, row fault and column fault.

[0091] For example, when the pre-stored correspondence between the fault identifier and the fault type is that the fault identifier "001" corresponds to possible fault types including column fault and rank fault, the OS, after obtaining the possible fault types, can determine the rank fault as the fault type corresponding to the high-level fault in the fault information, and determine the rank fault as the fault type of the first storage unit.

[0092] In S105, the OS in the CPU determines at least one second storage unit in the memory based on the fault type of the first storage unit in the memory.

[0093] In the embodiments of the present application, after the OS in the CPU receives the fault information of the first storage unit, the OS can determine the fault type of the first storage unit based on the fault information of the first storage unit in the memory, and determine one or more second storage units in the memory according to the fault type of the first storage unit. Alternatively, after the OS in the CPU receives the fault information of the first storage unit, the OS can determine the fault type of the first storage unit based on the fault information of the first storage unit in the memory, and determine one or more second storage units in the memory in combination with the fault information of the first storage unit and the fault type of the first storage unit.

[0094] The second storage unit can be a storage unit affected by the CE of the first storage unit. That is, the second storage unit can be a storage unit that is likely to fail, which is determined from other storage units not accessed to trigger the first storage unit to fail, according to the information including the location information, the fault type, and the fault level of the first storage unit, when the memory is read or written.

[0095] In a possible implementation, when the fault type is a preset granularity fault, the at least one second storage unit is a storage unit in a preset granularity range where the first storage unit is located.

[0096] The preset granularity fault is a fault type divided according to a preset granularity, and the preset granularity can be a refinement degree of the memory space involved in the correctable error CE generated by the first storage unit. The preset granularity range is a range of memory addresses determined according to the preset granularity. In the case of different preset granularity faults, the second storage unit can be determined as follows.

[0097] In a first possible case, the preset granularity fault can be a fault with a preset granularity of a row or a column, and at this time, the fault type can be a row fault or a column fault, and the preset granularity range can be the corresponding same row or column, or can also be the corresponding row or column within a specified range around the row or column where the first storage unit is located.

[0098] The row-around specified range can refer to all rows with an interval of less than or equal to a specified threshold number of rows from the row where the first storage unit is located; and the column-around specified range can refer to all columns with an interval of less than or equal to a specified threshold number of columns from the column where the first storage unit is located.

[0099] For example, if the fault type is a row fault, the at least one second storage unit can be a storage unit in the row where the first storage unit is located; and if the fault type is a column fault, the at least one second storage unit can be a storage unit in the column where the first storage unit is located.

[0100] Alternatively, if the fault type is a row fault, the at least one second storage unit can be a storage unit in the row where the first storage unit is located and the corresponding row within the specified range around the row; and if the fault type is a column fault, the at least one second storage unit can be a storage unit in the column where the first storage unit is located and the corresponding column within the specified range around the column.

[0101] The specified range around can be a preset range, and can also be a range determined according to the fault level in the fault information of the first storage unit.

[0102] For example, in a possible case, if the specified range around is a preset range, and the preset specified range around is one adjacent, if the fault type is a row fault, the at least one second storage unit can be a storage unit in the row where the first storage unit is located and the adjacent row; and if the fault type is a column fault, the at least one second storage unit can be a storage unit in the column where the first storage unit is located and the adjacent column.

[0103] In another possible case, if the specified range around is a range determined according to the fault level in the fault information of the first storage unit, the higher the fault level, the larger the determined specified range around.

[0104] For example, if the failure level in the failure information of the first storage unit is a high-level failure, and the surrounding specified range corresponding to the high-level failure is all rows within two rows of the row where the first storage unit is located, or all columns within two columns of the column where the first storage unit is located, the failure type is a row failure, and the failure level is a high-level failure, the at least one second storage unit can be storage units on rows within the row where the first storage unit is located and two adjacent rows of the row.

[0105] In a second possible case, the preset granularity failure can be a failure with a storage array as a preset granularity, and at this time, the failure type can be a bank failure. If the failure type is a bank failure, the at least one second storage unit can be storage units in the storage array where the first storage unit is located, or can also be storage units in the storage array corresponding to the surrounding specified range of the storage array where the first storage unit is located.

[0106] For example, if the failure type is a bank failure, the at least one second storage unit can be storage units in the storage array where the first storage unit is located. Alternatively, if the failure type is a bank failure, the at least one second storage unit can be storage units in the storage array where the first storage unit is located and the storage array corresponding to the surrounding specified range of the storage array.

[0107] The surrounding specified range of the storage array can refer to all storage arrays with a distance of less than or equal to a specified threshold number of storage arrays between the storage array where the first storage unit is located and the storage array. The surrounding specified range can be a range preset in advance, or a range determined according to the failure level in the failure information of the first storage unit.

[0108] For example, in a possible case, if the surrounding specified range is a range preset in advance, and the surrounding specified range is preset to be adjacent storage arrays, when the failure type is a bank failure, the at least one second storage unit can be storage units in the storage array where the first storage unit is located and the storage array adjacent to the storage array. In another possible case, if the surrounding specified range is a range determined according to the failure level in the failure information of the first storage unit, the higher the failure level, the larger the determined surrounding specified range.

[0109] In a third possible case, the preset granularity failure can be a failure with a memory particle as a preset granularity, and at this time, the failure type can be a device failure, and the preset granularity range can be a corresponding same memory particle, or can also be a memory particle corresponding to the surrounding specified range of the memory particle where the first storage unit is located.

[0110] The specified range around the memory grain can refer to all memory grains with a spacing of less than or equal to a specified threshold number of memory grains from the memory grain in which the first storage unit is located.

[0111] For example, if the fault type is a device fault, the at least one second storage unit can be a storage unit in the memory grain in which the first storage unit is located.

[0112] Alternatively, if the fault type is a device fault, the at least one second storage unit can be a storage unit in the memory grain in which the first storage unit is located and corresponding memory grains in a specified range around the memory grain.

[0113] For example, if the specified range around is a pre-set range and the pre-set specified range is adjacent memory grains, when the fault type is a device fault, the at least one second storage unit can be a storage unit in the memory grain in which the first storage unit is located and adjacent memory grains. If the specified range around is determined according to the fault level in the fault information of the first storage unit, the higher the fault level, the larger the determined specified range.

[0114] In a fourth possible case, the pre-set granularity fault can be a fault with a memory column as a pre-set granularity, and at this time, the fault type can be a rank fault, and the pre-set granularity range can be a corresponding same memory column.

[0115] For example, if the fault type is a rank fault, the at least one second storage unit can be a storage unit in the memory column in which the first storage unit is located.

[0116] In a fifth possible case, the pre-set granularity fault can be a fault with a memory bank as a pre-set granularity, and at this time, the fault type can be a dimm fault, and the pre-set granularity range can be a corresponding same memory bank.

[0117] For example, if the fault type is a dimm fault, the at least one second storage unit can be a storage unit in the memory bank in which the first storage unit is located.

[0118] In a possible implementation, the at least one second storage unit is specifically in a pre-set granularity range in which the first storage unit is located, and is a storage unit that is not triggered for access when the first storage unit is triggered for access.

[0119] That is, after the OS obtains the failure information of the first storage unit, the failure type of the first storage unit can be determined, and the preset granularity range corresponding to the failure type is determined in combination with the failure type, and the storage unit not triggered by the access in the preset granularity range is obtained as the at least one second storage unit.

[0120] Since the storage unit that has been triggered by the access, in one case, the storage unit that has been triggered by the access has been the first storage unit when the access trigger fails, the storage unit that has been triggered by the access does not need to be tested again to obtain the failure information, so the storage unit can be excluded when the second storage unit is determined; in another case, when the storage unit that has been triggered by the access does not fail when the access trigger, the possibility of the storage unit failing can be excluded, so as to reduce the access trigger to unnecessary storage units, and the failure information is actively obtained, so that the above-mentioned storage unit that has been triggered by the access can be excluded when the second storage unit is determined, thereby improving the efficiency of failure prediction.

[0121] In a possible implementation, the OS determines a target address range in the memory based on the failure type of the first storage unit in the memory and the position information of the first storage unit in the memory included in the failure information of the first storage unit.

[0122] The target address range is a memory address range including the at least one second storage unit.

[0123] For example, if it is determined that the failure type of the first storage unit is row failure, and the position of the first storage unit in the memory in the failure information of the first storage unit is the third row in the third memory particle in the first memory bank rank1, when the preset granularity range is the range in the same row as the first storage unit, the storage unit not triggered by the access in the third row in the third memory particle in the first memory bank rank1 can be determined as the second storage unit; or, if it is determined that the failure type of the first storage unit is row failure, the memory address range of the storage unit in the same row as the first storage unit can be determined as the target address range according to the memory address of the first storage unit in the failure information of the first storage unit, and each storage unit in the target address range is the second storage unit.

[0124] In the CPU, the OS transfers the memory data in the at least one second storage unit to the third storage unit, and stops allocating and using the at least one second storage unit.

[0125] In the embodiment of the present application, after the operating system determines the second storage unit from the memory, in order to ensure that subsequent access to the second storage unit triggers testing of whether each second storage unit has a fault, without affecting the data stored in each second storage unit, without causing damage and loss of memory data, and also without affecting the normal operation of the system during the testing process, the memory data stored in the second storage unit can be transferred to the third storage unit, and the allocation and use of each second storage unit can also be stopped.

[0126] The third storage unit can be an idle storage unit in the memory except for the first storage unit and the second storage unit.

[0127] In S107, the OS in the CPU tests at least one second storage unit, and determines a target storage unit from the at least one second storage unit.

[0128] In the embodiment of the present application, after the OS determines the at least one second storage unit, the OS in the CPU can test each second storage unit, which can be in the form of actively accessing to trigger each second storage unit, and determining a storage unit that has a fault after triggering the second storage unit as the target storage unit.

[0129] The target storage unit is a second storage unit that generates a CE after being tested from the at least one second storage unit.

[0130] In a possible implementation, the at least one second storage unit that is tested can include a storage unit without a fault, and can also include a storage unit with a fault.

[0131] That is, when the OS tests the at least one second storage unit, the OS can determine the second storage unit that generates a CE as the target storage unit, and exclude the second storage unit that does not generate a CE after being tested.

[0132] In a possible implementation, the test performed by the OS on the at least one second storage unit can include a stress test of load testing on the memory.

[0133] In a possible implementation, the OS in the CPU can access to trigger the at least one second storage unit according to a target test algorithm, and obtain fault information of the at least one second storage unit.

[0134] The OS in the CPU can determine a test algorithm corresponding to the fault type of the first storage unit as the target test algorithm, or can also combine at least two test algorithms corresponding to the fault type of the first storage unit to generate the target test algorithm.

[0135] The target test algorithm can include at least one of a frequency of read-write operation on the at least one second storage unit, and a program code used for the read-write operation on the at least one second storage unit. The target test algorithm can be used to determine the second storage unit on which the read-write operation is performed from the at least one second storage unit according to a preset density. The preset density can be used to represent a positional relationship of each second storage unit on which the read-write operation is performed from the at least one second storage unit.

[0136] That is, a correspondence between each fault type and each test algorithm is stored in advance. Each fault type can correspond to one or more test algorithms, and the same test algorithm can correspond to different fault types. Each test algorithm can include at least one of a program code used for read-write operation, a preset density used to determine the second storage unit on which the read-write operation is performed from the at least one second storage unit, and a frequency of read-write operation on the at least one second storage unit.

[0137] The preset density can be set by the program code in the target test algorithm, and is used to determine the storage unit corresponding to the position of the second storage unit on which the data read-write operation is performed in the test process.

[0138] For example, if the test algorithm corresponding to the fault type of the first storage unit is directly determined as the target test algorithm, when the fault type is a storage array fault, one of the test algorithms corresponding to the storage array fault stored in advance is selected as the target test algorithm. The target test algorithm includes a program code used for read-write operation, a preset density used to determine the position of the storage unit on which the data read-write operation is performed in the second storage unit, and a frequency of read-write operation on the second storage unit. According to the target test algorithm, the OS can determine the second storage unit on which the read-write operation is performed from the at least one second storage unit according to the preset density, and then perform the read-write operation on the second storage unit on which the read-write operation is performed according to the frequency of read-write operation on the second storage unit. That is, the OS can select some second storage units from the second storage units in the same storage array as the first storage unit according to the preset density, use the program code used for read-write operation in the target test algorithm to perform the read-write operation test on the selected second storage units according to the frequency in the target test algorithm, to obtain the second storage unit in which the fault occurs, and determine the second storage unit in which the fault occurs as the target storage unit.

[0139] Alternatively, if at least two test algorithms of the plurality of test algorithms corresponding to the fault type of the first storage unit are combined to generate a target test algorithm, when the fault type is a column fault, at least two test algorithms corresponding to the column fault are selected from the plurality of test algorithms stored in advance to combine and generate the target test algorithm. The program code for read-write operation included in the combined target test algorithm can be each program code for read-write operation included in the selected at least two test algorithms. The preset density of the second storage unit for determining read-write operation of the second storage unit included in the combined target test algorithm can be the maximum value of the preset densities included in the selected at least two test algorithms, or the average value of the preset densities included in the at least two test algorithms. The frequency of read-write operation of the at least one second storage unit included in the combined target test algorithm can be the maximum value of the frequencies included in the selected at least two test algorithms, or the average value of the frequencies included in the at least two test algorithms. The partial storage units can be selected from each second storage unit in the same column as the first storage unit according to the preset density in the determined target test algorithm, the program code for read-write operation in the target test algorithm is used for read-write operation test on each selected partial storage unit from the second storage unit according to the frequency in the target test algorithm, so as to obtain the fault information of the second storage unit in which the fault occurs.

[0140] In a possible implementation, if it is obtained that the second storage unit is a storage unit in which no data is stored, the second storage unit can be directly marked. If it is obtained that the second storage unit is a storage unit in which data is stored, the memory data in the second storage unit can be transferred to a third storage unit, and then the second storage unit can be marked. The at least one second storage unit after being marked is tested, and the target storage unit is determined from the at least one second storage unit.

[0141] In the embodiment of the present application, the at least one second storage unit after being marked can be at least one second storage unit in which the attribute of the storage unit is changed to indicate that the storage unit does not include memory data.

[0142] S108, obtaining the fault information of the target storage unit.

[0143] In the embodiment of the present application, the OS obtains the fault information of the target storage unit in which the fault occurs after the second storage unit is accessed.

[0144] The difference between the OS in the CPU actively accessing the second storage units and the OS in the CPU accessing the memory triggering the first storage unit to generate the CE includes that the access triggering of the second storage units is actively performed, that is, the access triggering can be independent of the operation requirement of the business system, while the access triggering of the first storage unit is passively performed based on the requirement when the business system is operated.

[0145] The fault information of the target storage unit can include a memory address of the target storage unit, position information of the target storage unit in the memory, and a fault type of the target storage unit when the target storage unit is triggered to cause the memory to generate the CE.

[0146] In S109, the OS obtains risk information of the memory generating the uncorrectable error UCE according to the fault information of the target storage unit.

[0147] In the embodiment of the present application, the OS in the CPU can perform fault risk prediction according to the fault information of the target storage unit by using a specified algorithm to obtain the risk information of the memory generating the UCE.

[0148] In a possible implementation, the OS in the CPU aggregates the fault information collected when each target storage unit generates a fault, and uses a memory fault prediction model to perform risk prediction and risk diagnosis on the memory according to the fault information of each target storage unit to obtain risk information, which is used for comprehensive analysis to obtain the risk of the memory generating the UCE in the future.

[0149] The memory fault prediction model can be a neural network model pre-trained for memory fault prediction, or a mathematical model pre-set.

[0150] An exemplary Figure 5 is a flowchart of a memory test and fault prediction process according to an embodiment of the present application. As shown in Figure 5As shown, when the computing device starts the memory test (S11), the memory address range to be tested and the fault type can be obtained by the operating system (S12), the target address range can be selected according to the fault type (S13), the corresponding memory test algorithm can be selected according to the fault type (S13), the target test algorithm in the above embodiment can be selected, and then the memory test algorithm is executed on the storage unit corresponding to each address in the memory address range to be tested (S14). The memory test algorithm is executed on the storage unit corresponding to each address in the memory address range (S15), and the execution is completed (S16). All detected memory fault information in the test process is summarized (S17), and then the detected memory fault information is imported into the memory fault prediction module (S18). The memory fault prediction module can be implemented as the memory fault prediction model in the above embodiment. The memory fault prediction module can include an artificial intelligence algorithm or a rule, and can also include a memory fault related parameter library. The memory related parameter library can include a pre-set parameter for calculating the fault risk according to the fault information (S19). When the result predicted by the memory fault prediction module indicates that the characteristics of the memory fault information meet the high risk standard, a high-risk memory warning is generated and a reminder is given (S20).

[0151] S110, in the case where the risk information indicates that the risk of UCE of the memory is less than or equal to the first specified risk, the OS in the CPU resumes the allocation and use of at least one second storage unit.

[0152] In the embodiment of the present application, if the risk information generated after the risk prediction of the memory indicates that the risk of UCE of the memory is less than or equal to the first specified risk, the OS can resume the allocation and use of at least one second storage unit.

[0153] That is, the risk information indicating that the risk of UCE of the memory is less than or equal to the first specified risk can mean that the possibility of UCE of the memory is small, and the normal read and write operations can continue to be performed on the memory, so the instruction of stopping the allocation during the fault test of each second storage unit is cancelled, and each second storage unit can resume the allocation and use.

[0154] In a possible implementation, the data stored in each second storage unit before being transferred to the third storage unit can be re-written.

[0155] Wherein, the risk information can indicate the risk of failure in the form of risk probability or risk level. When the risk information is the risk probability, the first specified risk can be the first specified risk probability; when the risk information is the risk level, the first specified risk can be the first specified risk level.

[0156] S111, in a case where the risk information indicates that the risk of the memory having UCE is greater than the second specified risk, the OS in the CPU generates a risk prompt.

[0157] In the embodiments of the present application, if the risk information generated after the risk prediction of the memory indicates that the risk of the memory having UCE is greater than the second specified risk, the OS in the CPU can generate a risk prompt.

[0158] In a possible implementation, after the OS in the CPU generates the risk prompt, the risk prompt can be sent to the BMC, and the BMC can warn the user that the memory has a high risk of having UCE, so that the user can replace the memory to avoid the UCE affecting the normal operation of the system after receiving the warning.

[0159] The second specified risk and the first specified risk can be risks of the same level or risks of different levels.

[0160] Optionally, the risk prompt generated by the OS in the CPU can include information of the memory bank that is predicted to have a failure.

[0161] Exemplarily, Figure 6 is a flowchart of a memory failure prediction process related to the embodiments of the present application, as shown in Figure 6As shown, the memory failure prediction method can be executed by interaction between the memory controller in the CPU, the BIOS, the BMC and the OS running in the CPU in the computing device. First, the OS can normally operate the business system to complete the specified business task (S21), and then normally initiates the read and write operation of the memory to the memory controller in the CPU in the process of operating the business system (S22). When the memory controller in the CPU receives the instruction for initiating the memory read and write operation, it can detect whether the storage unit of the corresponding memory has a memory failure (S23). If the memory controller in the CPU detects that a memory failure occurs, it can record the corresponding memory failure information into the failure register in the CPU (S24). Then the memory controller in the CPU triggers an SMI interrupt (S25), the BIOS responds to the interrupt triggered by the memory controller, and obtains the memory failure information in the interrupt processing program (S26). Then the memory failure information is reported to the OS (S27). The OS preliminarily judges the failure type of the memory according to the collected failure information, and determines the memory address range involved as a risk address region (S28). Then the data stored in the risk address region is transferred (S29), and the attributes of the free storage units after the transfer in the risk address region and the storage units without stored data are modified to mark each storage unit in the risk address region (S210). When the marking of each address in the memory address range is completed, the selected test algorithm is selected to test the risk address region involved in the failed memory, that is, the read and write operation test of the storage unit in the risk address region according to the test algorithm can be used to trigger the potential failure that may exist in the memory (S211). Finally, the memory failure information received in the test process is analyzed by the memory failure prediction algorithm to obtain the risk of UCE of the memory (S212). When it is judged that the risk of a certain memory exceeds a certain set risk, the memory information is reported to the BMC, the BMC receives the information and performs risk warning on the memory, informs the user that the memory has the risk of causing downtime, and suggests the user to perform planned maintenance for replacement (S213). When it is judged that the risk of a certain memory does not exceed a certain set risk, the marking of each address in the risk memory address is removed, and the normal use of the memory is restored (S214).

[0162] The above describes the scheme provided by the embodiments of the present application from the perspective of the method. The above memory failure prediction method can be applied to a memory failure prediction system. In hardware implementation, the memory failure prediction system can be implemented as a chip deployed in the CPU. In software, the memory failure prediction system can include an OS and a BIOS in communication with the OS, wherein the OS is used to execute the memory failure prediction method in the above embodiments.

[0163] The above describes the solutions provided by the embodiments of the present application mainly from the perspective of methods and systems. To implement the above functions, hardware structures and / or software modules corresponding to the respective functions are included. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of the examples described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is implemented in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0164] The embodiments of the present application can divide the functional modules of the memory failure prediction apparatus according to the above method examples. For example, each functional module can be divided according to each function, or two or more functions can be integrated in one processing module. The above integrated module can be implemented in the form of hardware or software functional module. It should be noted that the division of the modules in the embodiments of the present application is illustrative, and is only a logical function division. Actual implementation can have another division manner.

[0165] Figure 7 The structure schematic diagram of the memory failure prediction apparatus provided by the embodiments of the present application is shown. The memory failure prediction apparatus is used to execute the above memory failure prediction method, and the apparatus can be applied to a computing device. For example, the memory failure prediction method shown in the above is executed. The memory failure prediction apparatus can include a processing module 110 and a prediction module 120. Figure 4

[0166] The processing module 110 is configured to determine at least one second storage unit in the memory based on a failure type of a first storage unit in the memory. The first storage unit is any storage unit in the memory that triggers a correctable error (CE) of the memory when the processor accesses the memory based on an executed service during execution of the service. The failure type includes an address of the first storage unit, and the at least one second storage unit is determined based on the address of the first storage unit.

[0167] The processing module 110 is further configured to test the at least one second storage unit and obtain failure information of the at least one second storage unit.

[0168] The prediction module 120 is configured to obtain risk information of an uncorrectable error (UCE) of the memory based on the failure information of the at least one second storage unit.

[0169] For example, in combination with the above Figure 4 The processing module 110 can be configured to execute S105 and S107, and the prediction module 120 can be configured to execute S108.​

[0170] In a possible implementation, when the fault type is a preset granularity fault, the at least one second storage unit is a storage unit in a preset granularity range in which the first storage unit is located, the preset granularity fault is a fault type divided according to a preset granularity, the preset granularity is a refinement degree of an internal storage involved in a correctable error (CE) generated by the first storage unit, and the preset granularity range is a range of memory addresses determined according to the preset granularity.

[0171] In a possible implementation, the at least one second storage unit is specifically a storage unit in the preset granularity range in which the first storage unit is located, and is a storage unit that is not triggered by the access when the first storage unit is triggered by the access.

[0172] In a possible implementation, the fault information of the at least one second storage unit includes:

[0173] a memory address of the at least one second storage unit;

[0174] location information of the at least one second storage unit in the memory;

[0175] and a fault type of the at least one second storage unit when the at least one second storage unit causes the memory to generate a CE after being triggered.

[0176] In a possible implementation, the processing module 110 is further configured to:

[0177] test the at least one second storage unit according to a target test algorithm, and obtain the fault information of the at least one second storage unit; the target test algorithm includes at least one of a frequency of read-write operation on the at least one second storage unit and a program code used for the read-write operation on the at least one second storage unit; the target test algorithm is used to determine a second storage unit on which the read-write operation is performed from the at least one second storage unit according to a preset density; and the preset density is used to represent a positional relationship of each second storage unit on which the read-write operation is performed from the at least one second storage unit.

[0178] In a possible implementation, the apparatus is further configured to:

[0179] determine a test algorithm corresponding to the fault type of the first storage unit as the target test algorithm before testing the at least one second storage unit according to the target test algorithm and obtaining the target fault information of the at least one second storage unit;

[0180] or,

[0181] combine at least two test algorithms corresponding to the fault type of the first storage unit to generate the target test algorithm.

[0182] In a possible implementation, the processing module 110 is further configured to:

[0183] Before testing the at least one second storage unit to obtain the failure information of the at least one second storage unit, the memory data in the at least one second storage unit is transferred to a third storage unit, and the third storage unit is an idle storage unit in the memory except the first storage unit and the second storage unit.

[0184] In a possible implementation, the processing module 110 is further configured to:

[0185] The at least one second storage unit is tested to obtain the failure information of the at least one second storage unit, and the at least one second storage unit is the at least one second storage unit whose attribute is changed to indicate that the at least one second storage unit does not contain the memory data.

[0186] In a possible implementation, the processing module 110 is further configured to:

[0187] Before testing the at least one second storage unit to obtain the failure information of the at least one second storage unit, the use of the at least one second storage unit is stopped.

[0188] In a possible implementation, the processing module 110 is further configured to:

[0189] After predicting the risk information of the memory generating the uncorrectable error UCE according to the failure information of the at least one second storage unit, in a case where the risk information indicates that the risk of the memory generating the UCE is less than or equal to a first specified risk, the use of the at least one second storage unit is resumed.

[0190] In a possible implementation, the processing module 110 is further configured to:

[0191] After predicting the risk information of the memory generating the uncorrectable error UCE according to the failure information of the at least one second storage unit, in a case where the risk information indicates that the risk of the memory generating the UCE is greater than a second specified risk, a risk prompt is generated.

[0192] In a possible implementation, the processing module 110 is further configured to:

[0193] Before determining the at least one second storage unit in the memory based on the failure type of the first storage unit in the memory, the processing module 110 receives failure information of the first storage unit reported by a basic input output system BIOS; and the failure information of the first storage unit is information collected when the first storage unit generates the CE triggered by the access.

[0194] Determine a failure type of the first storage unit based on the failure information of the first storage unit.

[0195] In a possible implementation, the prediction module 120 is further configured to:

[0196] input the failure information of the at least one second storage unit into a memory failure prediction model, and obtain risk information of the memory generating an uncorrectable error (UCE) output by the memory failure prediction model, the memory failure prediction model being a neural network model used for memory failure prediction.

[0197] For a specific description of the above-mentioned optional manner, refer to the foregoing method embodiments, which will not be described here again. In addition, the foregoing explanations and beneficial effect descriptions of any one of the memory failure prediction apparatuses provided above can refer to the corresponding method embodiments described above, which will not be described here again.

[0198] For example, the functions implemented by part or all of the processing module 110 and the prediction module 120 can be implemented by a CPU. Figure 1

[0199] In an example embodiment, a CPU is further provided, which includes an interface and a logic circuit, the logic circuit being capable of reading computer instructions, the computer instructions being loaded and executed by the logic circuit in the CPU to implement all or part of the steps in the memory failure prediction method described above.

[0200] In an example embodiment, a computer readable storage medium is further provided, which stores at least one instruction, at least one program, a code set or an instruction set, the at least one instruction, the at least one program, the code set or the instruction set being loaded and executed by a processor to implement all or part of the steps in the memory failure prediction method described above. For example, the computer readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0201] In an example embodiment, a computer program product or a computer program is further provided, which includes computer instructions stored in a computer readable storage medium. A processor of a computing device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions to enable the computing device to perform all or part of the steps in the memory failure prediction method described above. Figure 4 all or part of the steps in the method shown in any of the embodiments.

[0202] ​In some embodiments, the method shown in the embodiments of the present application can be implemented as computer program instructions coded in a machine readable format on a computer readable storage medium or other non-transitory medium or article.

[0203] The embodiments of the present application also provide a chip system 140, as shown in Figure 8 The chip system 140 includes at least one processor 141 and at least one interface circuit 142.

[0204] For example, when the chip system 140 includes one processor and one interface circuit, the one processor can be the processor 141 shown in the solid line box (or the processor 141 shown in the dashed line box), and the one interface circuit can be the interface circuit 142 shown in the solid line box (or the interface circuit 142 shown in the dashed line box). When the chip system 140 includes two processors and two interface circuits, the two processors include the processor 141 shown in the solid line box and the processor 141 shown in the dashed line box, and the two interface circuits include the interface circuit 142 shown in the solid line box and the interface circuit 142 shown in the dashed line box. There is no limitation in this regard. Figure 8 Figure 8 For example, when the chip system 140 includes one processor and one interface circuit, the one processor can be the processor 141 shown in the solid line box (or the processor 141 shown in the dashed line box), and the one interface circuit can be the interface circuit 142 shown in the solid line box (or the interface circuit 142 shown in the dashed line box). When the chip system 140 includes two processors and two interface circuits, the two processors include the processor 141 shown in the solid line box and the processor 141 shown in the dashed line box, and the two interface circuits include the interface circuit 142 shown in the solid line box and the interface circuit 142 shown in the dashed line box. There is no limitation in this regard. Figure 8 Figure 8 For example, when the chip system 140 includes one processor and one interface circuit, the one processor can be the processor 141 shown in the solid line box (or the processor 141 shown in the dashed line box), and the one interface circuit can be the interface circuit 142 shown in the solid line box (or the interface circuit 142 shown in the dashed line box). When the chip system 140 includes two processors and two interface circuits, the two processors include the processor 141 shown in the solid line box and the processor 141 shown in the dashed line box, and the two interface circuits include the interface circuit 142 shown in the solid line box and the interface circuit 142 shown in the dashed line box. There is no limitation in this regard.

[0205] The processor 141 and the interface circuit 142 can be interconnected by a line. For example, the interface circuit 142 can be configured to receive a signal. For another example, the interface circuit 142 can be configured to send a signal to another device (e.g., the processor 141). For example, the interface circuit 142 can read computer instructions stored in a memory and send the computer instructions to the processor 141. The processor 141 executes the instructions and, in combination with an input / output device, implements various steps in the embodiments described above, such as implementing various steps performed in the method embodiment shown in Figure 3 Of course, the chip system can also include other discrete devices, and the embodiments of the present application do not make a specific limitation in this regard.

[0206] From the above description of the embodiments, those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above functional modules is taken as an example for illustration, and in actual application, the above functions can be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above.

[0207] ​​In several embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented by other manners. For example, the apparatus embodiments described above are merely illustrative, for example, the division of the modules or units is merely a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another apparatus, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units or components shown or discussed can be indirect coupling or communication connection through some interfaces, apparatuses or units, and can be electrical, mechanical or other forms.

[0208] The units described as separate components can or can not be physically separated, and the components shown as units can be one physical unit or a plurality of physical units, that is, can be located in one place or can be distributed to a plurality of different places. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0209] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0210] The integrated unit, if realized in the form of a software functional unit and sold or used as an independent product, can be stored in a readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application essentially or the part of the prior art that makes a contribution or the whole or part of the technical solutions can be embodied in the form of a software product, which is stored in a storage medium and includes a plurality of instructions for causing an apparatus (which can be a single-chip microcomputer, a chip, etc.) or a processor to execute all or part of the steps of the method described in the embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various program code storage media.

Claims

1. A memory failure prediction method applied to a processor, the memory failure prediction method comprising: The method comprises: determining at least one second storage unit in the memory based on a fault type of a first storage unit in the memory; the first storage unit is any storage unit in the memory that triggers a correctable error (CE) of the memory based on a service executed by the processor when the processor executes the service; the fault type comprises an address of the first storage unit, and the at least one second storage unit is determined based on the address of the first storage unit; testing the at least one second storage unit to obtain fault information of the at least one second storage unit; obtaining risk information of uncorrectable errors (UCE) of the memory according to the fault information of the at least one second storage unit.

2. The method of claim 1, wherein, When the fault type is a preset granularity fault, the at least one second storage unit is a storage unit in a preset granularity range in which the first storage unit is located, the preset granularity fault is a fault type divided according to a preset granularity, the preset granularity is a refinement degree of memory involved in a correctable error (CE) generated by the first storage unit in the memory, and the preset granularity range is a range of memory addresses determined according to the preset granularity.

3. The method of claim 2, wherein, The at least one second storage unit is specifically a storage unit in the preset granularity range in which the first storage unit is located, and is a storage unit that is not triggered when the first storage unit is triggered.

4. The method according to any one of claims 1 to 3, characterized in that, The fault information of the at least one second storage unit comprises: a memory address of the at least one second storage unit; position information of the at least one second storage unit in the memory; and a fault type of the at least one second storage unit when the at least one second storage unit triggers the memory to generate a CE.

5. The method of claim 1, wherein, The testing of the at least one second storage unit to obtain the fault information of the at least one second storage unit comprises: testing the at least one second storage unit according to a target test algorithm to obtain the fault information of the at least one second storage unit; wherein the target test algorithm comprises at least one of a frequency of read-write operation on the at least one second storage unit and a program code used for the read-write operation on the at least one second storage unit. The target test algorithm is used to determine a second storage unit for read-write operation from the at least one second storage unit according to a preset density; wherein the preset density is used to represent a positional relationship of each second storage unit determined for read-write operation from the at least one second storage unit.

6. The method of claim 5, wherein, Before the testing of the at least one second storage unit according to the target test algorithm to obtain the fault information of the at least one second storage unit, the method further comprises: determining a test algorithm corresponding to the fault type of the first storage unit as the target test algorithm; or combining at least two test algorithms corresponding to the fault type of the first storage unit to generate the target test algorithm. Before the testing of the at least one second storage unit to obtain the fault information of the at least one second storage unit, the method further comprises:

7. The method of claim 1, wherein, ​ transferring memory data in the at least one second storage unit to a third storage unit, the third storage unit being an idle storage unit in the memory except for the first storage unit and the second storage unit.

8. The method of claim 1, wherein, The testing of the at least one second storage unit and obtaining of the failure information of the at least one second storage unit comprises: testing the at least one second storage unit after the marking and obtaining the failure information of the at least one second storage unit; the marking is used to represent the change of the attribute of the second storage unit and indicates that the second storage unit does not contain memory data.

9. The method of claim 1, wherein, Before the testing of the at least one second storage unit and obtaining of the failure information of the at least one second storage unit, the method further comprises: stopping the allocation and use of the at least one second storage unit.

10. The method of claim 1, wherein, After the obtaining of the risk information of the memory generating the UCE according to the failure information of the at least one second storage unit, the method further comprises: in a case where the risk information indicates that the risk of the memory generating the UCE is less than or equal to a first specified risk, resuming the allocation and use of the at least one second storage unit.

11. The method of claim 1, wherein, After the obtaining of the risk information of the memory generating the UCE according to the failure information of the at least one second storage unit, the method further comprises: in a case where the risk information indicates that the risk of the memory generating the UCE is greater than a second specified risk, generating a risk prompt.

12. The method of claim 1, wherein, Before the determining of the at least one second storage unit in the memory based on the failure type of the first storage unit in the memory, the method further comprises: receiving the failure information of the first storage unit reported by a basic input output system (BIOS); the failure information of the first storage unit is information collected when the access triggers the first storage unit to generate the CE; determining the failure type of the first storage unit based on the failure information of the first storage unit.

13. The method of claim 1, wherein, The obtaining of the risk information of the memory generating the UCE according to the failure information of the at least one second storage unit comprises: inputting the failure information of the at least one second storage unit into a memory failure prediction model to obtain the risk information of the memory generating the UCE output by the memory failure prediction model, the memory failure prediction model being a neural network model used for memory failure prediction.

14. A central processing unit (CPU), comprising: comprise: an interface and a logic circuit, the logic circuit being used to execute the memory failure prediction method according to any one of claims 1 to 13.

15. A memory failure prediction system, comprising: comprise: an operating system (OS) and a basic input output system (BIOS) in communication with the OS; the OS being used to execute the memory failure prediction method according to any one of claims 1 to 13.

16. A computing device, comprising: The computing device comprises a processor and a memory; the processor is coupled with the memory; the memory is used to store computer instructions, the computer instructions are loaded and executed by the processor to enable the computing device to implement the memory failure prediction method according to any one of claims 1 to 13.

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