A server startup failure detection device, method and server

Abstract

The application discloses a server startup fault detection device and method and a server, relates to the technical field of servers, and is used for detecting the startup fault of a server. In view of the problem that the current server startup detection scheme is invalid when a CPLD is unavailable, a server startup fault detection device is provided. The MCU detects the enable end and the output end of the voltage conversion chip involved in the power-on process of the server mainboard, so as to determine whether the server power-on timing and voltage output are normal, and to realize supplementary detection of the server startup fault when the CPLD has not been powered on. When the server is normally powered on, if the CPLD fails, the MCU can control the channel switching module to switch to be connected to the BMC, acquire and analyze the startup information sent by the BMC, so as to detect whether the server fails to start and the cause of the failure, and to make up for the server startup fault detection in another CPLD unavailable scenario.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of servers, in particular to a server startup fault detection device and method and a server. BACKGROUND

[0002] In actual application of the server, the server often cannot start up. Since the server startup process involves too many links, and the server display is in a non-display state in the early stage of the startup process, it is difficult to determine the problem point of the fault.

[0003] Therefore, the problem point is currently analyzed and determined by a complex programmable logic device (CPLD) arranged at the server. However, this method of detecting the startup problem by the CPLD naturally requires the CPLD to be in a normal working state. When the CPLD is in an unpowered state or the CPLD fails, the server startup fault problem cannot be determined, and there is a deficiency.

[0004] Therefore, the technical personnel in the field urgently need a server startup fault detection device to solve the problem that the current server startup detection scheme is invalid when the CPLD is unavailable. SUMMARY

[0005] The application aims to provide a server startup fault detection device and method and a server to solve the problem that the current server startup detection scheme is invalid when the CPLD is unavailable.

[0006] To solve the above technical problems, the application provides a server startup fault detection device, which comprises an MCU, a battery module, a channel switching module and a memory.

[0007] The MCU is connected with the enable end and the output end of each voltage conversion chip in the server mainboard.

[0008] The battery module is connected with the MCU to supply power for the MCU.

[0009] The two input ends of the channel switching module are connected with the server CPLD and the server BMC respectively, and the output end and the control end are connected with the MCU.

[0010] The memory is connected with the MCU and stores fault information of abnormal power-on timing or abnormal output of each voltage conversion chip, and analysis code for analyzing startup information sent by the server CPLD or the server BMC.

[0011] Preferably, the application further comprises a display module connected with the MCU.

[0012] Preferably, the display module is arranged at the rear window of the server.

[0013] Preferably, the server further comprises a power supply switching module.

[0014] The MCU is connected with the battery module through the power supply switching module, the power supply switching module has two input ends, which are connected with the battery module and the power supply end of the server mainboard respectively, and the output end and the control end of the power supply switching module are connected with the MCU.

[0015] Preferably, the server further comprises a multiplexer arranged between each voltage conversion chip and the MCU.

[0016] The input end of the multiplexer is connected with the enable end and the output end of each voltage conversion chip respectively, and the output end and the control end of the multiplexer are connected with the MCU.

[0017] Preferably, the server further comprises a delay circuit arranged between the enable end of each voltage conversion chip and the MCU, and the control end of the delay circuit is connected with the MCU.

[0018] To solve the above technical problems, the application further provides a server startup fault detection method applied to a server startup fault detection device comprising an MCU, a battery module, a channel switching module and a memory, wherein the MCU is connected with the enable end and the output end of each voltage conversion chip in the server mainboard respectively; the battery module is connected with the MCU to supply power for the MCU; the two input ends of the channel switching module are connected with the server CPLD and the server BMC respectively, and the output end and the control end are connected with the MCU; the memory is connected with the MCU and stores fault information matching power-on timing sequence abnormality or output abnormality of each voltage conversion chip and analysis code for analyzing startup information sent by the server CPLD or the server BMC, which comprises:

[0019] When the server is powered on, the MCU detects the enable state and the output voltage of each voltage conversion chip, matches the fault information in the memory, and returns the matching successful fault information.

[0020] When the server is powered on and the server CPLD has no information output, the MCU controls the channel switching module to switch to be connected with the server BMC, acquires the startup information sent by the server BMC, analyzes the startup information through the analysis code stored in the memory and returns the analysis result.

[0021] Preferably, the server startup fault detection device further comprises a power supply switching module, the MCU is connected with the battery module through the power supply switching module, the power supply switching module has two input ends, which are connected with the battery module and the power supply end of the server mainboard respectively, and the output end and the control end of the power supply switching module are connected with the MCU; the method further comprises:

[0022] The MCU detects the output voltage of the server mainboard power supply end, and if the condition of exceeding the preset voltage value and maintaining the preset time length is met, the MCU controls the power supply switching module to switch to be powered by the server mainboard.

[0023] Preferably, the server startup fault detection device further comprises:

[0024] When it is detected that the output voltage of any voltage conversion chip does not reach the corresponding expected output value, the voltage conversion chip is re-enabled.

[0025] Preferably, the server startup fault detection device further comprises a delay circuit arranged between the enable end of each voltage conversion chip and the MCU; the control end of the delay circuit is connected with the MCU; and the method further comprises:

[0026] When it is detected that the actual power-on time length of any voltage conversion chip does not reach the corresponding expected power-on time length, the compensation power-on time length is determined according to the difference between the actual power-on time length and the corresponding expected power-on time length.

[0027] The MCU sends an enable signal to the voltage conversion chip through the delay circuit, and controls the delay circuit to keep the enable signal within the compensation power-on time length.

[0028] To solve the above technical problems, the application also provides a server comprising the above server startup fault detection device.

[0029] The server startup fault detection device provided by the application is powered by the battery module, so that the MCU can perform fault detection on the server when the server is not powered on. Specifically, the MCU detects the enable end and the output end of the 12V_STBY, 3V3_STBY, 5V, 3V, 1V8, etc. key voltage conversion chips involved in the power-on process of the server mainboard, so as to determine whether the server power-on timing and the converted voltage output are normal, and to match the fault information. The server startup fault detection device can perform supplementary detection on the server startup fault in the early stage of the server power-on process, when the server CPLD has not been powered on completely. When the server is normally powered on, if the server CPLD works normally, the CPLD can still perform startup fault detection, so as to ensure the best startup fault detection effect. If the CPLD fails, i.e. no data is output, the MCU can control the channel switching module to switch to the BMC, acquire the startup information sent by the BMC, and analyze the startup information through the memory storing the corresponding analysis code, so as to detect whether the server has a startup fault and the cause of the fault, thereby making up for the server startup fault detection in the scenario where the other CPLD is unavailable. The application starts from two application scenarios where the CPLD is unavailable, respectively performs startup fault detection through the voltage conversion chip enable end and the output end and the BMC, supplements the existing CPLD fault detection scheme, widens the use scenarios of the server startup fault detection, and better guarantees the normal startup of the server.

[0030] The application provides a server startup fault detection method and a server, which correspond to the above device and have the same effect. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings described in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0032] Figure 1 A structural diagram of a server startup fault detection device provided by the present application is shown in the figure.

[0033] Figure 2 A flowchart of a server startup fault detection method provided by the present application is shown in the figure.

[0034] Figure 3 A flowchart of another server startup fault detection method provided by the present application is shown in the figure. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0036] The core of the present application is to provide a server startup fault detection device, method and server.

[0037] In order to enable those skilled in the art to better understand the present application, the present application will be further described in detail in combination with the drawings and specific embodiments.

[0038] At present, the judgment of startup abnormality in the server startup process excessively depends on CPLD. Therefore, in order to fill the blank in the startup problem detection when the server is in the early stage of the startup process, the CPLD is not powered on, and the CPLD fails, the present application provides a server startup fault detection device, as shown in the figure. Figure 1 The server startup fault detection device comprises a microcontroller unit (MCU) 11, a battery module 12, a channel switching module 13 and a memory 14.

[0039] The MCU 11 is connected with the enable end and the output end of each voltage conversion chip 21 in the server mainboard 20.

[0040] The battery module 12 is connected with the MCU 11 to supply power for the MCU 11.

[0041] The two input ends of the channel switching module 13 are connected with the server CPLD 15 and the server baseboard management controller (BMC) 16 respectively, and the output end and the control end are connected with the MCU 11.

[0042] The memory 14 is connected with the MCU 11 and stores fault information matching power-on timing sequence abnormality or output abnormality of each voltage conversion chip 21, and analysis code for analyzing the power-on information sent by the server CPLD 15 or the server BMC 16. It should be noted that the BMC 16 and the CPLD 15 are not the same in the power-on self-checking link of the server, so the corresponding analysis codes are also different, and the memory 14 should store two sets of analysis codes corresponding to the CPLD 15 and the BMC 16 respectively to support data analysis when the channel switching module 13 switches the data source.

[0043] The MCU 11 is the existing MCU in the server, and does not need to be additionally added. As can be easily known from the above, there is a scheme for detecting server power-on faults by using a CPLD and a MCU in the existing server, and the MCU 11 in the present application is the MCU in the existing scheme. Considering the requirements in actual application, the MCU 11 above usually has certain requirements for low power consumption.

[0044] For the battery module 12, since there are many mature design schemes of battery modules at present, how to realize direct current or alternating current and each level output voltage is known to those skilled in the art, so the present application does not repeat it here. The form and voltage of the output power of the battery module 12 used to replace the power supply for the MCU 11 during the power-on of the mainboard should be the same as that of the mainboard power, and adaptive adjustment can be made according to the different output of the actual mainboard power.

[0045] For the channel switching module 13, based on the existing server architecture, the CPLD 15 and the BMC 16 are connected with the MCU 11 through the I2C bus to establish communication, so a possible implementation of the channel switching circuit includes: an I2C switch chip, and an I2C channel between the I2C switch chip and the CPLD 15, the BMC 16 and the MCU 11. The I2C switch chip is also connected with the MCU 11 and controlled by the MCU 11, and the MCU 11 sends a control signal to control the switching of the MCU 11 and the CPLD 15 or the BMC 16 to obtain the power-on information sent by the CPLD 15 or the BMC 16.

[0046] For the selection of the memory 14, the application does not make any limitation, considering that the memory 14 is applied to the server for storing data such as parsing code, generally, the flash memory can be selected as the memory 14 for storing the above-mentioned data.

[0047] It needs to be explained that for the detection of the power-on timing of the server mainboard 20, specifically, whether the sequence of enabling each voltage conversion chip 21 is correct, and whether the output voltage of the corresponding voltage conversion chip 21 reaches a sufficient voltage value when it is enabled, whether the output voltage or the enable state maintains for a time satisfying the requirement, and whether the power-on timing of the server mainboard 20 is correct are comprehensively considered.

[0048] It also needs to be explained that like the connection relationship of the MCU 11 in the above-mentioned embodiment connecting with the output end of each voltage conversion chip 21 of the server mainboard 20 to obtain the output voltage, the MCU 11 can adopt the analog-to-digital converter (ADC) to collect the output voltage and convert it into a digital signal recognizable by itself. Since the collection of the voltage through the analog-to-digital converter is well known to the person skilled in the art, this embodiment will not be repeated here, and the structure and steps of the MCU 11 detecting the voltage involved in the subsequent can also be realized through the analog-to-digital converter. Similarly, the MCU 11 detecting the high and low levels of the enable end of each voltage conversion chip 21 is also well known to the person skilled in the art, which will not be repeated here.

[0049] The server boot failure detection device provided by the application can supply power for the MCU 11 through the battery module 12, so that the MCU 11 can realize functions when the server is not powered on. The MCU 11 is connected with the output end and the enable end of each voltage conversion chip 21 of the server mainboard 20 respectively, so as to detect the enable state and the voltage output of each voltage conversion chip 21, and thus whether the server power-on timing is abnormal can be known. The fault information matching the power-on timing abnormality is stored in the memory 14, and when the server power-on timing abnormality is matched, the corresponding fault information can be returned, so that the server boot detection is performed to a certain extent, and the device can be applied to the application scenario in which the CPLD 15 and the BMC 16 and the like have not worked normally at the beginning of the server power-on, so as to make up for the blank of the existing server boot detection method. In addition, for the application scenario in which the server has been powered on, the MCU 11 can be connected with the CPLD 15 or the BMC 16 through the channel switching module 13, when the CPLD 15 cannot perform the boot failure detection due to the abnormality, the MCU 11 can be connected with the BMC 16 through the channel switching module 13, the boot information can be acquired, and the boot information can be analyzed through the analysis code stored in the memory 14, so as to perform the server failure detection, and the same can make up for the deficiency that the existing scheme of using the CPLD 15 to perform the server boot detection cannot detect when the CPLD 15 is faulty.

[0050] As can be known from the above embodiment, through the server boot failure detection device provided by the application, when the CPLD 15 is not powered on, whether the server mainboard 20 is powered on abnormally can be judged through the MCU 11 by detecting the output end and the enable end of each voltage conversion chip 21, the power-on abnormality of the server mainboard 20 is also one of the main situations of the server boot failure, and to a certain extent, the deficiency of the boot failure detection in this application scenario is made up, and when the CPLD 15 is powered on but is faulty, the BMC 16 can be used to perform the boot failure detection, and another blank of the existing scheme is made up.

[0051] After the server boot failure detection is performed, the MCU 11 outputs the corresponding fault information, and for this, the application provides a preferred embodiment, and the server boot failure detection device further comprises a display module 17 connected with the MCU 11.

[0052] For the specific implementation of the display module 17, the application is not limited, and the display module 17 can be a liquid crystal screen, a light-emitting diode matrix, a mobile terminal or the like having an information display function. Similarly, for the setting position of the display screen, the display screen can be arranged in a management room where an operation and maintenance personnel usually stays, or arranged on the outer surface of the server, or arranged at the rear window of the server, and the application is not limited in this regard, and in actual implementation, the display screen is generally arranged at the rear window of the server.

[0053] The embodiment adds the display module 17 connected with the MCU 11, so that the MCU 11 can display the fault information after detecting that the server has a boot failure and generating corresponding fault information, so that the operation and maintenance personnel can know the current boot failure of the server in a timely and intuitive manner, so as to perform targeted processing and ensure the stability of the server operation. Further, the display device can be arranged at the rear window of the server, ensuring a certain field of view, facilitating the operation and maintenance personnel to check, and thus ensuring the smooth development of the server operation and maintenance work.

[0054] As can be known from the above embodiment, the MCU 11 in the server boot failure detection device provided by the application is powered by the battery module 12, so that the MCU 11 can also realize server boot failure power supply detection at the beginning of server power-on. However, it is easy to know that the energy storage device such as the battery module 12 has limited storage capacity, and even if the MCU 11 selects a low-power model, the problem of insufficient power supply will inevitably occur. When the power is insufficient, charging or replacing the battery needs to be performed, which is very inconvenient, especially when the above device is arranged in the server, the server needs to be opened, which is not only cumbersome but also easy to cause other problems.

[0055] Based on this, the embodiment provides a preferred implementation scheme, and the server boot failure detection device further comprises a power supply switching module 18.

[0056] The MCU 11 is connected with the battery module 12 through the power supply switching module 18. The power supply switching module 18 has two input ends, which are connected with the battery module 12 and the mainboard power supply end 22 of the server mainboard 20 respectively. The output end and the control end of the power supply switching module 18 are connected with the MCU 11 respectively.

[0057] The power supply switching module 18 can be realized by a voltage switching circuit composed of a low-active tri-state gate and a high-active tri-state gate. For example, the power supply switching module 18 has two power supply channels, which are controlled by the low-active tri-state gate and the high-active tri-state gate respectively. The power supply channel corresponding to the low-active tri-state gate is powered by the battery module 12, and the power supply channel corresponding to the high-active tri-state gate is powered by the mainboard power supply end 22. The input ends of the two tri-state gates are the control ends connected with the MCU 11. When the MCU 11 outputs a low level, the voltage channel controlled by the low-active tri-state gate is turned on, and the voltage channel controlled by the high-active tri-state gate is turned off. The MCU 11 is connected with the battery module 12, and the power supply is battery power. When the MCU 11 outputs a high level, the voltage channel controlled by the high-active tri-state gate is turned on, and the voltage channel controlled by the low-active tri-state gate is turned off. The MCU 11 is connected with the server mainboard power supply end 22, and the power supply is mainboard power.

[0058] Correspondingly, when the MCU 11 outputs high level or low level, it can be realized by detecting the voltage of the mainboard power supply end 22. The MCU 11 outputs low level in the default state, and outputs high level when the voltage of the mainboard power supply end 22 is detected to be stable, thereby switching to the mainboard power supply and saving the power of the battery module 12.

[0059] Furthermore, if the energy storage device of the battery module 12 supports the charging function, a power supply channel of the mainboard power to the energy storage device of the battery module 12 can be added to realize the charging function of the battery module 12 when the mainboard power is stable.

[0060] The preferred scheme provided by the embodiment switches the power supply of the MCU 11 by the power supply switching module 18, that is, the power supply of the battery module 12 or the power supply of the mainboard power supply end 22. On the one hand, the battery module 12 is used to meet the power supply requirement of the MCU 11 when the server is not powered on, so as to realize the above-mentioned boot failure detection function. On the other hand, the server mainboard power supply end 22 is used to realize the power supply of the MCU 11 after the server is powered on, reduce the loss of the power of the battery module 12, improve the service life of the battery module 12, and also improve the endurance of the above-mentioned server boot failure detection device.

[0061] In addition, as known from the above, the server boot failure detection device provided by the application needs to detect the power-on sequence and output voltage of each voltage conversion chip 21 of the server mainboard 20 by the MCU 11 to determine whether a boot failure occurs. In actual application, there are many voltage conversion chips 21 on the server mainboard 20, and the mainboard power-on process involves 12V_STBY, 3V3_STBY, 5V, 3V, 1V8 and other key voltage conversion chips 21. If a pin of the MCU 11 is allocated to each output end and enable end of the voltage conversion chip 21, a large number of pin resources of the MCU 11 will be undoubtedly occupied, which affects the realization of other functions of the MCU 11. Therefore, the embodiment further provides a preferred implementation scheme, and the above-mentioned device further comprises:

[0062] A multiplexer is arranged between each voltage conversion chip 21 and the MCU 11.

[0063] The input end of the multiplexer is connected with the enable end and the output end of each voltage conversion chip 21, and the output end and the control end of the multiplexer are connected with the MCU 11.

[0064] It is easy to understand that the number of the multiplexer is not limited in the embodiment, and the corresponding relationship between each multiplexer and the output end and the enable end of the different voltage conversion chips 21 is not limited when multiple multiplexers are used. The person skilled in the art can make adaptive adjustment according to actual needs.

[0065] Exemplary, in a possible implementation, taking the above 12V_STBY, 3V3_STBY, 5V, 3V, 1V8 five voltage conversion chips 21 as an example, according to the distinction of the enable end and the output end, it is realized by two 8-to-1 multiplexers (multiplexers are commonly 4-to-1 and 8-to-1, but there are five voltage conversion chips 21 in the above example, so 8-to-1 multiplexers are selected), specifically:

[0066] The output end of the above five voltage conversion chips 21 is connected with any five of the eight input ends of the 8-to-1 multiplexer A; similarly, the enable end of the five voltage conversion chips 21 is connected with the input end of another multiplexer B; the output end and the control end of the multiplexers A and B are connected with different pins of the MCU 11, at most occupying four pins of the MCU 11, and when the MCU 11 detects the output end and the enable end of only one voltage conversion chip 21 at the same time, it can also be realized by three pins (the control ends of the two multiplexers share the same pin), compared with the 10 pins required for direct connection, the occupation of the MCU 11 pin resources is greatly reduced.

[0067] The preferred scheme provided by the embodiment is that the MCU 11 pin is multiplexed by the multiplexer to detect the output voltage and the enable state of each voltage chip, which saves the number of MCU 11 pins required to be occupied, to a certain extent, liberates the MCU 11 pin resources, so that the MCU 11 can realize other functions by saving the pin resources.

[0068] In the above embodiment, how to detect the power-on sequence is described, whether the power-on sequence is abnormal is mainly determined by the following aspects: 1, whether the enable sequence of each voltage conversion chip is correct; 2, whether the size of the output voltage of each voltage conversion chip meets the expected requirement; 3, whether the holding time of the enable state of each voltage conversion chip meets the expected requirement; 4, whether the output voltage stabilization time (when the output voltage size meets the requirement) of each voltage conversion chip meets the expected requirement.

[0069] Based on the above description, if the enable holding time of the voltage conversion chip is insufficient, the embodiment provides a preferred implementation, the above device further comprises: a delay circuit arranged between the enable end of each voltage conversion chip 21 and the MCU 11; the control end of the delay circuit is connected with the MCU 11.

[0070] It is easy to know that the connection relationship between the enable terminals of the voltage conversion chips 21 and the MCU 11 in the embodiment can be different from that in the above embodiment. In the above embodiment, the connection between the enable terminals of the voltage conversion chips 21 and the MCU 11 is to enable the MCU 11 to detect the enable state of each voltage conversion chip 21, that is, the MCU 11 detects the enable terminals. In the embodiment, the connection is to enable the MCU 11 to control the re-enable or compensation enable time of each voltage conversion chip 21, that is, the MCU 11 controls the enable terminals. Therefore, in actual implementation, the enable terminals of the voltage conversion chips 21 can be connected to different pins of the MCU 11 to distinguish and avoid confusion. Figure 1 In the above embodiment, only the connection relationship for detecting the enable state is shown.

[0071] The level signal output by the MCU 11 is kept for a period of time after passing through the delay circuit, and the delay time can be controlled by the MCU 11. Therefore, when the enable keeping time of the voltage conversion chip 21 is insufficient, the MCU 11 can compensate the output enable signal to provide an enable signal for the corresponding voltage conversion chip 21, which can solve the problem of abnormal power sequence of the server mainboard 20 to a certain extent.

[0072] As for the implementation of the delay circuit, since the delay circuit is a mature circuit structure widely used, there are various types, and the simplest delay circuit can be implemented by only MOS tubes (MOSFET) and current-limiting resistors. Those skilled in the art can set a suitable delay circuit under the premise of known delay requirement, so the embodiment will not be described here.

[0073] It should be noted that there are delay time adjustable delay circuits represented by delay chips in existing delay circuits, and there are also delay time unadjustable delay circuits composed of MOS tubes and current-limiting resistors as described above. The delay time of such delay circuits is determined according to the circuit structure and the parameters of each device.

[0074] When the delay circuit is used to keep the enable signal of the voltage conversion chip 21 in the embodiment, there are usually different delay time requirements. Therefore, if an adjustable delay time delay circuit is used, one delay circuit can meet the above requirements. If a delay time unadjustable delay circuit is used, multiple delay circuits are needed, and correspondingly, each delay circuit with different delay time is independent of each other and can be controlled by a multiplexer or other devices. The delay time of the delay circuit can be controlled by the MCU 11.

[0075] Further, the MCU 11 is connected to the enable terminals of the voltage conversion chips 21, and can control the re-enable of each voltage conversion chip 21 by outputting a control signal, which can also solve some fault problems to a certain extent, for example, some probabilistic faults of chips can be solved by restarting. Further, the MCU 11 is connected to the enable terminals of the voltage conversion chips 21, and can control the re-enable of each voltage conversion chip 21 by outputting a control signal, which can also solve some fault problems to a certain extent, for example, some probabilistic faults of chips can be solved by restarting.

[0076] The embodiment provides a preferred solution. The MCU 11 is connected with the enable end of each voltage conversion chip 21 through a delay circuit, so that the output enable signal can be compensated, and the problem of insufficient enable signal holding time of each voltage conversion chip 21 can be solved. Similarly, the MCU 11 can also control the re-enable of each voltage conversion chip 21, that is, the restart of each voltage conversion chip 21, which plays a good solving effect on the probabilistic failure of each voltage conversion chip 21 in the boot process, and further guarantees the normal boot of the server.

[0077] In the above embodiment, a server boot failure detection device is described in detail, and the application also provides an embodiment of a corresponding server boot failure detection method, which is applied to the above-mentioned server boot failure detection device, as shown in the figure, comprising: Figure 2

[0078] S11: When the server is powered on, the MCU detects the enable state and output voltage of each voltage conversion chip, and matches the fault information in the memory, and returns the matched fault information.

[0079] S12: When the server is powered on, and the server CPLD has no information output, the MCU controls the channel switching module to switch to be connected with the server BMC, acquires the boot information sent by the server BMC, analyzes the boot information through the analysis code stored in the memory, and returns the analysis result.

[0080] As can be easily seen from the above embodiment, the application scenario of step S11 is at the beginning of the server power-on, when the CPLD and BMC devices are normally working, and the MCU powered by the battery module can detect the server mainboard power-on timing by detecting the enable state and output voltage of the voltage conversion chip, to a certain extent, to realize the detection of the server boot failure. As for step S12, the application scenario thereof is when the server is powered on, that is, after the CPLD and BMC are powered on, but the CPLD fails to output. At this time, the MCU is connected with the BMC through the channel switching module, acquires the boot information sent by the BMC, and analyzes the boot information through the analysis code stored in the memory, to detect the boot failure of the server. The above two steps correspond to different application scenarios, and are in parallel relationship with each other, and there is actually no sequence restriction, Figure 2 The above is only one possible implementation, which is implemented based on the sequence of power-on and power-off in the server boot process, and does not cause the sequence restriction of each step in the server boot failure detection method provided by the application.

[0081] ​It is easy to know that the above two cases are for the application scenarios when the CPLD is unavailable, and when the CPLD works normally, the CPLD is connected with the MCU through the channel switching module to receive the power-on information of the CPLD and analyze it, so as to realize more accurate power-on fault detection effect.

[0082] It also needs to be explained that, since the information output by the BMC and the CPLD is quite different, two analysis codes need to be stored in the memory for the analysis of the power-on information. The two analysis codes are preferably used to analyze the power-on information output by the CPLD and the BMC into the same output, that is, into the same fault information. In this way, when the channel switching module switches the data source of the power-on information, it can jump to the corresponding running place of the other analysis code, realize seamless switching of fault information analysis, and guarantee the effect of server power-on fault detection.

[0083] The server power-on fault detection method provided in the embodiment can detect the enable state of each voltage conversion chip and the output voltage to realize the power-on timing detection when the server is powered on. If the CPLD has no information output after the server is powered on, it means that the CPLD may be faulty and unavailable. The MCU controls the channel switching module to control the connection with the BMC, uses the analysis code stored in the memory to analyze the power-on information sent by the BMC, and realizes the function of server power-on fault detection instead of the CPLD, which makes up for the deficiency of the prior art that relies too much on the CPLD. When the CPLD is unavailable, the server power-on fault detection function can still be realized, and the stability of the server operation is further guaranteed.

[0084] In the above-mentioned embodiment of the device part, there is a preferred scheme that further includes a power supply switching module. The power supply switching module can realize the switching of the power supply of the MCU from the mainboard power supply to the battery power supply. Correspondingly, the embodiment also provides a corresponding control method, which is as follows:

[0085] The MCU detects the output voltage of the server mainboard power supply end. If the condition of exceeding the preset voltage value and maintaining the preset time length is met, the power supply switching module is controlled to switch the power supply of the MCU from the server mainboard power supply.

[0086] The above-mentioned step is to determine the output voltage and stability of the mainboard power supply. If the output voltage exceeds the preset voltage, it means that the output voltage size meets the demand, and if the preset time length is maintained, it means that the stability also meets the demand. At this time, it can be considered that the mainboard power supply is stable enough to support the function realization of the MCU, so the MCU sends a corresponding control signal to the control end of the power supply switching module to realize the switching of the power supply.

[0087] In a possible implementation of the above device, the power supply switching module is composed of a low-active tri-state gate and a high-active tri-state gate and corresponding voltage channels. In this structure, the MCU outputs a low level when not powered on and in a default state, the low-active tri-state gate is open and the high-active tri-state gate is off, and the battery module supplies power to the MCU. When the MCU detects that the mainboard power meets the requirements, the MCU outputs a high level, the low-active tri-state gate is off, and the high-active tri-state gate is open, and the mainboard power supplies power to the MCU, thereby saving the battery module power and prolonging the service life and endurance of the battery module.

[0088] Similarly, in the above device, the MCU is connected to the enable terminals of the voltage conversion chips through a delay circuit. In the corresponding circuit structure of this preferred solution, the present embodiment also provides a preferred solution of a server startup fault detection method, as shown in Figure 3 The method further includes the following steps:

[0089] S21: When it is detected that the output voltage of any voltage conversion chip does not reach the corresponding expected output value, the voltage conversion chip is re-enabled.

[0090] It is easy to know that the MCU is connected to the enable terminals of the voltage conversion chips, and in addition to detecting the enable state of the voltage conversion chips, the enable state of the voltage conversion chips can also be controlled. Based on this, when the MCU detects that the output voltage of any voltage conversion chip does not reach the corresponding expected output value, it can be considered that the output of the voltage conversion chip fails, and the output failure can be a probabilistic failure of the voltage conversion chip, which can be solved by restarting the voltage conversion chip. Therefore, by re-enabling the voltage conversion chip through the above method, the partial failure problem that may occur during the server startup process is solved to a certain extent, and the success rate of the normal startup of the server is improved.

[0091] Similarly, based on the above circuit structure, the present embodiment also provides another preferred implementation, as shown in Figure 3 The method further includes the following steps:

[0092] S22: When it is detected that the actual power-on duration of any voltage conversion chip does not reach the corresponding expected power-on duration, the compensation power-on duration is determined according to the difference between the actual power-on duration and the corresponding expected power-on duration.

[0093] S23: The MCU sends an enable signal to the voltage conversion chip through a delay circuit, and controls the delay circuit to keep the enable signal for the compensation power-on duration.

[0094] It should be noted that there is no sequence relationship between steps S21 and steps S22 and S23, which are respectively a solution means for probabilistic failure of the voltage conversion chip and a solution means for insufficient enable time of the voltage conversion chip, Figure 3The present embodiment is only one possible implementation, and does not limit the execution sequence of the present embodiment.

[0095] As can be seen from the above embodiment of the device part, the server startup fault detection device provided by the present application can preliminarily detect the startup fault of the server by detecting whether the power-on sequence of each voltage conversion chip in the server mainboard is abnormal, and accordingly, the standard of whether the power-on sequence is abnormal can be a set of standards saved in the memory, which is manifested as fault information for matching the power-on sequence abnormality or output abnormality of each voltage conversion chip. As can be seen from the above power-on sequence standard, the abnormality of the power-on sequence of each voltage conversion chip can naturally determine the difference between the actual enable time and the standard enable time, and further determine the required compensation power-on duration. The delay circuit outputs the corresponding duration of the enable signal, thereby ensuring the normal power-on of the server mainboard.

[0096] The preferred scheme provided by the present embodiment attempts to solve the fault by re-enabling the voltage conversion chip when detecting the failure of the output voltage of the voltage conversion chip, which can effectively solve the probabilistic fault occurring in the power-on process of the server mainboard, improve the success rate of the normal startup of the server, and ensure the normal use of the server. In addition, when the MCU detects that the enable duration of the power-on sequence of the voltage conversion chip is insufficient, the required compensation duration can be calculated, and the enable signal output to the voltage conversion chip can be kept for a period of time by controlling the delay circuit, thereby solving the problem of insufficient enable duration of the voltage conversion chip, providing a solution to the possible fault problem in the server startup process from another aspect, and further ensuring the smooth implementation of the server startup.

[0097] Finally, the present application also provides a server comprising the above-mentioned server startup fault detection device, and the specific implementation and beneficial effects of the embodiment correspond to those of the above-mentioned device part. Therefore, the embodiment of the server part also refers to the description of the embodiment of the device part, and will not be described here.

[0098] The above describes in detail a server startup fault detection device, method and server provided by the present application. The embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts of each embodiment can be referred to each other. For the device disclosed in the embodiments, the description is relatively simple because it corresponds to the method disclosed in the embodiments. The relevant parts can be referred to the description of the method part. It should be pointed out that the ordinary skilled in the art can make some improvements and modifications to the present application without departing from the principles of the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

[0099] It also needs to be explained that in the present specification, the relational terms such as first and second and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

Claims

1. A server boot failure detection apparatus, characterized by comprising: It comprises: MCU, battery module, channel switching module, memory; The MCU is connected with the enable end and output end of each voltage conversion chip in the server mainboard respectively; The battery module is connected with the MCU to supply power for the MCU; The two input ends of the channel switching module are connected with the server CPLD and server BMC respectively, and the output end and control end are connected with the MCU; The memory is connected with the MCU, and stores fault information matching power-on timing sequence abnormality or output abnormality of each voltage conversion chip, and analysis code for analyzing boot information sent by the server CPLD or server BMC.

2. The server boot failure detection apparatus according to claim 1, characterized by, It also comprises a display module connected with the MCU.

3. The server boot failure detection apparatus according to claim 2, characterized by, The display module is arranged at the rear window of the server.

4. The server boot failure detection apparatus according to claim 1, characterized by It further comprises: a power supply switching module; The MCU is connected with the battery module through the power supply switching module, and the power supply switching module has two input ends connected with the power supply end of the battery module and server mainboard respectively, and the output end and control end of the power supply switching module are connected with the MCU respectively.

5. The server boot failure detection apparatus according to claim 1, wherein It further comprises a multiplexer arranged between each voltage conversion chip and the MCU; The input end of the multiplexer is connected with the enable end and output end of each voltage conversion chip respectively, and the output end and control end of the multiplexer are connected with the MCU.

6. The server boot failure detection apparatus according to claim 1, wherein It further comprises a delay circuit arranged between the enable end of each voltage conversion chip and the MCU; and the control end of the delay circuit is connected with the MCU.

7. A server boot failure detection method, characterized by, The server boot failure detection device comprises an MCU, a battery module, a channel switching module and a memory; wherein the MCU is connected with the enable end and output end of each voltage conversion chip in the server mainboard respectively; the battery module is connected with the MCU to supply power for the MCU; the two input ends of the channel switching module are connected with the server CPLD and server BMC respectively, and the output end and control end are connected with the MCU; the memory is connected with the MCU, and stores fault information matching power-on timing sequence abnormality or output abnormality of each voltage conversion chip, and analysis code for analyzing boot information sent by the server CPLD or server BMC, comprising: When the server is powered on, the MCU detects the enable state and output voltage of each voltage conversion chip, matches the fault information in the memory, and returns the matching successful fault information; When the server is powered on and the server CPLD has no information output, the MCU controls the channel switching module to switch to be connected with the server BMC, acquires the boot information sent by the server BMC, analyzes the boot information through the analysis code stored in the memory, and returns the analysis result.

8. The server boot failure detection method of claim 7, wherein, The server startup failure detection device further comprises a power supply switching module; the MCU is connected with the battery module through the power supply switching module, two input ends of the power supply switching module are connected with the power supply end of the server mainboard and the battery module respectively, and the output end and the control end of the power supply switching module are connected with the MCU respectively; the method further comprises: The MCU detects the output voltage of the power supply end of the server mainboard, and if the condition of exceeding the preset voltage value and maintaining the preset time length is met, the power supply switching module is controlled to switch to supply power to the MCU by the server mainboard.

9. The server boot failure detection method of claim 7, wherein, Further comprising: When it is detected that the output voltage of any of the voltage conversion chips does not reach the corresponding expected output value, the voltage conversion chip is re-enabled. 10.The server boot failure detection method of claim 7, wherein, The server startup failure detection device further comprises a delay circuit arranged between the enable end of each voltage conversion chip and the MCU; The control end of the delay circuit is connected with the MCU; the method further comprises: When it is detected that the actual power-on time length of any of the voltage conversion chips does not reach the corresponding expected power-on time length, the compensation power-on time length is determined according to the difference between the actual power-on time length and the corresponding expected power-on time length; The MCU sends an enable signal to the voltage conversion chip through the delay circuit, and controls the delay circuit to keep the enable signal within the compensation power-on time length.

11. A server, characterized by The server startup failure detection device according to any one of claims 1 to 6.

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