Word line system architecture supporting erase operations and i-v characterization

Abstract

The present disclosure relates to integrated circuits, and more specifically to word line system architectures supporting erase operations and current-voltage (I-V) characterization and methods of manufacture and operation. In particular, the present disclosure relates to a structure comprising: a dual-primarily circuit connected to a word line of a memory array; a source line driver connected to a source line of the memory array for providing a primarilly level current-voltage (I-V) access of the dual-primarily circuit; and an integrated analog multiplexer connected to the dual-primarily circuit.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to integrated circuits, and more particularly to word line system architecture supporting erase operations and current-voltage (I-V) characterization and methods of manufacture and operation. BACKGROUND

[0002] In memory, a sense amplifier is one of the elements that make up the circuit on a semiconductor memory chip. A sense amplifier is part of the read circuit used when reading data from memory. The sense amplifier senses a low power signal from a bit line that represents the data bit (1 or 0) stored in a memory cell and amplifies the small voltage swing to a recognizable logic level so that the data can be integrated by logic external to the memory.

[0003] In static random access memory (SRAM) operation, to read a bit from a particular memory cell, the word line and the row of the particular memory cell are turned on, thereby activating all the cells in the row. The stored value (0 or 1) from the particular memory cell is then sent to the bit line associated with the particular memory cell. A sense amplifier located at the end of both complementary bit lines amplifies the small voltage to a normal logic level. The bit from the desired cell is then latched from the sense amplifier of the particular memory cell into a buffer and placed on the output bus.

[0004] In dynamic random access memory (DRAM) operation, the sense amplifier is similar to SRAM, but performs additional functions. Specifically, data in a DRAM chip is stored as an electric charge in a capacitor in the memory cell. A read operation depletes the charge in the cell, destroying the data, so the sense amplifier must immediately write the data back into the cell (i.e., memory refresh) by applying a voltage to it after the data is read out. In known circuits as described above, current-voltage (I-V) characterization can only be performed on discrete devices, not on field effect transistors (FETs) in a functional memory array. SUMMARY

[0005] In one aspect of the present disclosure, a structure includes a dual cell circuit connected to a word line of a memory array, a source line driver connected to a source line of the memory array for providing cell level current-voltage (I-V) access of the dual cell circuit, and an integrated analog multiplexer connected to the dual cell circuit.

[0006] In another aspect of the disclosure, a circuit includes a dual bitcell memory array including at least one dual bitcell circuit connected to a word line, a bit line true signal, and an integrated analog multiplexer circuit configured to provide a plurality of voltages as input to a word line driver circuit based on a predetermined pattern of the at least one dual bitcell circuit.

[0007] According to another aspect of the disclosure, a method includes enabling a word line of a dual bitcell circuit connected to a memory array using an integrated analog multiplexer and measuring a current in a voltage range of the dual bitcell circuit in a current saturation monitoring mode. BRIEF DESCRIPTION OF DRAWINGS

[0008] In the following detailed description, the disclosure is described, by way of non-limiting example only, with reference to the drawings mentioned.

[0009] Figure 1 A word line system test architecture in a memory structure according to some aspects of the disclosure is shown.

[0010] Figure 2 A block diagram of a word line system test architecture in a memory structure according to some aspects of the disclosure is shown.

[0011] Figure 3A And 3B A programming mode of an analog composite multiplexer integrated switch of a word line system test architecture in a memory structure according to some aspects of the disclosure is shown.

[0012] Figure 4A And 4B A read / Idsatmon mode of an analog composite multiplexer integrated switch according to some aspects of the disclosure is shown.

[0013] Figure 5A And 5B A graph of current Id vs. voltage Vg for different modes and states of a word line system test architecture in a memory structure according to some aspects of the disclosure is shown. DETAILED DESCRIPTION

[0014] The present disclosure relates to integrated circuits, and more particularly to word line system architecture that supports erase operations and current-voltage (I-V) characterization and methods of fabrication and operation. More specifically, in the word line system, a word line can take a negative voltage during an erase operation. Further, the word line system can take any value between zero ("0") volts and a power supply VDD to support current-voltage (I-V) characterization of bit cells in a functional memory array during a debug mode. In further embodiments, the word line system facilitates associating a bit cell array with discrete devices for various modes of operation (i.e., native state, program operation, and erase operation). Advantageously, the memory system supports multiple modes of operation, including read operations, program operations, erase operations, and current saturation monitoring operations (i.e., Idsatmonitor) for current-voltage (I-V) characterization of individual bit cells in the memory array.

[0015] In known circuits, current-voltage (I-V) characterization is performed only on discrete devices. For example, known circuits are unable to perform current-voltage (I-V) characterization on field effect transistors (FETs) in a memory array. In known circuits, a source line SL has a zero value, a power supply is boosted to a high voltage level (e.g., a VDD level), a word line is boosted to a voltage read VREAD level, and a bit line is sensed. In particular, for a sensing operation (i.e., a read operation) of a bit line, a threshold voltage of one field effect transistor (FET) in a bit cell (i.e., a dual cell array) is increased relative to another field effect transistor (FET) in the bit cell (i.e., the dual cell array). Then, the bit line and a complementary bit line are sensed such that a "0" or a "1" is sensed on the bit line and the complementary bit line in the sensing operation (i.e., the read operation). The sensing operation of the bit line and the complementary bit line is performed using a sense amplifier that senses the "0" or the "1" of a discrete device in the memory array. However, known circuits are unable to perform I-V characterization on FETs in a memory array. In contrast, the present disclosure performs I-V characterization using a current saturation monitoring operation (i.e., Idsatmonitor) for FETs in a memory array.

[0016] In embodiments, a word line system architecture includes a dual cell circuit connected to a word line of a memory array, and a source line driver connected to a source line of the memory array for providing a cell level current-voltage (I-V) access of the dual cell circuit. In alternative embodiments, the circuit can include a dual cell memory array including at least one dual cell circuit connected to a word line, a bit line true signal, and a bit line complement signal, a bit line driver circuit connected to the bit line true signal and the bit line complement signal, and a source line driver circuit connected to a source line of the dual cell memory array. Other embodiments include a method of enabling a word line connected to a dual cell circuit of a memory array and measuring a current within a voltage range of the dual cell circuit in a current saturation monitoring mode.

[0017] Figure 1 A word line system test architecture in a memory structure is shown in accordance with some aspects of the present disclosure. The word line system test architecture circuit 10 includes a memory array including n-type metal oxide semiconductor (NMOS) transistors 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70, 75, 80, 85, 90, 95, 100, 105, 110, 115, 120, 125, and 130. As an example, bitcell_0 (e.g., a dual cell array) includes NMOS transistors 15 and 20. The remaining transistors can also be part of individual bit cells having similar characteristics as bitcell_0 (e.g., NMOS transistors 25 and 30 are part of dual cell array bitcell_1, NMOS transistors 35 and 40 are part of dual cell array bitcell_7, NMOS transistors 45 and 50 are part of dual cell array bitcell_8, and so on). The word line system test architecture circuit 10 also includes bit lines BLT0, BLT1, BLT7, complementary bit lines BLC0, BLC1, BLC7, BLC8, a source line SL, a word line enable signal WL_EN, word lines WL0, WL1, WLn, a row decoder 275, a bit line driver 280, a distributed source line driver 285, and word line drivers 286, 287, and 288.

[0018] NMOS transistors 15, 20, 25, 30, 35, 40, 45, and 50 are connected in series with each other. In an embodiment, the gates of NMOS transistors 15, 20, 25, 30, 35, 40, 45, and 50 are connected to word line WL0. NMOS transistors 55, 60, 65, 70, 75, 80, 85, and 90 are connected in series with each other. The gates of NMOS transistors 55, 60, 65, 70, 75, 80, 85, and 90 are all connected to word line WL1. NMOS transistors 95, 100, 105, 110, 115, 120, 125, and 130 are connected in series with each other. The gates of NMOS transistors 95, 100, 105, 110, 115, 120, 125, and 130 are connected to word line WLn. Row decoder 275 is connected to word lines WL0, WL1, and WLn through word line drivers 286, 287, and 288.

[0019] Bit line driver 280 of word line system test architecture circuit 10 includes NMOS transistors 135, 140, 145, 150, 155, 160, 165, 170, 175, 180, 185, 190, 195, 200, 205, 210. NMOS transistors 135 and 140 are connected in series, NMOS transistors 145 and 150 are connected in series, NMOS transistors 155 and 160 are connected in series, NMOS transistors 165 and 170 are connected in series, NMOS transistors 175 and 180 are connected in series, NMOS transistors 185 and 190 are connected in series, NMOS transistors 195 and 200 are connected in series, and NMOS transistors 205 and 210 are connected in series.

[0020] In an embodiment, NMOS transistors 135, 140 are connected to bit line BLTO, NMOS transistors 145, 150 are connected to complementary bit line BLC0, NMOS transistors 155, 160 are connected to bit line BLTl, NMOS transistors 165, 170 are connected to complementary bit line BLC1, NMOS transistors 175, 180 are connected to bit line BLT7, NMOS transistors 185, 190 are connected to complementary bit line BLC7, NMOS transistors 195, 200 are connected to bit line BLT8, and NMOS transistors 205, 210 are connected to complementary bit line BLC8.

[0021] The distributed source line driver 285 of the word line system test architecture circuit 10 includes PMOS transistors 215, 230, 245, and 260 and NMOS transistors 220, 225, 235, 240, 250, 255, 265, and 270. The PMOS transistor 215 and the NMOS transistors 220 and 225 are connected in series, the PMOS transistor 230 and the NMOS transistors 235 and 240 are connected in series, the PMOS transistor 245 and the NMOS transistors 250 and 255 are connected in series, and the PMOS transistor 260 and the NMOS transistors 265 and 270 are connected in series.

[0022] In an embodiment, the source line SL is connected between the PMOS transistor 215 and the NMOS transistors 220, the PMOS transistor 230 and the NMOS transistors 235, the PMOS transistor 245 and the NMOS transistors 250, and the PMOS transistor 260 and the NMOS transistors 265. The distributed source line driver 285 supports a primary data line (PDL) with 8-to-l column decoding.

[0023] In operation of the word line system test architecture circuit 10, a floor current extraction operation can be performed to characterize leakage current. In particular, the floor current extraction operation turns off the word line enable WL_EN signals to the word line drivers 286, 287, and 288 and measures the floor current through the voltage of the source line VSL. Further, a cell current-voltage (I-V) characterization operation can be performed, where the cell I-V characterization operation pulls one of the bit lines BLTO, BLT1, BLT7, and BLT8 to zero (“0”) volts, changes the voltage of the source line VSL to about 0.8 volts, changes the word line WL to a voltage value within a range between 0 volts and the level of the power supply VDD, and enables the word line enable WL_EN signal to the word line drivers 286, 287, and 288 to receive cell level access for at least one of a write operation and a current saturation monitoring operation (i.e., Idsatmonitor) for the FETs in the memory array. In particular, the cell level access for the write operation and the current saturation monitoring operation (i.e., Idsatmonitor) for the FETs in the memory array measures the current at the voltage input / output VIO point, as the voltage input / output VIO point will reach the voltage of the source line VSL. And, the floor current through the voltage of the source line VSL is removed from the current at the voltage input / output VIO point to minimize the leakage current impact (i.e., current at the voltage input / output VIO point with WL_EN enabled minus the floor current through the voltage of the source line VSL with WL_EN turned off to minimize the leakage current impact), thereby providing accurate cell current-voltage (I-V) characterization.

[0024] In the word line system test architecture circuit 10, the voltage of the source line VSL regulator bypass mode can also be used to measure the sub-current through the source line VSL to minimize the leakage current impact. In a non-limiting example, for a 12 kilobyte (Kb) selected from 96 kilobytes (Kb) (i.e., 8 VSL domains), a typical sub-current is less than 100 μΑ. Further, the multiple voltages of the source line VSL domains can be used for large arrays to perform the cell current-voltage (I-V) characterization operation.

[0025] In the word line system test architecture circuit 10, the maximum voltage program VPP level can be greater than the maximum voltage erase VERASE. Further, the word line system test architecture circuit 10 can include a voltage read VREAD level that is greater than or equal to the voltage read reference VRREF level. For example, the maximum voltage program VPP level can be 3.6 volts, the maximum voltage erase VERASE can be -1.8 volts, the voltage read VREAD level can be in a range between zero ("0") volts to the power supply VDD, and the voltage read reference VRREF level can be in a range between zero ("0") volts and -0.5 volts. It will be appreciated by those skilled in the art that other values are contemplated herein as well.

[0026] Further, a read operation can be performed with a selected word line WL having the voltage read VREAD level (e.g., 0.5 volts) and an unselected word line WL having the voltage read reference VRREF level (e.g., -0.4 volts). In an embodiment, the voltage read reference VRREF level can be a negative value to minimize the current leakage impact. In contrast, known circuits of the unselected word line WL have a second power supply VSS value (e.g., 0 volts) but do not account for the current leakage impact.

[0027] In further embodiments, a program operation can also be performed with a selected word line WL having the voltage program VPP level (e.g., 2.8 volts) and an unselected word line WL having the voltage read reference VRREF level (e.g., -0.4 volts). Further, an erase operation (i.e., bulk erase) can be performed with a selected word line WL having the voltage erase VERASE level (e.g., -1.5 volts) and an unselected word line WL having the voltage erase VERASE level (e.g., -1.5 volts).

[0028] Furthermore, current saturation monitoring operations Idsatmonitor (e.g., performing current-voltage (Id-Vg) characterization) can also be performed with selected word lines WL having a range of zero (“0”) volts to power supply VDD and unselected word lines WL at a voltage read reference VRREF level (e.g., -0.4 volts). In contrast, known systems perform read and program operations but cannot perform current saturation monitoring operations Idsatmon.

[0029] Figure 2 A block diagram of a word line system test architecture in a memory structure is shown in accordance with some aspects of the present disclosure. In the block diagram 300, an up level translator 305 receives a global word line x GWLX signal, a power supply VDD, a voltage program VPP level, a power supply VSS, and a voltage word reference VWREF signal. The up level translator 305 outputs a global word line for level translator GWL LT signal to a down level translator 310 and outputs a select voltage program SEL VPP PRG signal. The down level translator 310 receives the global word line for level translator GWL LT, a voltage read VREAD level, a voltage word reference VWREF signal, a power supply VSS, and a voltage read reference VRREF level. The down level translator 310 outputs a global word line level translator driver GWL LT D signal and a select voltage program read SEL VPP READ signal to a word line driver select logic 315.

[0030] The word line driver select logic 315 receives the global word line level translator driver GWL LT D, the select voltage program read SEL VPP READ signal, a read enable READ signal, a program enable PROG signal, an erase enable ERASE signal, and the select voltage program SEL VPP PRG signal. The word line driver select logic 315 also outputs a voltage word reference p VWREF P signal, a select p program SELP VPP signal, and a select n program voltage word line SELN VWL signal to a local word line driver 320. The local word line driver 320 receives the voltage word reference p VWREF P signal, the select p program SELP VPP signal, and the select n program voltage word line SELN VWL signal, a word line source WLSRC signal, a word line reset WLRST signal, and a voltage word line reference n VWREF N signal and outputs a word line WL.

[0031] In the block diagram 300, the upper level translator 325 receives the global word line y GWLY signal, the power supply VDD, the voltage program VPP level, the second power supply VSS, and the voltage word reference VWREF signal and outputs the global word line for the level translator GWL LT signal to the lower level translator 330 and outputs the select voltage program SEL VPP PRG signal. The lower level translator 330 receives the global word line for the level translator GWL LT, the voltage read VREAD level, the voltage word reference VWREF signal, the power supply VSS, and the voltage read reference VRREF level, and outputs the select voltage program read SEL VPP READ signal to the word line driver selection logic 335.

[0032] The word line driver selection logic 335 receives the select voltage program read SEL VPP READ signal, the control CONTROL signal, the global word line for the level translator GWL LT, the select voltage program SEL VPP PRG signal, and outputs the select p program SELP VPP signal and the select n program voltage word line SELN VWL signal to the local word line driver 340. The local word line driver 340 receives the select p program SELP VPP signal, the select n program voltage word line SELN VWL signal, the word line source low WLSRCL signal, the word line source high WLSRCH signal, and outputs the word line source WLSRC signal and the word line reset WLRST signal.

[0033] The word line driver selection logic 315 and the word line driver selection logic 335 include an analog compound multiplexer integrated switch 400 configured to perform a current saturation monitoring operation Idsatmonitor (e.g., perform a current-voltage (Id-Vg) characterization). As described above, the word line driver selection logic 315 and the word line driver selection logic 335 perform a current-voltage (Id-Vg) characterization that cannot be performed in known circuits. The analog compound multiplexer integrated switch 400 can also be used to disable reliability voltage limit violations. The analog compound multiplexer integrated switch 400 for performing a current saturation monitoring operation Idsatmonitor (e.g., performing a current-voltage (Id-Vg) characterization) will be discussed in detail in Figure 3A , 3B , 4A and 4B.

[0034] Figure 3A and 3B A programming mode of the analog compound multiplexer integrated switch of the word line system test architecture in a memory structure is shown. In Figure 3AIn the selected word line SEL WL programming mode PRGMODE for the analog compound multiplexer integrated switch 400 for the first word line driver select logic 315 and the second word line driver select logic 335, the first voltage can be greater than the second voltage, the second voltage can be greater than the third voltage, and the third voltage can be greater than the fourth voltage. In particular, in the illustrative non-limiting embodiment, the first voltage can be about 2.8 volts, the second voltage can be about 1.4 volts, the third voltage can be about 0 volts, and the fourth voltage can be about -0.4 volts. Figure 3A and 3B In the selected word line SEL WL programming mode PRGMODE for the analog compound multiplexer integrated switch 400, different voltage values can be used to disable reliability voltage limit violations and support programming characteristics. In the selected word line SEL WL programming mode PRGMODE for the analog compound multiplexer integrated switch 400, the first voltage can be greater than the second voltage, the second voltage can be greater than the third voltage, and the third voltage can be greater than the fourth voltage. In particular, in the illustrative non-limiting embodiment, the first voltage can be about 2.8 volts, the second voltage can be about 1.4 volts, the third voltage can be about 0 volts, and the fourth voltage can be about -0.4 volts.

[0035] In the selected word line SEL WL programming mode PRGMODE for the analog compound multiplexer integrated switch 400, different voltage values can be used to disable reliability voltage limit violations and support programming characteristics. In the selected word line SEL WL programming mode PRGMODE for the analog compound multiplexer integrated switch 400, the first voltage can be greater than the second voltage, the second voltage can be greater than the third voltage, and the third voltage can be greater than the fourth voltage. In particular, in the illustrative non-limiting embodiment, the first voltage can be about 2.8 volts, the second voltage can be about 1.4 volts, the third voltage can be about 0 volts, and the fourth voltage can be about -0.4 volts. Figure 3A In the selected word line SEL WL programming mode PRGMODE for the analog compound multiplexer integrated switch 400, the drain of the NMOS transistor 430 has a voltage word reference VWREF signal value of the second voltage. In addition, the gate of the NMOS transistor 430 also has a value of the second voltage. The first switch 405 has an input of the second voltage and receives the second voltage at the PMOS portion of the switch 405 and the first voltage at the NMOS portion of the switch 405. This allows the switch 405 to turn on and output the second voltage from the input of the switch 405. In contrast, the second switch 410 has an input of the second voltage and receives the third voltage at the PMOS portion of the switch 410 and the fourth voltage at the NMOS portion of the second switch 410. In this case, the switch 410 turns on and the second voltage is passed to the select programming SEL VPP signal.

[0036] In the selected word line SEL WL programming mode PRGMODE for the analog compound multiplexer integrated switch 400, different voltage values can be used to disable reliability voltage limit violations and support programming characteristics. In the selected word line SEL WL programming mode PRGMODE for the analog compound multiplexer integrated switch 400, the first voltage can be greater than the second voltage, the second voltage can be greater than the third voltage, and the third voltage can be greater than the fourth voltage. In particular, in the illustrative non-limiting embodiment, the first voltage can be about 2.8 volts, the second voltage can be about 1.4 volts, the third voltage can be about 0 volts, and the fourth voltage can be about -0.4 volts. Figure 3AIn this circuit, the source of PMOS transistor 415 has a voltage word reference value VWREF for a second voltage. Furthermore, the gate of the NMOS transistor has a fourth voltage value. Since the gate of NMOS transistor 425 has a second voltage value, this second voltage is applied to the drain of NMOS transistor 415. The gate of NMOS transistor 420 has a fourth voltage value. Therefore, PMOS transistor 415 can be configured as a protective switch to prevent reverse conditions, as indicated by "X" in the analog multiplexer integrated switch 400. Furthermore, the analog multiplexer integrated switch 400 supports four voltage domains: 2.8V, 1.4V, -0.4V, or the read voltage VREAD. The analog multiplexer integrated switch 400 also ensures that there are no reliability limit violations. Moreover, for N voltage domains, the analog multiplexer integrated switch 400 can be cascaded multiple times in the circuit, where N is an integer.

[0037] exist Figure 3B The diagram shows the programming mode PRG MODE for the unselected word line UNSEL WL of the analog composite multiplexer integrated switch 400 used for word line driver selection logic unit 315 and word line driver selection logic unit 335. Figure 3B In the programming mode PRG MODE where the word line UNSEL WL is not selected, the drain of NMOS transistor 430 has a second voltage value. Additionally, the gate of NMOS transistor 430 has a second voltage value. Switch 405 has a first voltage input and receives the second voltage at its PMOS portion and the first voltage at its NMOS portion. This allows switch 405 to be turned on and output the first voltage from its input. In contrast, switch 410 has a first voltage input and receives the second voltage at its PMOS portion and the second voltage at its NMOS portion. In this case, switch 410 is turned on and the first voltage is passed to the select programming SEL_VPP signal.

[0038] exist Figure 3B In this circuit, the source of PMOS transistor 415 has a voltage word reference value VWREF. Furthermore, the gate of PMOS transistor 415 has a fourth voltage value. Since the gate of NMOS transistor 425 has a second voltage value, this second voltage is applied to the drain of NMOS transistor 415. The gate of NMOS transistor 420 has a fourth voltage value. For N voltage domains, the analog composite multiplexer integrated switch 400 can be cascaded multiple times in the circuit, where N is an integer.

[0039] Figure 4A and 4BA read / Idsatmon mode of the analog composite multiplexer integrated switch is shown for the word line system test architecture in the memory structure. In Figure 4A , a read / Idsatmon READ / IDSATMON mode of the analog composite multiplexer integrated switch 400 for the selected word line SEL WL for the word line driver selection logic 315 and the word line driver selection logic 335 is shown. Similar to Figure 3A and 3B , the first voltage, the second voltage, the third voltage, and the fourth voltage can be used in Figure 4A and 4B to disable reliability voltage limit violations and support cell current-voltage (I-V) characterization. In a non-limiting example, each of the first, second, third, and fourth voltages can have different voltage values. In the read / Idsatmon READ / IDSATMON mode for the selected word line SEL of the analog composite multiplexer integrated switch 400, the first voltage can be greater than the second voltage, the second voltage greater than the third voltage, and the third voltage greater than the fourth voltage. In particular, in one embodiment, the first voltage can be about 2.8 volts, the second voltage can be about 1.4 volts, the third voltage can be about 0 volts, and the fourth voltage can be about -0.4 volts.

[0040] In Figure 4A , for the READ / IDSATMON MODE of the selected word line SEL WL, the drain of the NMOS transistor 430 has the voltage word reference VWREF signal. Further, the gate of the NMOS transistor 430 has a value of the first voltage. The first switch 405 has an input of the second voltage and receives the first voltage at the PMOS portion of the first switch 405 and the second voltage at the NMOS portion of the first switch 405. The second switch 410 has an input of the second voltage and receives the second voltage at the PMOS portion of the second switch 410 and the fourth voltage at the NMOS portion of the second switch 410. In this case, the second switch 410 is a protection switch that prevents a reverse condition, as indicated by the “X” in the analog composite multiplexer integrated switch 400.

[0041] In Figure 4A , the source of the PMOS transistor 415 has the voltage word reference VWREF signal value. Further, the gate of the NMOS transistor has a value of the second voltage. The gates of the NMOS transistors 420 and 425 have a value of the second voltage. This allows the fourth voltage to be passed to the select program SEL VPP signal. The analog composite multiplexer integrated switch 400 can be cascaded multiple times in a circuit for N voltage domains, where N is an integer.

[0042] In Figure 4BIn the READ / IDSATMON mode for the unselected word line UNSEL WL, the drain of the NMOS transistor 430 has the voltage word reference VWREF signal. Further, the gate of the NMOS transistor 430 has a value of the first voltage. The first switch 405 has an input of the first voltage and receives the first voltage at the PMOS portion of the first switch 405 and receives the second voltage at the NMOS portion of the first switch 405. The second switch 410 has an input of the second voltage and receives the second voltage at the PMOS portion of the second switch 410 and receives the fourth voltage at the NMOS portion of the second switch 410. Figure 4B

[0043] In the READ / IDSATMON mode for the unselected word line UNSEL WL, the drain of the NMOS transistor 430 has the voltage word reference VWREF signal. Further, the gate of the NMOS transistor 430 has a value of the first voltage. The first switch 405 has an input of the first voltage and receives the first voltage at the PMOS portion of the first switch 405 and receives the second voltage at the NMOS portion of the first switch 405. The second switch 410 has an input of the second voltage and receives the second voltage at the PMOS portion of the second switch 410 and receives the fourth voltage at the NMOS portion of the second switch 410. Figure 4B

[0044] Figure 5A and 5B A graph showing the relationship of current Id and voltage Vg for different modes and states of a word line system test architecture in a memory structure in accordance with some aspects of the present disclosure is shown. In Figure 5A In the READ / IDSATMON mode for the unselected word line UNSEL WL, the drain of the NMOS transistor 430 has the voltage word reference VWREF signal. Further, the gate of the NMOS transistor 430 has a value of the first voltage. The first switch 405 has an input of the first voltage and receives the first voltage at the PMOS portion of the first switch 405 and receives the second voltage at the NMOS portion of the first switch 405. The second switch 410 has an input of the second voltage and receives the second voltage at the PMOS portion of the second switch 410 and receives the fourth voltage at the NMOS portion of the second switch 410.

[0045] Figure 5B ​​A graph 600 is shown that includes gate voltage Vg on the x-axis and drain current Id in mA on the y-axis. The graph 600 shows the I-V characterization of the pristine state (i.e., unactivated state E), the programmed state (F), and the erased state (D) of a functional memory (i.e., a field effect transistor). In the graph 600, the programmed state (F) of the functional memory (i.e., a field effect transistor) has less current than the pristine state (E) and the erased state (D) at a certain voltage above 0.3 volts. Figure 5B

[0046] A variety of different tools can be used to fabricate the word line system architecture circuit in a variety of ways. Generally, however, these methods and tools are used to form structures having micrometer and nanometer scale dimensions. Methods (i.e., techniques) used to fabricate sense amplifier circuits have been adopted in integrated circuit (IC) technology. For example, the word line system architecture circuit can be built on a wafer and implemented in a material film patterned on top of the wafer by a photolithography process. In particular, the fabrication of the word line system architecture circuit uses three basic building blocks: (i) deposition of a thin film of material on a substrate; (ii) application of a patterned mask on top of the film by photolithographic imaging; and (iii) etching of the film selectively to the mask.

[0047] The word line system architecture circuit for current sensing in memory structures can be utilized in system on a chip (SoC) technology. As will be appreciated by those skilled in the art, an SoC is an integrated circuit (also known as a “chip”) that integrates all components of an electronic system on a single chip or substrate. Because the components are integrated on a single substrate, an SoC consumes much less power and occupies much less area than a multi-chip design with equivalent functionality. As a result, SoCs are becoming a dominant force in the mobile computing (e.g., smartphones) and edge computing markets. SoCs are also commonly used in embedded systems and the Internet of Things.

[0048] The above-described structures and methods are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricant in raw wafer form (i.e., as a single wafer having a plurality of unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to the motherboard or other higher level carrier) or in a multi-chip package (such as a ceramic carrier that has

[0049] ​The description of various embodiments of the present disclosure has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A word line system architecture, comprising: a dual cell circuit connected to a word line of a memory array, wherein the word line of the memory array is disabled during a sub-threshold current extraction operation to minimize a leakage current of the dual cell circuit; a source line driver connected to a source line of the memory array for providing a cell level current-voltage (I-V) access of the dual cell circuit; and an integrated analog multiplexer connected to the dual cell circuit.

2. The architecture of claim 1, wherein the dual cell circuit comprises a first NMOS transistor and a second NMOS transistor.

3. The architecture of claim 2, wherein the word line of the memory array is connected to a gate of the first NMOS transistor and a gate of the second NMOS transistor.

4. The architecture of claim 3, wherein the source line driver comprises a PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor.

5. The architecture of claim 4, wherein the source line of the memory array is connected between the PMOS transistor and the third NMOS transistor of the source line driver.

6. The architecture of claim 1, wherein the cell level I-V access of the dual cell circuit comprises measuring a current within a voltage range of the dual cell circuit in at least one of a current saturation monitoring mode and a write mode.

7. The architecture of claim 6, wherein the word line of the memory array is enabled using the integrated analog multiplexer during the at least one of the current saturation monitoring mode and the write mode.

8. The architecture of claim 1, wherein a sub-threshold current of the source line is measured during the sub-threshold current extraction operation.

9. The architecture of claim 1, wherein the dual cell circuit is connected between a bit line true signal and a bit line complement signal of the memory array.

10. The architecture of claim 9, wherein the bit line true signal is set to zero volts and a voltage of the source line is set to 0.8 volts.

11. An integrated circuit, comprising: a dual cell memory array comprising at least one dual cell circuit connected to a word line, a bit line true signal, and a bit line complement signal, wherein the word line of the dual cell memory array is disabled during a sub-threshold current extraction operation to minimize a leakage current of the dual cell circuit; and an integrated analog multiplexer circuit configured to provide a plurality of voltages as inputs to a word line driver circuit based on a predetermined mode of the at least one dual cell circuit.

12. The circuit of claim 11, further comprising a bit line driver circuit connected to the bit line true signal and the bit line complement signal, and the dual cell circuit comprises a first NMOS transistor and a second NMOS transistor.

13. The circuit of claim 12, wherein the word line of the memory array is connected to a gate of the first NMOS transistor and a gate of the second NMOS transistor. ​ ​ 14. The circuit of claim 13, further comprising a source line driver circuit connected to a source line of the dual cell memory array, and the source line driver circuit comprises a PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor.

15. The circuit of claim 14, wherein the source line of the memory array is connected between the PMOS transistor and the third NMOS transistor of the source line driver.

16. The circuit of claim 14, wherein the source line of the memory array provides a cell level access of the dual cell circuit.

17. The circuit of claim 16, wherein performing the cell level access of the dual cell circuit comprises measuring a current within a voltage range of the dual cell circuit in at least one of a current saturation monitoring mode and a write mode.

18. The circuit of claim 17, wherein the word line of the memory array is enabled using an integrated analog multiplexer comprising at least three PMOS transistors and at least two NMOS transistors during the at least one of the current saturation monitoring mode and the write mode.

19. A method of operating a word line system, comprising: enabling a word line of a dual cell circuit connected to a memory array using an integrated analog multiplexer; disabling the word line of the memory array during a bottom current extraction operation to minimize a leakage current of the dual cell circuit; and measuring a current within a voltage range of the dual cell circuit in a current saturation monitoring mode. ​

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