GaN amplitude-phase control multifunction chip and phased array system

Abstract

The application provides a GaN amplitude-phase control multifunctional chip and a phased array system, and belongs to the technical field of microelectronics. The GaN amplitude-phase control multifunctional chip comprises an input port, an output port, a distributed current multiplexing amplifier, a phase shifter, a first DC blocking capacitor and a second DC blocking capacitor; the distributed current multiplexing amplifier comprises a first switch tube, a second switch tube, a first gate voltage supply circuit, a DC self-bias circuit, a negative feedback circuit, a first choke filter circuit, a second gate voltage supply circuit, a second choke filter circuit and a voltage source. The application is based on the above-mentioned components and the connection relationship between the components, so that the push stage amplifier in the GaN amplitude-phase control multifunctional chip adopts a distributed current multiplexing structure, thereby reducing the power consumption of the push stage amplifier, improving the efficiency of the GaN amplitude-phase control multifunctional chip, and enabling the GaN amplitude-phase control multifunctional chip to realize high efficiency under the condition of small size and high power.

Description

Technical Field

[0001] This invention relates to the field of microelectronics technology, and in particular to a GaN amplitude and phase control multifunctional chip and phased array system. Background Technology

[0002] With the increasingly widespread application of phased array systems in communication, detection, and other fields, the demand for miniaturized and high-power multifunctional chips for amplitude and phase control, as their core components, is becoming increasingly urgent. In recent years, due to the high breakdown, high power, and high efficiency characteristics of GaN HEMT devices, GaN HEMT-based amplitude and phase control chips have also attracted much attention.

[0003] However, since the leakage current of GaN chips is generally a high voltage of +15V or higher, the power consumption of GaN amplitude and phase control multifunctional chips in low-power driver amplifiers is relatively large, resulting in low overall efficiency. Summary of the Invention

[0004] This invention provides a GaN amplitude and phase control multifunctional chip and phased array system to solve the problem that the high power consumption of the driver stage amplifier in the prior art leads to the low efficiency of the GaN amplitude and phase control multifunctional chip.

[0005] In a first aspect, embodiments of the present invention provide a GaN amplitude and phase control multifunctional chip, including an input port, an output port, a distributed current multiplexing amplifier, a phase shifter, a first DC blocking capacitor, and a second DC blocking capacitor;

[0006] The distributed current multiplexing amplifier includes a first switching transistor, a second switching transistor, a first gate voltage supply circuit, a DC self-biasing circuit, a negative feedback circuit, a first choke filter circuit, a second gate voltage supply circuit, a second choke filter circuit, and a voltage source;

[0007] The first terminal of the first gate voltage providing circuit is connected to the input port. The second terminal of the first gate voltage providing circuit is connected to the control terminal of the first switching transistor and the first terminal of the negative feedback circuit. The first terminal of the first switching transistor is connected to the second terminal of the negative feedback circuit, and the second terminal of the first switching transistor is connected to the first terminal of the DC self-biasing circuit. The third terminal of the negative feedback circuit is connected to the first terminal of the first DC blocking capacitor and the first terminal of the first choke filter circuit. The second terminal of the first DC blocking capacitor is connected to the first terminal of the phase shifter, and the second terminal of the phase shifter is connected to the first terminal of the second DC blocking capacitor. The second terminal of the second DC blocking capacitor is connected to the first terminal of the second gate voltage providing circuit and the control terminal of the second switching transistor. The first terminal of the second switching transistor is connected to the first terminal of the second choke filter circuit, and the second terminal of the second switching transistor is connected to the second terminal of the first choke filter circuit. The second terminals of the second gate voltage providing circuit and the second choke filter circuit are both connected to the positive terminal of the voltage source. The third terminal of the second choke filter circuit is connected to the output port.

[0008] In one possible implementation, the first gate voltage providing circuit includes a first inductor, a second inductor, and a first resistor;

[0009] The first end of the first inductor serves as the first end of the first gate voltage supply circuit. The second end of the first inductor is connected to the first end of the second inductor, and the second end of the first inductor also serves as the second end of the first gate voltage supply circuit. The second end of the second inductor is connected to the first end of the first resistor, and the second end of the first resistor is grounded.

[0010] In one possible implementation, the DC self-biasing circuit includes a first microstrip line, a second capacitor, and a third resistor;

[0011] The first end of the first microstrip line serves as the first end of the DC self-biasing circuit. The second end of the first microstrip line is connected to the first end of the second capacitor and the first end of the third resistor. The second ends of the second capacitor and the third resistor are both grounded.

[0012] In one possible implementation, the negative feedback circuit includes a third inductor, a third capacitor, and a second resistor;

[0013] The first end of the second resistor serves as the first end of the negative feedback circuit, and the second end of the second resistor is connected to the first end of the third capacitor. The second end of the third capacitor serves as the third end of the negative feedback circuit. The first end of the third inductor serves as the second end of the negative feedback circuit, and the second end of the third inductor is connected to the second end of the third capacitor.

[0014] In one possible implementation, the first choke filter circuit includes a second microstrip line, a third microstrip line, a fourth resistor, and a fifth capacitor;

[0015] The first end of the third microstrip line serves as the first end of the first choke filter circuit, and the second end of the third microstrip line is connected to the first end of the fourth resistor; the first end of the second microstrip line serves as the second end of the first choke filter circuit, and the second end of the second microstrip line is connected to the second end of the fourth resistor and the first end of the fifth capacitor, and the second end of the fifth capacitor is grounded.

[0016] In one possible implementation, the second gate voltage providing circuit includes a fifth resistor, a sixth resistor, and a seventh resistor;

[0017] The first end of the fifth resistor is grounded, and the second end of the fifth resistor is connected to the first end of the sixth resistor and the first end of the seventh resistor. The second end of the seventh resistor serves as the first end of the second gate voltage supply circuit, and the second end of the sixth resistor serves as the second end of the second gate voltage supply circuit.

[0018] In one possible implementation, the second choke filter circuit includes a fifth inductor, a sixth inductor, and a seventh capacitor;

[0019] The first end of the fifth inductor serves as the first end of the second choke filter circuit, the second end of the fifth inductor serves as the third end of the second choke filter circuit, the second end of the fifth inductor is also connected to the first end of the sixth inductor, the second end of the sixth inductor serves as the second end of the second choke filter circuit, the second end of the sixth inductor is also connected to the first end of the seventh capacitor, and the second end of the seventh capacitor is grounded.

[0020] In one possible implementation, the distributed current multiplexing amplifier also includes a first capacitor and a sixth capacitor;

[0021] The first terminal of the first gate voltage supply circuit is connected to the input port through the first capacitor;

[0022] The third terminal of the second choke filter circuit is connected to the output port through the sixth capacitor.

[0023] In one possible implementation, the GaN amplitude and phase control multifunctional chip also includes an attenuator and a power amplifier;

[0024] The third terminal of the second choke filter circuit is connected to the output port in sequence through an attenuator and a power amplifier.

[0025] Secondly, embodiments of the present invention provide a phased array system, including a GaN amplitude and phase control multifunctional chip in the first aspect or any possible implementation of the first aspect.

[0026] This invention provides a GaN amplitude and phase control multifunctional chip and a phased array system. The GaN amplitude and phase control multifunctional chip includes a distributed current multiplexed amplifier, a phase shifter, a first DC blocking capacitor, and a second DC blocking capacitor. The distributed current multiplexed amplifier includes a first switching transistor, a second switching transistor, a first gate voltage supply circuit, a DC self-biasing circuit, a negative feedback circuit, a first choke filter circuit, a second gate voltage supply circuit, a second choke filter circuit, and a voltage source. Based on the above components and their interconnections, the driver stage amplifier in the GaN amplitude and phase control multifunctional chip adopts a distributed current multiplexing structure, thereby reducing the power consumption of the driver stage amplifier and improving the efficiency of the GaN amplitude and phase control multifunctional chip. This allows the GaN amplitude and phase control multifunctional chip to achieve high efficiency in a small size and high power configuration. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1This is a schematic diagram of the structure of a GaN amplitude and phase control multifunctional chip provided in an embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram of the layout of a GaN amplitude and phase control multifunctional chip provided in an embodiment of the present invention;

[0030] Figure 3 This is a schematic diagram of the insertion loss curve of the phase shifter in a GaN amplitude-phase control multifunctional chip provided in an embodiment of the present invention;

[0031] Figure 4 This is a schematic diagram of the phase shifting accuracy RMS curve of the phase shifter in a GaN amplitude-phase control multifunctional chip provided in an embodiment of the present invention;

[0032] Figure 5 This is a schematic diagram of the insertion loss curve of the attenuator in a GaN amplitude-phase control multifunctional chip provided in an embodiment of the present invention;

[0033] Figure 6 This is a schematic diagram of the attenuation accuracy RMS curve of the attenuator in a GaN amplitude-phase control multifunctional chip provided in an embodiment of the present invention;

[0034] Figure 7 This is a schematic diagram of the power gain curve of the distributed current multiplexing amplifier in a GaN amplitude and phase control multifunctional chip provided in an embodiment of the present invention;

[0035] Figure 8 This is a schematic diagram of the stability factor curve of the distributed current multiplexing amplifier in a GaN amplitude and phase control multifunctional chip provided in an embodiment of the present invention.

[0036] Figure 9 This is a schematic diagram of the output power curve of the distributed current multiplexing amplifier in a GaN amplitude and phase control multifunctional chip provided in an embodiment of the present invention;

[0037] Figure 10 This is a current schematic diagram of the distributed current multiplexing amplifier in a GaN amplitude and phase control multifunctional chip provided in an embodiment of the present invention;

[0038] Figure 11 This is a schematic diagram of the output power curve of a GaN amplitude and phase control multifunctional chip provided in an embodiment of the present invention;

[0039] Figure 12 This is a schematic diagram of the current curve of a GaN amplitude and phase control multifunctional chip provided in an embodiment of the present invention. Detailed Implementation

[0040] To enable those skilled in the art to better understand this solution, the technical solutions in the embodiments of this solution will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this solution, not all of them. Based on the embodiments of this solution, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this solution.

[0041] The term "comprising" and any other variations thereof in the specification, claims, and accompanying drawings of this invention mean "including but not limited to," and are intended to cover a non-exclusive inclusion, not limited to the examples listed herein. Furthermore, the terms "first" and "second," etc., are used to distinguish different objects, not to describe a specific order.

[0042] With the increasing performance of phased array systems, the demand for higher single-channel output power, efficiency, and miniaturization is becoming more urgent. GaN amplitude-phase control multifunctional chips offer an optimal solution for miniaturization and high power. In related technologies, research on GaN amplitude-phase control multifunctional chips has primarily focused on high power and miniaturization, with less emphasis on high efficiency. Furthermore, driver amplifiers with output power below 20dBm cannot significantly reduce the HEMT gate width due to frequency and impedance matching limitations, resulting in higher power consumption and consequently lower efficiency for GaN amplitude-phase control multifunctional chips.

[0043] In related technologies, in order to reduce the power consumption of the driver amplifier, a structure in which two amplifiers are placed together (without a passive functional module network in between) is commonly used. However, in the link design of GaN amplitude and phase control multifunctional chips, the local gain of the link is relatively high, and this structure cannot solve the problem of high power consumption.

[0044] To address the aforementioned issues, this application provides a GaN amplitude and phase control multifunctional chip.

[0045] Figure 1 This is a schematic diagram of the structure of a GaN amplitude and phase control multifunctional chip provided in an embodiment of the present invention. (Refer to...) Figure 1 The GaN amplitude and phase control multifunctional chip includes an input port, an output port, a distributed current multiplexing amplifier, a phase shifter S1, a first DC blocking capacitor C4, and a second DC blocking capacitor C8.

[0046] The distributed current multiplexing amplifier includes a first switch Q1, a second switch Q2, a first gate voltage supply circuit 11, a DC self-biasing circuit 12, a negative feedback circuit 13, a first choke filter circuit 14, a second gate voltage supply circuit 15, a second choke filter circuit 16, and a voltage source V1;

[0047] The first terminal of the first gate voltage providing circuit 11 is connected to the input port. The second terminal of the first gate voltage providing circuit 11 is connected to the control terminal of the first switch Q1 and the first terminal of the negative feedback circuit 13. The first terminal of the first switch Q1 is connected to the second terminal of the negative feedback circuit 13 and the first terminal of the DC self-biasing circuit 12. The third terminal of the negative feedback circuit 13 is connected to the first terminal of the first DC blocking capacitor C4 and the first terminal of the first choke filter circuit 14. The second terminal of the first DC blocking capacitor C4 is connected to the first terminal of the phase shifter S1 and the second terminal of the phase shifter S1 is connected to the first terminal of the second DC blocking capacitor C8. The second terminal of the second DC blocking capacitor C8 is connected to the first terminal of the second gate voltage providing circuit 15 and the control terminal of the second switch Q2. The first terminal of the second switch Q2 is connected to the first terminal of the second choke filter circuit 16 and the second terminal of the second switch Q2 is connected to the second terminal of the first choke filter circuit 14. The second terminals of the second gate voltage providing circuit 15 and the second choke filter circuit 16 are both connected to the positive terminal of the voltage source V1. The third terminal of the second choke filter circuit 16 is connected to the output port.

[0048] The distributed current multiplexing amplifier in this embodiment serves as a driver stage amplifier, comprising two driver amplifier stages: a first driver amplifier and a second driver amplifier. The first and second driver amplifiers employ a distributed structure, and their currents are multiplexed. See also... Figure 1 , Figure 1 The arrows in the diagram represent current, which is... Figure 1 As can be seen from the arrows, the current of the first driver amplifier and the second driver amplifier is multiplexed.

[0049] In the link structure, a phase shifter S1 is connected between the first driver amplifier and the second driver amplifier. The first driver amplifier, phase shifter S1, and second driver amplifier adopt a distributed current multiplexing structure. For the specific topology, please refer to [link to relevant documentation]. Figure 1 After adopting the distributed current multiplexing structure provided in this application embodiment, the current of the first driver amplifier and the second driver amplifier is about 70mA, and their gain, power and stability can meet the chip's usage requirements.

[0050] To ensure the normal DC operating point of the distributed current multiplexing amplifier, and because there is an RF branch to ground in the phase shifter S1, this embodiment requires the addition of DC blocking capacitors before and after the phase shifter S1, namely, a first DC blocking capacitor C4 and a second DC blocking capacitor C8. Specifically, the first DC blocking capacitor C4 is the DC blocking capacitor between the first driver amplifier and the phase shifter S1, and the second DC blocking capacitor C8 is the DC blocking capacitor between the phase shifter S1 and the second driver amplifier.

[0051] To ensure phase shift accuracy, it is necessary to ensure that after the phase shift is disconnected, the output after the first DC blocking capacitor C4 and the input before the second DC blocking capacitor C8 are 50Ω matched.

[0052] The first gate voltage providing circuit 11 can also be called the first gate voltage providing network. It can provide the gate voltage zero potential for the first driver amplifier, and can also be used as an input matching network or input matching circuit. Therefore, the first gate voltage providing circuit 11 can be called the first input matching and gate voltage zero potential providing circuit or the first input matching and gate voltage zero potential providing network.

[0053] The DC self-biasing circuit 12 can also be called a DC self-biasing network.

[0054] The negative feedback circuit 13 can also be called a negative feedback network, which can be used to improve stability. Therefore, it can also be called a negative feedback stability network or a negative feedback stability circuit.

[0055] The first choke filter circuit 14 can also be called the first choke filter network, specifically the choke filter network of the first driver amplifier.

[0056] The second gate voltage supply circuit 15, also known as the second gate voltage supply network, can provide gate voltage for the second driver amplifier.

[0057] The second choke filter circuit 16 can also be called the second choke filter network, which is the choke filter network of the second driver amplifier, specifically the choke and filter network of the DC network of the second driver amplifier.

[0058] The input port can also be called the RF input port, and the output port can also be called the RF output port.

[0059] The current source can provide a +15V voltage, and the negative terminal of the current source is grounded.

[0060] The first switch Q1 and the second switch Q2 can be any applicable type of switch, without any specific restrictions.

[0061] The GaN amplitude and phase control multifunctional chip provided in this application embodiment includes a distributed current multiplexed amplifier, a phase shifter S1, a first DC blocking capacitor C4, and a second DC blocking capacitor C8. The distributed current multiplexed amplifier includes a first switch Q1, a second switch Q2, a first gate voltage supply circuit 11, a DC self-biasing circuit 12, a negative feedback circuit 13, a first choke filter circuit 14, a second gate voltage supply circuit 15, a second choke filter circuit 16, and a voltage source V1. Based on the above components and the connection relationship between them, the driver stage amplifier in the GaN amplitude and phase control multifunctional chip adopts a distributed current multiplexed structure, which can reduce the power consumption of the driver stage amplifier and improve the efficiency of the GaN amplitude and phase control multifunctional chip. This allows the GaN amplitude and phase control multifunctional chip to achieve high efficiency in a small size and high power.

[0062] The structure of the GaN amplitude and phase control multifunctional chip provided in this application embodiment can reduce the power consumption of the driver amplifier to half of its original value.

[0063] The foregoing embodiments describe a distributed current multiplexing amplifier including a first gate voltage providing circuit 11, a DC self-biasing circuit 12, a negative feedback circuit 13, a first choke filter circuit 14, a second gate voltage providing circuit 15, and a second choke filter circuit 16. The specific structures of the first gate voltage providing circuit 11, the DC self-biasing circuit 12, the negative feedback circuit 13, the first choke filter circuit 14, the second gate voltage providing circuit 15, and the second choke filter circuit 16 are further described below.

[0064] In some embodiments, see Figure 1 The first gate voltage supply circuit 11 includes a first inductor L1, a second inductor L2, and a first resistor R1;

[0065] The first end of the first inductor L1 serves as the first end of the first gate voltage supply circuit 11. The second end of the first inductor L1 is connected to the first end of the second inductor L2. The second end of the first inductor L1 also serves as the second end of the first gate voltage supply circuit 11. The second end of the second inductor L2 is connected to the first end of the first resistor R1. The second end of the first resistor R1 is grounded.

[0066] In some embodiments, see Figure 1 The DC self-biasing circuit 12 includes a first microstrip line MLIN1, a second capacitor C2, and a third resistor R3.

[0067] The first end of the first microstrip line MLIN1 serves as the first end of the DC self-biasing circuit 12. The second end of the first microstrip line MLIN1 is connected to the first end of the second capacitor C2 and the first end of the third resistor R3. The second ends of the second capacitor C2 and the second ends of the third resistor R3 are both grounded.

[0068] In some embodiments, see Figure 1 The negative feedback circuit 13 includes a third inductor L3, a third capacitor C3, and a second resistor R2.

[0069] The first end of the second resistor R2 serves as the first end of the negative feedback circuit 13, and the second end of the second resistor R2 is connected to the first end of the third capacitor C3. The second end of the third capacitor C3 serves as the third end of the negative feedback circuit 13. The first end of the third inductor L3 serves as the second end of the negative feedback circuit 13, and the second end of the third inductor L3 is connected to the second end of the third capacitor C3.

[0070] In some embodiments, see Figure 1 The first choke filter circuit 14 includes a second microstrip line MLIN2, a third microstrip line MLIN3, a fourth resistor R4, and a fifth capacitor C5.

[0071] The first end of the third microstrip line MLIN3 serves as the first end of the first choke filter circuit 14, and the second end of the third microstrip line MLIN3 is connected to the first end of the fourth resistor R4; the first end of the second microstrip line MLIN2 serves as the second end of the first choke filter circuit 14, and the second end of the second microstrip line MLIN2 is connected to the second end of the fourth resistor R4 and the first end of the fifth capacitor C5, and the second end of the fifth capacitor C5 is grounded.

[0072] See Figure 2 The diagram shows a layout schematic of a GaN amplitude and phase control multifunctional chip. Due to the large size of the phase shifter S1, the first and second driver amplifiers are far apart in the layout, and the choke inductance between the stages (between the first and second driver amplifiers) needs to be represented by a long microstrip line, namely the aforementioned third microstrip line MLIN3.

[0073] In some embodiments, see Figure 1 The second gate voltage supply circuit 15 includes a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7;

[0074] The first end of the fifth resistor R5 is grounded, and the second end of the fifth resistor R5 is connected to the first end of the sixth resistor R6 and the first end of the seventh resistor R7. The second end of the seventh resistor R7 serves as the first end of the second gate voltage supply circuit 15, and the second end of the sixth resistor R6 serves as the second end of the second gate voltage supply circuit 15.

[0075] In some embodiments, see Figure 1 The second choke filter circuit 16 includes a fifth inductor L5, a sixth inductor L6 and a seventh capacitor C7;

[0076] The first end of the fifth inductor L5 serves as the first end of the second choke filter circuit 16, the second end of the fifth inductor L5 serves as the third end of the second choke filter circuit 16, the second end of the fifth inductor L5 is also connected to the first end of the sixth inductor L6, the second end of the sixth inductor L6 serves as the second end of the second choke filter circuit 16, the second end of the sixth inductor L6 is also connected to the first end of the seventh capacitor C7, and the second end of the seventh capacitor C7 is grounded.

[0077] In some embodiments, see Figure 1 The distributed current multiplexing amplifier also includes a first capacitor C1 and a sixth capacitor C6;

[0078] The first terminal of the first gate voltage supply circuit 11 is connected to the input port through the first capacitor C1;

[0079] The third terminal of the second choke filter circuit 16 is connected to the output port through the sixth capacitor C6.

[0080] The first capacitor C1 serves as the input DC blocking capacitor; the sixth capacitor C6 serves as the output DC blocking capacitor.

[0081] In some embodiments, see Figure 2 The GaN amplitude and phase control multifunctional chip also includes an attenuator and a power amplifier;

[0082] The third terminal of the second choke filter circuit 16 is connected to the output port in sequence through an attenuator and a power amplifier.

[0083] The link sequence of the GaN amplitude and phase control multifunctional chip provided in this application embodiment is as follows: input port, first driver amplifier, phase shifter S1, second driver amplifier, attenuator, power amplifier and output port.

[0084] In some possible implementations, in conjunction with other embodiments, the third terminal of the second choke filter circuit 16 is connected to the output port in sequence through the sixth capacitor C6, the attenuator, and the power amplifier.

[0085] The distributed current multiplexing amplifier topology provided in this application can reduce the power consumption of GaN-based high drain voltage amplitude-phase multifunctional chips, and can be widely applied to other microwave RF multifunctional chips, with broad application prospects in the fields of communication and detection.

[0086] The GaN amplitude and phase control multifunctional chip provided in this application embodiment can be applied to phased array systems, providing technical support for the miniaturization, high precision and low power consumption of phased array systems, and providing solutions for the energy saving and heat dissipation problems of phased array systems.

[0087] For the GaN amplitude and phase control multifunctional chip provided in this application embodiment, the circuits of the phase shifter S1 and attenuator are designed first to meet the high precision requirements. Then, the insertion loss is confirmed. Specific simulation results can be found in [reference needed]. Figures 3 to 6 .in, Figure 3 This is a schematic diagram of the insertion loss curve of the phase shifter S1 in the GaN amplitude and phase control multifunctional chip. The horizontal axis represents the frequency, and the vertical axis represents the insertion loss of the phase shifter S1. Figure 4 This is a schematic diagram of the phase shifting accuracy RMS curve of phase shifter S1 in a GaN amplitude and phase control multifunctional chip. The horizontal axis represents frequency, and the vertical axis represents phase shifting accuracy RMS. Figure 5 This is a schematic diagram of the insertion loss curve of the attenuator in a GaN amplitude-phase control multifunctional chip. The horizontal axis represents the frequency and the vertical axis represents the insertion loss of the attenuator. Figure 6 This is a schematic diagram of the attenuation accuracy RMS curve of the attenuator in a GaN amplitude-phase control multi-functional chip. The horizontal axis represents frequency, and the vertical axis represents attenuation accuracy RMS.

[0088] Then, based on the output power and power gain requirements of the entire multi-functional circuit of the GaN amplitude-phase control multi-functional chip, and considering power consumption and stability, the position of the driver amplifier in the multi-functional circuit is rationally optimized within the entire link. Ultimately, the link structure of the first driver amplifier, phase shifter S1, and second driver amplifier is selected. To reduce power consumption, a distributed current multiplexing amplifier structure is adopted. Through the cascaded design of two stages of amplification and phase shifter S1, its output power and current simulation are as follows: Figures 7 to 10 As shown, its current is reduced by half compared to a typical two-stage amplifier.

[0089] in, Figure 7 This is a schematic diagram of the power gain curve of the distributed current multiplexed amplifier in a GaN amplitude and phase control multifunctional chip. The horizontal axis represents frequency, and the vertical axis represents the power gain of the distributed current multiplexed amplifier. Figure 8 This is a schematic diagram of the stability factor curve of the distributed current multiplexed amplifier in a GaN amplitude and phase control multifunctional chip. The horizontal axis represents frequency, and the vertical axis represents the stability factor of the distributed current multiplexed amplifier. Figure 9 This is a schematic diagram of the output power curve of the distributed current multiplexed amplifier in a GaN amplitude and phase control multifunctional chip. The horizontal axis represents frequency, and the vertical axis represents the output power of the distributed current multiplexed amplifier. Figure 10 This is a schematic diagram of the current of the distributed current multiplexer amplifier in a GaN amplitude and phase control multifunctional chip. The horizontal axis represents the frequency, and the vertical axis represents the current of the distributed current multiplexer amplifier.

[0090] Figure 11 and Figure 12 This is a schematic diagram of the overall simulation curves for a GaN amplitude and phase control multifunctional chip. Figure 11This is a schematic diagram of the output power curve of a GaN amplitude-phase control multifunctional chip. The horizontal axis represents frequency, and the vertical axis represents the output power of the GaN amplitude-phase control multifunctional chip. Figure 12 This is a schematic diagram of the current curve of a GaN amplitude-phase control multifunctional chip. The horizontal axis represents the frequency, and the vertical axis represents the current of the GaN amplitude-phase control multifunctional chip.

[0091] Corresponding to the above-mentioned GaN amplitude and phase control multifunctional chip, this application embodiment also provides a phased array system, including any of the above-mentioned GaN amplitude and phase control multifunctional chips, and has the beneficial effects of any of the above-mentioned GaN amplitude and phase control multifunctional chips.

[0092] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A GaN amplitude and phase control multifunctional chip, characterized in that, Includes input port, output port, distributed current multiplexing amplifier, phase shifter, first DC blocking capacitor and second DC blocking capacitor; The distributed current multiplexing amplifier includes a first switching transistor, a second switching transistor, a first gate voltage supply circuit, a DC self-biasing circuit, a negative feedback circuit, a first choke filter circuit, a second gate voltage supply circuit, a second choke filter circuit, and a voltage source; the voltage source provides a +15V voltage, and the negative terminal of the voltage source is grounded; The first terminal of the first gate voltage providing circuit is connected to the input port; the second terminal of the first gate voltage providing circuit is connected to the control terminal of the first switching transistor and the first terminal of the negative feedback circuit; the first terminal of the first switching transistor is connected to the second terminal of the negative feedback circuit, and the second terminal of the first switching transistor is connected to the first terminal of the DC self-biasing circuit; the third terminal of the negative feedback circuit is connected to the first terminal of the first DC blocking capacitor and the first terminal of the first choke filter circuit; the second terminal of the first DC blocking capacitor is connected to the first terminal of the phase shifter, the second terminal of the phase shifter is connected to the first terminal of the second DC blocking capacitor, and the second terminal of the second DC blocking capacitor is connected to the first terminal of the second gate voltage providing circuit and the control terminal of the second switching transistor; the first terminal of the second switching transistor is connected to the first terminal of the second choke filter circuit, and the second terminal of the second switching transistor is connected to the second terminal of the first choke filter circuit; the second terminal of the second gate voltage providing circuit and the second terminal of the second choke filter circuit are both connected to the positive terminal of the voltage source; the third terminal of the second choke filter circuit is connected to the output port. The first choke filter circuit includes a second microstrip line, a third microstrip line, a fourth resistor, and a fifth capacitor; the first end of the third microstrip line serves as the first end of the first choke filter circuit, and the second end of the third microstrip line is connected to the first end of the fourth resistor; The first end of the second microstrip line serves as the second end of the first choke filter circuit. The second end of the second microstrip line is connected to the second end of the fourth resistor and the first end of the fifth capacitor. The second end of the fifth capacitor is grounded.

2. The GaN amplitude and phase control multifunctional chip according to claim 1, characterized in that, The first gate voltage providing circuit includes a first inductor, a second inductor, and a first resistor; The first end of the first inductor serves as the first end of the first gate voltage supply circuit, and the second end of the first inductor is connected to the first end of the second inductor. The second end of the first inductor also serves as the second end of the first gate voltage supply circuit. The second end of the second inductor is connected to the first end of the first resistor, and the second end of the first resistor is grounded.

3. The GaN amplitude and phase control multifunctional chip according to claim 1, characterized in that, The DC self-biasing circuit includes a first microstrip line, a second capacitor, and a third resistor; The first end of the first microstrip line serves as the first end of the DC self-biasing circuit, and the second end of the first microstrip line is connected to the first end of the second capacitor and the first end of the third resistor. The second end of the second capacitor and the second end of the third resistor are both grounded.

4. The GaN amplitude and phase control multifunctional chip according to claim 1, characterized in that, The negative feedback circuit includes a third inductor, a third capacitor, and a second resistor; The first end of the second resistor serves as the first end of the negative feedback circuit, the second end of the second resistor is connected to the first end of the third capacitor, and the second end of the third capacitor serves as the third end of the negative feedback circuit; the first end of the third inductor serves as the second end of the negative feedback circuit, and the second end of the third inductor is connected to the second end of the third capacitor.

5. The GaN amplitude and phase control multifunctional chip according to claim 1, characterized in that, The second gate voltage supply circuit includes a fifth resistor, a sixth resistor, and a seventh resistor; The first end of the fifth resistor is grounded, and the second end of the fifth resistor is connected to the first end of the sixth resistor and the first end of the seventh resistor. The second end of the seventh resistor serves as the first end of the second gate voltage supply circuit, and the second end of the sixth resistor serves as the second end of the second gate voltage supply circuit.

6. The GaN amplitude and phase control multifunctional chip according to claim 1, characterized in that, The second choke filter circuit includes a fifth inductor, a sixth inductor, and a seventh capacitor; The first end of the fifth inductor serves as the first end of the second choke filter circuit, the second end of the fifth inductor serves as the third end of the second choke filter circuit, the second end of the fifth inductor is also connected to the first end of the sixth inductor, the second end of the sixth inductor serves as the second end of the second choke filter circuit, the second end of the sixth inductor is also connected to the first end of the seventh capacitor, and the second end of the seventh capacitor is grounded.

7. The GaN amplitude and phase control multifunctional chip according to any one of claims 1 to 6, characterized in that, The distributed current multiplexing amplifier also includes a first capacitor and a sixth capacitor; The first terminal of the first gate voltage providing circuit is connected to the input port through the first capacitor; The third terminal of the second choke filter circuit is connected to the output port through the sixth capacitor.

8. The GaN amplitude and phase control multifunctional chip according to any one of claims 1 to 6, characterized in that, The GaN amplitude-phase control multifunctional chip also includes an attenuator and a power amplifier; The third terminal of the second choke filter circuit is connected to the output port in sequence through the attenuator and the power amplifier.

9. A phased array system, characterized in that, Including the GaN amplitude and phase control multifunctional chip as described in any one of claims 1 to 8.

Images