Methods for adjusting wafer distortion and semiconductor structure

Abstract

This application discloses a method for adjusting wafer deformation and a semiconductor structure. The method includes: determining the deformation location and degree of the wafer; forming at least one trench on the back side of the wafer according to the deformation location and degree of deformation; forming a stress film on the back side of the wafer having the at least one trench, which exerts stress on the deformation of the wafer; and the stress film covering the inner wall of the at least one trench.

Description

Technical Field

[0001] This application relates to semiconductor manufacturing technology, including but not limited to a method for adjusting wafer distortion and a semiconductor structure. Background Technology

[0002] A wafer is a single-crystal silicon material used to fabricate semiconductor devices. It is formed by grinding, polishing, and slicing cylindrical single-crystal silicon wafers. Wafers are the raw materials and substrates for manufacturing various semiconductor products. During the semiconductor product manufacturing process, various techniques, including photolithography, ion implantation, coating, and cleaning, can be performed on the surface of the wafer to form complex device and circuit structures. However, the stress generated during these manufacturing processes can cause wafer deformation, leading to product failure, low yield, and other problems. Summary of the Invention

[0003] In view of this, the present application provides a method for adjusting wafer distortion and a semiconductor structure to solve at least one problem existing in the prior art.

[0004] In a first aspect, the wafer distortion adjustment method provided in the embodiments of this application includes:

[0005] Determine the location and degree of deformation of the wafer;

[0006] At least one trench is formed on the back side of the wafer according to the location and degree of deformation;

[0007] A stress film is formed on the back side of the wafer having at least one trench, which exerts stress on the deformation of the wafer; the stress film covers the inner wall of the at least one trench.

[0008] Secondly, the semiconductor structure provided in the embodiments of this application includes:

[0009] wafers;

[0010] The back side of the wafer has at least one trench;

[0011] The back side of the at least one trench includes a stress film that exerts stress on the deformation of the wafer; wherein the stress film covers the inner wall of the at least one trench for adjusting the deformation of the wafer.

[0012] The technical solution and method of this application embodiment form a trench on the back side of the wafer according to the deformation location and degree of the wafer, and cover the inner wall of the trench with a stress film, thereby realizing stress adjustment of the wafer, improving wafer deformation, enhancing product performance, and increasing production yield. Attached Figure Description

[0013] Figure 1This is a flowchart of a method for adjusting wafer distortion according to an embodiment of this application;

[0014] Figure 2 This is a schematic diagram of forming trenches and stress films in a method for adjusting wafer deformation according to an embodiment of this application;

[0015] Figure 3 This is a schematic diagram of filling trenches in a method for adjusting wafer distortion according to an embodiment of this application;

[0016] Figure 4 This is a schematic diagram of a semiconductor structure according to an embodiment of this application;

[0017] Figure 5 This is a schematic diagram illustrating the stress effect on the wafer during thin film deposition on the wafer surface according to an embodiment of this application.

[0018] Figure 6 This is a schematic diagram illustrating the principle of forming a protective film on the wafer surface in a wafer deformation adjustment method according to an embodiment of this application.

[0019] Figure 7 This is a schematic diagram illustrating the principle of forming trenches on the back side of a wafer in a wafer deformation adjustment method according to an embodiment of this application.

[0020] Figure 8 This is a schematic diagram illustrating the principle of forming an STO (strontium titanate) thin film on the back side of a wafer in a method for adjusting wafer distortion according to an embodiment of this application.

[0021] Figure 9 This is a schematic diagram illustrating the principle of forming a stress film by annealing on the back side of the wafer in a wafer deformation adjustment method according to an embodiment of this application.

[0022] Figure 10 This is a schematic diagram illustrating the principle of removing the protective film in a method for adjusting wafer distortion according to an embodiment of this application.

[0023] Figure 11 This is a schematic diagram of an STO thin film serving as a stress membrane in a method for adjusting wafer deformation according to an embodiment of this application. Detailed Implementation

[0024] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0026] This application provides a method for adjusting wafer distortion, such as... Figure 1 As shown, the method includes:

[0027] Step S101: Determine the location and degree of deformation of the wafer;

[0028] Step S102: Based on the deformation location and degree, form at least one trench on the back side of the wafer;

[0029] Step S103: Form a stress film on the back side of the wafer having at least one trench, which exerts stress on the deformation of the wafer; the stress film covers the inner wall of the at least one trench.

[0030] In the semiconductor manufacturing process, various techniques, including photolithography, ion implantation, coating, and cleaning, can be used on the surface of wafers to form complex device and circuit structures. The stress generated during these manufacturing processes can cause wafer deformation, also known as wafer warpage. If left uncontrolled, wafer deformation can lead to positional deviations in subsequent processes, affecting manufacturing precision and ultimately causing product failure.

[0031] Therefore, in the embodiments of this application, such as Figure 2 As shown, the deformation of wafer 20 can be adjusted by forming trenches 21 on the back side of the wafer. These trenches can be narrow slits, circular holes, or other shapes. The shape and depth of the trenches can be determined based on the aforementioned degree of deformation. The trenches can generate stress at the deformation locations of the wafer, thereby adjusting the wafer's deformation.

[0032] Furthermore, considering that the direction and intensity of the stress generated by the trench are limited, and the deformation of the wafer may be irregular, this embodiment of the application further adjusts the stress of the wafer 20 by forming a stress film 22 on the surface of the trench 21.

[0033] It should be noted that the above-mentioned processes of forming trenches and stress films can be carried out at any time during the manufacturing process of semiconductor products. For example, when wafer deformation occurs, causing some processes to be unable to be aligned or prone to large deviations, wafer deformation can be measured; or, after some processes where wafer deformation is prone to occur, wafer deformation can be measured, and the wafer can be further flipped, and the deformation can be adjusted on the back of the wafer using the above-mentioned method.

[0034] In this way, the deformation of the wafer can be adjusted during the manufacturing process of semiconductor products. The adjustment method is simple and easy to implement, and it is not likely to interfere with the manufacturing of semiconductor products, which can effectively improve product performance and production yield.

[0035] In some embodiments, the material of the stress film can be a material with a coefficient of thermal expansion greater than that of the wafer. In this way, the stress can be adjusted by the thermal expansion of the stress film, thereby improving the deformation of the wafer.

[0036] For example, the stress membrane material can be STO, i.e., strontium titanate, with the chemical formula SrTiO3, or it can be a doped STO material. STO is a widely used electroceramic material with a high coefficient of thermal expansion, high thermal stability, high dielectric constant, and low cost.

[0037] In some embodiments, the stress film is made of a crystalline material; forming a stress film on the back side of a wafer having at least one trench, which exerts stress on the deformation of the wafer, includes:

[0038] Material of the stress film is deposited on the back side of a wafer having at least one trench;

[0039] The material of the stress membrane is annealed to crystallize and form the stress membrane.

[0040] The aforementioned stress film is a crystalline material, meaning it can be formed on the trench surface on the back side of a wafer. In this embodiment, the stress film material can be deposited first to form a liquid or solid film, and then annealed to form a crystalline stress film. During the crystallization process of the stress film, lattice changes occur, thereby achieving stress adjustment.

[0041] In some embodiments, annealing the material of the stress membrane to crystallize and form the stress membrane includes:

[0042] Based on the degree of deformation, the material of the stress membrane is annealed at a corresponding temperature to crystallize and form the stress membrane.

[0043] Since the temperature during annealing can affect the stress level of the stress membrane, different temperatures can be used for annealing the stress membrane material depending on the degree of deformation. For example, the greater the deformation, the higher the annealing temperature; the smaller the deformation, the lower the annealing temperature. Furthermore, the magnitude of deformation can be monitored in real time during annealing, and the annealing temperature can be adjusted accordingly.

[0044] In some embodiments, the back side of the wafer has multiple deformation locations; the step of annealing the material of the stress film at a corresponding temperature according to the degree of deformation to crystallize and form the stress film includes:

[0045] Depending on the degree of deformation at different deformation locations, the materials of the stress membranes covering different deformation locations are annealed at different temperatures to crystallize and form the stress membranes.

[0046] Considering that different locations on the wafer may have different degrees of deformation, the deformation locations on the back of the wafer can be adjusted according to the degree of deformation.

[0047] Since different annealing temperatures will generate different amounts of stress during the stress film formation process, the deformation of the wafer can be annealed at different temperatures according to the degree of deformation at different deformation locations, thereby flexibly adjusting the wafer deformation.

[0048] In some embodiments, the step of annealing the material of the stress membrane at a corresponding temperature according to the degree of deformation to crystallize and form the stress membrane includes:

[0049] In coverage such as Figure 3 An amorphous silicon thin film 31 is deposited on the back side of the wafer 20 of the material of the stress film 22 shown, filling the at least one trench;

[0050] Depending on the degree of deformation, the back side of the wafer is annealed at a corresponding temperature to crystallize and form the stress film.

[0051] In this embodiment, the stress film material covering the trench formed on the back side of the wafer is a thin film with a small thickness. Therefore, it may only cover the inner wall of the trench and not fill the entire trench. When annealing the stress film, an amorphous silicon layer can be first coated on the surface of the stress film material, so that the amorphous silicon fills the trench and covers the back side of the wafer, making the back side of the wafer present a smooth plane.

[0052] Annealing amorphous silicon thin films can crystallize the amorphous silicon to form polycrystalline silicon. At the same time, the material of the stress film covering the amorphous silicon thin film can also crystallize to form the aforementioned stress film. During the crystallization process, stress can be adjusted to improve wafer deformation.

[0053] In some embodiments, forming at least one trench on the back side of the wafer according to the deformation location and degree includes:

[0054] Based on the deformation location, an adjustment area for forming the at least one trench is determined on the back side of the wafer;

[0055] Depending on the degree of deformation, at least one groove of corresponding depth is formed within the adjustment area.

[0056] In this embodiment, the locations where the wafer deforms can be detected first, and adjustment regions can be determined at the deformed locations. The range of the adjustment region can cover the entire deformed location, or it can be determined based on the stress effect to identify a region corresponding to the deformed location. Then, the aforementioned trenches are formed within each adjustment region.

[0057] Because different areas deform to varying degrees, grooves of different depths, widths, or lengths can be formed within different adjustment areas, thus enabling flexible adjustments.

[0058] In some embodiments, forming at least one groove of corresponding depth within the adjustment area according to the degree of deformation includes:

[0059] Depending on the degree of deformation, at least one trench of the corresponding depth is formed in the adjustment area by etching.

[0060] In this embodiment, the trenches formed on the back side of the wafer can be formed by etching, including dry etching, wet etching, etc. The silicon on the back side of the wafer is peeled off from the wafer using a corrosive solution, reactive ions, or other gases, thereby forming the trenches.

[0061] In some embodiments, forming at least one groove of corresponding depth within the adjustment area according to the degree of deformation includes:

[0062] A mask layer with an etched pattern is formed on the surface of the adjustment area;

[0063] According to the degree of deformation, at least one trench of the corresponding depth is formed in the adjustment area by etching at the location not covered by the mask layer;

[0064] Remove the mask layer.

[0065] Trench formation via etching allows for the use of a mask layer to shield areas that do not need to be etched, exposing the areas where trenches need to be formed. The mask layer can be a thin film of materials such as silicon nitride or silicon oxide. Patterned areas are formed using processes such as photolithography, followed by etching to create trenches. Finally, the mask layer can be further removed by grinding or etching, ultimately forming trenches on the back side of the wafer.

[0066] In some embodiments, a semiconductor device is formed on the front side of the wafer and within a first thickness extending from the front side of the wafer to the interior of the wafer; the depth of the at least one trench is less than the difference between the thickness of the wafer and the first thickness.

[0067] In this embodiment, the back side of the wafer is used to form trenches and stress films to adjust wafer deformation, while the front side of the wafer is used to manufacture semiconductor devices. Since semiconductor devices require processes such as ion implantation and etching on the wafer surface, a certain thickness (the aforementioned first thickness) from the front side of the wafer to the interior of the wafer is used to form the semiconductor device. Therefore, the trenches formed on the back side of the wafer cannot affect the area required for the semiconductor device; that is, the bottom of the trench does not exceed the bottom of the wafer thickness occupied by the semiconductor device. Therefore, the depth of the first trench needs to be less than the difference between the wafer thickness and the aforementioned first thickness.

[0068] In some embodiments, the trench includes at least two trenches, each of which may have a different shape, depth, or width.

[0069] Since the degree of deformation may vary in different regions of a wafer, different trenches can be used to adjust for different degrees of deformation at different locations. That is, the shape, depth, or width of each trench can be different. Of course, considering that further adjustments can be made using stress films, the shape, depth, or width of each trench can also be the same.

[0070] In this way, the deformation of the wafer can be flexibly adjusted from multiple dimensions, reducing the failure of semiconductor devices caused by wafer deformation and improving product yield.

[0071] In some embodiments, before forming at least one trench on the back side of the wafer, the method further includes:

[0072] A protective film is formed on the surface of the semiconductor device on the front side of the wafer;

[0073] Flip the wafer so that the back side of the wafer faces vertically upward.

[0074] When forming trenches on the back side of a wafer, the wafer needs to be flipped so that the back side faces upwards, and etching and other processes are required. The front side of the wafer may have already undergone some semiconductor device manufacturing processes, forming some or all of the semiconductor devices. To protect the semiconductor devices on the front side of the wafer from damage and to facilitate flipping and securing the wafer when forming trenches on the back side, a protective film can first be formed on the surface of the semiconductor devices on the front side. This protective film can be made of materials such as polycrystalline carbon, polycrystalline silicon, oxide, or silicon nitride.

[0075] In some embodiments, after forming the stress film on the back side of the wafer, the method further includes:

[0076] Flip the wafer so that the front side of the wafer faces vertically upward;

[0077] Remove the protective film from the front side of the wafer.

[0078] After forming the trenches and stress film on the back side of the wafer, the wafer needs to be flipped back to face up to facilitate subsequent semiconductor device manufacturing processes or the formation of semiconductor device products. Therefore, the protective film on the wafer surface can be removed by chemical or physical polishing methods after flipping the wafer back to face up.

[0079] For example, to prevent damage to semiconductor devices during the removal of the protective film, the protective film can first be thinned using physical mechanical polishing to quickly remove most of the material while retaining a portion of the protective film. Then, a chemical agent that corrodes the protective film material can be used for etching to remove the remaining protective film.

[0080] In some embodiments, determining the location and degree of deformation of the wafer includes:

[0081] Deformation detection is performed on the back side of the wafer to determine the location and degree of deformation.

[0082] In this embodiment, deformation detection can first determine whether the wafer is deformed, as well as the location and degree of deformation. If the wafer is deformed, but the degree of deformation is small, for example, less than a predetermined adjustment threshold, then it can be considered that the wafer is not deformed or does not require deformation adjustment. However, if the wafer is deformed and the degree of deformation is greater than the predetermined adjustment threshold, then deformation adjustment can be further performed using the method described in the above embodiment.

[0083] Deformation detection can be achieved through optical detection methods, probe methods, or various other methods. The timing of deformation detection can be performed at any stage of the semiconductor device manufacturing process. In practical applications, it can be determined based on the degree to which each process affects wafer deformation or the precision of the product, or it can be performed during process steps with high requirements for wafer flatness (e.g., before wafer bonding). After detection, the wafer deformation can be further adjusted based on the detection results using the adjustment methods described in the above embodiments.

[0084] like Figure 4 As shown, this application embodiment also provides a semiconductor structure 200, including:

[0085] Wafer 210;

[0086] The back side of the wafer 210 has at least one trench 220;

[0087] The back side of the wafer of the at least one trench 220 includes a stress film 230 that exerts stress on the deformation of the wafer 210; wherein the stress film 230 covers the inner wall of the at least one trench 220 for adjusting the deformation of the wafer 210.

[0088] In the semiconductor manufacturing process, various techniques, including photolithography, ion implantation, coating, and cleaning, can be used on the surface of wafers to form complex device and circuit structures. The stress generated during these manufacturing processes can cause wafer deformation, also known as wafer warpage. If left uncontrolled, wafer deformation can lead to positional deviations in subsequent processes, affecting manufacturing precision and ultimately causing product failure.

[0089] Therefore, the semiconductor structure provided in this application embodiment, including trenches and stress films, can be used to adjust the deformation of the wafer.

[0090] It should be noted that stress films and trenches on the back of a wafer can provide stress. The shape, depth, and number of trenches, as well as the thickness of the stress film, the degree of crystallinity of the stress film, and the annealing temperature during formation, will all generate stress on the wafer to different degrees and in different directions. Therefore, complex wafer deformations can be precisely adjusted, thereby improving the performance of semiconductor products and increasing yield.

[0091] In some embodiments, different deformation positions on the back side of the wafer correspond to adjustment areas;

[0092] Each of the adjustment regions has at least one of the grooves.

[0093] The back side of the wafer may have different orientations and degrees of deformation at different locations. Therefore, the wafer can be divided into different adjustment areas, and different adjustment areas can be adjusted separately.

[0094] Therefore, parameters such as the number, shape, depth, and thickness of the stress membrane in different adjustment areas can be different, thereby achieving precise adjustment of different adjustment areas.

[0095] In some embodiments, the depth of the at least one trench is related to the degree of deformation of the adjustment region.

[0096] Different trench depths produce varying degrees of stress on the wafer. Therefore, trenches of different depths can be used in different adjustment regions, and the trench depth is determined by the degree of deformation. Furthermore, different degrees of deformation adjustment can also be achieved by using different annealing temperatures during stress film formation.

[0097] In some embodiments, the front side of the wafer has semiconductor devices.

[0098] In this embodiment, the front side of the wafer is used to form various semiconductor devices, including large-scale integrated circuits such as memory and chips. The trenches and stress films on the back side of the wafer can be formed after the semiconductor devices are formed on the front side of the wafer, thereby adjusting the wafer stress and improving the device lifespan; alternatively, they can be formed during the semiconductor device manufacturing process. For example, if a certain process in semiconductor device manufacturing is prone to wafer deformation, the wafer can be flipped after that process and the aforementioned trenches and stress films can be formed to adjust the deformation and reduce the impact of deformation in subsequent processes; or, if a certain process in semiconductor device manufacturing has high requirements for wafer flatness, the aforementioned trenches and stress films can be formed on the back side of the wafer beforehand to improve wafer flatness and reduce the defect rate of that process.

[0099] This application also provides the following examples in its embodiments:

[0100] As semiconductor manufacturing processes continue to improve, device sizes are becoming increasingly smaller, thus requiring higher precision in the manufacturing process. Different processing steps cause wafer deformation, which in turn affects photolithography accuracy. Furthermore, because wafers are single-crystal materials, they exhibit anisotropy, meaning the deformation varies in different directions, making it difficult to adjust and control.

[0101] In related technologies, stress adjustment can be achieved by depositing different thin films on the wafer surface, such as... Figure 5As shown, depositing an oxide (OX) thin film 51 can generate compressive stress on the wafer 50, while depositing a silicon nitride (SIN) thin film 52 can generate tensile stress on the wafer 50. Depositing an oxide thin film and a silicon nitride thin film respectively can achieve stress balance.

[0102] In this embodiment, to achieve precise control over wafer deformation and minimize its impact on photolithography accuracy, STO or doped STO material is used for thin film deposition in trenches. After annealing, crystallization occurs, thereby allowing adjustment of wafer deformation in a specific direction. Furthermore, this solution enables precise adjustment of wafer deformation by controlling parameters such as trench depth and annealing temperature.

[0103] The wafer distortion adjustment method provided in this application embodiment may include the following process: Figure 6 As shown, after a portion of the semiconductor device 601 is formed through a process, amorphous carbon (AC) is deposited on the surface of the wafer 600 to form a protective film 602, and then the wafer is flipped so that the back side of the wafer faces upward.

[0104] like Figure 7 As shown, multiple trenches 603 are formed on the back side of wafer 600 by etching. The depth, shape, and number of trenches can be adjusted according to the actual needs of deformation adjustment, and more efficient parameters can be selected according to the equipment capacity or process time requirements.

[0105] like Figure 8 As shown, after trench 603 is formed, STO can be deposited on the back side of wafer 600 so that the STO material covers the inner wall of the trench and the surface of wafer 600 to form STO thin film 604.

[0106] Then, as Figure 9 As shown, amorphous silicon material (A-Si) 605 can be filled into the trench and the amorphous silicon material 605 can cover the back side of the wafer 600. At this time, the back side of the wafer 600 can be annealed, for example, by spike annealing. This causes the STO material to form a crystalline film and the polycrystalline silicon material to further crystallize to form polycrystalline silicon. The crystallized STO and polycrystalline silicon then act as stress films to adjust the wafer warp.

[0107] like Figure 10 As shown, after the stress film fabrication process is completed, the wafer 600 can be flipped so that the front side of the wafer 600 faces upwards. The amorphous carbon protective film 602 on the front side of the wafer 600 can be removed by methods such as grinding or etching, so that the semiconductor device 601 on the surface of the wafer 600 is exposed again for subsequent processes.

[0108] like Figure 11As shown, the STO thin film on the back of the wafer can achieve a wide range of stress adjustment. For example, an STO thin film with a thickness of 3 nm can achieve a deformation of about 100 micrometers, and the deformation during the annealing process can be further adjusted by doping process and annealing temperature.

[0109] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0110] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0111] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0112] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0113] In addition, each functional unit in the various embodiments of this application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0114] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for adjusting wafer distortion, characterized in that, The method includes: Determine the location and degree of deformation of the wafer; At least one trench is formed on the back side of the wafer according to the location and degree of deformation; A stress film is formed on the back side of a wafer having at least one trench, which exerts stress on the wafer in response to deformation; the stress film covers the inner wall of the at least one trench; Wherein, the material of the stress film is a crystalline material; the formation of a stress film on the back side of a wafer having at least one trench, which exerts stress on the deformation of the wafer, includes: Material of the stress film is deposited on the back side of a wafer having at least one trench; According to the degree of deformation, the material of the stress membrane is annealed at a corresponding temperature to crystallize and form the stress membrane; The step of annealing the stress membrane material at a corresponding temperature according to the degree of deformation to crystallize and form the stress membrane includes: An amorphous silicon thin film is deposited on the back side of the wafer covered with the stress film to fill the at least one trench; Depending on the degree of deformation, the back side of the wafer is annealed at a corresponding temperature to crystallize and form the stress film.

2. The method according to claim 1, characterized in that, The back side of the wafer has multiple deformation sites; the step of annealing the stress film material at a corresponding temperature according to the degree of deformation to crystallize and form the stress film includes: Depending on the degree of deformation at different deformation locations, the materials of the stress membranes covering different deformation locations are annealed at different temperatures to crystallize and form the stress membranes.

3. The method according to claim 1 or 2, characterized in that, The step of forming at least one trench on the back side of the wafer according to the deformation location and degree includes: Based on the deformation location, an adjustment area for forming the at least one trench is determined on the back side of the wafer; Depending on the degree of deformation, at least one groove of corresponding depth is formed within the adjustment area.

4. The method according to claim 3, characterized in that, The step of forming at least one groove of corresponding depth within the adjustment area according to the degree of deformation includes: Depending on the degree of deformation, at least one trench of the corresponding depth is formed in the adjustment area by etching.

5. The method according to claim 4, characterized in that, The step of forming at least one groove of corresponding depth within the adjustment area according to the degree of deformation includes: A mask layer with an etched pattern is formed on the surface of the adjustment area; According to the degree of deformation, at least one trench of the corresponding depth is formed in the adjustment area by etching at the location not covered by the mask layer; Remove the mask layer.

6. The method according to claim 3, characterized in that, Semiconductor devices are formed on the front side of the wafer and within a first thickness extending from the front side of the wafer to the interior of the wafer; the depth of the at least one trench is less than the difference between the thickness of the wafer and the first thickness.

7. The method according to claim 1, characterized in that, The trench includes at least two trenches that differ in shape, depth, or width.

8. The method according to claim 1, characterized in that Before forming at least one trench on the back side of the wafer, the method further includes: A protective film is formed on the surface of the semiconductor device on the front side of the wafer; Flip the wafer so that the back side of the wafer faces vertically upward.

9. The method according to claim 8, characterized in that, After forming the stress film on the back side of the wafer, the method further includes: Flip the wafer so that the front side of the wafer faces vertically upward; Remove the protective film from the front side of the wafer.

10. The method according to claim 1, characterized in that Determining the location and degree of deformation of the wafer includes: Deformation detection is performed on the back side of the wafer to determine the location and degree of deformation.

11. The method according to claim 1, characterized in that, The thermal expansion coefficient of the stress membrane material is greater than that of the wafer.

12. The method according to claim 11, characterized in that, The stress membrane is made of strontium titanate (STO) or doped STO material.

13. A semiconductor structure, characterized in that, include: wafers; The back side of the wafer has at least one trench; The back side of the wafer with the at least one trench includes a stress film that exerts stress on the deformation of the wafer; wherein the stress film covers the inner wall of the at least one trench for adjusting the deformation of the wafer. The semiconductor structure is obtained by the method according to any one of claims 1-12.

14. The semiconductor structure according to claim 13, characterized in that, The different deformation positions on the back side of the wafer correspond to adjustment areas; Each of the adjustment regions has at least one of the grooves.

15. The semiconductor structure according to claim 14, characterized in that, The depth of the at least one groove is related to the degree of deformation of the adjustment area.

16. The semiconductor structure according to claim 13, characterized in that, The front side of the wafer has semiconductor devices.

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