Plasma Etching Monitoring Structure, Preparation Method and Monitoring Method

Abstract

The present invention relates to a plasma etching monitoring structure, a preparation method thereof, and a plasma etching monitoring method. The plasma monitoring structure includes: a substrate; a metal layer located on the substrate; a covering dielectric layer located on the substrate and covering the metal layer; and a deep through-hole located within the covering dielectric layer and on at least one side of the covering dielectric layer. By providing a deep through-hole near the metal layer in this application, it is beneficial for the local discharge of charges at the edge of the metal layer. Once there is a relatively large increase in plasma during the dry etching process, it is easy to have an arc phenomenon visible by visual inspection on the local surface of the substrate. The plasma etching monitoring structure of this application can monitor whether the plasma is unstable and determine the area where the plasma is unstable when the plasma is unstable.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technologies, and particularly to a plasma etching monitoring structure, a preparation method thereof, and a plasma etching monitoring method. Background Art

[0002] In existing semiconductor processes, dry etching is a very important process. In the dry etching process, if the plasma is unstable, it will break down the metal layer and the dielectric layer located outside the metal layer, thereby damaging the device. In order to ensure the performance of the obtained device and avoid damaging the device, the plasma needs to have good stability. However, there is currently no structure for effectively monitoring the stability of the plasma in the dry etching process.

[0003] Therefore, how to monitor the plasma characteristics is a technical problem that needs to be solved urgently at present. Summary of the Invention

[0004] Based on this, it is necessary to provide a plasma etching monitoring structure, a preparation method thereof, and a plasma etching monitoring method to effectively monitor the plasma characteristics.

[0005] The embodiment of the present application provides a preparation method for a plasma etching monitoring structure, including the following steps: providing a substrate; forming a metal layer on the substrate; forming a covering dielectric layer on the substrate, the covering dielectric layer covering the metal layer; forming a deep through hole in the covering dielectric layer, the deep through hole being located on at least one side of the covering dielectric layer, and the deep through hole being used to monitor the breakdown of the plasma to the metal layer and the covering dielectric layer located outside the metal layer, so as to realize the monitoring of the plasma characteristics.

[0006] In the above preparation method for the plasma etching monitoring structure, first, a metal layer is formed on the substrate, second, a covering dielectric layer is formed on the substrate, the covering dielectric layer covering the metal layer, and then, a deep through hole is formed in the covering dielectric layer, wherein the deep through hole is located on at least one side of the covering dielectric layer. In this way, by arranging a deep through hole near the metal layer, it is beneficial for the charge to be locally discharged at the edge of the metal layer. Once the plasma increases significantly in the dry etching process, it is easy to cause the breakdown phenomenon of the dielectric layer caused by visible arc discharge (arcing) on the local surface of the substrate. The plasma etching monitoring structure of the present application can monitor whether the plasma is unstable and determine the area where the plasma is unstable through the loss position on the wafer.

[0007] Optionally, before forming the metal layer on the substrate, it further includes: forming an interlayer dielectric layer on the upper surface of the substrate; the covering dielectric layer is located on the upper surface of the interlayer dielectric layer; forming the metal layer on the substrate includes: forming the metal layer on the upper surface or inside the interlayer dielectric layer.

[0008] Optionally, forming an interlayer dielectric layer on the upper surface of the substrate includes: forming a first dielectric layer on the upper surface of the substrate; forming a second dielectric layer on the upper surface of the first dielectric layer; a capping dielectric layer is located on the upper surface of the second dielectric layer; forming a metal layer on the upper surface of the interlayer dielectric layer includes: forming a metal material layer on the upper surface of the second dielectric layer; patterning the metal material layer to obtain the metal layer; forming a metal layer within the interlayer dielectric layer includes: forming a groove on the upper surface of the second dielectric layer; forming a metal material layer within the groove and on the upper surface of the second dielectric layer, and the metal material layer fills the groove; removing the metal material layer located on the upper surface of the second dielectric layer, and the metal material layer remaining within the groove is the metal layer.

[0009] Based on the same inventive concept, the present application further provides a plasma etching monitoring structure, including: a substrate; a metal layer located on the substrate; a capping dielectric layer located on the substrate and covering the metal layer; a deep through-hole located within the capping dielectric layer and on at least one side of the capping dielectric layer, and the deep through-hole is used to monitor the breakdown of the plasma to the metal layer and the capping dielectric layer located outside the metal layer, so as to monitor the plasma characteristics.

[0010] In the above plasma etching monitoring structure, by arranging a deep through-hole near the metal layer, it is beneficial for the charge to be locally discharged at the edge of the metal layer. Once there is a large increase in plasma during the dry etching process, it is easy to occur the dielectric layer breakdown phenomenon caused by the visually observable arc discharge (arcing) on the local surface of the substrate. The plasma etching monitoring structure of the present application can monitor whether the plasma is unstable, and determine the area where the plasma is unstable through the loss position on the wafer.

[0011] Optionally, the number of deep through-holes is multiple, and the multiple deep through-holes are arranged at intervals along the circumferential direction of the metal layer.

[0012] Optionally, the widths of the multiple deep through-holes are not all the same, and / or the depths of the multiple deep through-holes are not all the same.

[0013] Optionally, the distance between the deep through-hole and the metal layer is 100 nm to 10 μm.

[0014] Optionally, the plasma etching monitoring structure further includes: an interlayer dielectric layer located on the upper surface of the substrate; the metal layer is located on the upper surface of the interlayer dielectric layer or embedded within the interlayer dielectric layer; the capping dielectric layer is located on the upper surface of the interlayer dielectric layer.

[0015] Optionally, the interlayer dielectric layer includes: a first dielectric layer located on the upper surface of the substrate; a second dielectric layer located on the upper surface of the first dielectric layer; the metal layer is located on the upper surface of the second dielectric layer or embedded within the second dielectric layer; the capping dielectric layer is located on the upper surface of the second dielectric layer.

[0016] Based on the same inventive concept, the present application also provides a plasma etching monitoring method, including:

[0017] Based on the plasma etching monitoring structure provided in any one of the above;

[0018] Using plasma etching to cover the dielectric layer, and monitoring the distribution and characteristics of the plasma during the etching process. Description of the Drawings

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0020] Figure 1 It is a flowchart of the preparation method of the plasma etching monitoring structure provided in an embodiment of the present application;

[0021] Figure 2 It is a schematic cross-sectional structure diagram of the structure obtained after providing a substrate in the preparation method of the plasma etching monitoring structure provided in an embodiment of the present application;

[0022] Figure 3 It is a schematic cross-sectional structure diagram of the structure obtained after forming an interlayer dielectric layer in the preparation method of the plasma etching monitoring structure provided in an embodiment of the present application;

[0023] Figure 4 And Figure 5 It is a schematic cross-sectional structure diagram of the structure obtained after forming a metal layer in the preparation method of the plasma etching monitoring structure provided in different embodiments of the present application;

[0024] Figure 6 It is a schematic cross-sectional structure diagram of the structure obtained after forming a covering dielectric layer in the preparation method of the plasma etching monitoring structure provided in an embodiment of the present application;

[0025] Figure 7 It is a schematic top view structure diagram of the structure obtained after forming a deep through hole in the preparation method of the plasma etching monitoring structure provided in an embodiment of the present application;

[0026] Figure 8 It is Figure 7 a schematic cross-sectional structure diagram along the AA direction in

[0027] Explanation of the Reference Numerals:

[0028] 10. Substrate; 20. Metal layer; 30. Covering dielectric layer; 40. Deep through-hole; 50. Interlayer dielectric layer; 501. First dielectric layer; 502. Second dielectric layer. Detailed implementation manners

[0029] For ease of understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present application is thorough and comprehensive.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application herein are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0031] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below may be referred to as the second element, component, region, layer or part; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types. For example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0032] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatial relationship terms also include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the figures is flipped, an element or feature described as "under other elements" or "beneath it" or "under it" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0033] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprise" and / or "include" are used in this specification, the presence of the stated features, integers, steps, operations, elements and / or components can be determined, but one or more other features, integers, steps, operations, elements, components and / or groups are not excluded from the presence or addition. Also, as used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0034] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the invention, and such variations in the shapes shown can be expected due to, for example, manufacturing techniques and / or tolerances. Thus, embodiments of the invention should not be limited to the particular shapes of regions shown herein, but include shape deviations due to, for example, manufacturing techniques. For example, an implanted region shown as rectangular typically has rounded or curved features at its edges and / or an implantation concentration gradient, rather than a binary change from the implanted region to the non-implanted region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation occurs. Thus, the regions shown in the figures are substantially schematic, their shapes do not represent the actual shapes of regions of the device, and do not limit the scope of the invention.

[0035] Dry etching is a very important process. In the dry etching process, if the plasma is unstable, it will break down the metal layer and the dielectric layer located around the metal layer, thereby damaging the device; in order to ensure the performance of the resulting device and avoid damaging the device, the plasma needs to have good stability. However, there is currently no structure for effectively monitoring the plasma stability in the dry etching process.

[0036] Therefore, how to achieve the monitoring of plasma characteristics is a technical problem that urgently needs to be solved at present.

[0037] In view of the deficiencies of the above-mentioned prior art, the purpose of the present application is to provide a method for preparing a plasma etching monitoring structure, aiming to effectively monitor the plasma characteristics.

[0038] Please refer to Figure 1 , the present application provides a method for preparing a plasma etching monitoring structure, including the following steps:

[0039] S10: Provide a substrate;

[0040] S20: Form a metal layer on the substrate;

[0041] S30: Form a covering dielectric layer on the substrate, and the covering dielectric layer covers the metal layer;

[0042] S40: Form a deep through-hole in the covering dielectric layer, and the deep through-hole is located on at least one side of the covering dielectric layer.

[0043] In the above method for preparing a plasma etching monitoring structure, first, a substrate is provided and a metal layer is formed on the substrate. Secondly, a covering dielectric layer is formed on the substrate, and the covering dielectric layer covers the metal layer. Then, a deep through-hole is formed in the covering dielectric layer, wherein the deep through-hole is located on at least one side of the covering dielectric layer. In this way, by arranging the deep through-hole near the metal layer, it is beneficial for the charge to be locally discharged at the edge of the metal layer. Once the plasma increases significantly in the dry etching process, it is easy to cause dielectric breakdown due to visible arcing on the local surface of the substrate. The plasma etching monitoring structure of the present application can monitor whether the plasma is unstable and determine the area where the plasma is unstable through the loss position on the wafer.

[0044] The following Figures 2 to 8 will be used to describe in detail the method for preparing a plasma etching monitoring structure provided by the embodiments of the present application.

[0045] In step S10, please refer to Figure 1 the S10 step in Figure 2 , and provide the substrate 10.

[0046] In some examples, the substrate 10 may include but is not limited to a silicon substrate. Of course, in other examples, the substrate 10 may also be a sapphire substrate, a gallium nitride substrate, a germanium substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate, etc.

[0047] In an alternative embodiment, after step S10, a step of cleaning the substrate 10 may further be included. By cleaning the substrate 10, impurities existing on the surface of the substrate 10 can be removed, avoiding the influence of impurities on subsequent processes, and thus ensuring the performance of the device.

[0048] Specifically, the substrate 10 can be cleaned using a cleaning solution to achieve the cleaning of the substrate 10, or the substrate 10 can be purged using a gas such as nitrogen to achieve the cleaning of the substrate 10.

[0049] In an alternative embodiment, please refer to Figure 3 , after step S10, it may further include: forming an interlayer dielectric layer 50 on the upper surface of the substrate 10. It should be noted that when there is a step of cleaning the substrate 10, the interlayer dielectric layer 50 can be formed on the upper surface of the substrate 10 after cleaning the substrate 10.

[0050] In an alternative embodiment, forming the interlayer dielectric layer 50 on the upper surface of the substrate 10 may include:

[0051] forming a first dielectric layer 501 on the upper surface of the substrate 10;

[0052] forming a second dielectric layer 502 on the upper surface of the first dielectric layer 501.

[0053] Specifically, a thermal oxidation process, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process can be used to form the first dielectric layer 501 on the upper surface of the substrate 10; a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process can be used to form the second dielectric layer 502 on the upper surface of the first dielectric layer 501.

[0054] More specifically, the first dielectric layer 501 may include but is not limited to a silicon dioxide layer, and the second dielectric layer 502 may include but is not limited to a silicon nitride layer.

[0055] As an example, the thickness of the first dielectric layer 501 and the thickness of the second dielectric layer 502 can be set according to actual needs. The thickness of the first dielectric layer 501 can be the same as the thickness of the second dielectric layer 502, or can be different from the thickness of the second dielectric layer 502; preferably, in this embodiment, the thickness of the first dielectric layer 501 is less than the thickness of the second dielectric layer 502.

[0056] Of course, the interlayer dielectric layer 50 is not limited to the double-layer structure including the first dielectric layer 501 and the second dielectric layer 502 as shown in Figure 3 . In other examples, the interlayer dielectric layer 50 can also be a single-layer structure, or can be a multi-layer stack structure including the first dielectric layer 501 and the second dielectric layer 502 stacked alternately in sequence.

[0057] In step S20, please refer to Figure 1 the S20 step in Figure 4 and Figure 5 , and form a metal layer 20 on the substrate 10.

[0058] In an alternative embodiment, as Figure 4 shown, a subtractive process may be employed to form a metal layer 20 on the upper surface of the second dielectric layer 502. Specifically, the following steps may be included:

[0059] S201: Form a metal material layer (not shown) on the upper surface of the second dielectric layer 502;

[0060] S202: Pattern the metal material layer to obtain the metal layer 20.

[0061] Specifically, in step S201, a plating process or an evaporation process, among others, may be used to form the metal material layer on the upper surface of the second dielectric layer 502.

[0062] Specifically, in step S202, patterning the metal material layer to obtain the metal layer 20 may include:

[0063] S2021: Form a hard mask layer (not shown) on the upper surface of the metal material layer;

[0064] S2022: Form a photoresist layer (not shown) on the upper surface of the hard mask layer;

[0065] S2023: Expose and develop the photoresist layer to obtain a patterned photoresist layer;

[0066] S2024: Etch the hard mask layer based on the patterned photoresist layer to obtain a patterned hard mask layer; specifically, a dry etching process or the like may be used to etch the hard mask layer;

[0067] S2025: Remove the patterned photoresist layer; etch the metal material layer based on the patterned hard mask layer to obtain the metal layer 20; specifically, an ashing process or the like may be used to remove the patterned photoresist layer; a dry etching process or the like may be used to etch the metal material layer;

[0068] S2026: Remove the patterned hard mask layer; specifically, a chemical mechanical polishing process or an etching process or the like may be used to remove the patterned hard mask layer.

[0069] In another alternative embodiment, as Figure 5 shown, a damascene process may be employed to form the metal layer 20 within the second dielectric layer 502. Specifically, the following steps may be included:

[0070] S201: Form a groove (not shown) on the upper surface of the second dielectric layer 502;

[0071] S202: Form a metal material layer (not shown) within the groove and on the upper surface of the second dielectric layer 502, and the metal material layer fills the groove;

[0072] S203: Remove the metal material layer on the upper surface of the second dielectric layer 502, and the metal material layer remaining in the groove is the metal layer 20.

[0073] Specifically, in step S201, a photolithography etching process can be used to form a groove on the upper surface of the second dielectric layer 502, and the depth of the groove extending into the second dielectric layer 502 is less than the thickness of the second dielectric layer 502.

[0074] Specifically, in step S202, a metal material layer can be formed in the groove and on the upper surface of the second dielectric layer 502 by, but not limited to, electroplating process or evaporation process.

[0075] Specifically, in step S203, the metal material layer on the upper surface of the second dielectric layer 502 can be removed by, but not limited to, chemical mechanical polishing process.

[0076] As an example, the metal layer 20 can include, but not limited to, copper layer, aluminum layer, nickel layer or gold layer, etc.; in this embodiment, the metal layer 20 is preferably a copper layer.

[0077] As an example, the shape of the metal layer 20 can be set according to actual needs. For example, the shape of the metal layer 20 can be a rectangular strip, or a square block, a circular block or an oval block, etc.

[0078] In step S30, please refer to Figure 1 the S30 step in Figure 6 , and form a capping dielectric layer 30 on the substrate 10, and the capping dielectric layer 30 covers the metal layer 20.

[0079] As an example, a capping dielectric layer 30 can be formed on the upper surface of the second dielectric layer 502 by, but not limited to, physical vapor deposition process, chemical vapor deposition process or atomic layer deposition process, etc.

[0080] Specifically, the thickness of the capping dielectric layer 30 is greater than the thickness of the metal layer 20, and the capping dielectric layer 30 covers the metal layer 20. The thickness of the capping dielectric layer 30 can be in the micron range. For example, it can be 10μm, 20μm, 30μm, 50μm, 100μm or 200μm, etc.

[0081] In some examples, the capping dielectric layer 30 can include, but not limited to, a silicon oxide layer.

[0082] In step S40, please refer to Figure 1 the S40 step in Figures 7 to 8 , and form a deep through-hole 40 in the capping dielectric layer 30, and the deep through-hole 40 is located on at least one side of the capping dielectric layer 30.

[0083] As an example, but not limited to, a dry etching process can be used to etch the covering dielectric layer 30 to form deep through-holes 40 in the covering dielectric layer 30.

[0084] Specifically, the number of the deep through-holes 40 can be set according to actual needs; in this embodiment, the number of the deep through-holes 40 is multiple. Figure 7 Taking the number of the deep through-holes 40 being 4 as an example, the 4 deep through-holes 40 are arranged at intervals along the circumferential direction of the metal layer 20 and are respectively located in different layers of the metal layer 20; of course, in other examples, the number of the deep through-holes 40 is not limited to Figure 7 the 4 in the above.

[0085] In an alternative example, the widths of the multiple deep through-holes 40 can be exactly the same.

[0086] In another alternative example, the widths of the multiple deep through-holes 40 can be different; that is, the widths of the multiple deep through-holes 40 can be different from each other, or only some of the multiple deep through-holes 40 have the same width. The deep through-holes 40 with different widths have different charge accumulations, and the breakdown of the plasma to the metal layer 20 and the covering dielectric layer 30 located outside the metal layer 20 can be monitored, so as to realize the monitoring of the plasma characteristics, where the characteristics of the plasma include stability and position. That is to say, it is possible to monitor whether there is an unstable phenomenon in the plasma and the corresponding unstable position.

[0087] In an alternative example, the depths of the multiple deep through-holes 40 can be exactly the same.

[0088] In another alternative example, the depths of the multiple deep through-holes 40 can be different; that is, the depths of the multiple deep through-holes 40 can be different from each other, or only some of the multiple deep through-holes 40 have the same depth. The deep through-holes 40 with different depths have different charge accumulations, and the breakdown of the plasma to the metal layer 20 and the covering dielectric layer 30 located outside the metal layer 20 can be monitored, so as to realize the monitoring of whether there is an unstable phenomenon in the plasma and the corresponding unstable position.

[0089] Specifically, the multiple deep through-holes 40 can have the same width and depth; or only the same width but different depths; or different widths but the same depth; or both the depth and width are different.

[0090] As an example, the depths of the multiple deep through-holes 40 are all less than or equal to the thickness of the covering dielectric layer 30.

[0091] It should be noted that Figures 6 to 8 taking the metal layer 20 being located on the upper surface of the second interlayer dielectric layer 502 as an example; for example Figure 5An example of the metal layer 20 embedded in the second interlayer dielectric layer 502 is shown. The resulting structure is the same as that obtained in Figure 8 except for the different position of the metal layer 20, and the other structures can be the same, so they will not be repeated here. Of course, in other examples, for the example of the metal layer 20 embedded in the second interlayer dielectric layer 502, the deep through-hole 40 can penetrate through the covering dielectric layer 30 along the thickness direction and extend into the second interlayer dielectric layer 502.

[0092] As an example, the distance between the deep through-hole 40 and the metal layer 20 can be set according to actual needs, but the distance between the deep through-hole 40 and the metal layer 20 cannot be too large. In this embodiment, the distance between the deep through-hole 40 and the metal layer 20 can be 100 nm to 10 μm; specifically, the distance between the deep through-hole 40 and the metal layer 20 can be 100 nm, 500 nm, 1 μm, 5 μm or 10 μm, etc.

[0093] In this application, by designing the deep through-hole 40 near the metal layer 20, it is beneficial to achieve the effect of local charge discharge at the edge of the metal layer 40.

[0094] Based on the same inventive concept, please continue to refer to Figures 4 to 8 , this application also provides a plasma etching monitoring structure, including: a substrate 10; a metal layer 20, the metal layer 20 is located on the substrate 10; a covering dielectric layer 30, the covering dielectric layer 30 is located on the substrate 10 and covers the metal layer 20; a deep through-hole 40, the deep through-hole 40 is located in the covering dielectric layer 30 and is located on at least one side of the covering dielectric layer 30.

[0095] In the above plasma etching monitoring structure, by arranging the deep through-hole 40 near the metal layer 20, it is beneficial to the local charge discharge at the edge of the metal layer 20. Once there is a large increase in plasma in the dry etching process, it is easy to cause dielectric breakdown due to visible arcing on the local surface of the substrate 10. Through the plasma etching monitoring structure of this application, it can be monitored whether the plasma is unstable, and the area where the plasma is unstable can be determined through the loss position on the wafer.

[0096] In some examples, the substrate 10 can include but is not limited to a silicon substrate. Of course, in other examples, the substrate 10 can also be a sapphire substrate, a gallium nitride substrate, a germanium substrate, a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc.

[0097] In one example, the plasma etching monitoring structure can further include an interlayer dielectric layer 50, and the interlayer dielectric layer 50 is located on the upper surface of the substrate 10.

[0098] Specifically, the interlayer dielectric layer 50 may include a first interlayer dielectric layer 501 and a second interlayer dielectric layer 502; the first interlayer dielectric layer 501 may be located on the upper surface of the substrate 10, and the second interlayer dielectric layer 502 may be located on the upper surface of the first interlayer dielectric layer 201.

[0099] Specifically, the first dielectric layer 501 may include, but is not limited to, a silicon dioxide layer, and the second dielectric layer 502 may include, but is not limited to, a silicon nitride layer.

[0100] As an example, the thickness of the first dielectric layer 501 and the thickness of the second dielectric layer 502 can be set according to actual needs. The thickness of the first dielectric layer 501 may be the same as or different from the thickness of the second dielectric layer 502; preferably, in this embodiment, the thickness of the first dielectric layer 501 is less than the thickness of the second dielectric layer 502.

[0101] Of course, the interlayer dielectric layer 50 is not limited to Figure 8 the double-layer structure including the first dielectric layer 501 and the second dielectric layer 502 as shown. In other examples, the interlayer dielectric layer 50 may also be a single-layer structure or a multi-layer stacked structure including the first dielectric layer 501 and the second dielectric layer 502 stacked alternately in sequence.

[0102] In one example, as Figure 4 and Figure 8 shown, the metal layer 20 is located on the upper surface of the second interlayer dielectric layer 502. In another example, as Figure 5 shown, the metal layer 20 may be embedded in the second interlayer dielectric layer 502.

[0103] As an example, the metal layer 20 may include, but is not limited to, a copper layer, an aluminum layer, a nickel layer, or a gold layer, etc.; in this embodiment, the metal layer 20 is preferably a copper layer.

[0104] As an example, the shape of the metal layer 20 can be set according to actual needs. For example, the shape of the metal layer 20 can be a rectangular strip, or a square block, a circular block, or an oval block, etc.

[0105] As an example, the thickness of the covering dielectric layer 30 is greater than the thickness of the metal layer 20, and the covering dielectric layer 30 covers the metal layer 20. The thickness of the covering dielectric layer 30 can be in the micron range. For example, it can be 10μm, 20μm, 30μm, 50μm, 100μm, or 200μm, etc.

[0106] In some examples, the covering dielectric layer 30 may include, but is not limited to, a silicon dioxide layer.

[0107] As an example, the number of the deep through-holes 40 can be set according to actual needs; in this embodiment, the number of the deep through-holes 40 is multiple, Figure 7 in Figure 7 , taking the number of the deep through-holes 40 being 4 as an example, the 4 deep through-holes 40 are arranged at intervals along the circumferential direction of the metal layer 20 and are respectively located in different layers of the metal layer 20; of course, in other examples, the number of the deep through-holes 40 is not limited to Figure 7 the 4 in Figure 7 .

[0108] In an alternative example, the widths of the multiple deep through-holes 40 can be exactly the same.

[0109] In another alternative example, the widths of the multiple deep through-holes 40 can be different; that is, the widths of the multiple deep through-holes 40 can be different from each other, or only some of the multiple deep through-holes 40 have the same width. The deep through-holes 40 with different widths have different charge accumulations, and the breakdown of the plasma on the metal layer 20 and the capping dielectric layer 30 located outside the metal layer 20 can be monitored, so as to realize the monitoring of the plasma characteristics, wherein the plasma characteristics include stability and position. That is to say, it is possible to monitor whether there is an unstable phenomenon in the plasma and the corresponding unstable position.

[0110] In an alternative example, the depths of the multiple deep through-holes 40 can be exactly the same.

[0111] In another alternative example, the depths of the multiple deep through-holes 40 can be different; that is, the depths of the multiple deep through-holes 40 can be different from each other, or only some of the multiple deep through-holes 40 have the same depth. The deep through-holes 40 with different depths have different charge accumulations, and the breakdown of the plasma on the metal layer 20 and the capping dielectric layer 30 located outside the metal layer 20 can be monitored, so as to realize the monitoring of whether there is an unstable phenomenon in the plasma and the corresponding unstable position.

[0112] Specifically, the multiple deep through-holes 40 can have the same width and depth; or only the same width but different depths; or different widths but the same depth; or both the depth and width are different.

[0113] As an example, the depths of the multiple deep through-holes 40 are all less than or equal to the thickness of the capping dielectric layer 30.

[0114] It should be noted that, Figures 6 to 8 taking the metal layer 20 being located on the upper surface of the second interlayer dielectric layer 502 as an example; for the example where the metal layer 20 is embedded in the second interlayer dielectric layer 502 as shown in Figure 5 Figure 5 , the finally obtained structure is the same as that in Figure 8Except for the different positions of the metal layer 20, the other structures can be the same, and will not be repeated here. Of course, in other examples, for the example where the metal layer 20 is embedded in the second interlayer dielectric layer 502, the deep through hole 40 can penetrate the covering dielectric layer 30 along the thickness direction and extend into the second interlayer dielectric layer 502.

[0115] As an example, the distance between the deep through hole 40 and the metal layer 20 can be set according to actual needs, but the distance between the deep through hole 40 and the metal layer 20 cannot be too large. In this embodiment, the distance between the deep through hole 40 and the metal layer 20 can be 100 nm to 10 μm; specifically, the distance between the deep through hole 40 and the metal layer 20 can be 100 nm, 500 nm, 1 μm, 5 μm or 10 μm, etc.

[0116] In this application, by designing the deep through hole 40 near the metal layer 20, it is beneficial to achieve the effect of local charge discharge at the edge of the metal layer 40.

[0117] Based on the same inventive concept, please continue to refer to Figures 1 to 8 , this application also provides a plasma etching monitoring method, including:

[0118] Providing the above plasma etching monitoring structure;

[0119] Using plasma to etch the covering dielectric layer and monitoring the distribution and characteristics of the plasma during the etching process.

[0120] In this embodiment, during the process of etching the covering dielectric layer by plasma, the breakdown of the plasma on the metal layer and the covering dielectric layer located outside the metal layer can be monitored, so as to monitor whether there is an unstable phenomenon in the plasma and the corresponding unstable positions.

[0121] The above plasma etching monitoring method, through the plasma monitoring structure with a deep through hole 40 provided near the metal layer 20, is beneficial to the local charge discharge at the edge of the metal layer 20. Once there is a large increase in plasma in the dry etching process, it is easy to cause dielectric layer breakdown phenomena visible to visual inspection (arcing) on the local surface of the substrate 10. Through the plasma etching monitoring structure of this application, it can be monitored whether the plasma is unstable, and the area where the plasma is unstable can be determined through the loss position on the wafer.

[0122] It should be understood that although Figure 1 the steps in the flowchart of Figure 1At least some of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily executed and completed at the same moment, but can be executed at different moments. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turns with at least some of the steps or stages in other steps or other steps.

[0123] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0124] The above-described embodiments only express several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A plasma etching monitoring structure, characterized in that, it includes: a substrate; a metal layer located on the substrate; a covering dielectric layer located on the substrate and covering the metal layer; a deep through-hole located within the covering dielectric layer and on at least one side of the covering dielectric layer; the deep through-hole is used to monitor the breakdown of the plasma on the metal layer and the covering dielectric layer located outside the metal layer, so as to realize the monitoring of plasma characteristics.

2. The plasma etching monitoring structure according to claim 1, characterized in that, the number of the deep through-holes is multiple, and the multiple deep through-holes are arranged at intervals along the circumferential direction of the metal layer.

3. The plasma etching monitoring structure according to claim 2, characterized in that, the widths of the multiple deep through-holes are not all the same, and / or the depths of the multiple deep through-holes are not all the same.

4. The plasma etching monitoring structure according to claim 1, characterized in that, the distance between the deep through-hole and the metal layer is 100 nm to 10 μm.

5. The plasma etching monitoring structure according to any one of claims 1 to 4, characterized in that, the plasma etching monitoring structure further includes: an interlayer dielectric layer located on the upper surface of the substrate; the metal layer is located on the upper surface of the interlayer dielectric layer or embedded within the interlayer dielectric layer; the covering dielectric layer is located on the upper surface of the interlayer dielectric layer.

6. The plasma etching monitoring structure according to claim 5, characterized in that, the interlayer dielectric layer includes: a first dielectric layer located on the upper surface of the substrate; a second dielectric layer located on the upper surface of the first dielectric layer; the metal layer is located on the upper surface of the second dielectric layer or embedded within the second dielectric layer; the covering dielectric layer is located on the upper surface of the second dielectric layer.

7. A method for preparing a plasma etching monitoring structure, characterized in that, it includes: providing a substrate; forming a metal layer on the substrate; forming a covering dielectric layer on the substrate, the covering dielectric layer covering the metal layer; forming a deep through-hole within the covering dielectric layer, the deep through-hole being on at least one side of the covering dielectric layer; the deep through-hole is used to monitor the breakdown of the plasma on the metal layer and the covering dielectric layer located outside the metal layer, so as to realize the monitoring of plasma characteristics.

8. The method for preparing a plasma etching monitoring structure according to claim 7, characterized in that, before forming the metal layer on the substrate, it further includes: forming an interlayer dielectric layer on the upper surface of the substrate; the covering dielectric layer is located on the upper surface of the interlayer dielectric layer; forming the metal layer on the substrate includes: forming the metal layer on the upper surface of the interlayer dielectric layer or within the interlayer dielectric layer.

9. The method for preparing a plasma etching monitoring structure according to claim 8, characterized in that, forming the interlayer dielectric layer on the upper surface of the substrate includes: forming a first dielectric layer on the upper surface of the substrate; forming a second dielectric layer on the upper surface of the first dielectric layer; the covering dielectric layer is located on the upper surface of the second dielectric layer; Forming the metal layer on the upper surface of the interlayer dielectric layer includes: forming a metal material layer on the upper surface of the second dielectric layer; patterning the metal material layer to obtain the metal layer; Forming the metal layer within the interlayer dielectric layer includes: forming a groove on the upper surface of the second dielectric layer; forming a metal material layer within the groove and on the upper surface of the second dielectric layer, the metal material layer filling the groove; removing the metal material layer located on the upper surface of the second dielectric layer, and the metal material layer remaining within the groove is the metal layer.

10. A method for monitoring plasma etching Characterized in that It includes: Providing a plasma etching monitoring structure as described in any one of claims 1 to 6; Using plasma to etch the covering dielectric layer and monitoring the distribution and characteristics of the plasma during the etching process.

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