Semiconductor structure

Abstract

The embodiment of the present application relates to the field of semiconductor, and provides a semiconductor structure, comprising: at least one ground layer and at least one power supply layer arranged along a preset direction, and a via structure extending along the preset direction; a first protection structure and a second protection structure, the first protection structure and the second protection structure are sequentially arranged around the side wall of the via structure in a direction around the side wall of the via structure, and the first protection structure and the second protection structure are spaced from each other, the first protection structure has a first interval with the via structure, at least a part of the first protection structure is electrically connected with the at least one ground layer, the second protection structure has a second interval between at least a part of the second protection structure and the via structure, and the second protection structure is electrically connected with the at least one power supply layer. The embodiment of the present application is beneficial to optimize the reflow path of the via structure and reduce the crosstalk between the via structure and the surrounding circuit, so as to improve the transmission quality of the via structure for transmitting electrical signals.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor, and in particular, to a semiconductor structure. BACKGROUND

[0002] With the high integration of semiconductor structures, it is very common that the semiconductor structures have complex multi-layer circuit structures, and electrical signals often need to be switched through via structures. With the increase of signal frequency and bandwidth, the via structure as a connection structure between conductive lines of different layers will cause impedance discontinuity to electrical signals, resulting in serious reflection problems, and also increase crosstalk between adjacent electrical signals, leading to some timing problems, thereby adversely affecting the transmission quality of electrical signals transmitted by the via structure.

[0003] Therefore, there is an urgent need to design a new semiconductor structure to improve the transmission quality of electrical signals transmitted by the via structure. SUMMARY

[0004] Embodiments of the present application provide a semiconductor structure, which at least helps to improve the transmission quality of electrical signals transmitted by the via structure.

[0005] According to some embodiments of the present application, a semiconductor structure is provided, which includes: at least one ground layer and at least one power layer arranged along a preset direction, and a via structure extending along the preset direction; a first protection structure and a second protection structure, the first protection structure and the second protection structure are sequentially arranged around the side wall of the via structure in a direction around the side wall of the via structure, and the first protection structure and the second protection structure are spaced apart from each other, the first protection structure has a first spacing with the via structure, at least a part of the first protection structure is electrically connected with at least one ground layer, the second protection structure has a second spacing with the via structure in at least a part of the second protection structure, and the second protection structure is electrically connected with at least one power layer.

[0006] In addition, in the preset direction, the length of the first protection structure and the length of the second protection structure are both less than or equal to the length of the via structure.

[0007] In addition, in the preset direction, the via structure has opposite top end and bottom end, the semiconductor structure further includes: a first pad, the first pad is in contact with the top end and electrically connected; a second pad, the second pad is in contact with the bottom end and electrically connected, the first protection structure and the second protection structure are both located between the first pad and the second pad, and the first protection structure and the second protection structure are both spaced apart from the first pad, and the first protection structure and the second protection structure are also both spaced apart from the second pad.

[0008] In addition, the plane where the bottom end is located is a projection plane, and the combined orthographic projection of the first protection structure and the second protection structure on the projection plane is located in the orthographic projection of the first pad on the projection plane and in the orthographic projection of the second pad on the projection plane.

[0009] In addition, in a direction along the periphery of the side wall of the via structure, the ratio of the length of the first protection structure along the periphery of the side wall of the via structure to the circumference of the side wall of the via structure is 0.4-0.6, and the ratio of the length of the second protection structure along the periphery of the side wall of the via structure to the circumference of the side wall of the via structure is 0.4-0.6.

[0010] In addition, in a direction along the periphery of the side wall of the via structure, the first protection structure includes at least two first sub-protection structures spaced from each other, and at least one of the first sub-protection structures is electrically connected to the ground layer; and the second protection structure includes at least two second sub-protection structures spaced from each other, and at least one of the second sub-protection structures is electrically connected to the power supply layer.

[0011] In addition, in the preset direction, the first protection structure includes at least two first sub-protection structures spaced from each other, and at least one of the first sub-protection structures is electrically connected to the ground layer; and the second protection structure includes at least two second sub-protection structures spaced from each other, and at least one of the second sub-protection structures is electrically connected to the power supply layer.

[0012] In addition, at least one of the first sub-protection structures is electrically connected to the power supply layer.

[0013] In addition, at least one of the second sub-protection structures is electrically connected to the ground layer.

[0014] In addition, the semiconductor structure further includes: a reverse pad area extending in the preset direction, and the via structure, the first protection structure, and the second protection structure are located in the reverse pad area.

[0015] In addition, in a plane perpendicular to the preset direction, the ratio of the cross-sectional area of the reverse pad area to the cross-sectional area of the via structure is 9-12.25.

[0016] In addition, in a direction perpendicular to the preset direction, the first protection structure and the reverse pad area have a third spacing, the second protection structure and the reverse pad area have a fourth spacing, the ratio of the width of the first spacing to the width of the third spacing is 0.8-4.5, and the ratio of the width of the second spacing to the width of the fourth spacing is 0.8-4.5.

[0017] In addition, the width of the first interval and the width of the second interval are both 150um-225um.

[0018] In addition, in a direction perpendicular to the preset direction, the thickness of the first protective layer and the thickness of the second protective layer are both 8um-25um.

[0019] In addition, in the preset direction, the via structure has opposite top and bottom ends, and the semiconductor structure further comprises: a first conductive layer in contact with the top end for electrical connection, the first conductive layer passing through the interval between the first protective structure and the second protective structure; a second conductive layer in contact with the bottom end for electrical connection, the second conductive layer passing through the interval between the first protective structure and the second protective structure.

[0020] The technical scheme provided by the embodiments of the present application has at least the following advantages:

[0021] In the above technical scheme, the sidewall of the via structure is mostly surrounded by the first protective structure and the second protective structure, so that the first protective structure and the second protective structure can jointly serve as a protective shell of the sidewall of the via structure, for isolating the via structure from the surrounding electrical devices, thereby reducing the electromagnetic interference between adjacent via structures and between the via structure and other electrical devices in the surrounding, to improve the transmission quality of the electrical signals transmitted by the via structure. In addition, since the number of via structures in the semiconductor junction is large, the reference plane for the backflow of the electrical signals in part of the via structures is the ground layer, and since at least part of the area of the first protective structure is electrically connected to the ground layer, the electrical signals in this part of the via structure can be backflowed by means of the first protective structure adjacent to the sidewall of the via structure. The reference plane for the backflow of the electrical signals in part of the via structures is the power supply layer, and since at least part of the area of the second protective structure is electrically connected to the power supply layer, the electrical signals in this part of the via structure can be backflowed by means of the second protective structure adjacent to the sidewall of the via structure. Therefore, for the via structures with different reference planes during backflow, the first protective structure or the second protective structure can serve as a new reference plane, providing a shorter backflow path for the via structures wrapped by the first protective structure or the second protective structure, to reduce the surrounding area during backflow of the electrical signals, thereby reducing the radiation energy generated during backflow of the electrical signals, and reducing the electromagnetic interference on various electrical devices in the semiconductor structure during backflow of the electrical signals, to improve the transmission quality of the electrical signals transmitted by the via structure. BRIEF DESCRIPTION OF DRAWINGS

[0022] One or more embodiments are illustrated by way of example in the figures that are part of this disclosure and which are illustrative, but not limiting of the embodiments, unless otherwise specifically indicated, the drawings shown in the figures do not constitute a proportional limitation.

[0023] Figure 1A three-dimensional structure diagram corresponding to the semiconductor structure provided in the embodiments of the present application is shown in the following.

[0024] Figure 2 A sectional structure diagram of the combination of the via structure, the first protection structure, the second protection structure, the first pad and the second pad in the semiconductor structure is shown in the following.

[0025] Figures 3 to 5 Three three-dimensional structure diagrams of the via structure, the first protection structure and the second protection structure in the semiconductor structure are shown in the following.

[0026] Figure 6 A top view structure diagram of the via structure, the first protection structure, the second protection structure and the reverse pad area in the semiconductor structure is shown in the following. DETAILED DESCRIPTION

[0027] As known from the background, the transmission quality of the via structure for transmitting electrical signals needs to be improved.

[0028] It is found through analysis that the electrical signals usually rely on the ground layer or the power layer as a reference plane to realize reflow, and the electrical signals transmitted by different via structures can be different. The electrical signals are divided into high-frequency signals and low-frequency signals. Since the ground layer has no current passing through except the return current, the ground layer can avoid causing additional electromagnetic interference to the high-frequency signals and the low-frequency signals. For high-frequency signals with high frequency, if the power layer is selected as the reference plane, there is noise in the power layer because of the large current passing through in addition to the return current, which can cause great electromagnetic interference to the high-frequency signals with high frequency, affecting the transmission quality of the high-frequency signals. For low-frequency signals, if the power layer is selected as the reference plane, the electromagnetic interference caused by the power layer to the low-frequency signals is generally within an acceptable range. Therefore, whether it is a high-frequency signal or a low-frequency signal, selecting the ground layer as the reference plane to realize reflow is a better choice.

[0029] However, because of the diversity of electrical devices in the semiconductor structure, more via structures are needed to realize electrical connection between different devices. In order to meet the requirement that different via structures all rely on the ground layer to realize reflow, the circuit in the semiconductor structure is complex and the number of layers of the semiconductor structure stack is increased, which increases the preparation cost of the semiconductor structure. Therefore, generally, high-frequency signals rely on the ground layer as a reference plane to realize reflow, and low-frequency signals rely on the power layer as a reference plane to realize reflow.

[0030] Even so, the via structure has both parasitic capacitance and parasitic inductance when transmitting an electrical signal, and both the parasitic inductance and the parasitic capacitance of the via structure will cause harm to the transmission of the electrical signal in the design of a high-speed digital circuit. The parasitic inductance of the via structure will weaken the contribution of the bypass capacitor in the semiconductor structure, weaken the filtering effect of the entire semiconductor structure, and increase the voltage drop generated by the electrical signal flowing through the via structure, and the increase of the voltage drop will cause the transmission line effect, such as electromagnetic interference problems such as sudden change, crosstalk, switching noise, rail collapse, and ground bounce. The main effect of the parasitic capacitance of the via structure on the transmission of the electrical signal is to prolong the rise time of the electrical signal and reduce the transmission speed of the electrical signal.

[0031] Therefore, it is urgent to design a new semiconductor structure to reduce the complexity of the circuit in the semiconductor structure and improve the transmission quality of the via structure transmitting an electrical signal.

[0032] The semiconductor structure provided by the embodiments of the present application is provided, and the sidewall of the via structure is mostly surrounded by the first protection structure and the second protection structure, and at least part of the area of the first protection structure is electrically connected with the ground layer, and at least part of the area of the second protection structure is electrically connected with the power supply layer, so that for the via structure transmitting electrical signals of different frequencies, the first protection structure or the second protection structure can provide a shorter return path for the via structure, and the scheme that the first protection structure and the second protection structure jointly wrap the via structure is suitable for the via structure transmitting high-frequency signals and the via structure transmitting low-frequency signals, which is beneficial to simplify the circuit layout in the semiconductor structure, and relative to the case that all the via structures return by means of the ground layer, it is beneficial to reduce the preparation cost of the semiconductor structure, and the shortening of the return path is beneficial to improve the transmission quality of the via structure transmitting an electrical signal. In addition, the first protection structure and the second protection structure can jointly serve as a protective shell of the via structure, and are used for isolating the via structure from the surrounding electrical devices, so as to reduce the electromagnetic interference between adjacent via structures and between the via structure and other surrounding electrical devices.

[0033] The embodiments of the present application will be described in detail below with reference to the drawings. However, those skilled in the art can understand that in the embodiments of the present application, many technical details are proposed in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed by the present application can be implemented.

[0034] The semiconductor structure provided by the embodiments of the present application is provided, and the sidewall of the via structure is mostly surrounded by the first protection structure and the second protection structure, and at least part of the area of the first protection structure is electrically connected with the ground layer, and at least part of the area of the second protection structure is electrically connected with the power supply layer, so that for the via structure transmitting electrical signals of different frequencies, the first protection structure or the second protection structure can provide a shorter return path for the via structure, and the scheme that the first protection structure and the second protection structure jointly wrap the via structure is suitable for the via structure transmitting high-frequency signals and the via structure transmitting low-frequency signals, which is beneficial to simplify the circuit layout in the semiconductor structure, and relative to the case that all the via structures return by means of the ground layer, it is beneficial to reduce the preparation cost of the semiconductor structure, and the shortening of the return path is beneficial to improve the transmission quality of the via structure transmitting an electrical signal. In addition, the first protection structure and the second protection structure can jointly serve as a protective shell of the via structure, and are used for isolating the via structure from the surrounding electrical devices, so as to reduce the electromagnetic interference between adjacent via structures and between the via structure and other surrounding electrical devices. Figure 1 The semiconductor structure provided by the embodiments of the present application is provided, and the sidewall of the via structure is mostly surrounded by the first protection structure and the second protection structure, and at least part of the area of the first protection structure is electrically connected with the ground layer, and at least part of the area of the second protection structure is electrically connected with the power supply layer, so that for the via structure transmitting electrical signals of different frequencies, the first protection structure or the second protection structure can provide a shorter return path for the via structure, and the scheme that the first protection structure and the second protection structure jointly wrap the via structure is suitable for the via structure transmitting high-frequency signals and the via structure transmitting low-frequency signals, which is beneficial to simplify the circuit layout in the semiconductor structure, and relative to the case that all the via structures return by means of the ground layer, it is beneficial to reduce the preparation cost of the semiconductor structure, and the shortening of the return path is beneficial to improve the transmission quality of the via structure transmitting an electrical signal. In addition, the first protection structure and the second protection structure can jointly serve as a protective shell of the via structure, and are used for isolating the via structure from the surrounding electrical devices, so as to reduce the electromagnetic interference between adjacent via structures and between the via structure and other surrounding electrical devices. Figure 2Fig. 1 is a sectional view of a via structure, a first protective structure, a second protective structure, a first pad and a second pad in a semiconductor structure; Figures 3 to 5 Fig. 2 is a perspective view of a via structure, a first protective structure and a second protective structure in a semiconductor structure; Figure 6 Fig. 3 is a top view of a via structure, a first protective structure, a second protective structure and a reverse pad region in a semiconductor structure.

[0035] In combination with reference to Figure 1 and Figure 2 The semiconductor structure comprises: at least one ground layer 100 and at least one power supply layer 101 arranged along a preset direction X, and a via structure 102 extending along the preset direction X; a first protective structure 103 and a second protective structure 104, the first protective structure 103 and the second protective structure 104 are arranged in sequence around the side wall of the via structure 102 in a direction around the side wall of the via structure 102, and the first protective structure 103 and the second protective structure 104 are spaced from each other, the first protective structure 103 has a first spacing c with the via structure 102, at least a part of the first protective structure 103 is electrically connected with the at least one ground layer 100, the second protective structure 104 has a second spacing d with the via structure 102 in at least a part of the second protective structure 104, and the second protective structure 104 is electrically connected with the at least one power supply layer 101.

[0036] When an electric signal flows through the via structure 102, a voltage drop is generated at both ends of the via structure 102, which is related to the self-inductance of the via structure 102, the mutual inductance of the via structure 102 and its surrounding electrical devices, and the rate of change of the current when the electric signal flows through the via structure 102. Specifically, it can be expressed by the following formula:

[0037]

[0038] Wherein, V gb is the voltage drop generated at both ends of the via structure 102, L a is the self-inductance of the via structure 102, L ab is the mutual inductance of the via structure 102 and its surrounding electrical devices, is the rate of change of the current when the electric signal flows through the via structure 102.

[0039] It should be noted that in the embodiments of the present application, the electric signal transmitted by the via structure 102 is reflowed with the first protective structure 103 as the reference plane, and in actual application, the electric signal transmitted by the via structure 102 can also be reflowed with the second protective structure 104 as the reference plane. For the same via structure 102, the rate of change of the current when the electric signal flows through the via structure 102 is a constant value, the side wall of the via structure 102 is surrounded by the first protective structure 103, Lab The first protective structure 103 is close to the side wall of the via structure 102, which is conducive to increasing the mutual inductance between the via structure 102 and the first protective structure 103. Compared with the reflow of the via structure 102 by means of the stratum 100 far away from the via structure 102, the via structure 102 in the embodiment of the application is conducive to providing a shorter reflow path for the via structure 102 by the first protective structure 103, and the mutual inductance L between the via structure 102 and the first protective structure 103 is increased to reduce the voltage drop V of the electrical signal at both ends of the via structure 102. ab gb Thus, it is conducive to avoiding the transmission line effect caused by a larger voltage drop, thereby improving the transmission quality of the via structure 102 in transmitting the electrical signal.

[0040] In addition, on the one hand, different via structures 102 can achieve reflow by means of the first protective structure 103 closest to the via structure 102, avoiding the cross partition of the reflow path of the electrical signal in the via structure 102, and reducing the surrounding area when the electrical signal is reflowed, thereby reducing the radiation energy generated when the electrical signal is reflowed, and reducing the electromagnetic interference on various electrical devices in the semiconductor structure when the electrical signal is reflowed. On the other hand, the first protective structure 103 and the second protective structure 104 can jointly serve as a protective shell of the side wall of the via structure 102, for isolating the via structure 102 from the electrical devices around it, thereby reducing the electromagnetic interference between adjacent via structures 102 and between the via structure 102 and other electrical devices around it. The above two aspects are conducive to reducing the electromagnetic interference between the via structure 102 and the electrical devices around it, thereby improving the transmission quality of the via structure 102 in transmitting the electrical signal.

[0041] It should be noted that, Figure 1 In some embodiments, the semiconductor structure has 5 strata 100 and 1 power layer 101 as an example, and in other embodiments, the number of strata 100 and the number of power layers 101 can be reasonably set according to actual electrical requirements. Figure 1 In some embodiments, the various electrical devices and conductive structures are separated by a dielectric layer.

[0042] In some embodiments, continuing to refer to Figure 1 or Figure 2 ​In the preset direction X, the via structure 102 has opposite top end a and bottom end b, and the semiconductor structure can further comprise: a first pad 115 in contact and electrically connected with the top end a; a second pad 125 in contact and electrically connected with the bottom end b, the first protection structure 103 and the second protection structure 104 are both located between the first pad 115 and the second pad 125, and the first protection structure 103 and the second protection structure 104 are both spaced apart from the first pad 115, and the first protection structure 103 and the second protection structure 104 are also both spaced apart from the second pad 125.

[0043] Therefore, in the preset direction X, the length of the first protection structure 103 and the length of the second protection structure 104 are both less than the length of the via structure 102. For example, in the preset direction X, the length of the via structure 102 minus the length of the first pad 115 and minus the length of the second pad 125 is a reference length, and the length of the first protection structure 103 and the length of the second protection structure 104 are both less than the reference length, so as to ensure that the first protection structure 103 and the second protection structure 104 are both not in contact with the first pad 115 and are also both not in contact with the second pad 125. Moreover, under the premise that the length of the first protection structure 103 around the side wall of the via structure 102 and the length of the second protection structure 104 around the side wall of the via structure 102 are both constant, the length of the first protection structure 103 and the length of the second protection structure 104 are both close to the reference length, which is beneficial to ensure that the first protection structure 103 and the second protection structure 104 have a larger wrapping area around the side wall of the via structure 102, thereby increasing the protection effect of the first protection structure 103 and the second protection structure 104 on the via structure 102. Specifically, ensuring that the first protection structure 103 has a larger wrapping area around the side wall of the via structure 102 is beneficial to ensure that the via structure 102 and the first protection structure 103 have a larger mutual inductance, thereby being beneficial to reduce the voltage drop of the electrical signal at both ends of the via structure 102, thereby being beneficial to avoid the transmission line effect caused by the larger voltage drop, thereby being beneficial to improve the transmission quality of the via structure 102 in transmitting the electrical signal; ensuring that the first protection structure 103 and the second protection structure 104 have a larger wrapping area around the side wall of the via structure 102 is beneficial to improve the isolation effect between the via structure 102 and the surrounding electrical devices, thereby reducing the electromagnetic interference between adjacent via structures 102 and between the via structure 102 and other surrounding electrical devices.

[0044] The semiconductor structure can further comprise: a first wire layer 106 in contact and electrically connected with the first pad 115; a second wire layer 126 in contact and electrically connected with the second pad 125. Figure 1The first conductive layer 106 and the second conductive layer are used in common to transmit the electrical signal in the via structure 102 to other electrical devices.

[0045] The first protection structure 103 and the second protection structure 104 are combined in the orthographic projection on the projection plane, and the combined orthographic projection is located in the orthographic projection of the first pad 115 on the projection plane and in the orthographic projection of the second pad 125 on the projection plane. In this way, when the via structure 102 has the first pad 115 and the second pad 125, the first protection structure 103 and the second protection structure 104 do not occupy too much layout space in the direction perpendicular to the preset direction X, which is conducive to reducing the layout range of the semiconductor structure in the direction, thereby improving the integration density of the semiconductor structure. Moreover, compared with increasing the via hole to optimize the reflow path of the electrical signal in the via structure 102, the embodiments of the present application are conducive to saving the space occupied by the via hole in the semiconductor structure and reducing the complexity of the circuit connection in the semiconductor structure.

[0046] In other embodiments, in the preset direction, the via structure has opposite top and bottom ends, and the semiconductor structure can further include: a first conductive layer in electrical contact with the top end, the first conductive layer passing through the interval between the first protection structure and the second protection structure; and a second conductive layer in electrical contact with the bottom end, the second conductive layer passing through the interval between the first protection structure and the second protection structure. The first conductive layer and the second conductive layer are used in common to transmit the electrical signal in the via structure to other electrical devices.

[0047] Moreover, since the semiconductor structure does not have the first pad in contact with the top end and does not have the second pad in contact with the bottom end, in the preset direction, the length of the first protection structure and the length of the second protection structure can be not only less than the length of the via structure, but also greater than or equal to the length of the via structure. For example, the length of the first protection structure and the length of the second protection structure can both be equal to the length of the via structure. On the one hand, on the premise that the length of the first protection structure around the side wall of the via structure and the length of the second protection structure around the side wall of the via structure are both constant in the direction around the side wall of the via structure, it is conducive to increasing the wrapping area of the first protection structure and the second protection structure around the side wall of the via structure. The specific advantages of the larger wrapping area of the first protection structure and the second protection structure around the side wall of the via structure are the same as those of the foregoing embodiments, and will not be described here. On the other hand, while increasing the wrapping area of the first protection structure and the second protection structure around the side wall of the via structure, the small volume of the first protection structure and the second protection structure is ensured, which is conducive to reducing the layout space of the first protection structure and the second protection structure in the semiconductor structure and reducing the manufacturing cost of the first protection structure and the second protection structure.

[0048] In some embodiments, regardless of whether the semiconductor structure has the first pad 115 and the second pad 125, the ratio of the length of the first protective structure 103 to the length of the via structure 102 is not less than 3 / 4, and the ratio of the length of the second protective structure 104 to the length of the via structure 102 is not less than 3 / 4 in the preset direction X, so as to ensure that the first protective structure 103 and the second protective structure 104 have a large wrapping area on the sidewall of the via structure 102, thereby ensuring a good protection effect of the first protective structure 103 and the second protective structure 104 on the via structure 102, and ensuring a good transmission quality of the via structure 102 on the electrical signal.

[0049] It should be noted that, Figure 1 In the embodiments of the present application, the via structure 102 is taken as an example of a hollow cylindrical structure, that is, the cross-sectional shape of the via structure 102 in the plane where the bottom end b is located is a circular ring. In actual applications, the cross-sectional shape of the via structure in the plane where the bottom end is located can also be a square ring, a circle or a rectangle, and the embodiments of the present application do not limit the cross-sectional shape of the via structure. In addition, in the embodiments of the present application, the first protective structure 103 and the second protective structure 104 surrounding the via structure 102 are taken as examples of arc-shaped structures, that is, the cross-sectional shape of the first protective structure 103 and the cross-sectional shape of the second protective structure 104 in the plane where the bottom end b is located are both sector rings. In actual applications, the first protective structure and the second protective structure can be set to other types of structures according to actual circuit needs, and the embodiments of the present application do not limit the cross-sectional shape of the first protective structure and the second protective structure.

[0050] In some embodiments, when the via structure 102 is a hollow cylindrical structure, it is beneficial to adjust the difference between the resistance of the via structure 102 and the resistance of the first conductive layer 106 and the resistance of the second conductive layer electrically connected to the via structure 102, so that the resistance of the via structure 102, the resistance of the first conductive layer 106 and the resistance of the second conductive layer are similar or equal, which is beneficial to reduce the impedance discontinuity of the electrical signal when passing through the first conductive layer 106, the via structure 102 and the second conductive layer, so as to improve the transmission quality of the electrical signal in the first conductive layer 106, the via structure 102 and the second conductive layer.

[0051] In the above embodiments, the ratio of the length of the first protective structure 103 wrapping around the sidewall of the via structure 102 to the circumference of the sidewall of the via structure 102 is 0.4-0.6 in the direction along the sidewall of the via structure 102, and the ratio of the length of the second protective structure 104 wrapping around the sidewall of the via structure 102 to the circumference of the sidewall of the via structure 102 is 0.4-0.6. When the first protective structure 103 and the second protective structure 104 are both arc-shaped structures, i.e., the angle of the first protective structure 103 wrapping around the via structure 102 is 144°-216°, and the angle of the second protective structure 104 wrapping around the via structure 102 is 144°-216°. In this way, under the premise that the length of the first protective structure and the length of the second protective structure are both constant in the preset direction X, the angles of the first protective structure 103 and the second protective structure 104 wrapping around the via structure 102 are both in the range, which is conducive to ensuring that the first protective structure 103 and the second protective structure 104 have a large wrapping area of the sidewall of the via structure 102, thereby ensuring that the first protective structure 103 and the second protective structure 104 have a good protection effect on the via structure 102, so as to ensure that the via structure 102 has a good transmission quality of the electrical signal.

[0052] For example, the angle of the first protective structure 103 wrapping around the via structure 102 is less than 180° but close to 180°, and the angle of the second protective structure 104 wrapping around the via structure 102 is less than 180° but close to 180°, which is conducive to reducing the voltage drop of the electrical signal generated at both ends of the via structure 102 by ensuring that the first protective structure 103 or the second protective structure 104 has a large wrapping area of the sidewall of the via structure 102, thereby reducing the electromagnetic interference between the via structure 102 and the electrical devices around the via structure 102, and improving the transmission quality of the via structure 102 in transmitting the electrical signal. In addition, it is conducive to increasing the total wrapping area of the first protective structure 103 and the second protective structure 104 on the sidewall of the via structure 102, so as to improve the isolation effect between the via structure 102 and the electrical devices around the via structure 102, thereby reducing the electromagnetic interference between adjacent via structures 102 and between the via structure 102 and other electrical devices around the via structure 102.

[0053] Reference Figures 3 to 5 , Figures 3 to 5 are schematic diagrams of three three-dimensional structures of the via structure 102, the first protective structure 103, and the second protective structure 104 in the semiconductor structure. It should be noted that, Figures 3 to 5 In the above embodiments, the via structure 102 is taken as an example of a solid cylindrical structure, and in actual applications, the via structure 102 can also be a hollow cylindrical structure. The specific descriptions of the via structure 102, the first protective structure 103, and the second protective structure 104 are as follows:

[0054] In some embodiments, referring to Figure 3 , the first protection structure 103 and the second protection structure 104 are both full-film layer structures, the reference plane for reflow of the electrical signal in the via structure 102 is a complete plane, which is conducive to avoiding the cross partition of the reflow path of the electrical signal in the via structure 102, causing interference to the electrical signal in the via structure 102, so as to improve the transmission quality of the via structure 102 for transmitting the electrical signal.

[0055] In other embodiments, referring to Figure 4 , in the direction along the side wall of the via structure 102, the first protection structure 103 includes at least two first sub-protection structures 113 spaced from each other, and at least one first sub-protection structure 113 is electrically connected to the ground layer 100 (referring to Figure 1 ); the second protection structure 104 includes at least two second sub-protection structures 114 spaced from each other, and at least one second sub-protection structure 114 is electrically connected to the power supply layer 101 (referring to Figure 1 ).

[0056] In yet other embodiments, referring to Figure 5 , in the preset direction X, the first protection structure 103 includes at least two first sub-protection structures 113 spaced from each other, and at least one first sub-protection structure 113 is electrically connected to the ground layer 100 (referring to Figure 1 ); the second protection structure 104 includes at least two second sub-protection structures 114 spaced from each other, and at least one second sub-protection structure 114 is electrically connected to the power supply layer 101 (referring to Figure 1 ).

[0057] It should be noted that, Figure 4 and Figure 5 both take the example that the first protection structure 103 includes two first sub-protection structures 113 spaced from each other, and the second protection structure 104 includes two second sub-protection structures 114 spaced from each other, and the number of the first sub-protection structures 113 included in the first protection structure 103 and the number of the second sub-protection structures 114 included in the second protection structure 104 are not limited in actual application.

[0058] In Figure 4 and Figure 5In the illustrated embodiment, at least another first sub-protection structure 113 can be electrically connected with the power layer 101. For example, when the electrical signal in the via structure 102 takes the power layer 101 as a reference plane, the first sub-protection structure 113 can be electrically connected with the power layer 101, so as to further increase the total mutual inductance between the via structure 102 and the first protection structure 103 and the second protection structure 104, thereby further reducing the voltage drop of the electrical signal at both ends of the via structure 102, so as to avoid the transmission line effect caused by the large voltage drop, thereby facilitating to improve the transmission quality of the via structure 102 for transmitting the electrical signal.

[0059] In the illustrated embodiment, at least another first sub-protection structure 113 can be electrically connected with the power layer 101. For example, when the electrical signal in the via structure 102 takes the power layer 101 as a reference plane, the first sub-protection structure 113 can be electrically connected with the power layer 101, so as to further increase the total mutual inductance between the via structure 102 and the first protection structure 103 and the second protection structure 104, thereby further reducing the voltage drop of the electrical signal at both ends of the via structure 102, so as to avoid the transmission line effect caused by the large voltage drop, thereby facilitating to improve the transmission quality of the via structure 102 for transmitting the electrical signal. Figure 4 and Figure 5 In the illustrated embodiment, at least another first sub-protection structure 113 can be electrically connected with the power layer 101. For example, when the electrical signal in the via structure 102 takes the power layer 101 as a reference plane, the first sub-protection structure 113 can be electrically connected with the power layer 101, so as to further increase the total mutual inductance between the via structure 102 and the first protection structure 103 and the second protection structure 104, thereby further reducing the voltage drop of the electrical signal at both ends of the via structure 102, so as to avoid the transmission line effect caused by the large voltage drop, thereby facilitating to improve the transmission quality of the via structure 102 for transmitting the electrical signal.

[0060] In the above embodiment, the thickness of the first protection structure 103 and the thickness of the second protection structure 104 are both 8um-25um in the direction perpendicular to the preset direction X. When the thickness of the first protection structure 103 and the thickness of the second protection structure 104 are greater than 25um, the first protection structure 103 and the second protection structure 104 are prone to fall off from the connected ground layer 100 or power layer 101, and when the thickness of the first protection structure 103 and the thickness of the second protection structure 104 are less than 8um, the process precision for preparing the first protection structure 103 and the second protection structure 104 is difficult to control, which affects the electrical characteristics of the first protection structure 103 and the second protection structure 104. Therefore, the thickness of the first protection structure 103 and the thickness of the second protection structure 104 are both in the range of 8um-25um, which is more appropriate. For example, the thickness of the first protection structure 103 and the thickness of the second protection structure 104 are both 20um, which has less influence on the electrical characteristics of the first protection structure 103 and the second protection structure 104. In other embodiments, the thickness of the first protection structure and the thickness of the second protection structure can not be equal.

[0061] The material of the first protection structure 103 is the same as the material of the ground layer 100, and the material of the second protection structure 104 is the same as the material of the power supply layer 101. In this way, the difference in electrical properties between the material of the first protection structure 103 and the material of the ground layer 100 is reduced, and the impedance discontinuity of the electrical signal when the electrical signal is transmitted between the first protection structure 103 and the ground layer 100 is reduced. The difference in electrical properties between the material of the second protection structure 104 and the material of the power supply layer 101 is also reduced, and the impedance discontinuity of the electrical signal when the electrical signal is transmitted between the second protection structure 104 and the power supply layer 101 is reduced.

[0062] Specifically, the material of the first protection structure 103 and the material of the second protection structure 104 are one of copper, silver, platinum, and other conductive materials. For example, the material of the first protection structure 103 and the material of the second protection structure 104 are the same and are both copper, which helps to reduce the manufacturing cost of the first protection structure 103 and the second protection structure 104. In addition, under the premise that the material of the first protection structure 103 and the material of the second protection structure 104 are the same, the length of the first protection structure 103 and the length of the second protection structure 104 can also be equal in the preset direction X, which helps to form the first protection structure 103 and the second protection structure 104 by the same step, and helps to simplify the manufacturing process steps of the first protection structure 103 and the second protection structure 104.

[0063] In the embodiments of the present application, in combination with the reference Figure 1 and Figure 6 The semiconductor structure can further include: a reverse pad area I extending in the preset direction X, and the via structure 102, the first protection structure 103, and the second protection structure 104 are all located in the reverse pad area I. Figure 1 and Figure 6 In the via structure 102 is a hollow cylindrical structure as an example in both of them, the reverse pad area I is a cylindrical area, that is, the cross-sectional shape of the reverse pad area I is also a circular ring in the plane where the bottom end b is located. In some embodiments, the via structure 102 is coaxially arranged with the reverse pad area I. The reverse pad area I is used to ensure that the via structure 102 has a spacing with other electrical devices and conductive structures in the semiconductor structure, and the spacing has a dielectric layer for isolating the via structure 102 from other electrical devices and conductive structures in the semiconductor structure.

[0064] In the plane perpendicular to the preset direction X, the ratio of the cross-sectional area of the anti-pad region I to the cross-sectional area of the via structure 102 is 9-12.25. In some embodiments, when the via structure 102 is a hollow cylindrical structure and the anti-pad region I is also a cylindrical region, the diameter of the outer wall of the via structure 102 can be 200 um, which can ensure that the via structure 102 has good electrical characteristics while ensuring that the via structure 102 has low material costs. The diameter of the periphery of the anti-pad region I is 600 um-700 um. The anti-pad region I having a size in this range is conducive to ensuring that the via structure 102 has a suitable spacing from other electrical devices and conductive structures in the semiconductor structure, while also being conducive to controlling the layout space occupied by the anti-pad region I in the semiconductor structure. The diameter of the periphery of the anti-pad region I can be 650 um.

[0065] In the direction perpendicular to the preset direction X, the third spacing e is between the first protective structure 103 and the anti-pad region I, and the fourth spacing f is between the second protective structure 104 and the anti-pad region I. The ratio of the width of the first spacing c to the width of the third spacing e is 0.8-4.5, and the ratio of the width of the second spacing d to the width of the fourth spacing f is 0.8-4.5.

[0066] In some embodiments, the width of the first spacing c and the width of the second spacing d can not be equal. When the electrical signal is reflowed with the first protective structure 103 as the reference plane, the smaller the width of the first spacing c, the more conducive it is to form a tight coupling between the first protective structure 103 and the via structure 102, which is conducive to reducing the crosstalk effect of the via structure 102 on other via structures 102, effectively protecting the via structure 102 from interference from other via structures 102, reducing noise in the via structure 102, and reducing the reflow path of the electrical signal in the via structure 102 to reduce the voltage drop generated by the electrical signal flowing through the via structure 102, ensuring a more stable voltage across the via structure 102, thereby improving the transmission quality of the via structure 102 in transmitting electrical signals. At this time, the second spacing d can act as a protective shell to isolate the via structure 102 from the electrical devices around it, thereby reducing the electromagnetic interference between adjacent via structures 102 and between the via structure 102 and other electrical devices around it. In other embodiments, the width of the first spacing and the width of the second spacing can also be the same.

[0067] In other embodiments, when the electrical signal is reflowed with the second protective structure 104 as the reference plane, the smaller the width of the second spacing d, the more beneficial effects it brings to the semiconductor structure, as described in the foregoing embodiments.

[0068] However, in the above embodiment, if the width of the first interval c and the width of the second interval d are too small, the first protection structure 103 and the second protection structure 104 will be too close to the via structure 102, which increases the difficulty of manufacturing the first protection structure 103 and the second protection structure 104, and the first protection structure 103 and the second protection structure 104 are prone to contact the via structure 102 to cause short circuit problem. Therefore, the width of the first interval c and the width of the second interval d can be limited to 10um-225um, so that it is beneficial to improve the transmission quality of the via structure 102 in transmitting electrical signals, reduce the manufacturing difficulty of the first protection structure 103 and the second protection structure 104, and avoid the first protection structure 103 and the second protection structure 104 from contacting the via structure 102 to cause short circuit problem.

[0069] In one specific embodiment, the via structure 102 is a hollow cylindrical structure, the solder pad region I is a cylindrical region, the diameter of the outer wall of the via structure 102 is 200um, the distance between the outer wall and the inner wall of the via structure 102 is 13um-25um, the diameter of the solder pad region I is 650um, and the width of the first interval c and the width of the second interval d can be 150um-225um.

[0070] In another specific embodiment, the via structure 102 is a hollow cylindrical structure, the solder pad region I is a cylindrical region, the diameter of the outer wall of the via structure 102 is 200um, the distance between the outer wall and the inner wall of the via structure 102 is 13um-25um, the diameter of the solder pad region I is 650um, and the width of the third interval e and the width of the fourth interval f can be 0um-125um.

[0071] In summary, the sidewall of the via structure 102 can be mostly surrounded by the first protection structure 103 and the second protection structure 104, and at least a partial region of the first protection structure 103 is electrically connected with the ground layer 100, and at least a partial region of the second protection structure 104 is electrically connected with the power supply layer 101, thus for the via structure 102 transmitting electrical signals of different frequencies, the first protection structure 103 or the second protection structure 104 can provide a shorter return flow path for the via structure 102, and the scheme that the first protection structure 103 and the second protection structure 104 jointly wrap the via structure 102 is applicable to the via structure 102 transmitting high-frequency signals and the via structure 102 transmitting low-frequency signals, which is beneficial to simplify the circuit layout in the semiconductor structure, and compared with making all the via structures 102 return flow by means of the ground layer, it is beneficial to reduce the preparation cost of the semiconductor structure, and the shortening of the return flow path is beneficial to improve the transmission quality of the via structure 102 transmitting electrical signals. In addition, the first protection structure 103 and the second protection structure 104 can jointly serve as a protective shell of the via structure 102, for isolating the via structure 102 from the surrounding electrical devices, so as to reduce the electromagnetic interference between adjacent via structures 102 and between the via structure 102 and other surrounding electrical devices.

[0072] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present application, and in actual application, various changes can be made in form and details without departing from the spirit and scope of the present application. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, therefore the protection scope of the present application should be limited by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: at least one layer of ground layer and at least one layer of power supply layer arranged along a preset direction, and a via structure extending along the preset direction; a first protection structure and a second protection structure, the first protection structure and the second protection structure are arranged in sequence around the side wall of the via structure in a direction surrounding the side wall of the via structure, and the first protection structure and the second protection structure are spaced from each other, the first protection structure has a first interval with the via structure, at least a part of the first protection structure is electrically connected with the ground layer, the second protection structure has a second interval with the via structure at least in a part of the second protection structure, and the second protection structure is electrically connected with the power supply layer; wherein, in the direction surrounding the side wall of the via structure, the ratio of the length of the first protection structure surrounding the side wall of the via structure to the circumference of the side wall of the via structure is 0.4-0.6, and the ratio of the length of the second protection structure surrounding the side wall of the via structure to the circumference of the side wall of the via structure is 0.4-0.

6.

2. The semiconductor structure of claim 1, wherein, In the preset direction, the length of the first protection structure and the length of the second protection structure are both less than or equal to the length of the via structure.

3. The semiconductor structure of claim 1, wherein, In the preset direction, the via structure has opposite top end and bottom end, and the semiconductor structure further comprises: a first pad in contact with the top end for electrical connection; a second pad in contact with the bottom end for electrical connection, the first protection structure and the second protection structure are both located between the first pad and the second pad, and the first protection structure and the second protection structure are both spaced from the first pad, and the first protection structure and the second protection structure are also both spaced from the second pad.

4. The semiconductor structure of claim 3, wherein, The plane where the bottom end is located is a projection plane, and the combined orthographic projection of the first protection structure and the second protection structure on the projection plane is located in the orthographic projection of the first pad on the projection plane and also in the orthographic projection of the second pad on the projection plane.

5. The semiconductor structure of claim 1, wherein, In the direction surrounding the side wall of the via structure, the first protection structure comprises at least two first sub-protection structures spaced from each other, and at least one of the first sub-protection structures is electrically connected with the ground layer; the second protection structure comprises at least two second sub-protection structures spaced from each other, and at least one of the second sub-protection structures is electrically connected with the power supply layer.

6. The semiconductor structure of claim 1, wherein, In the preset direction, the first protection structure comprises at least two first sub-protection structures spaced from each other, and at least one of the first sub-protection structures is electrically connected with the ground layer; the second protection structure comprises at least two second sub-protection structures spaced from each other, and at least one of the second sub-protection structures is electrically connected with the power supply layer.

7. The semiconductor structure of claim 5 or 6, wherein the semiconductor structure is a vertical semiconductor structure. At least another first sub-protection structure is electrically connected with the power supply layer.

8. The semiconductor structure of claim 5 or 6, wherein, At least another second sub-protection structure is electrically connected with the ground layer.

9. The semiconductor structure of claim 1 or 3, wherein, Further comprising: a reverse pad area extending along the preset direction, and the via structure, the first protection structure and the second protection structure are all located in the reverse pad area.

10. The semiconductor structure of claim 9, wherein, In a plane perpendicular to the preset direction, a ratio of a cross-sectional area of the anti-pad region to a cross-sectional area of the via structure is 9-12.

25.

11. The semiconductor structure of claim 9, wherein, In a direction perpendicular to the preset direction, the first protection structure and the anti-pad region have a third interval, and the second protection structure and the anti-pad region have a fourth interval, a ratio of a width of the first interval to a width of the third interval is 0.8-4.5, and a ratio of a width of the second interval to a width of the fourth interval is 0.8-4.

5.

12. The semiconductor structure of claim 11, wherein, The width of the first interval and the width of the second interval are both 150-225 um.

13. The semiconductor structure of claim 1, wherein, In a direction perpendicular to the preset direction, a thickness of the first protection structure and a thickness of the second protection structure are both 8-25 um.

14. The semiconductor structure of claim 1, wherein, In the preset direction, the via structure has opposite top and bottom ends, and the semiconductor structure further comprises: A first wire layer in contact with the top end for electrical connection, the first wire layer passing through the interval between the first protection structure and the second protection structure; A second wire layer in contact with the bottom end for electrical connection, the second wire layer passing through the interval between the first protection structure and the second protection structure.

15. A semiconductor structure, characterized by Comprising: At least one layer of ground layer and at least one layer of power supply layer arranged in a preset direction, and a via structure extending in the preset direction; A first protection structure and a second protection structure, in a direction surrounding the side wall of the via structure, the first protection structure and the second protection structure are arranged in sequence around the side wall of the via structure, and the first protection structure and the second protection structure are spaced apart from each other, the first protection structure and the via structure have a first interval, the first protection structure is electrically connected to at least one layer of the ground layer in at least a partial region, the second protection structure and the via structure have a second interval in at least a partial region, and the second protection structure is electrically connected to at least one layer of the power supply layer; wherein, in the direction surrounding the side wall of the via structure, the first protection structure comprises at least two first sub-protection structures spaced apart from each other, and at least one of the first sub-protection structures is electrically connected to the ground layer; the second protection structure comprises at least two second sub-protection structures spaced apart from each other, and at least one of the second sub-protection structures is electrically connected to the power supply layer.

16. The semiconductor structure of claim 15, wherein, At least another first sub-protection structure is electrically connected to the power supply layer.

17. The semiconductor structure of claim 15 or 16, wherein, At least another second sub-protection structure is electrically connected to the ground layer.

18. A semiconductor structure, characterized by Comprising: At least one layer of ground layer and at least one layer of power supply layer arranged in a preset direction, and a via structure extending in the preset direction; The first protection structure and the second protection structure are arranged in sequence around the side wall of the via structure in a direction around the side wall of the via structure, and the first protection structure and the second protection structure are spaced from each other, the first protection structure has a first spacing from the via structure, at least a part of the first protection structure is electrically connected to at least one ground layer, the second protection structure has a second spacing from the via structure at least in a part of the second protection structure, and the second protection structure is electrically connected to at least one power supply layer; wherein, in the preset direction, the first protection structure includes at least two first sub-protection structures spaced from each other, at least one first sub-protection structure is electrically connected to the ground layer; the second protection structure includes at least two second sub-protection structures spaced from each other, and at least one second sub-protection structure is electrically connected to the power supply layer.

19. The semiconductor structure of claim 18, wherein, At least another first sub-protection structure is electrically connected to the power supply layer.

20. The semiconductor structure of claim 18 or 19, wherein, At least another second sub-protection structure is electrically connected to the ground layer.

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