Semiconductor structure and method for manufacturing semiconductor structure

Abstract

The present disclosure relates to the field of semiconductor technology, and proposes a semiconductor structure and a method for manufacturing the semiconductor structure. The semiconductor structure includes a substrate, an NMOS transistor, and a PMOS transistor. The NMOS transistor includes a first dielectric layer, a first work function layer, and a first conductive layer stacked in sequence, and the PMOS transistor includes a second dielectric layer, a second work function layer, and a second conductive layer stacked in sequence. During the manufacturing process of the semiconductor structure, the metal elements in the first work function layer and the second work function layer will diffuse, which may affect the adjustment of the threshold voltage of the semiconductor structure. By providing a first sidewall isolation layer on the side of the first work function layer facing the second work function layer, and / or providing a second sidewall isolation layer on the side of the second work function layer facing the first work function layer, the cross-diffusion of metal elements can be prevented, thereby avoiding the situation where the threshold voltage of the semiconductor structure is difficult to adjust, thereby improving the performance of the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the semiconductor structure. Background Art

[0002] In the DRAM (Dynamic Random Access Memory) manufacturing process, high-k metal gate (HKMG) technology has begun to be applied in the peripheral region to achieve high performance requirements by reducing the equivalent oxide thickness (EOT) and leakage of the device. However, the high number of internal defects in high-k materials makes it difficult to directly adjust the device threshold voltage through traditional ion implantation. Related technologies introduce a work function layer for adjustment, but due to structural limitations, the work function layer itself can cause a series of problems, thus affecting device performance. Summary of the Invention

[0003] The present disclosure provides a semiconductor structure and a method for manufacturing the semiconductor structure to improve the performance of the semiconductor structure.

[0004] According to a first aspect of the present disclosure, there is provided a semiconductor structure comprising a substrate and an NMOS transistor and a PMOS transistor located on the substrate;

[0005] NMOS transistors include:

[0006] a first dielectric layer, the first dielectric layer being located on the substrate;

[0007] a first work function layer, the first work function layer being located on the first dielectric layer;

[0008] a first conductive layer, the first conductive layer being located on the first work function layer;

[0009] PMOS transistors include:

[0010] a second dielectric layer, the second dielectric layer being located on the substrate;

[0011] a second work function layer, the second work function layer being located on the second dielectric layer;

[0012] a second conductive layer, the second conductive layer being located on the second work function layer;

[0013] A first sidewall spacer is provided on a side of the first work function layer facing the second work function layer, and / or a second sidewall spacer is provided on a side of the second work function layer facing the first work function layer.

[0014] In one embodiment of the present disclosure, the first sidewall spacer and the second sidewall spacer are spaced apart from each other.

[0015] In one embodiment of the present disclosure, the first sidewall spacer is located below the second sidewall spacer.

[0016] In one embodiment of the present disclosure, a bottom end of the first sidewall spacer is higher than a bottom end of the first work function layer.

[0017] In one embodiment of the present disclosure, a top end of the first sidewall spacer layer is higher than a top end of the first work function layer to cover a sidewall of the first conductive layer.

[0018] In one embodiment of the present disclosure, a bottom end of the second sidewall spacer is higher than a bottom end of the second work function layer.

[0019] In one embodiment of the present disclosure, a top end of the second sidewall spacer layer is lower than a top end of the second work function layer.

[0020] In one embodiment of the present disclosure, an isolation structure is formed in the substrate to isolate a first active region and a second active region for the NMOS transistor and the PMOS transistor, respectively, in the substrate;

[0021] At least one of the NMOS transistor and the PMOS transistor covers a portion of the isolation structure.

[0022] In one embodiment of the present disclosure, the semiconductor structure further includes:

[0023] an isolation stack structure, the isolation stack structure being located above the isolation structure and between the NMOS transistor and the PMOS transistor;

[0024] The first sidewall spacer is located between the NMOS transistor and the isolation stack structure, and / or the second sidewall spacer is located between the PMOS transistor and the isolation stack structure.

[0025] In one embodiment of the present disclosure, the isolation stack structure includes:

[0026] a third dielectric layer, the third dielectric layer being located on the isolation structure;

[0027] a third work function layer, the third work function layer being located on the third dielectric layer;

[0028] a third conductive layer, the third conductive layer being located on the third work function layer;

[0029] The first sidewall isolation layer covers the sidewall of the third work function layer, and the second sidewall isolation layer covers the sidewall of the third work function layer.

[0030] In one embodiment of the present disclosure, a bottom end of the first sidewall spacer layer is higher than a bottom end of the third work function layer, and a top end of the first sidewall spacer layer is lower than a top end of the third work function layer.

[0031] In one embodiment of the present disclosure, the bottom end of the second sidewall spacer is higher than the bottom end of the third work function layer, and the top end of the second sidewall spacer is higher than the top end of the third work function layer to cover the sidewall of the third conductive layer.

[0032] In one embodiment of the present disclosure, both the NMOS transistor and the PMOS transistor are connected to the isolation stack structure.

[0033] In one embodiment of the present disclosure, the substrate has a stepped structure, such that a top end of the second dielectric layer is higher than a top end of the first dielectric layer.

[0034] In one embodiment of the present disclosure, the NMOS transistor, the isolation stack structure, and the PMOS transistor form a stair-like structure.

[0035] According to a second aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising:

[0036] Providing a substrate, wherein an isolation structure is formed in the substrate to isolate a first active area and a second active area;

[0037] forming a dielectric layer, wherein the dielectric layer above the first active region serves as a first dielectric layer, the dielectric layer above the second active region serves as a second dielectric layer, and forming a first initial work function layer on the second dielectric layer;

[0038] forming a first sidewall spacer on a side of the first dielectric layer close to the second dielectric layer, and / or forming a second sidewall spacer on a sidewall of the first initial work function layer close to the first dielectric layer;

[0039] forming a second initial work function layer, wherein the second initial work function layer on the first dielectric layer serves as a first work function layer, and the first initial work function layer and the second initial work function layer on the first initial work function layer serve as a second work function layer;

[0040] A conductive layer is formed, wherein the conductive layer on the first work function layer serves as the first conductive layer, and the conductive layer on the second work function layer serves as the second conductive layer.

[0041] In one embodiment of the present disclosure, the first sidewall spacer covers the sidewall of the first work function layer.

[0042] In one embodiment of the present disclosure, while forming the first initial work function layer on the second dielectric layer, the first initial work function layer is also formed on the first dielectric layer, and before forming the first sidewall isolation layer and / or the second sidewall isolation layer, the first initial work function layer on the first dielectric layer is removed.

[0043] In one embodiment of the present disclosure, the first sidewall spacer and the second sidewall spacer are formed in the same process step.

[0044] In one embodiment of the present disclosure, forming the first sidewall spacer and the second sidewall spacer includes:

[0045] forming an initial isolation layer on the first dielectric layer and the first initial work function layer;

[0046] The initial isolation layer is partially etched to expose a portion of the first dielectric layer and an upper surface of the first initial work function layer to form a first sidewall spacer and a second sidewall spacer.

[0047] In one embodiment of the present disclosure, the first initial work function layer includes a first layer segment and a second layer segment, the first layer segment is located above the isolation structure, and the second layer segment is located on the second dielectric layer, the first layer segment and the second layer segment form a stepped structure so that the initial isolation layer is a stepped structure, and after partially etching the initial isolation layer, the first sidewall isolation layer and the second sidewall isolation layer are formed to cover the sidewalls of the first layer segment and the sidewalls of the second layer segment, respectively.

[0048] In one embodiment of the present disclosure, forming the first sidewall spacer and the second sidewall spacer includes:

[0049] forming an interface layer on the substrate;

[0050] forming a high-K dielectric layer on the interface layer;

[0051] forming a cutoff layer on the high-K dielectric layer;

[0052] forming a first transition metal layer on the cutoff layer;

[0053] forming a metal isolation layer on the first transition metal layer;

[0054] Using a mask structure, the metal isolation layer and the first transition metal layer located above the first active region, as well as the metal isolation layer and the first transition metal layer located above a portion of the isolation structure are removed, and the remaining portion of the cutoff layer, the first transition metal layer, and the metal isolation layer serve as a first initial work function layer;

[0055] forming an initial isolation layer on the stop layer and the metal isolation layer, so that the initial isolation layer covers the sidewalls of the stop layer, the first transition metal layer and the metal isolation layer;

[0056] The initial isolation layer is partially etched to expose the cutoff layer and the metal isolation layer, and the initial isolation layer covering the cutoff layer, the first transition metal layer, and the side walls of the metal isolation layer above the isolation structure serves as a first sidewall isolation layer, and the initial isolation layer covering the cutoff layer, the first transition metal layer, and the side walls of the metal isolation layer above the second active area serves as a second sidewall isolation layer.

[0057] In one embodiment of the present disclosure, forming an NMOS transistor and a PMOS transistor on a substrate includes:

[0058] After forming the first sidewall spacer and the second sidewall spacer,

[0059] removing the exposed cutoff layer;

[0060] forming a second transition metal layer, a barrier layer, a polysilicon layer, and a metal layer in sequence on the high-K dielectric layer and the metal isolation layer, wherein the second transition metal layer and the barrier layer above the second active region serve as a second initial work function layer;

[0061] The interface layer and the high-K dielectric layer above the first active area and the high-K dielectric layer above a portion of the isolation structure serve as a first dielectric layer; the second transition metal layer and the barrier layer above the first active area and a portion of the isolation structure serve as a second work function layer; and the polysilicon layer and the metal layer above the first active area and a portion of the isolation structure serve as a first conductive layer.

[0062] The interface layer and the high-K dielectric layer above the second active region serve as a second dielectric layer; the cutoff layer, the first transition metal layer, the metal isolation layer, the second transition metal layer, and the barrier layer above the second active region serve as a second work function layer; and the polysilicon layer and the metal layer above the second active region serve as a second conductive layer;

[0063] The high-K dielectric layer above the partial isolation structure serves as the third dielectric layer of the isolation stack structure; the cutoff layer, the first transition metal layer, the metal isolation layer, the second transition metal layer and the barrier layer above the partial isolation structure serve as the third work function layer of the isolation stack structure; the polysilicon layer and the metal layer above the partial isolation structure serve as the third conductive layer of the isolation stack structure.

[0064] The semiconductor structure of the embodiment of the present disclosure includes a substrate, an NMOS transistor, and a PMOS transistor. The NMOS transistor includes a first dielectric layer, a first work function layer, and a first conductive layer stacked in sequence, and the PMOS transistor includes a second dielectric layer, a second work function layer, and a second conductive layer stacked in sequence. The first work function layer and the second work function layer can adjust the work functions of the NMOS transistor and the PMOS transistor, respectively. However, during the manufacturing process of the semiconductor structure, metal elements in the first work function layer and the second work function layer may diffuse, which may affect the adjustment of the threshold voltage of the semiconductor structure. By providing a first sidewall isolation layer on the side of the first work function layer facing the second work function layer, and / or providing a second sidewall isolation layer on the side of the second work function layer facing the first work function layer, cross-diffusion of metal elements can be prevented, thereby avoiding the situation where the threshold voltage of the semiconductor structure is difficult to adjust, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] The various objects, features, and advantages of the present disclosure will become more apparent upon consideration of the following detailed description of preferred embodiments of the present disclosure in conjunction with the accompanying drawings. The accompanying drawings are merely illustrative illustrations of the present disclosure and are not necessarily drawn to scale. In the drawings, like reference numerals refer to the same or similar parts throughout.

[0066] Figure 1 is a schematic structural diagram of a semiconductor structure according to an exemplary embodiment;

[0067] Figure 2 is a schematic flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment;

[0068] Figure 3 is a schematic structural diagram of a method for manufacturing a semiconductor structure according to an exemplary embodiment;

[0069] Figure 4 is a structural schematic diagram showing a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present invention for forming an interface layer;

[0070] Figure 5 is a structural schematic diagram showing a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present invention, showing a high-K dielectric layer;

[0071] Figure 6 is a structural schematic diagram showing a method for manufacturing a semiconductor structure according to an exemplary embodiment, in which a metal isolation layer is formed;

[0072] Figure 7 is a schematic structural diagram of a method for manufacturing a semiconductor structure covering a mask structure according to an exemplary embodiment;

[0073] Figure 8 is a schematic structural diagram showing a method for manufacturing a semiconductor structure according to an exemplary embodiment, wherein a portion of a cutoff layer is exposed;

[0074] Figure 9 is a structural schematic diagram showing a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present invention, showing an initial isolation layer;

[0075] Figure 10 is a structural schematic diagram showing a method for manufacturing a semiconductor structure according to an exemplary embodiment, in which a portion of an initial isolation layer is removed;

[0076] Figure 11 is a structural schematic diagram showing a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present invention, showing a barrier layer;

[0077] Figure 12is a structural schematic diagram of forming a polysilicon layer according to a method for manufacturing a semiconductor structure according to an exemplary embodiment;

[0078] Figure 13 FIG. 1 is a structural diagram illustrating a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present invention for forming a metal layer.

[0079] The following are the descriptions of the reference numerals:

[0080] 10. Substrate; 11. Isolation structure; 12. First active region; 13. Second active region; 14. SiGe layer; 20. NMOS transistor; 21. First dielectric layer; 22. First work function layer; 23. First conductive layer; 30. PMOS transistor; 31. Second dielectric layer; 32. Second work function layer; 33. Second conductive layer; 40. First sidewall spacer; 50. Second sidewall spacer; 60. Isolation stack structure; 61. Third dielectric layer; 62. Third work function layer; 63. Third conductive layer;

[0081] 70. Interface layer; 71. High-K dielectric layer; 72. Stop layer; 73. First transition metal layer; 74. Metal isolation layer; 75. Mask structure; 76. Initial isolation layer; 77. Second transition metal layer; 78. Barrier layer; 79. Polysilicon layer; 80. Metal layer. DETAILED DESCRIPTION

[0082] Typical embodiments that embody the features and advantages of the present disclosure will be described in detail in the following description. It should be understood that the present disclosure can have various variations in different embodiments without departing from the scope of the present disclosure, and the description and drawings therein are essentially for illustrative purposes rather than for limiting the present disclosure.

[0083] In the following description of different exemplary embodiments of the present disclosure, reference is made to the accompanying drawings, which form a part of this disclosure and in which are shown by way of example different exemplary structures, systems and steps that may implement aspects of the present disclosure. It will be understood that other specific schemes of components, structures, exemplary devices, systems and steps may be used, and structural and functional modifications may be made without departing from the scope of the present disclosure. Furthermore, although the terms "above", "between", "within", etc. may be used in this specification to describe different exemplary features and elements of the present disclosure, these terms are used herein for convenience only, for example, according to the orientation of the examples in the accompanying drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of a structure to fall within the scope of the present disclosure.

[0084] An embodiment of the present disclosure provides a semiconductor structure. Figure 1The semiconductor structure includes a substrate 10 and an NMOS transistor 20 and a PMOS transistor 30 located on the substrate 10; the NMOS transistor 20 includes: a first dielectric layer 21, the first dielectric layer 21 is located on the substrate 10; a first work function layer 22, the first work function layer 22 is located on the first dielectric layer 21; a first conductive layer 23, the first conductive layer 23 is located on the first work function layer 22; the PMOS transistor 30 includes: a second dielectric layer 31, the second dielectric layer 31 is located on the substrate 10; a second work function layer 32, the second work function layer 32 is located on the second dielectric layer 31; a second conductive layer 33, the second conductive layer 33 is located on the second work function layer 32; wherein, a first sidewall isolation layer 40 is provided on the side of the first work function layer 22 facing the second work function layer 32, and / or a second sidewall isolation layer 50 is provided on the side of the second work function layer 32 facing the first work function layer 22.

[0085] A semiconductor structure according to an embodiment of the present disclosure includes a substrate 10, an NMOS transistor 20, and a PMOS transistor 30. The NMOS transistor 20 includes a first dielectric layer 21, a first work function layer 22, and a first conductive layer 23 stacked in sequence. The PMOS transistor 30 includes a second dielectric layer 31, a second work function layer 32, and a second conductive layer 33 stacked in sequence. The first work function layer 22 and the second work function layer 32 can adjust the work functions of the NMOS transistor 20 and the PMOS transistor 30, respectively. However, during the fabrication of the semiconductor structure, metal elements within the first work function layer 22 and the second work function layer 32 may diffuse, potentially affecting the adjustment of the threshold voltage of the semiconductor structure. By providing a first sidewall spacer 40 on the side of the first work function layer 22 facing the second work function layer 32, and / or providing a second sidewall spacer 50 on the side of the second work function layer 32 facing the first work function layer 22, cross-diffusion of metal elements can be prevented, thereby preventing difficulty in adjusting the threshold voltage of the semiconductor structure and improving the performance of the semiconductor structure.

[0086] The semiconductor structure in this embodiment is a CMOS (Complementary Metal Oxide Semiconductor) transistor, which includes an NMOS transistor 20 and a PMOS transistor 30 . The NMOS transistor 20 and the PMOS transistor 30 are independently provided.

[0087] Combine Figure 1As shown, an isolation structure 11 is formed in the substrate 10 to isolate a first active region 12 and a second active region 13 for the NMOS transistor 20 and the PMOS transistor 30, respectively, in the substrate 10. A first dielectric layer 21 of the NMOS transistor 20 is formed on the first active region 12, and a second dielectric layer 31 of the PMOS transistor 30 is formed in the second active region 13. The isolation structure 11 may include silicon oxide, silicon nitride, silicon oxynitride, fluorinated silicate glass (FSG), a low-K dielectric material, other suitable materials, or combinations of these materials.

[0088] The isolation structure 11 may define the first active region 12 and the second active region 13 and implement electrical isolation between the first active region 12 and the second active region 13 using isolation technology, such as local oxidation of silicon (LOCOS) or shallow trench isolation (STI) technology.

[0089] The number of film layers of the first work function layer 22 may be smaller than the number of film layers of the second work function layer 32 . Alternatively, the number of film layers of the first work function layer 22 may be equal to the number of film layers of the second work function layer 32 .

[0090] In one embodiment, the substrate 10 may include a silicon carbide substrate, a sapphire substrate, or a silicon substrate. In one embodiment, the substrate 10 may be formed of any suitable material, for example, including at least one of silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, and carbon-doped silicon.

[0091] The first dielectric layer 21 may be a single layer or a multilayer structure. In this embodiment, the first dielectric layer 21 may include an interface layer 70 and a high-K dielectric layer 71 stacked in sequence. The interface layer 70 may include a silicon oxide layer, and the material of the high-K dielectric layer 71 may include materials such as hafnium oxide, hafnium oxide silicon, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium oxide silicon, tantalum oxide, tantalum oxide silicon, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, silicon oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0092] The first work function layer 22 may be a single layer or a multilayer structure. The first work function layer 22 may include scandium (Sc), yttrium (Y), actinium (Ac), hafnium (Hf), titanium (Ti), zirconium (Zr), tantalum (Ta), Al (aluminum), lanthanum (La), lanthanide elements, and actinide elements. In this embodiment, the first work function layer 22 may include a second transition metal layer 77 and a barrier layer 78 stacked in sequence. The second transition metal layer 77 may include lanthanum (La), and the barrier layer 78 may include titanium nitride (TiN).

[0093] The first conductive layer 23 may be a single layer or a multi-layer structure. In this embodiment, the first conductive layer 23 may include a polysilicon layer 79 and a metal layer 80 stacked in sequence. The metal layer 80 may include conventional conductive metals such as tungsten (W) and copper (Cu).

[0094] Accordingly, the second dielectric layer 31 may be a single layer or a multi-layer structure. In this embodiment, the first dielectric layer 21 may include an interface layer 70 and a high-K dielectric layer 71 stacked in sequence.

[0095] The second work function layer 32 may be a single layer or a multilayer structure. The second work function layer 32 may include scandium (Sc), yttrium (Y), actinium (Ac), hafnium (Hf), titanium (Ti), zirconium (Zr), tantalum (Ta), aluminum (Al), lanthanum (La), lanthanides, and actinides. In this embodiment, the first work function layer 22 may include a cutoff layer 72, a first transition metal layer 73, a metal isolation layer 74, a second transition metal layer 77, and a barrier layer 78 stacked in sequence. The cutoff layer 72 may include titanium nitride (TiN), the first transition metal layer 73 may include aluminum (Al), and the metal isolation layer 74 may include titanium nitride (TiN).

[0096] The second conductive layer 33 may be a single layer or a multi-layer structure. In this embodiment, the second conductive layer 33 may include a polysilicon layer 79 and a metal layer 80 stacked in sequence.

[0097] The first sidewall spacer 40 and the second sidewall spacer 50 are oxide layers, such as silicon oxide layers, silicon oxynitride layers, etc.

[0098] In one embodiment, the first sidewall spacer 40 and the second sidewall spacer 50 are spaced apart from each other, that is, the first sidewall spacer 40 and the second sidewall spacer 50 independently cover the first work function layer 22 and the second work function layer 32 to avoid diffusion of metal elements.

[0099] The side wall of the first work function layer 22 facing the second work function layer 32 is the first side wall, and the first side wall can be entirely provided with the first side wall isolation layer 40, or the first side wall can be partially provided with the first side wall isolation layer 40, that is, the first side wall isolation layer 40 is provided on at least a portion of the first side wall.

[0100] Correspondingly, the sidewall of the second work function layer 32 facing the first work function layer 22 is a second sidewall, and a second sidewall isolation layer 50 is disposed on at least a portion of the second sidewall.

[0101] In one embodiment, the width of the first sidewall spacer 40 is 3 nm to 5 nm, and the width of the second sidewall spacer 50 is 3 nm to 5 nm. The heights of the first sidewall spacer 40 and the second sidewall spacer 50 are not limited.

[0102] In one embodiment, the first sidewall spacer 40 is located below the second sidewall spacer 50 , that is, the first sidewall spacer 40 and the second sidewall spacer 50 form a large-sized barrier in the height direction, which can increase the area for blocking diffusion.

[0103] The top end of the first sidewall spacer 40 may be flush with the bottom end of the second sidewall spacer 50 , or the top end of the first sidewall spacer 40 may be located below the bottom end of the second sidewall spacer 50 .

[0104] In one embodiment, the bottom end of the first sidewall spacer 40 is higher than the bottom end of the first work function layer 22, that is, the first sidewall spacer 40 covers a portion of the first sidewall of the first work function layer 22, thereby leaving the portion of the first work function layer 22 adjacent to the first dielectric layer 21 uncovered. Specifically, the first sidewall spacer 40 covers the barrier layer 78 of the first work function layer 22, but may not cover the second transition metal layer 77 of the first work function layer 22.

[0105] In one embodiment, the top of the first sidewall spacer 40 is higher than the top of the first work function layer 22 to cover the sidewall of the first conductive layer 23 , that is, a portion of the first sidewall spacer 40 may cover the polysilicon layer 79 of the first conductive layer 23 .

[0106] In one embodiment, the bottom end of the second sidewall isolation layer 50 is higher than the bottom end of the second work function layer 32, that is, the second sidewall isolation layer 50 covers a portion of the second side wall of the second work function layer 32, so that the portion of the second work function layer 32 close to the second dielectric layer 31 is not covered by the second sidewall isolation layer 50.

[0107] In one embodiment, the top of the second sidewall spacer 50 is lower than the top of the second work function layer 32 , that is, the portion of the second work function layer 32 close to the second conductive layer 33 is not covered by the second sidewall spacer 50 .

[0108] Specifically, the second sidewall spacer 50 covers a portion of the stop layer 72 , the first transition metal layer 73 , and the metal isolation layer 74 of the first work function layer 22 .

[0109] In one embodiment, neither the NMOS transistor 20 nor the PMOS transistor 30 covers the isolation structure 11 .

[0110] In one embodiment, at least one of the NMOS transistor 20 and the PMOS transistor 30 covers a portion of the isolation structure 11. Figure 1 As shown, the first dielectric layer 21 of the NMOS transistor 20 may directly cover the isolation structure 11 .

[0111] In one embodiment, Figure 1 As shown, the semiconductor structure further includes an isolation stack structure 60, which is located above the isolation structure 11 and between the NMOS transistor 20 and the PMOS transistor 30; wherein the first sidewall spacer 40 is located between the NMOS transistor 20 and the isolation stack structure 60, and / or the second sidewall spacer 50 is located between the PMOS transistor 30 and the isolation stack structure 60. The first sidewall spacer 40 and the second sidewall spacer 50 can not only prevent the metal elements in the first work function layer 22 and the second work function layer 32 from diffusing into each other, but also prevent the metal elements in the isolation stack structure 60 from diffusing into the NMOS transistor 20 and the PMOS transistor 30.

[0112] In one embodiment, Figure 1 As shown, the isolation stack structure 60 includes: a third dielectric layer 61, which is located on the isolation structure 11; a third work function layer 62, which is located on the third dielectric layer 61; and a third conductive layer 63, which is located on the third work function layer 62. The first sidewall spacer 40 covers the sidewalls of the third work function layer 62, and the second sidewall spacer 50 covers the sidewalls of the third work function layer 62. During the fabrication of semiconductor structures, metal elements within the work function layers are most likely to diffuse. Therefore, in this embodiment, the first sidewall spacer 40 is sandwiched between the first work function layer 22 and the third work function layer 62, and the second sidewall spacer 50 is sandwiched between the second work function layer 32 and the third work function layer 62, which can effectively prevent metal diffusion.

[0113] The third dielectric layer 61 may be a single layer or a multi-layer structure. In this embodiment, the third dielectric layer 61 may include a high-K dielectric layer 71 .

[0114] The third work function layer 62 can be a single layer or a multilayer structure. The third work function layer 62 can include scandium (Sc), yttrium (Y), actinium (Ac), hafnium (Hf), titanium (Ti), zirconium (Zr), tantalum (Ta), Al (aluminum), lanthanum (La), lanthanides, and actinides. In this embodiment, the third work function layer 62 can include a cutoff layer 72, a first transition metal layer 73, a metal isolation layer 74, a second transition metal layer 77, and a barrier layer 78 stacked in sequence.

[0115] The third conductive layer 63 may be a single layer or a multi-layer structure. In this embodiment, the third conductive layer 63 may include a polysilicon layer 79 and a metal layer 80 stacked in sequence.

[0116] In one embodiment, a bottom end of the first sidewall spacer 40 is higher than a bottom end of the third work function layer 62 , and a top end of the first sidewall spacer 40 is lower than a top end of the third work function layer 62 .

[0117] In one embodiment, the bottom of the second sidewall spacer 50 is higher than the bottom of the third work function layer 62 , and the top of the second sidewall spacer 50 is higher than the top of the third work function layer 62 to cover the sidewall of the third conductive layer 63 .

[0118] Specifically, the first sidewall spacer 40 and the second sidewall spacer 50 respectively cover two opposite sidewalls of the third work function layer 62, and the first sidewall spacer 40 and the second sidewall spacer 50 are arranged in sequence in the vertical direction, thereby forming a relatively large coverage area in the vertical direction. The first sidewall spacer 40 can cover a portion of the cutoff layer 72, the first transition metal layer 73, and the metal isolation layer 74 of the third work function layer 62. The second sidewall spacer 50 can cover the second transition metal layer 77, the barrier layer 78, and a portion of the polysilicon layer 79 of the third work function layer 62. The first sidewall spacer 40 and the second sidewall spacer 50 block the first transition metal layer 73 and the second transition metal layer 77 of the third work function layer 62 from diffusing into the NMOS transistor 20 and the PMOS transistor 30, allowing them to diffuse preferentially into the isolation structure 11.

[0119] In one embodiment, the NMOS transistor 20 and the PMOS transistor 30 are both connected to the isolation stack structure 60 , thereby reducing the manufacturing process so that the NMOS transistor 20 , the PMOS transistor 30 and the isolation stack structure 60 can be formed simultaneously.

[0120] In one embodiment, substrate 10 has a stepped structure, i.e., the upper surface of substrate 10 has a height difference. In this embodiment, the first upper surface corresponding to first active region 12 is lower than the second upper surface corresponding to second active region 13. First dielectric layer 21 is located on the first upper surface, and second dielectric layer 31 is located on the second upper surface. It should be noted that portions of first dielectric layer 21 and second dielectric layer 31 may be located within substrate 10.

[0121] In one embodiment, the substrate 10 corresponding to the second active region 13 includes a SiGe layer 14, and the SiGe layer 14 forms the second upper surface. The NMOS transistor 20 uses Si as a channel, and the isolation stack structure 60 uses SiGe as a channel.

[0122] Considering that the substrate 10 has a stepped structure, the top of the second dielectric layer 31 is higher than the top of the first dielectric layer 21 .

[0123] In one embodiment, the upper surface of the substrate 10 may be a plane. In this case, the height of the first dielectric layer 21 may be lower than the height of the second dielectric layer 31 , thereby forming a stair-like structure between the NMOS transistor 20 and the PMOS transistor 30 .

[0124] In one embodiment, the upper surface of the substrate 10 can be a plane. In this case, the height of the first dielectric layer 21 can be equal to the height of the second dielectric layer 31, and the height of the first work function layer 22 is lower than the height of the second work function layer 32, thereby forming a stepped structure of the NMOS transistor 20 and the PMOS transistor 30.

[0125] In one embodiment, the upper surface of the substrate 10 can be a plane. In this case, the height of the first dielectric layer 21 can be equal to the height of the second dielectric layer 31, the height of the first work function layer 22 can be equal to the height of the second work function layer 32, and the height of the first conductive layer 23 is lower than the height of the second conductive layer 33, thereby forming a stepped structure of the NMOS transistor 20 and the PMOS transistor 30.

[0126] It should be noted that the NMOS transistor 20 and the PMOS transistor 30 form a stepped structure. In this embodiment, the substrate 10 is a stepped structure, and the height of the first dielectric layer 21 can be equal to the height of the second dielectric layer 31, the height of the first work function layer 22 is lower than the height of the second work function layer 32, and the height of the first conductive layer 23 is equal to the height of the second conductive layer 33.

[0127] In one embodiment, the NMOS transistor 20 , the isolation stack structure 60 , and the PMOS transistor 30 form a staircase structure. The substrate 10 may be a staircase structure, and the height of the second work function layer 32 may be equal to the height of the third work function layer 62 .

[0128] An embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure, please refer to Figure 2 ,include:

[0129] S101, providing a substrate 10, wherein an isolation structure 11 is formed in the substrate 10 to isolate a first active region 12 and a second active region 13;

[0130] S103, forming a dielectric layer, wherein the dielectric layer above the first active region 12 serves as the first dielectric layer 21, and the dielectric layer above the second active region 13 serves as the second dielectric layer 31, and forming a first initial work function layer on the second dielectric layer 31;

[0131] S105, forming a first sidewall spacer 40 on a side of the first dielectric layer 21 close to the second dielectric layer 31, and / or forming a second sidewall spacer 50 on a sidewall of the first initial work function layer close to the first dielectric layer 21;

[0132] S107 , forming a second initial work function layer, wherein the second initial work function layer of the first dielectric layer 21 serves as the first work function layer 22 , and the first initial work function layer and the second initial work function layer on the first initial work function layer serve as the second work function layer 32 ;

[0133] S109 , forming a conductive layer. The conductive layer on the first work function layer 22 serves as the first conductive layer 23 , and the conductive layer on the second work function layer 32 serves as the second conductive layer 33 .

[0134] A method for fabricating a semiconductor structure according to an embodiment of the present disclosure includes forming an NMOS transistor 20 and a PMOS transistor 30 on a substrate 10. The NMOS transistor 20 includes a first dielectric layer 21, a first work function layer 22, and a first conductive layer 23 formed in sequence, and the PMOS transistor 30 includes a second dielectric layer 31, a second work function layer 32, and a second conductive layer 33 formed in sequence. By forming a first sidewall spacer 40 on the side of the first work function layer 22 facing the second work function layer 32, and / or forming a second sidewall spacer 50 on the side of the second work function layer 32 facing the first work function layer 22, cross-diffusion of metal elements can be prevented, thereby preventing the difficulty in adjusting the threshold voltage of the semiconductor structure and improving the performance of the semiconductor structure.

[0135] It should be noted that the first sidewall isolation layer 40 is formed after the first dielectric layer 21 and before the first work function layer 22, and the second sidewall isolation layer 50 is formed in the process of forming the second work function layer 32, thereby ensuring that the first sidewall isolation layer 40 and the second sidewall isolation layer 50 can play a blocking role in the process of forming the first work function layer 22 and the second work function layer 32, thereby avoiding large-scale diffusion of metal and affecting the performance of the semiconductor structure.

[0136] Specifically, the formation of the second work function layer 32 includes the sequential formation of a first initial work function layer and a second initial work function layer, and the first sidewall isolation layer 40 and the second sidewall isolation layer 50 are formed after the formation of the first initial work function layer and before the formation of the second initial work function layer. Therefore, when forming the second initial work function layer, a large amount of diffusion of metal in the first initial work function layer can be avoided.

[0137] It should be noted that the dielectric layer formed on the substrate 10 serves as the first dielectric layer 21 of the NMOS transistor 20, the second dielectric layer 31 of the PMOS transistor 30, and the third dielectric layer 61 of the isolation stack structure 60. The second initial work function layer formed above the substrate 10 serves as the first work function layer 22 of the NMOS transistor 20, a portion of the second work function layer 32 of the PMOS transistor 30, and a portion of the third work function layer 62 of the isolation stack structure 60. The conductive layer formed above the substrate 10 serves as the first conductive layer 23 of the NMOS transistor 20, the second conductive layer 33 of the PMOS transistor 30, and the third conductive layer 63 of the isolation stack structure 60.

[0138] A selective epitaxial growth (SEPI) method is used to form a PMOS substrate 10 with SiGe as the channel and an NMOS substrate 10 with Si as the channel. Figure 3 As shown, a SiGe layer 14 is located above the second active region 13 .

[0139] In one embodiment, the first sidewall spacer 40 covers the sidewalls of the first work function layer 22 , thereby reliably blocking the diffusion of metal elements.

[0140] In some embodiments, a gap may be formed between the first sidewall isolation layer 40 and the sidewall of the first work function layer 22 . The gap may be filled with other materials, or an air gap may be directly formed. However, due to the presence of the first sidewall isolation layer 40 , a barrier to metal elements may still be formed.

[0141] In one embodiment, while the first initial work function layer is formed on the second dielectric layer 31, the first initial work function layer is also formed on the first dielectric layer 21, and before forming the first sidewall isolation layer 40 and / or the second sidewall isolation layer 50, the first initial work function layer on the first dielectric layer 21 is removed, so that the thickness of the subsequently formed first work function layer 22 is less than the thickness of the second work function layer 32.

[0142] It should be noted that when forming the first initial work function layer, the first initial work function layer can cover the entire area above the substrate 10, but the portion of the first initial work function layer covering the first active area 12 and part of the isolation structure 11 needs to be removed.

[0143] In one embodiment, the first sidewall spacer 40 and the second sidewall spacer 50 are formed in the same process step, thereby improving the manufacturing efficiency of the semiconductor structure and ensuring the stability of the structure formation.

[0144] In one embodiment, forming the first sidewall spacer 40 and the second sidewall spacer 50 includes: forming an initial spacer 76 on the first dielectric layer 21 and the first initial work function layer; partially etching the initial spacer 76 to expose a portion of the first dielectric layer 21 and the upper surface of the first initial work function layer to form the first sidewall spacer 40 and the second sidewall spacer 50, that is, the first sidewall spacer 40 is formed on a small section of the first dielectric layer 21, and the sidewall of the first initial work function layer is covered with the second sidewall spacer 50, thereby forming a barrier to metal elements.

[0145] In one embodiment, the first initial work function layer includes a first layer segment and a second layer segment, the first layer segment is located above the isolation structure 11, and the second layer segment is located on the second dielectric layer 31, the first layer segment and the second layer segment form a stepped structure so that the initial isolation layer 76 is a stepped structure, and after partially etching the initial isolation layer 76, the first sidewall isolation layer 40 and the second sidewall isolation layer 50 are formed to cover the sidewalls of the first layer segment and the sidewalls of the second layer segment respectively.

[0146] In one embodiment, forming the first sidewall spacer 40 and the second sidewall spacer 50 includes:

[0147] An interface layer 70 is formed on the substrate 10, such as Figure 4 As shown, the interface layer 70 now covers the first active region 12 and the SiGe layer 14. Specifically, high temperature thermal oxidation is performed at 900°C to 1000°C with 3slm to 5slm of pure O2 introduced, and the interface layer 70 with a thickness of 0.8 Å to 1 nm is in situ formed within 10s to 15s.

[0148] A high-K dielectric layer 71 is formed on the interface layer 70, as shown in FIG. Figure 5 As shown, at this time, the high-K dielectric layer 71 covers the interface layer 70 and the isolation structure 11. Specifically, HfO2 is grown as the high-K dielectric layer 71 by atomic layer deposition (ALD), and HfCl4 is introduced as a precursor and reacts with H2O at 200°C to 250°C and a working pressure of 1 to 2 Torr to generate HfO2.

[0149] At this time, the interface layer 70 and the high-K dielectric layer 71 serve as dielectric layers formed on the substrate 10. The interface layer 70 and the high-K dielectric layer 71 above the first active region 12 and the high-K dielectric layer 71 above a portion of the isolation structure 11 serve as the first dielectric layer 21. The interface layer 70 and the high-K dielectric layer 71 above the second active region 13 serve as the second dielectric layer 31. The high-K dielectric layer 71 above a portion of the isolation structure 11 serves as the third dielectric layer 61 of the isolation stack structure 60.

[0150] A stop layer 72 is formed on the high-K dielectric layer 71, a first transition metal layer 73 is formed on the stop layer 72, and a metal isolation layer 74 is formed on the first transition metal layer 73. Figure 6 Specifically, a TiN layer is grown on the high-K dielectric layer 71 by ALD, forming a cutoff layer 72. An Al layer, namely a first transition metal layer 73, is grown on the cutoff layer 72 by physical vapor deposition (PVD). Furthermore, a TiN layer, namely a metal isolation layer 74, is formed on the first transition metal layer 73 by PVD.

[0151] At this time, a first initial work function layer is formed on both the first dielectric layer 21 and the second dielectric layer 31 , and the cutoff layer 72 , the first transition metal layer 73 and the metal isolation layer 74 serve as the first initial work function layer.

[0152] The metal isolation layer 74 and the first transition metal layer 73 located above the first active region 12, as well as the metal isolation layer 74 and the first transition metal layer 73 located above a portion of the isolation structure 11, are removed using the mask structure 75. Figure 7 As shown, the mask structure 75 covers the area where the second active region 13 and the area where part of the isolation structure 11 are located, and the metal isolation layer 74 and the first transition metal layer 73 not covered by the mask structure 75 are removed by photolithography and etching processes. The stop layer 72 under the first transition metal layer 73 serves as an etch stop layer (etch stop layer), forming the following. Figure 8 The structure shown.

[0153] At this time, the cutoff layer 72, the first transition metal layer 73 and the metal isolation layer 74 above the partial isolation structure 11 serve as the first layer segment of the first initial work function layer, and the cutoff layer 72, the first transition metal layer 73 and the metal isolation layer 74 above the second active area 13 serve as the second layer segment of the first initial work function layer.

[0154] An initial isolation layer 76 is formed on the stop layer 72 and the metal isolation layer 74, and the initial isolation layer 76 covers the sidewalls of the stop layer 72, the first transition metal layer 73 and the metal isolation layer 74. Figure 9 Specifically, the initial isolation layer 76 is grown by ALD.

[0155] The initial isolation layer 76 is partially etched to expose the stop layer 72 and the metal isolation layer 74. The initial isolation layer 76 covering the sidewalls of the stop layer 72, the first transition metal layer 73, and the metal isolation layer 74 above the isolation structure 11 serves as the first sidewall isolation layer 40. The initial isolation layer 76 covering the sidewalls of the stop layer 72, the first transition metal layer 73, and the metal isolation layer 74 above the second active region 13 serves as the second sidewall isolation layer 50. Figure 10 Specifically, dry etching is used to perform etching, and CF4, C2H6 and Ar are introduced. Under the action of fluorine radicals, the initial isolation layer 76 is reacted to generate SiF4, which is then removed in a vacuum environment.

[0156] In one embodiment, forming an NMOS transistor 20 and a PMOS transistor 30 on a substrate 10 includes: after forming a first sidewall spacer 40 and a second sidewall spacer 50, removing the exposed stop layer 72, and sequentially forming a second transition metal layer 77, a barrier layer 78, a polysilicon layer 79, and a metal layer 80 on the high-K dielectric layer 71 and the metal isolation layer 74. Specifically, a wet etch method is used to remove the remaining stop layer 72, and the second transition metal layer 77 and the barrier layer 78 are formed in this manner. Figure 11 As shown, the formation Figure 12 The polysilicon layer 79 shown, and finally formed as shown Figure 13 The metal layer 80 shown, the second transition metal layer 77 and the barrier layer 78 serve as a second initial work function layer, and the polysilicon layer 79 and the metal layer 80 serve as conductive layers formed above the substrate 10.

[0157] The second transition metal layer 77 and the barrier layer 78 above the first active region 12 and a portion of the isolation structure 11 serve as the first work function layer 22 . The polysilicon layer 79 and the metal layer 80 above the first active region 12 and a portion of the isolation structure 11 serve as the first conductive layer 23 .

[0158] The second transition metal layer 77 and the barrier layer 78 above the second active area 13 serve as a second initial work function layer, that is, the cutoff layer 72, the first transition metal layer 73, the metal isolation layer 74, the second transition metal layer 77, and the barrier layer 78 above the second active area 13 serve as the second work function layer 32, and the polysilicon layer 79 and the metal layer 80 above the second active area 13 serve as the second conductive layer 33. The second initial work function layer and the first work function layer 22 include the same structural layers.

[0159] The cutoff layer 72, the first transition metal layer 73, the metal isolation layer 74, the second transition metal layer 77 and the barrier layer 78 above the partial isolation structure 11 serve as the third work function layer 62 of the isolation stack structure 60, and the polysilicon layer 79 and the metal layer 80 above the partial isolation structure 11 serve as the third conductive layer 63 of the isolation stack structure 60.

[0160] It should be noted that the materials of each structural layer appearing in the method for manufacturing the semiconductor structure can refer to the above-mentioned semiconductor structure, and will not be described in detail here.

[0161] In one embodiment, the method for manufacturing the semiconductor structure further includes removing the isolation stack structure 60 to form an independent NMOS transistor 20 and a PMOS transistor 30 , and completely exposing the isolation structure 11 .

[0162] In one embodiment, a method for fabricating a semiconductor structure is used to form the aforementioned semiconductor structure. The disclosed semiconductor structure, by employing an ALD oxide spacer solution (i.e., forming a first sidewall spacer 40 and a second sidewall spacer 50), can prevent cross-diffusion of a work function metal layer of the semiconductor structure, thereby improving the work function adjustment capability of the semiconductor structure.

[0163] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and example embodiments are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

[0164] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A semiconductor structure, characterized in that comprising a substrate and an NMOS transistor and a PMOS transistor located on the substrate; The NMOS transistor includes: a first dielectric layer, the first dielectric layer being located on the substrate; a first work function layer, the first work function layer being located on the first dielectric layer; a first conductive layer, wherein the first conductive layer is located on the first work function layer; The PMOS transistor includes: a second dielectric layer, the second dielectric layer being located on the substrate; a second work function layer, the second work function layer being located on the second dielectric layer; a second conductive layer, the second conductive layer being located on the second work function layer; A first sidewall isolation layer is provided on the side of the first work function layer facing the second work function layer, a second sidewall isolation layer is provided on the side of the second work function layer facing the first work function layer, and the first sidewall isolation layer is located below the second sidewall isolation layer.

2. The semiconductor structure according to claim 1, wherein: The first sidewall spacer is spaced apart from the second sidewall spacer.

3. The semiconductor structure according to claim 1, wherein: The bottom end of the first sidewall spacer layer is higher than the bottom end of the first work function layer; and / or, The top of the first sidewall spacer layer is higher than the top of the first work function layer to cover the sidewall of the first conductive layer; and / or, a bottom end of the second sidewall spacer layer is higher than a bottom end of the second work function layer; and / or, A top of the second sidewall spacer layer is lower than a top of the second work function layer.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that An isolation structure is formed in the substrate to isolate a first active area and a second active area for the NMOS transistor and the PMOS transistor respectively in the substrate; At least one of the NMOS transistor and the PMOS transistor covers a portion of the isolation structure.

5. The semiconductor structure according to claim 4, wherein: The semiconductor structure further comprises: an isolation stack structure, the isolation stack structure being located above the isolation structure and between the NMOS transistor and the PMOS transistor; The first sidewall spacer is located between the NMOS transistor and the isolation stack structure, and / or the second sidewall spacer is located between the PMOS transistor and the isolation stack structure.

6. The semiconductor structure according to claim 5, wherein: The isolated stacking structure comprises: a third dielectric layer, the third dielectric layer being located on the isolation structure; a third work function layer, the third work function layer being located on the third dielectric layer; a third conductive layer, the third conductive layer being located on the third work function layer; The first sidewall spacer layer covers the sidewall of the third work function layer, and the second sidewall spacer layer covers the sidewall of the third work function layer.

7. The semiconductor structure according to claim 6, wherein: The bottom end of the first sidewall spacer layer is higher than the bottom end of the third work function layer, and the top end of the first sidewall spacer layer is lower than the top end of the third work function layer; and / or, The bottom end of the second sidewall spacer is higher than the bottom end of the third work function layer, and the top end of the second sidewall spacer is higher than the top end of the third work function layer to cover the sidewall of the third conductive layer.

8. The semiconductor structure according to claim 5, wherein: The substrate has a stepped structure, so that the top of the second dielectric layer is higher than the top of the first dielectric layer; and / or, The NMOS transistor, the isolation stack structure, and the PMOS transistor form a stair-like structure.

9. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, wherein an isolation structure is formed in the substrate to isolate a first active area and a second active area; forming a dielectric layer, wherein the dielectric layer above the first active region serves as a first dielectric layer, the dielectric layer above the second active region serves as a second dielectric layer, and forming a first initial work function layer on the second dielectric layer; forming a first sidewall spacer on a side of the first dielectric layer close to the second dielectric layer, and / or forming a second sidewall spacer on a sidewall of the first initial work function layer close to the first dielectric layer, wherein the first sidewall spacer and the second sidewall spacer are formed in the same process step, and forming the first sidewall spacer and the second sidewall spacer comprises: forming an initial spacer on the first dielectric layer and the first initial work function layer; and partially etching the initial spacer to expose a portion of the first dielectric layer and an upper surface of the first initial work function layer, thereby forming the first sidewall spacer and the second sidewall spacer; forming a second initial work function layer, wherein the second initial work function layer on the first dielectric layer serves as a first work function layer, the first sidewall spacer covers the sidewalls of the first work function layer, and the first initial work function layer and the second initial work function layer on the first initial work function layer serve as a second work function layer; A conductive layer is formed, wherein the conductive layer on the first work function layer serves as a first conductive layer, and the conductive layer on the second work function layer serves as a second conductive layer.

10. The method for manufacturing a semiconductor structure according to claim 9, wherein: While forming the first initial work function layer on the second dielectric layer, the first initial work function layer is also formed on the first dielectric layer, and before forming the first sidewall isolation layer and / or the second sidewall isolation layer, the first initial work function layer on the first dielectric layer is removed.

11. The method for manufacturing a semiconductor structure according to claim 10, wherein: The first initial work function layer includes a first layer segment and a second layer segment, the first layer segment is located above the isolation structure, and the second layer segment is located on the second dielectric layer. The first layer segment and the second layer segment form a stepped structure so that the initial isolation layer is a stepped structure, and after partially etching the initial isolation layer, the first sidewall isolation layer and the second sidewall isolation layer are formed to cover the sidewalls of the first layer segment and the sidewalls of the second layer segment respectively.

12. A semiconductor structure, characterized in that comprising a substrate and an NMOS transistor and a PMOS transistor located on the substrate; The NMOS transistor includes: a first dielectric layer, the first dielectric layer being located on the substrate; a first work function layer, the first work function layer being located on the first dielectric layer; a first conductive layer, wherein the first conductive layer is located on the first work function layer; The PMOS transistor includes: a second dielectric layer, the second dielectric layer being located on the substrate; a second work function layer, the second work function layer being located on the second dielectric layer; a second conductive layer, the second conductive layer being located on the second work function layer; wherein a first sidewall spacer is provided on a side of the first work function layer facing the second work function layer, and / or a second sidewall spacer is provided on a side of the second work function layer facing the first work function layer; an isolation structure is formed in the substrate to isolate a first active area and a second active area for the NMOS transistor and the PMOS transistor respectively in the substrate; At least one of the NMOS transistor and the PMOS transistor covers a portion of the isolation structure.

13. The semiconductor structure according to claim 12, wherein: The semiconductor structure further comprises: an isolation stack structure, the isolation stack structure being located above the isolation structure and between the NMOS transistor and the PMOS transistor; The first sidewall spacer is located between the NMOS transistor and the isolation stack structure, and / or the second sidewall spacer is located between the PMOS transistor and the isolation stack structure.

14. The semiconductor structure according to claim 13, wherein: The isolated stacking structure comprises: a third dielectric layer, the third dielectric layer being located on the isolation structure; a third work function layer, the third work function layer being located on the third dielectric layer; a third conductive layer, the third conductive layer being located on the third work function layer; The first sidewall spacer layer covers the sidewall of the third work function layer, and the second sidewall spacer layer covers the sidewall of the third work function layer.

15. The semiconductor structure according to claim 14, wherein: The bottom end of the first sidewall spacer layer is higher than the bottom end of the third work function layer, and the top end of the first sidewall spacer layer is lower than the top end of the third work function layer; and / or, The bottom end of the second sidewall spacer is higher than the bottom end of the third work function layer, and the top end of the second sidewall spacer is higher than the top end of the third work function layer to cover the sidewall of the third conductive layer.

16. The semiconductor structure according to claim 13, wherein: The substrate has a stepped structure, so that the top of the second dielectric layer is higher than the top of the first dielectric layer; and / or, The NMOS transistor, the isolation stack structure, and the PMOS transistor form a stair-like structure.

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