Full vertical power device and manufacturing method thereof, and chip

Abstract

The application provides a full-vertical power device and a manufacturing method and a chip thereof, wherein the full-vertical power device comprises a substrate, a buffer layer, a gallium nitride high-doped N+ layer, a gallium nitride low-doped N- layer, a gallium nitride P-type substrate and a gallium nitride N-type active region which are sequentially arranged in a first direction on the substrate; the full-vertical power device is provided with two grooves and is respectively provided with ohmic contact metal and Schottky contact metal to realize ohmic contact and Schottky contact; meanwhile, a first P+ doped region and a second P+ doped region are added below the gate of the full-vertical MOSFET to respectively form a full-vertical MOSFET and a junction barrier diode, and the quasi-vertical MOSFET and the junction barrier diode are integrated in parallel; the P+ doped region improves the reverse voltage resistance of the junction barrier diode; meanwhile, the formed groove provides the full-vertical MOSFET with greater current capacity and smaller on-resistance.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a full vertical power device, a manufacturing method thereof, and a chip. Background Art

[0002] Semiconductor power devices are the core elements for efficient conversion, control, and regulation of electrical energy. Today, they are widely used in a wide range of applications, from traditional industrial control to personal computers, consumer electronics, smart cars, new energy systems, rail transit, smart grids, and more.

[0003] Among them, power devices based on wide-bandgap GaN (gallium nitride) materials have the characteristics of high reverse blocking voltage, low forward on-resistance, high operating frequency, and high efficiency. They can meet the power electronics system's requirements for semiconductor devices with higher power, higher frequency, smaller size, lower power consumption, and harsher working environment.

[0004] Traditional quasi-vertical MOSFETs integrated with SBDs (Schottky barrier diodes) have fast reverse recovery and low power consumption, but their SBD withstand voltage is low. In addition, they experience severe current congestion during forward conduction, significantly increasing on-resistance, especially in large-area devices. Summary of the Invention

[0005] The object of the present invention is to provide a fully vertical power device, aiming to solve the problems of low withstand voltage and severe current crowding effect during forward conduction of conventional quasi-vertical MOSFET integrated SBD.

[0006] A first aspect of an embodiment of the present invention provides a fully vertical power device, including:

[0007] A substrate, on which a buffer layer, a highly doped gallium nitride N+ layer, a lowly doped gallium nitride N- layer, a gallium nitride P-type substrate, and a gallium nitride N-type active region are sequentially stacked along a first direction;

[0008] a first P+ doping region and a second P+ doping region formed in the gallium nitride low-doped N-layer, wherein the first P+ doping region and the second P+ doping region are sequentially arranged along a second direction, and the first direction and the second direction intersect;

[0009] a first groove and a second groove arranged side by side along the second direction, the first groove and the second groove penetrating the gallium nitride N-type active region and the gallium nitride P-type substrate and extending to the gallium nitride low-doped N-layer;

[0010] an insulating layer disposed on surfaces of the first groove and the second groove, respectively, wherein the insulating layer located at the bottom of the first groove contacts the first P+ doped region;

[0011] an ohmic contact metal and a Schottky contact metal disposed on the surface of the insulating layer, wherein the ohmic contact metal is located in the first groove, and the Schottky contact metal is located in the second groove, wherein a portion of the Schottky contact metal located at the bottom of the groove is in contact with the gallium nitride low-doped N-layer, the first P+ doped region, and the second P+ doped region;

[0012] a trench, wherein the trench penetrates the substrate and the buffer layer and extends to the gallium nitride highly doped N+ layer;

[0013] A drain electrode is provided on the surface of the trench, and two source electrodes are respectively provided on the surface of the gallium nitride N-type active region, wherein the two source electrodes are provided on both sides of the gallium nitride N-type active region along the second direction.

[0014] Optionally, along the second direction, a size of the first P+ doping region is larger than a size of the second P+ doping region.

[0015] Optionally, the first P+ doping region and the second P+ doping region are formed by ion implantation or diffusion.

[0016] Optionally, the insulating layer is a SiO2 insulating layer formed by deposition.

[0017] Optionally, the ohmic contact metal is a Cr / Au double-layer metal film, and the Schottky contact metal is a Ni / Au double-layer metal film.

[0018] Optionally, the first groove and the second groove are V-shaped grooves.

[0019] A second aspect of an embodiment of the present invention provides a method for manufacturing a full vertical power device, comprising:

[0020] A buffer layer, a highly doped gallium nitride N+ layer, and a lowly doped gallium nitride N- layer are sequentially grown on a substrate along a first direction, and a first P+ doped region and a second P+ doped region are formed in the lowly doped gallium nitride N- layer, wherein the first P+ doped region and the second P+ doped region are sequentially arranged along a second direction, and the first direction and the second direction intersect;

[0021] Growing a gallium nitride P-type substrate and a gallium nitride N-type active region in sequence along the first direction on the gallium nitride low-doped N-layer;

[0022] Etching a first groove and a second groove side by side along the second direction, wherein the first groove and the second groove penetrate the gallium nitride N-type active area and the gallium nitride P-type substrate and extend to the gallium nitride low-doped N-layer;

[0023] Depositing an insulating layer on the surfaces of the first groove and the second groove, wherein the insulating layer at the bottom of the first groove contacts the first P+ doped region;

[0024] forming an ohmic contact metal and a Schottky contact metal on the surface of the insulating layer, wherein the ohmic contact metal is located in the first groove, and the Schottky contact metal is located in the second groove, wherein a portion of the Schottky contact metal located at the bottom of the groove is in contact with the gallium nitride low-doped N-layer, the first P+ doped region, and the second P+ doped region;

[0025] Etching a trench at the bottom of the full vertical power device, wherein the trench penetrates the substrate and the buffer layer and extends to the gallium nitride highly doped N+ layer;

[0026] A drain electrode is deposited on the surface of the trench, and two source electrodes are deposited on the surface of the gallium nitride N-type active region. The two source electrodes are arranged on both sides of the gallium nitride N-type active region along the second direction.

[0027] Optionally, a size of the first P+ doping region formed along the second direction is larger than a size of the second P+ doping region.

[0028] Optionally, the first P+ doping region and the second P+ doping region are formed by ion implantation or diffusion.

[0029] A third aspect of the embodiments of the present invention provides a chip including at least one full vertical power device as described above.

[0030] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: the above-mentioned full-vertical power device performs ohmic contact and Schottky contact by setting two grooves and setting ohmic contact metal and Schottky contact metal respectively. At the same time, a first P+ doping region and a second P+ doping region are added under the gate of the full-vertical MOSFET, respectively forming a full-vertical MOSFET and a junction barrier diode. The quasi-vertical MOSFET and the junction barrier diode are integrated in parallel, and the P+ doping region improves the reverse withstand voltage of the junction barrier diode. At the same time, by forming a groove, the full-vertical MOSFET is provided with a larger current capacity and a smaller on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A schematic diagram of the cross-sectional structure of a fully vertical power device provided in an embodiment of the present application;

[0032] Figure 2 Schematic diagram of the equivalent circuit of the full vertical power device provided in an embodiment of the present application;

[0033] Figure 3A schematic flow chart of a method for manufacturing a fully vertical power device provided in an embodiment of the present application;

[0034] Figure 4 for Figure 3 A schematic cross-sectional structure diagram of a full vertical power device corresponding to step S11 in the method for manufacturing the full vertical power device is shown;

[0035] Figure 5 for Figure 3 A schematic cross-sectional structure diagram of a full vertical power device corresponding to step S12 in the method for manufacturing the full vertical power device is shown;

[0036] Figure 6 for Figure 3 A schematic diagram of the cross-sectional structure of the full vertical power device corresponding to step S13 in the method for manufacturing the full vertical power device is shown;

[0037] Figure 7 for Figure 3 A schematic diagram of the cross-sectional structure of a full vertical power device corresponding to step S14 in the method for manufacturing the full vertical power device is shown;

[0038] Figure 8 for Figure 3 A schematic diagram of the cross-sectional structure of a full vertical power device corresponding to step S15 in the method for manufacturing the full vertical power device is shown;

[0039] Figure 9 for Figure 3 A schematic diagram of the cross-sectional structure of the full vertical power device corresponding to step S16 in the method for manufacturing the full vertical power device is shown;

[0040] Figure 10 for Figure 3 FIG. 1 is a schematic diagram of a cross-sectional structure of a full vertical power device corresponding to step S17 in a method for manufacturing a full vertical power device. DETAILED DESCRIPTION

[0041] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0042] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention.

[0043] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0044] A first aspect of an embodiment of the present invention provides a full vertical power device, such as Figure 1 As shown, Figure 1 This is a schematic diagram of the cross-sectional structure of a fully vertical power device provided in an embodiment of the present application. In this embodiment, the fully vertical power device includes a substrate 11, a buffer layer 12, a highly doped gallium nitride N+ layer 13, a low-doped gallium nitride N- layer 14, a gallium nitride P-type substrate 15, and a gallium nitride N-type active region 16 stacked in sequence on the substrate 11 along a first direction X, wherein the highly doped gallium nitride N+ layer 13 constitutes a drain region, the low-doped gallium nitride N- layer 14 constitutes a drift region, the highly doped gallium nitride N+ layer 13 is grown on the buffer layer 12, and the low-doped gallium nitride N- layer 14, the gallium nitride P-type substrate 15, and the gallium nitride N-type active region 16 are formed by epitaxial growth on the highly doped gallium nitride N+ layer 13.

[0045] The substrate 11 may be a crystalline silicon substrate 11. Alternatively, the substrate 11 may be formed of other semiconductor materials, such as silicon germanium. In addition, the substrate 11 may be a bulk substrate 11. The substrate 11 may be lightly doped with p-type impurities, such as boron or indium.

[0046] At the same time, in order to improve the reverse withstand voltage of the junction barrier diode, the first P+ doping region 21 and the second P+ doping region 22 are formed in the gallium nitride low-doped N-layer 14. The first P+ doping region 21 and the second P+ doping region 22 are arranged in sequence along the second direction Y. The first direction X and the second direction Y intersect. At the same time, in order to form a full vertical power device, the gallium nitride low-doped N-layer 14, the gallium nitride P-type substrate 15 and the gallium nitride N-type active region 16 are further etched by etching to form a first concave region arranged side by side along the second direction Y. The groove 31 and the second groove 32, the first groove 31 and the second groove 32 penetrate the gallium nitride N-type active area 16 and the gallium nitride P-type substrate 15 and extend to the gallium nitride low-doped N-layer 14, the first groove 31 and the second groove 32 can be set as vertical grooves, V-shaped grooves or grooves of other shapes, the specific shape is not limited, optionally, in order to simplify the manufacturing process, the first groove 31 and the second groove 32 are V-shaped grooves, the MOSFET channel is formed within the V-shaped groove, and the current flows along the path in the V shape in the plane of the V-shaped groove.

[0047] At the same time, an insulating layer 40 is also deposited on the surface of the first groove 31 and the second groove 32, wherein the insulating layer 40 is deposited on the bottom and sidewalls of the first groove 31, the insulating layer 40 located at the bottom of the first groove 31 is in contact with the first P+ doping region 21, the insulating layer 40 is deposited on the sidewalls of the second groove 32, and the insulating layer 40 is not deposited on the bottom of the second groove 32. Optionally, the insulating layer 40 is a SiO2 insulating layer 40 formed by deposition, and the silicon oxide (SiO2) insulating layer 40 is often used as an insulating layer 40 and forms an insulator.

[0048] In order to form a full vertical MOSFET and a junction barrier diode, an ohmic contact metal 51 and a Schottky contact metal 52 are further provided on the surface of the insulating layer 40 of the full vertical power device. The ohmic contact metal 51 is used for ohmic contact, and the Schottky contact metal 52 is used for Schottky contact. The ohmic contact metal is located in the first groove 31, and the Schottky contact metal is located in the second groove 32. Part of the Schottky contact metal 52 located at the bottom of the groove is in contact with the gallium nitride low-doped N-layer 14, the first P+ doped region 21 and the second P+ doped region 22. The gallium nitride N-type active region 16, the gallium nitride P-type substrate 15, the gallium nitride low-doped N-layer 14, the P+ doped region and the gallium nitride high-doped N+ layer 13 constitute a full vertical MOSFET, and the gallium nitride low-doped N-layer 14, the P+ doped region and the gallium nitride high-doped N+ layer 13 constitute a junction barrier diode.

[0049] like Figure 1 As shown by the dotted lines, the first P+ doped region 21 and the second P+ doped region 22 respectively cut off the leakage current generated by the full vertical MOSFET and the junction barrier diode, thereby improving the reverse withstand voltage of the diode, providing a larger current capacity and a smaller on-resistance.

[0050] Meanwhile, in order to form the full vertical MOSFET structure, a trench 60 is also provided at the bottom of the full vertical power device, the trench 60 penetrates through the substrate 11 and the buffer layer 12 and extends to the gallium nitride high-doped N+ layer 13, meanwhile, the surface of the trench 60 is used to lay the drain electrode 70, the two source electrodes 81 and 82 of the full vertical MOSFET structure are respectively arranged on the surface of the gallium nitride N-type active region 16, and the two source electrodes 81 and 82 are arranged on the two sides of the gallium nitride N-type active region 16 along the second direction Y, the ohmic contact metal 51, the drain electrode 61 and the source electrodes 81 and 82 respectively form the gate terminal, the drain terminal and the source terminal of the full vertical MOSFET, and input and output corresponding power signals and control signals, thereby forming Figure 2 the equivalent circuit as shown, wherein Q1 represents the full vertical MOSFET, and D1 represents the junction barrier diode.

[0051] By etching part of the substrate 11 and the gallium nitride high-doped N+ layer 13 at the drain electrode 70, the overall resistance can be reduced, and by adding the second P+ doped region 22 at the Schottky contact metal 52, the JEFT region can shield the Schottky barrier diode when reverse biased.

[0052] By monolithically integrating the junction barrier diode (JBS) with the full vertical MOSFET and adding the first P+ doped region 21 and the second P+ doped region 22 for drain current protection under the gate of the MOSFET, the reverse withstand voltage of the JBS is improved, providing greater current capacity and smaller on-resistance. Compared with the quasi-vertical power device, the full vertical design will accommodate more devices per unit area. Excellent electrical contact and mechanical stability are provided.

[0053] In order to simultaneously contact the Schottky contact metal 52 and ensure that the first P+ doped region 21 is located below the ohmic contact metal 51, optionally, as Figure 1 shown, along the second direction Y, the size of the first P+ doped region 21 is greater than the size of the second P+ doped region 22.

[0054] The first P+ doped region 21 and the second P+ doped region 22 can be formed by corresponding manufacturing processes, and optionally, the first P+ doped region 21 and the second P+ doped region 22 are formed by ion implantation or diffusion.

[0055] The insulating layer 40 is arranged in the two grooves respectively, and during manufacturing, each groove is deposited separately, that is, the mesa region between the first groove 31 and the second groove 32 of the gallium nitride N-type active region 16 is not provided with the insulating layer 40.

[0056] The ohmic contact metal 51 and the Schottky contact metal 52 can be optionally implemented using corresponding single-layer or multi-layer metal films. For example, a four-layer metal film of Cr / Au / Ni / Au is used to prepare the gallium nitride contact. Optionally, in order to simplify the process, the ohmic contact metal 51 is a double-layer metal film of Cr / Au, and the Schottky contact metal 52 is a double-layer metal film of Ni / Au.

[0057] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: the above-mentioned full-vertical power device performs ohmic contact and Schottky contact by setting two grooves and setting an ohmic contact metal 51 and a Schottky contact metal 52 respectively. At the same time, a first P+ doping region 21 and a second P+ doping region 22 are added under the gate of the full-vertical MOSFET to form an equivalent full-vertical MOSFET and a junction barrier diode respectively. The quasi-vertical MOSFET and the junction barrier diode are integrated in parallel, and the P+ doping region improves the reverse withstand voltage of the junction barrier diode. At the same time, by forming a groove 60, a larger current capacity and a smaller on-resistance are provided for the full-vertical MOSFET.

[0058] The second aspect of the embodiment of the present invention provides a method for manufacturing a full vertical power device, such as Figure 3 As shown, the production method includes the following steps:

[0059] S11, such as Figure 4 As shown, a buffer layer 12, a highly doped gallium nitride N+ layer 13, and a lowly doped gallium nitride N- layer 14 are sequentially grown on a substrate 11 along a first direction X. A first P+ doped region 21 and a second P+ doped region 22 are formed within the lowly doped gallium nitride N- layer 14. The first P+ doped region 21 and the second P+ doped region 22 are sequentially arranged along a second direction Y, with the first direction X and the second direction Y intersecting. The substrate 11 may be a crystalline silicon substrate 11. Alternatively, the substrate 11 may be formed of other semiconductor materials, such as silicon germanium. Furthermore, the substrate 11 may be a bulk substrate 11. The substrate 11 may be lightly doped with p-type impurities, such as boron or indium.

[0060] At the same time, the first P+ doping region 21 and the second P+ doping region 22 formed in the GaN low-doped N-layer 14 improve the reverse withstand voltage of the junction barrier diode.

[0061] S12, such as Figure 5 As shown, a GaN P-type substrate 15 and a GaN N-type active region 16 are sequentially grown along a first direction X on the GaN low-doped N-layer 14, wherein the GaN high-doped N+ layer 13 constitutes a drain region, the GaN low-doped N-layer 14 constitutes a drift region, the GaN high-doped N+ layer 13 is grown on the buffer layer 12, and the GaN low-doped N-layer 14, the GaN P-type substrate 15 and the GaN N-type active region 16 are epitaxially grown on the GaN high-doped N+ layer 13.

[0062] S13, such as Figure 6 As shown, in order to form a fully vertical power device, the gallium nitride low-doped N-layer 14, the gallium nitride P-type substrate 15 and the gallium nitride N-type active area 16 are further etched by etching to form a first groove 31 and a second groove 32 etched side by side along the second direction Y. The first groove 31 and the second groove 32 penetrate the gallium nitride N-type active area 16 and the gallium nitride P-type substrate 15 and extend to the gallium nitride low-doped N-layer 14. The first groove 31 and the second groove 32 can be set as vertical grooves, V-shaped grooves or grooves of other shapes. The specific shape is not limited. Optionally, in order to simplify the manufacturing process, the first groove 31 and the second groove 32 are V-shaped grooves. The MOSFET channel is formed within the V-shaped groove, and the current flows within the plane of the V-shaped groove along the path in the V shape.

[0063] S14, such as Figure 7 As shown, an insulating layer 40 is deposited on the surfaces of the first groove 31 and the second groove 32, wherein the insulating layer 40 located at the bottom of the first groove 31 is in contact with the first P+ doping region 21, wherein the insulating layer 40 is deposited on the bottom and sidewalls of the first groove 31, the insulating layer 40 located at the bottom of the first groove 31 is in contact with the first P+ doping region 21, the insulating layer 40 is deposited on the sidewalls of the second groove 32, and the insulating layer 40 is not deposited on the bottom of the second groove 32. Optionally, the insulating layer 40 is a SiO2 insulating layer 40 formed by deposition, and the silicon oxide (SiO2) insulating layer 40 is often used as an insulating layer 40 and forms an insulator.

[0064] S15, such as Figure 8 As shown, in order to form a full vertical MOSFET and a junction barrier diode, an ohmic contact metal 51 and a Schottky contact metal 52 are formed on the surface of the insulating layer 40. The ohmic contact metal 51 is used for ohmic contact, and the Schottky contact metal 52 is used for Schottky contact. The ohmic contact metal 51 is located in the first groove 31, and the Schottky contact metal is located in the second groove 32. Part of the Schottky contact metal 52 located at the bottom of the groove is in contact with the gallium nitride low-doped N-layer 14, the first P+ doped region 21, and the second P+ doped region 22. The gallium nitride N-type active region 16, the gallium nitride P-type substrate 15, the gallium nitride low-doped N-layer 14, the P+ doped region, and the gallium nitride high-doped N+ layer 13 constitute a full vertical MOSFET, and the gallium nitride low-doped N-layer 14, the P+ doped region, and the gallium nitride high-doped N+ layer 13 constitute a junction barrier diode.

[0065] like Figure 1 As shown by the dotted lines, the first P+ doped region 21 and the second P+ doped region 22 respectively cut off the leakage current generated by the full vertical MOSFET and the junction barrier diode, thereby improving the reverse withstand voltage of the diode, providing a larger current capacity and a smaller on-resistance.

[0066] S16, such as Figure 9 As shown, in order to form a fully vertical MOSFET structure, a trench 60 is etched at the bottom of the fully vertical power device. The trench 60 penetrates the substrate 11 and the buffer layer 12 and extends to the gallium nitride highly doped N+ layer 13. By etching away a portion of the substrate 11 and the gallium nitride highly doped N+ layer 13 at the drain 70, the overall resistance can be reduced. In addition, adding a second P+ doped region 22 at the Schottky contact metal 52 can form a JEFT region to shield the Schottky barrier diode when reverse biased.

[0067] S17, such as Figure 10 As shown, a drain electrode is deposited on the surface of the trench 60, and two source electrodes 81 and 82 are deposited on the surface of the gallium nitride N-type active region 16. The two source electrodes 81 and 82 are arranged on both sides of the gallium nitride N-type active region 16 along the second direction Y. The ohmic contact metal 51, the drain electrode 61, and the source electrodes 81 and 82 71 and 72 respectively constitute the gate terminal, drain terminal, and source terminal of the full vertical MOSFET, and input and output corresponding power supply signals and control signals, thereby forming Figure 2 The equivalent circuit shown in FIG, where Q1 represents a full vertical MOSFET and D1 represents a junction barrier diode.

[0068] By monolithically integrating a junction barrier diode (JBS) with a fully vertical MOSFET and adding a first P+ doped region 21 and a second P+ doped region 22 for leakage current protection under the MOSFET gate, the JBS's reverse withstand voltage is increased, providing greater current capacity and lower on-resistance. Compared to quasi-vertical power devices, the fully vertical design accommodates more devices per unit area and provides excellent electrical contact and mechanical stability.

[0069] In order to simultaneously contact the Schottky contact metal 52 and ensure that the first P+ doped region 21 is located below the ohmic contact metal 51, optionally, as Figure 1 As shown, along the second direction Y, the size of the first P+ doping region 21 is larger than the size of the second P+ doping region 22 .

[0070] The first P+ doping region 21 and the second P+ doping region 22 may be formed by corresponding manufacturing processes. Optionally, the first P+ doping region 21 and the second P+ doping region 22 may be formed by ion implantation or diffusion.

[0071] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0072] The insulating layer 40 is disposed in the two grooves respectively. During fabrication, each groove is deposited separately. That is, no insulating layer 40 is disposed in the mesa region of the GaN N-type active region 16 between the first groove 31 and the second groove 32 .

[0073] The ohmic contact metal 51 and the Schottky contact metal 52 can be optionally implemented using corresponding single-layer or multi-layer metal films. For example, a four-layer metal film of Cr / Au / Ni / Au is used to prepare the gallium nitride contact. Optionally, in order to simplify the process, the ohmic contact metal 51 is a double-layer metal film of Cr / Au, and the Schottky contact metal 52 is a double-layer metal film of Ni / Au.

[0074] The present invention also proposes a chip, which includes a full vertical power device. The specific structure of the full vertical power device refers to the above embodiment. Since this chip adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be repeated here.

[0075] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the scope of protection of the present invention.

Claims

1. A fully vertical power device, characterized in that: include: A substrate, on which a buffer layer, a highly doped gallium nitride N+ layer, a lowly doped gallium nitride N- layer, a gallium nitride P-type substrate, and a gallium nitride N-type active region are sequentially stacked along a first direction; a first P+ doping region and a second P+ doping region formed in the gallium nitride low-doped N-layer, wherein the first P+ doping region and the second P+ doping region are sequentially arranged along a second direction, and the first direction and the second direction intersect; a first groove and a second groove arranged side by side along the second direction, the first groove and the second groove penetrating the gallium nitride N-type active region and the gallium nitride P-type substrate and extending to the gallium nitride low-doped N-layer; an insulating layer disposed on surfaces of the first groove and the second groove, respectively, wherein the insulating layer located at the bottom of the first groove contacts the first P+ doped region; an ohmic contact metal and a Schottky contact metal disposed on the surface of the insulating layer, wherein the ohmic contact metal is located in the first groove, and the Schottky contact metal is located in the second groove, wherein a portion of the Schottky contact metal located at the bottom of the groove is in contact with the gallium nitride low-doped N-layer, the first P+ doped region, and the second P+ doped region; a trench, wherein the trench penetrates the substrate and the buffer layer and extends to the gallium nitride highly doped N+ layer; A drain electrode is provided on the surface of the trench, and two source electrodes are respectively provided on the surface of the gallium nitride N-type active region, wherein the two source electrodes are provided on both sides of the gallium nitride N-type active region along the second direction.

2. The full vertical power device according to claim 1, wherein: Along the second direction, a size of the first P+ doping region is larger than a size of the second P+ doping region.

3. The full vertical power device according to claim 2, wherein: The first P+ doping region and the second P+ doping region are formed by ion implantation or diffusion.

4. The full vertical power device according to claim 1, wherein: The insulating layer is a SiO2 insulating layer formed by deposition.

5. The full vertical power device according to claim 1, wherein: The ohmic contact metal is a Cr / Au double-layer metal film, and the Schottky contact metal is a Ni / Au double-layer metal film.

6. The full vertical power device according to claim 1, wherein: The first groove and the second groove are V-shaped grooves.

7. A method for manufacturing a fully vertical power device, characterized in that: include: A buffer layer, a highly doped gallium nitride N+ layer, and a lowly doped gallium nitride N- layer are sequentially grown on a substrate along a first direction, and a first P+ doped region and a second P+ doped region are formed in the lowly doped gallium nitride N- layer, wherein the first P+ doped region and the second P+ doped region are sequentially arranged along a second direction, and the first direction and the second direction intersect; Growing a gallium nitride P-type substrate and a gallium nitride N-type active region in sequence along the first direction on the gallium nitride low-doped N-layer; Etching a first groove and a second groove side by side along the second direction, wherein the first groove and the second groove penetrate the gallium nitride N-type active area and the gallium nitride P-type substrate and extend to the gallium nitride low-doped N-layer; Depositing an insulating layer on the surfaces of the first groove and the second groove, wherein the insulating layer at the bottom of the first groove contacts the first P+ doped region; forming an ohmic contact metal and a Schottky contact metal on the surface of the insulating layer, wherein the ohmic contact metal is located in the first groove, and the Schottky contact metal is located in the second groove, wherein a portion of the Schottky contact metal located at the bottom of the groove is in contact with the gallium nitride low-doped N-layer, the first P+ doped region, and the second P+ doped region; Etching a trench at the bottom of the full vertical power device, wherein the trench penetrates the substrate and the buffer layer and extends to the gallium nitride highly doped N+ layer; A drain electrode is deposited on the surface of the trench, and two source electrodes are deposited on the surface of the gallium nitride N-type active region. The two source electrodes are arranged on both sides of the gallium nitride N-type active region along the second direction.

8. The method for manufacturing a full vertical power device according to claim 7, wherein: The size of the first P+ doping region formed along the second direction is larger than the size of the second P+ doping region.

9. The method for manufacturing a full vertical power device according to claim 8, wherein: The first P+ doping region and the second P+ doping region are formed by ion implantation or diffusion.

10. A chip, characterized in that: The device comprises at least one full vertical power device according to any one of claims 1 to 6.

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