Semiconductor structure and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor structure and a method for manufacturing the same. The method for manufacturing the semiconductor structure comprises: providing a substrate, a plurality of parallel and spaced-apart bit lines being formed on the substrate; forming a contact plug between adjacent bit lines, and forming a metal silicide layer on the upper surface of the contact plug; the upper surface of the contact plug being lower than the upper surface of the bit lines, and a gap being formed between the metal silicide layer and the bit lines; forming a contact pad on the metal silicide layer, the contact pad and the metal silicide layer and the contact plug jointly forming a storage node contact structure; the contact pad extending partially into the gap, and the length of the contact pad extending into the gap being less than the height of the gap, so that an air gap is reserved between the metal silicide layer and the bit lines. The present disclosure can reduce the contact resistance, reduce the parasitic capacitance, reduce the risk of leakage, improve the electrical performance of the semiconductor structure, and improve the yield of the semiconductor structure.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor integrated circuit manufacturing, and particularly relates to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory in electronic devices such as computers, which is composed of a plurality of memory cells. Each memory cell includes a storage capacitor and a transistor electrically connected to the storage capacitor. The transistor includes a gate, a source region, and a drain region. The gate of the transistor is used to be electrically connected to a word line. The source region of the transistor is used to form a bit line contact region to be electrically connected to a bit line through a bit line contact structure. The drain region of the transistor is used to form a storage node contact region to be electrically connected to the storage capacitor through a storage node contact structure.

[0003] However, as the size of the DRAM becomes smaller and smaller, the size of the storage node contact structure is also reduced accordingly, which makes it easy to generate a large contact resistance between the transistor and the storage capacitor, resulting in a slow speed of the DRAM, and even causing the device (e.g., a chip) in which the DRAM is located to fail. Therefore, how to reduce the contact resistance between the transistor and the storage capacitor and improve the performance of the DRAM device has become a technical problem to be solved in the current advanced semiconductor process. SUMMARY

[0004] Based on this, the embodiments of the present disclosure provide a semiconductor structure and a preparation method thereof, which can reduce the contact resistance inside the semiconductor structure, effectively reduce the risk of leakage of the storage node contact structure, and reduce the parasitic capacitance between the storage node contact structure and the bit line. Thus, the electrical performance of the semiconductor structure is improved to improve the yield of the semiconductor structure.

[0005] To achieve the above-mentioned purpose, in one aspect, some embodiments of the present disclosure provide a preparation method of a semiconductor structure, which includes the following steps.

[0006] A substrate is provided, and a plurality of parallel and spaced bit lines are formed on the substrate.

[0007] A contact plug is formed between the adjacent bit lines, and a metal silicide layer is formed on the upper surface of the contact plug. The upper surface of the contact plug is lower than the upper surface of the bit line, and there is a gap between the metal silicide layer and the bit line.

[0008] A contact pad is formed on the metal silicide layer, and the contact pad, the metal silicide layer and the contact plug jointly form a storage node contact structure. The contact pad extends partially into the gap, and the length of the contact pad extending into the gap is less than the height of the gap, so that an air gap is reserved between the metal silicide layer and the bit line.

[0009] In another aspect, some embodiments of the present disclosure provide a semiconductor structure prepared by the preparation method as described in some embodiments above.

[0010] The semiconductor structure includes a substrate and a storage node contact structure. The substrate has a plurality of parallel and spaced bit lines formed thereon. The storage node contact structure includes a contact plug, a metal silicide layer and a contact pad. The contact plug is located between adjacent bit lines, and the upper surface of the contact plug is lower than the upper surface of the bit line. The metal silicide layer is located on the upper surface of the contact plug, and an air gap is reserved between the metal silicide layer and the bit line. The contact pad is located on the metal silicide layer and extends partially between the metal silicide layer and the bit line and above the air gap.

[0011] In one example, the semiconductor structure further includes a first dielectric layer and a second dielectric layer. The first dielectric layer is located on the surface of the bit line and between the bit line and the storage node contact structure. The second dielectric layer is located on the surface of the first dielectric layer and between the first dielectric layer and the storage node contact structure, and below the air gap.

[0012] In the semiconductor structure and the preparation method thereof provided by the embodiments of the present disclosure, a gap is reserved between the metal silicide layer and the bit line, and a part of the contact pad extends into the gap, so that the contact pad can have a larger contact area with the metal silicide layer, and an air gap is reserved between the metal silicide layer and the bit line. Thus, the contact resistance between the contact pad and the contact plug can be reduced, the risk of leakage of the storage node contact structure can be reduced by the air gap, and the parasitic capacitance between the storage node contact structure and the bit line can be reduced. In turn, the electrical performance of the semiconductor structure can be effectively improved, and the yield of the semiconductor structure can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0014] Figure 1 Fig. 1 is a top view of a semiconductor structure provided in an embodiment of the present disclosure;

[0015] Figure 2 This is a schematic cross-sectional view of a semiconductor structure provided in one embodiment;

[0016] Figure 3 For example Figure 2 An enlarged schematic diagram of an I-region in the semiconductor structure shown;

[0017] Figure 4 For example Figure 2 An enlarged schematic diagram of another I region in the semiconductor structure shown;

[0018] Figure 5 This is a flowchart illustrating a method for fabricating a semiconductor structure in one embodiment;

[0019] Figure 6 for Figure 5 A schematic cross-sectional view of the structure obtained in step S11 of the preparation method shown;

[0020] Figure 7 for Figure 5 A schematic cross-sectional view of the structure obtained in step S12 of the preparation method shown;

[0021] Figure 8 for Figure 5 A schematic cross-sectional view of the structure obtained in step S13 of the preparation method shown;

[0022] Figure 9 This is a flowchart illustrating a method for preparing a metal silicide layer in a semiconductor structure, as provided in one embodiment.

[0023] Figure 10 for Figure 9 A schematic cross-sectional view of the structure obtained in step S121 of the preparation method shown;

[0024] Figure 11 This is a schematic cross-sectional view of the structure obtained after directly forming a second dielectric layer on the sidewall of the in-situ line in one embodiment;

[0025] Figure 12 for Figure 9 A schematic cross-sectional view of the structure obtained in step S122 of the preparation method shown;

[0026] Figure 13 for Figure 9 A schematic cross-sectional view of the structure obtained in step S123 of the preparation method shown;

[0027] Figure 14 This is a schematic cross-sectional view of the structure obtained after removing part of the first dielectric layer and part of the bit line sidewall in one embodiment;

[0028] Figure 15 for Figure 9A cross-sectional view of the structure obtained in step S124 of the preparation method shown;

[0029] Figure 16 A cross-sectional view of a metal layer provided in an embodiment;

[0030] Figure 17 A cross-sectional view of another metal layer provided in an embodiment;

[0031] Figure 18 A cross-sectional view of Figure 9 A cross-sectional view of the structure obtained in step S125 of the preparation method shown;

[0032] Figure 19 A cross-sectional view of Figure 9 A cross-sectional view of the structure obtained in step S126 of the preparation method shown;

[0033] Figure 20 A cross-sectional view of a metal silicide layer provided in an embodiment;

[0034] Figure 21 A cross-sectional view of another metal silicide layer provided in an embodiment;

[0035] Figure 22 A flow chart of a preparation method of a contact pad in a semiconductor structure provided in an embodiment;

[0036] Figure 23 A process chart of a preparation of a contact pad in a semiconductor structure provided in an embodiment;

[0037] Figure 24 A process chart of a preparation of a contact pad in a semiconductor structure provided in an embodiment.

[0038] BRIEF DESCRIPTION OF THE DRAWINGS

[0039] 100 - semiconductor structure, 1 - substrate, 10 - shallow trench isolation structure, 11 - insulating layer, 2 - active region, 3 - bit line,

[0040] 31 - bit line structure, 32 - sidewall structure, 321 - first silicon nitride layer, 322 - silicon oxide layer, 323 - second silicon nitride layer,

[0041] 4 - buried gate word line, 5 - storage node contact structure, 51 - contact plug, 52 - metal silicide layer,

[0042] 53 - contact pad, 531 - adhesion layer, 532 - pad conductive layer, 6 - first dielectric layer, 7 - second dielectric layer,

[0043] L - gap, G - air gap, S1 - upper surface of the contact plug, S2 - upper surface of the bit line,

[0044] S3 - upper surface of the second dielectric layer, H G - height of the air gap, H L - height of the gap,

[0045] L1 - length of the portion of the contact pad extending into the gap, 510 - layer of contact plug material,

[0046] H C - height of the contact plug, H W - height of the bit line, 512 - metal layer, V - void. DETAILED DESCRIPTION

[0047] For the purposes of this application, reference will be made to the accompanying drawings in which embodiments of the application are shown. The application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application.

[0049] It should be understood that when an element or layer is referred to as being "on", "adjacent", "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected" or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to each other. Further, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or analogous elements.

[0050] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0051] As used herein, the singular form "a", "an" and "the" include plural references unless the context clearly dictates otherwise. As used herein, the term "includes" and / or "including" or "has" and / or "having" or variants thereof are intended to be open-ended terms that specifically permit the presence of one or more other components, integers, steps, operations, elements, parts or combinations thereof, in addition to the elements specifically recited. Also, the term "consisting of" is intended to be synonymous with "consisting only of", in that the recited components are the only ones that are present in the composition, method or structure, as the case can be. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0052] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic and many of the regions are not drawn to scale. The same reference numerals in different figures identify the same components.

[0053] Referring to Figure 1 and Figure 2 One embodiment of the present disclosure provides a semiconductor structure 100. The semiconductor structure 100 comprises a substrate 1, and a storage node contact structure 5 disposed on the substrate 1.

[0054] In one example, the substrate 1 comprises, but not limited to, a silicon substrate or a silicon-based substrate.

[0055] In one example, a shallow trench isolation structure 10 is disposed in the substrate 1. The shallow trench isolation structure 10 isolates a plurality of active regions 2 in an array arrangement in the substrate 1, which includes source regions and drain regions Figure 1 (not shown).

[0056] Optionally, the shallow trench isolation structure 10 is a silicon oxide (SiO2) isolation structure.

[0057] Optionally, the active region 2 is made of polysilicon, and the source and drain regions of the active region 2 are doped regions of polysilicon.

[0058] In one example, such as Figure 1 As shown, a plurality of parallel spaced bit lines 3 and a plurality of parallel spaced buried gate word lines 4 are formed on the substrate 1. The buried gate word lines 4 extend along a first direction, and the bit lines 3 extend along a second direction, with the first direction and the second direction having an angle greater than 0° and less than or equal to 90°. An active region 2 spans two buried gate word lines 4, with the source region of the active region 2 located between the two buried gate word lines 4 spanned by the active region 2, and the drain region of the active region 2 located outside the two buried gate word lines 4 spanned by the active region 2.

[0059] Optional, such as Figure 2 As shown, bit line 3 includes bit line structure 31 and sidewall structure 32. Bit line structure 31 includes a conductive portion coupled to the source region of active region 2, and an insulating portion covering the top surface of the conductive portion. Sidewall structure 32 includes at least one dielectric layer. The materials of the insulating portion and dielectric layer are, for example, silicon oxide (SiO2) or silicon nitride (SiO2). x N y At least one of the following. The conductive part may have a single-layer structure or a multilayer structure, and the material of the conductive part includes, for example, at least one of polycrystalline silicon or metal.

[0060] In addition, optional, such as Figure 2 As shown, the bottom of some bit line structures 31 extends into the substrate 1 and is coupled to the corresponding source region. An insulating layer 11 filled within the substrate 1 is also disposed on the periphery of the bottom of the bit line structure 31. The material of the insulating layer 11 is, for example, silicon oxide (SiO2) or silicon nitride (SiO2). x N y At least one of the following.

[0061] Please continue reading. Figure 2 The storage node contact structure 5 includes a contact plug 51, a metal silicide layer 52, and contact pads 53. The contact plug 51 is located between adjacent bit lines 3, and the upper surface S1 of the contact plug 51 is lower than the upper surface S2 of the bit line 3. The metal silicide layer 52 is located on the upper surface of the contact plug 51, and an air gap G exists between the metal silicide layer 52 and the bit line 3. The contact pads 53 are located on the metal silicide layer 52, partially extending between the metal silicide layer 52 and the bit line 3, and are located above the air gap G.

[0062] Here, the upper surface of the contact plug 51 includes the upper surface S1 of the contact plug 51. For example, the upper surface of the contact plug 51 is the upper surface S1 of the contact plug 51, or the upper surface of the contact plug 51 is the upper surface S1 of the contact plug 51 and the adjacent side surface of the upper surface S1.

[0063] In one example, the contact plug 51 of the storage node contact structure 5 is coupled corresponding to the drain region of the active region 2, and the material of the contact plug 51 is, for example, polysilicon. Figure 1 Only the distribution of the active region 2, the bit line 3 and the buried gate word line 4 is schematically shown, and the storage node contact structure 5 is not schematically shown. Thus, the orthographic projection position of the storage node contact structure 5 on the substrate 1 can be understood according to the foregoing.

[0064] In one example, the contact plug 51 is a polysilicon layer, and the metal silicide layer 52 is a cobalt silicide (CoSi) layer.

[0065] In the embodiments of the present disclosure, there is a gap between the metal silicide layer 52 and the bit line 3, so that the contact pad 53 can partially extend into the gap, so as to ensure that the contact pad 53 has a larger contact area with the metal silicide layer 52, and the air gap G is reserved between the metal silicide layer 52 and the bit line 3. Thus, it is beneficial to reduce the contact resistance between the contact pad 53 and the contact plug 51, and to reduce the risk of leakage of the storage node contact structure 5 by using the air gap G, and to reduce the parasitic capacitance between the storage node contact structure 5 and the bit line 3. In turn, the electrical performance of the semiconductor structure 100 can be effectively improved to improve the yield of the semiconductor structure 100.

[0066] The height H of the air gap G G may be selected according to actual needs. In one example, as Figure 3 shown, the height H of the air gap G G is 20% to 80% of the height H of the gap L between the metal silicide layer 52 and the bit line 2. L For example, the height H of the air gap G G is 20%, 40%, 60% or 80% of the height H of the gap L between the metal silicide layer 52 and the bit line 2. L

[0067] In one example, please continue to refer to Figure 3 The semiconductor structure 100 further includes a first dielectric layer 6 and a second dielectric layer 7. The first dielectric layer 6 is located on the surface of the bit line 3 and between the bit line 3 and the storage node contact structure 5. For example, the first dielectric layer 6 is located on the surface of the side wall structure 32 of the bit line 3. The second dielectric layer 7 is located on the surface of the first dielectric layer 6 and between the first dielectric layer 6 and the storage node contact structure 5, and is located below the air gap G.​

[0068] Optionally, the first dielectric layer 6 includes a silicon nitride layer, and the second dielectric layer 7 includes a silicon oxide layer. However, it is not limited to this; the first dielectric layer 6 and the second dielectric layer 7 can be made of different insulating materials.

[0069] See another example. Figure 4 The sidewall structure 32 of bit line 3 includes a first silicon nitride layer 321, a silicon oxide layer 322, and a second silicon nitride layer 323 stacked in a direction opposite to the bit line structure 31. Therefore, if the thickness of the second silicon nitride layer 323 meets the usage requirements, the second silicon nitride layer 323 can be used as the first dielectric layer 6 in the aforementioned example. That is, in this example, the semiconductor structure 100 includes a second dielectric layer 7, which is located on the surface of the sidewall structure 32 of bit line 3. The material of the second dielectric layer 7 is different from the material of the outermost dielectric layer in the sidewall structure 32 of bit line 3. For example, the outermost dielectric layer in the sidewall structure 32 of bit line 3 is the second silicon nitride layer 323, and the second dielectric layer 7 is a silicon oxide layer.

[0070] It is understandable that the metal silicide layer 52 can be obtained by metallizing polycrystalline silicon material. Thus, the shape of the metal silicide layer 52 is related to the shape of the metallized portion in the polycrystalline silicon material.

[0071] In one example, such as Figure 3 As shown, the upper surface S1 of the contact plug 51 is flush with the upper surface S3 of the second dielectric layer 7, and the metal silicide layer 52 is located on the upper surface S1 of the contact plug 51. This means that the portion of the polycrystalline silicon material above the plane containing the upper surface S3 of the second dielectric layer 7 is completely metallized to form the metal silicide layer 52. The portion of the polycrystalline silicon material located at and below the plane containing the upper surface S3 of the second dielectric layer 7 constitutes the contact plug 51. Thus, the upper surface S1 of the contact plug 51 is a plane, and the aforementioned upper surface of the contact plug 51 is the upper surface S1 of the contact plug 51.

[0072] In another example, such as Figure 4 As shown, the upper surface S1 of the contact plug 51 is higher than the upper surface S3 of the second dielectric layer 7, and the metal silicide layer 52 covers the surface of the contact plug 51 above the second dielectric layer 7. That is, the surface of the polysilicon material above the plane containing the upper surface S3 of the second dielectric layer 7 is metallized to form the metal silicide layer 52. The unmetallized portion of the polysilicon material forms the contact plug 51. Thus, the upper surface of the contact plug 51 protrudes, and the upper surface of the contact plug 51 includes the upper surface S1 of the contact plug 51 and a side surface located above the plane containing the upper surface S3 of the second dielectric layer 7 and adjacent to the upper surface S1 of the contact plug 51.

[0073] In one example, as shown in FIG. 1, the contact pad 53 includes an adhesion layer 531 and a pad conductive layer 532. The adhesion layer 531 is located on the surface of the removed portion of the bit line 3 and the surface of the metal silicide layer 52, and the adhesion layer 531 partially extends to the metal silicide layer 52 and the bit line 3. The pad conductive layer 532 is located on the surface of the adhesion layer 531. Figure 3 and Figure 4 The contact pad 53 includes an adhesion layer 531 and a pad conductive layer 532. The adhesion layer 531 is located on the surface of the removed portion of the bit line 3 and the surface of the metal silicide layer 52, and the adhesion layer 531 partially extends to the metal silicide layer 52 and the bit line 3. The pad conductive layer 532 is located on the surface of the adhesion layer 531.

[0074] Here, the surface of the removed portion of the bit line 3 refers to the surface after removing part of the sidewall structure 32 of the bit line 3. In this way, the gap between adjacent bit lines 3 has a larger size compared to before the sidewall is removed, so as to ensure that the contact pad 53 has a larger footprint on the substrate 1. This is beneficial for ensuring good conductivity of the storage node contact structure 5 after further miniaturization of the DRAM size.

[0075] Optionally, as shown in FIG. 1, the sidewall structure 32 of the bit line 3 includes a first silicon nitride layer 321, a silicon oxide layer 322, and a second silicon nitride layer 323 stacked in a direction away from the bit line structure 31. The top surface of the first dielectric layer 6 is flush or substantially flush with the top surface of the metal silicide layer 52. The aforementioned removal of part of the sidewall of the bit line 3 includes removing part or all of the materials of the second silicon nitride layer 323 and the silicon oxide layer 322 that are higher than the plane of the top surface of the metal silicide layer 52. In this way, part of the surface of the adhesion layer 531 will be in direct contact with the surface of the first silicon nitride layer 321. Figure 3 Optionally, as shown in FIG. 1, the sidewall structure 32 of the bit line 3 includes a first silicon nitride layer 321, a silicon oxide layer 322, and a second silicon nitride layer 323 stacked in a direction away from the bit line structure 31. The second silicon nitride layer 323 can be used as the first dielectric layer 6 in the aforementioned example. The second dielectric layer 7 is located on the surface of the second silicon nitride layer 323. The aforementioned removal of part of the sidewall of the bit line 3 includes removing part or all of the materials of the second silicon nitride layer 323 and the silicon oxide layer 322 that are higher than the plane of the top surface of the metal silicide layer 52. For example, all of the materials of the second silicon nitride layer 323 that are higher than the plane of the top surface of the metal silicide layer 52 are removed, so that the top surface of the second silicon nitride layer 323 is flush or substantially flush with the top surface of the metal silicide layer 52. Part of the materials of the silicon oxide layer 322 that are higher than the plane of the top surface of the metal silicide layer 52 are removed. In this way, part of the surface of the adhesion layer 531 will be in direct contact with the surface of the first silicon nitride layer 321.

[0076] Figure 4 Optionally, as shown in FIG. 1, the sidewall structure 32 of the bit line 3 includes a first silicon nitride layer 321, a silicon oxide layer 322, and a second silicon nitride layer 323 stacked in a direction away from the bit line structure 31. The second silicon nitride layer 323 can be used as the first dielectric layer 6 in the aforementioned example. The second dielectric layer 7 is located on the surface of the second silicon nitride layer 323. The aforementioned removal of part of the sidewall of the bit line 3 includes removing part or all of the materials of the second silicon nitride layer 323 and the silicon oxide layer 322 that are higher than the plane of the top surface of the metal silicide layer 52. For example, all of the materials of the second silicon nitride layer 323 that are higher than the plane of the top surface of the metal silicide layer 52 are removed, so that the top surface of the second silicon nitride layer 323 is flush or substantially flush with the top surface of the metal silicide layer 52. Part of the materials of the silicon oxide layer 322 that are higher than the plane of the top surface of the metal silicide layer 52 are removed. In this way, part of the surface of the adhesion layer 531 will be in direct contact with the surface of the first silicon nitride layer 321.

[0077] In addition, the adhesion layer 531 can include, but is not limited to, a titanium nitride (TiN) layer.

[0078] ​Optionally, the pad conductive layer 532 comprises a metal layer. The material of the pad conductive layer 532 is, for example, at least one of tungsten (W), cobalt (Co), molybdenum (Mo), tantalum (Ta), titanium (Ti), ruthenium (Ru), rhodium (Rh), copper (Cu), iron (Fe), manganese (Mn), vanadium (V), niobium (Nb), hafnium (Hf), zirconium (Zr), yttrium (Y), aluminum (Al), tin (Sn), chromium (Cr), and lanthanum (La).

[0079] Referring to Figure 5 , an embodiment of the present disclosure provides a preparation method of a semiconductor structure, which is used for preparing the semiconductor structure 100 in some embodiments described above. The preparation method comprises the following steps.

[0080] S11: providing a substrate, and a plurality of parallel and spaced bit lines are formed on the substrate.

[0081] S12: forming a contact plug between adjacent bit lines, and forming a metal silicide layer on the upper surface of the contact plug. The upper surface of the contact plug is lower than the upper surface of the bit line, and there is a gap between the metal silicide layer and the bit line.

[0082] S13: forming a contact pad on the metal silicide layer, and the contact pad, the metal silicide layer, and the contact plug jointly constitute a storage node contact structure. The contact pad extends into the gap, and the length of the part of the contact pad extending into the gap is less than the height of the gap, so that an air gap is reserved between the metal silicide layer and the bit line.

[0083] In the embodiments of the present disclosure, a gap is formed between the metal silicide layer and the bit line, and a contact pad is formed on the metal silicide layer, so that part of the contact pad extends into the gap. In this way, the contact pad and the metal silicide layer have a larger contact area, and an air gap is reserved between the metal silicide layer and the bit line. Therefore, the contact resistance between the contact pad and the contact plug can be reduced, the risk of leakage of the storage node contact structure can be reduced by using the air gap, and the parasitic capacitance between the storage node contact structure and the bit line can be reduced. In turn, the electrical performance of the semiconductor structure can be effectively improved, and the yield of the semiconductor structure can be improved.

[0084] In step S11, referring to S11 in Figure 5 and Figure 6 , a substrate 1 is provided, and a plurality of parallel and spaced bit lines 3 are formed on the substrate 1.

[0085] In one example, substrate 1 includes, but is not limited to, a silicon substrate or a silicon-based substrate. A shallow trench isolation structure 10 is disposed within substrate 1, the shallow trench isolation structure 10 being, for example, a silicon oxide (SiO2) isolation structure. The shallow trench isolation structure 10 isolates a plurality of active regions 2 arranged in an array within substrate 1, each active region 2 including source and drain regions. The material of the active regions 2 is, for example, polysilicon, and the source and drain regions of the active regions 2 are doped regions of polysilicon.

[0086] Optional, such as Figure 6 As shown, bit line 3 includes bit line structure 31 and sidewall structure 32. Bit line structure 31 includes a conductive portion coupled to the source region of active region 2, and an insulating portion covering the top surface of the conductive portion. Sidewall structure 32 includes at least one dielectric layer. The materials of the insulating portion and dielectric layer are, for example, silicon oxide (SiO2) or silicon nitride (SiO2). x N y At least one of the following. The conductive part may have a single-layer structure or a multilayer structure, and the material of the conductive part includes, for example, at least one of polycrystalline silicon or metal.

[0087] In addition, optional, such as Figure 6 As shown, the bottom of some bit line structures 31 extends into the substrate 1 and is coupled to the corresponding source region. An insulating layer 11 filled within the substrate 1 is also disposed on the periphery of the bottom of the bit line structure 31. The material of the insulating layer 11 is, for example, silicon oxide (SiO2) or silicon nitride (SiO2). x N y At least one of the following.

[0088] In step S12, please refer to the figure. Figure 5 S12 and Figure 7 A contact plug 51 is formed between adjacent bit lines 3, and a metal silicide layer 52 is formed on the upper surface of the contact plug 51. The upper surface S1 of the contact plug 51 is lower than the upper surface S2 of the bit line 3, and there is a gap L between the metal silicide layer 52 and the bit line 3.

[0089] Here, the upper surface of the contact plug 51 includes the upper surface S1 of the contact plug 51. For example, the upper surface of the contact plug 51 is the upper surface S1 of the contact plug 51, or the upper surface of the contact plug 51 is the upper surface S1 of the contact plug 51 and the adjacent side surface of the upper surface S1.

[0090] Furthermore, the contact plug 51 is coupled to the drain region of the active region 2, and the contact plug 51 is, for example, a polysilicon layer. The metal silicide layer 52 is, for example, a cobalt silicide (CoSi) layer.

[0091] In step S13, please refer to Figure 5 S13 and Figure 8A contact pad 53 is formed on the metal silicide layer 52. The contact pad 53 extends partially into the gap L, and the length L1 of the contact pad 53 extending into the gap L is less than the height H of the gap L L , so that an air gap G is reserved between the metal silicide layer 52 and the bit line 3.

[0092] The height H of the air gap G G may be selected according to actual needs. Optionally, the height H of the air gap G G is 20% to 80% of the height H of the gap L. L For example, the height H of the air gap G G is 20%, 40%, 60% or 80% of the height H of the gap L. L

[0093] Accordingly, the contact pad 53, the metal silicide layer 52 and the contact plug 51 jointly constitute a storage node contact structure 5.

[0094] In one example, referring to Figure 9 , the step S12 forms a contact plug between adjacent bit lines, and forms a metal silicide layer on the upper surface of the contact plug, and the metal silicide layer has a gap with the bit line, including the following steps.

[0095] S121: Form a first dielectric layer on the sidewall of the bit line, and form a second dielectric layer on the surface of the first dielectric layer. The material of the second dielectric layer is different from that of the first dielectric layer.

[0096] S122: Form a contact plug between adjacent bit lines.

[0097] S123: Remove part of the second dielectric layer to form a gap between the contact plug and the first dielectric layer, and the gap exposes part of the contact plug.

[0098] S124: Form a metal layer on the exposed surface of the contact plug.

[0099] S125: Anneal the obtained structure to obtain a metal silicide layer.

[0100] S126: Remove the residual metal layer to expose the gap.

[0101] In the embodiments of the present disclosure, the metal silicide layer is obtained by metallizing part of the material of the contact plug, which can simplify the manufacturing process of the metal silicide layer. Moreover, the first dielectric layer and the second dielectric layer with different materials are formed on the sidewall of the bit line, so as to expose the surface of the contact plug to be metallized by the removal space of the second dielectric layer, and form the gap between the metal silicide layer and the first dielectric layer, which can reduce the process difficulty of the metal silicide layer and the gap.​

[0102] In step S121, please refer to Figure 9 S121 and Figure 10 As shown, a first dielectric layer 6 is formed on the sidewall of bit line 3, and a second dielectric layer 7 is formed on the surface of the first dielectric layer 6. The material of the second dielectric layer 7 is different from the material of the first dielectric layer 6.

[0103] Here, the first dielectric layer 6 and the second dielectric layer 7 can be obtained using, but are not limited to, deposition processes. The first dielectric layer 6 includes, but is not limited to, a silicon nitride layer. The second dielectric layer 7 includes, but is not limited to, a silicon oxide layer.

[0104] Understandably, in another example, such as Figure 11 As shown, the sidewall structure 32 of bit line 3 includes a first silicon nitride layer 321, a silicon oxide layer 322, and a second silicon nitride layer 323 stacked in a direction opposite to the bit line structure 31. Thus, if the thickness of the second silicon nitride layer 323 meets the usage requirements, the first dielectric layer 6 can be directly replaced by the second silicon nitride layer 323. That is, it is not necessary to form the first dielectric layer 6 on the sidewall structure 32 of bit line 3, but the second dielectric layer 7 can be directly formed on the surface of the second silicon nitride layer 323. The material of the second dielectric layer 7 is different from the material of the second silicon nitride layer 323; for example, the second dielectric layer 7 is a silicon oxide layer.

[0105] In step S122, please refer to Figure 9 S122 and Figure 12 As shown, a contact plug 51 is formed between adjacent bit lines 3.

[0106] Here, the contact plug 51 can be obtained by, but is not limited to, deposition and etching processes.

[0107] For example, such as Figure 12 As shown in (a), a contact plug material layer 510 is deposited on the substrate 1 such that the contact plug material layer 510 fills the gap between every two adjacent bit lines 3 and covers the bit lines 3. Figure 12 As shown in (b), the contact plug material layer 510 is etched using an etching process to form the contact plug 51. The etching process is, for example, wet etching.

[0108] Optional, such as Figure 12 As shown in (b), the height H of the contact plug 51 C For bit line 3 height H W 10% to 80%. For example, the height H of the contact plug 51. C For bit line 3 height H W 10%, 20%, 50%, 60%, or 80%.

[0109] In step S123, referring to Figure 9 S123 and Figure 13 , part of the second dielectric layer 7 is removed to form a gap L between the contact plug 51 and the first dielectric layer 6, the gap L exposes part of the contact plug 51.

[0110] In an example, the second dielectric layer 7 is a silicon oxide layer. Part of the material of the second dielectric layer 7 is removed by wet etching, for example, using a diluted hydrofluoric acid solution. The material of the first dielectric layer 6 is different from the material of the second dielectric layer 7, in the case of etching to remove part of the second dielectric layer 7, the first dielectric layer 6 can act as an etching stop layer in the etching process.

[0111] Optionally, the height of the removed part of the second dielectric layer 7 is 20% to 80% of the initial height of the second dielectric layer 7. For example, the height of the removed part of the second dielectric layer 7 is 20%, 40%, 60% or 80% of the initial height of the second dielectric layer 7.

[0112] Here, the height of the removed part of the second dielectric layer 7 is different, and the surface area of the subsequently formed metal silicide layer 52 for contacting the contact pad 53 is different. For example, the greater the height of the removed part of the second dielectric layer 7, the greater the height of the gap L formed between the contact plug 51 and the first dielectric layer 6. In this case, the greater the surface area of the contact plug 51 exposed, the greater the surface area of the metal silicide layer 52 that can be obtained. On this basis, the use of a gap L with a greater height facilitates the part of the subsequently formed contact pad 53 extending into the gap L also having a greater height, thereby ensuring that the subsequently formed metal silicide layer 52 and the contact pad 53 can have a greater contact area.

[0113] In one example, referring to Figure 14 , the method for manufacturing the semiconductor structure further comprises: removing part of the first dielectric layer 6 and part of the sidewall of the bit line 3. This can make the gap between adjacent bit lines 3 have a greater size compared to before part of the first dielectric layer 6 and part of the sidewall of the bit line 3 are removed, to ensure that the subsequently formed contact pad 53 has a greater footprint on the substrate 1. This is beneficial for ensuring that the storage node contact structure 5 has good conductivity after further miniaturization of the DRAM.

[0114] Optionally, part of the first dielectric layer 6 is removed so that the shaped top surface of the first dielectric layer 6 is flush or substantially flush with the upper surface of the contact plug 51 at this stage (the surface before the metalization process).

[0115] Optionally, the sidewall structure 32 of the bit line 3 comprises a first silicon nitride layer 321, a silicon oxide layer 322 and a second silicon nitride layer 323 stacked in a direction away from the bit line structure 31. Part of the sidewall of the bit line 3 is removed, including removing part or all of the second silicon nitride layer 323 and the silicon oxide layer 322 above the plane of the upper surface (the surface before being metallized) of the current contact plug 51.

[0116] In step S124, referring to S124 in Figure 9 and Figure 15 , a metal layer 512 is formed on the exposed surface of the contact plug 51.

[0117] Optionally, the thickness of the metal layer 512 is 5nm-16nm. For example, the thickness of the metal layer 512 is 5nm, 8nm, 10nm, 12nm or 16nm.

[0118] Optionally, the material of the metal layer 512 includes but is not limited to metal cobalt (Co).

[0119] In addition, the metal layer 512 can be prepared by but is not limited to deposition process. Moreover, the film forming quality of the metal layer 512 is related to the process parameters of the deposition process.

[0120] In one example, as shown in Figure 16 , the metal layer 512 covers the exposed surface of the contact plug 51, and fills the gap between the contact plug 51 and the first dielectric layer 6. In this way, the metal layer 512 is easy to have better density, thereby facilitating the exposed surface of the contact plug 51 to be fully metallized.

[0121] In another example, as shown in Figure 17 , the metal layer 512 covers the exposed surface of the contact plug 51, and the part of the metal layer 512 in the gap between the contact plug 51 and the first dielectric layer 6 has a void V. In this way, by using the void V in the metal layer 512, it is convenient to perform subsequent processes to remove the residual metal layer 512.

[0122] In step S125, referring to S125 in Figure 9 and Figure 18 , the obtained structure is annealed to obtain a metal silicide layer 52.

[0123] Optionally, the annealing temperature of the annealing process of the obtained structure is 300℃-700℃, for example, 300℃, 500℃ or 700℃.

[0124] In step S126, referring to S126 in Figure 9 and Figure 19The residual metal layer 512 is removed to expose the gap L.

[0125] Here, the residual metal layer 512 refers to the metal element, such as cobalt, remaining on the surface of the contact plug material layer 510 after the annealing process.

[0126] In addition, the residual metal layer 512 can be removed by a wet etching process, such as cleaning by a diluted sulfuric acid hydrogen peroxide mixture. The diluted sulfuric acid hydrogen peroxide mixture includes sulfuric acid (H2SO4), hydrogen peroxide (H2O2), and water (H2O).

[0127] It should be noted that after the annealing process on the resultant structure, part of the contact plug 51 is metallized, especially the exposed surface part of the contact plug 51. Therefore, the cross-sectional shape of the metal silicide layer 52 is related to the degree of metallization of the contact plug 51.

[0128] In one example, referring to Figure 20 , the annealing process on the resultant structure to obtain the metal silicide layer 52 includes: performing the annealing process on the resultant structure so that the exposed part of the contact plug 51 reacts with the metal layer 512 to be completely converted into the metal silicide layer 52. The cross-sectional shape of the metal silicide layer 52 is, for example, rectangular.

[0129] In another example, referring to Figure 21 , the annealing process on the resultant structure to obtain the metal silicide layer 52 includes: performing the annealing process on the resultant structure so that the exposed part of the contact plug 51 reacts with the metal layer 512 to form the metal silicide layer 52 on the surface of the exposed part of the contact plug 51. The cross-sectional shape of the metal silicide layer 52 is, for example, inverted U-shaped.

[0130] In one example, referring to Figure 22 , the step S13 of forming the contact pad on the metal silicide layer includes the following steps.

[0131] S131: forming an adhesion layer on the surface of the removed part of the bit line after the sidewall and the surface of the metal silicide layer, the adhesion layer partially extending into the gap, and the part of the adhesion layer extending into the gap is the part of the contact pad extending into the gap.

[0132] S132: forming a pad conductive layer on the surface of the adhesion layer.

[0133] In the embodiments of the present disclosure, the adhesion layer is formed on the surface of the removed part of the bit line and the surface of the metal silicide layer, and then the pad conductive layer is formed on the surface of the adhesion layer. The adhesion layer can enhance the adhesion between the pad conductive layer and the metal silicide layer and the adhesion between the pad conductive layer and the sidewall of the bit line, so as to ensure good electrical conductivity of the contact pad, good connection between the contact pad and the metal silicide layer, and good connection between the contact pad and the sidewall of the bit line, thereby ensuring the use reliability of the semiconductor structure. In addition, the adhesion layer extends into the gap, which can increase the contact area between the contact pad and the metal silicide layer, so as to reduce the contact resistance between the contact pad and the metal silicide layer. In addition, the contact pad is connected with the contact plug through the metal silicide layer, and the metal silicide layer can reduce the contact resistance between the contact pad and the contact plug.

[0134] In step S131, referring to S131 in FIG. 1 and Figure 22 , Figure 23 , Figure 24 , an adhesion layer 531 is formed on the surface of the removed part of the bit line 3 and the surface of the metal silicide layer 52.

[0135] Optionally, the material of the adhesion layer 531 includes but is not limited to titanium nitride. The adhesion layer 531 is also called a metal barrier layer.

[0136] Here, the adhesion layer 531 is used to seal the gap L, so as to keep the air gap G in the gap L. The adhesion layer 531 can be prepared by deposition process, but is not limited to this. By controlling the deposition rate of the adhesion layer 531, the forming height of the air gap G can be controlled.

[0137] In step S132, referring to S132 in FIG. 1 and Figure 22 , Figure 23 , Figure 24 , a pad conductive layer 532 is formed on the surface of the adhesion layer 531.

[0138] Optionally, the material of the pad conductive layer 532 includes but is not limited to tungsten (W).

[0139] Therefore, the adhesion layer 531 and the pad conductive layer 532 constitute the contact pad 53.

[0140] The technical features of the above-mentioned embodiments can be combined in any manner. In order to make the description simple, all possible combinations of the technical features of the above-mentioned embodiments are not described, but as long as the combinations of the technical features do not exist, they should be considered as the scope of the present disclosure.

[0141] The above embodiments only express several implementation ways of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation to the patent scope of the application. It should be pointed out that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, which all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided on which a plurality of parallel, spaced bit lines are formed; A contact plug is formed between adjacent bit lines, and a metal silicide layer is formed on the upper surface of the contact plug; the upper surface of the contact plug is lower than the upper surface of the bit line, and there is a gap between the metal silicide layer and the bit line; Contact pads are formed on the metal silicide layer, and the contact pads, together with the metal silicide layer and the contact plugs, constitute the memory node contact structure; the contact pads extend into the gap, and the length of the portion of the contact pads extending into the gap is less than the height of the gap, so that an air gap is maintained between the metal silicide layer and the bit line.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The step of forming a contact plug between adjacent bit lines and forming a metal silicide layer on the upper surface of the contact plug, wherein the metal silicide layer has a gap with the bit line, includes: A first dielectric layer is formed on the sidewall of the bit line, and a second dielectric layer is formed on the surface of the first dielectric layer; the material of the second dielectric layer is different from the material of the first dielectric layer. A contact plug is formed between adjacent bit lines; A portion of the second dielectric layer is removed to form a gap between the contact plug and the first dielectric layer, the gap exposing a portion of the contact plug; A metal layer is formed on the exposed surface of the contact plug; The obtained structure was annealed to obtain a metal silicide layer; Remove any remaining metal layer to expose the gap.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, Before forming a metal layer on the exposed surface of the contact plug, the method further includes: Remove a portion of the first dielectric layer and a portion of the sidewalls of the bit line.

4. The method for preparing a semiconductor structure according to claim 2, characterized in that, The metal layer covers the exposed surface of the contact plug and fills the gap; Alternatively, the metal layer covers the exposed surface of the contact plug, and the portion of the metal layer within the gap has pores.

5. The method for preparing a semiconductor structure according to claim 2, characterized in that, The annealing process performed on the obtained structure to obtain a metal silicide layer includes: The resulting structure is annealed so that the exposed portion of the contact plug reacts with the metal layer and is completely transformed into the metal silicide layer.

6. The method for preparing a semiconductor structure according to claim 2, characterized in that, The annealing process performed on the obtained structure to obtain a metal silicide layer includes: The resulting structure is annealed so that the exposed portion of the contact plug reacts with the metal layer to form the metal silicide layer on the surface of the exposed portion of the contact plug.

7. The method for preparing a semiconductor structure according to claim 2, characterized in that, The first dielectric layer includes a silicon nitride layer, and the second dielectric layer includes a silicon oxide layer; The bit line includes a bit line structure and a sidewall structure; the sidewall structure includes at least one dielectric layer, and the material of the outermost dielectric layer of the sidewall structure is the same as the material of the first dielectric layer.

8. The method for preparing a semiconductor structure according to claim 2, characterized in that, The annealing temperature for annealing the obtained structure is 300℃~700℃.

9. The method for preparing a semiconductor structure according to any one of claims 2 to 8, characterized in that, The formation of contact pads on the metal silicide layer includes: An adhesion layer is formed on the surface of the bit line after the removal of the sidewall portion and on the surface of the metal silicide layer. The adhesion layer extends into the gap, and the portion of the adhesion layer extending into the gap is the portion of the contact pad extending into the gap. A conductive pad layer is formed on the surface of the adhesion layer.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, The adhesion layer includes a titanium nitride layer, and the pad conductive layer includes a metal layer.

11. The method for preparing a semiconductor structure according to claim 1, characterized in that, The metal silicide layer includes a cobalt silicide layer.

12. The method for preparing a semiconductor structure according to claim 1, characterized in that, The height of the air gap is 20% to 80% of the height of the gap.

13. A semiconductor structure, characterized in that, include: A substrate on which multiple parallel, spaced bit lines are formed; And, a storage node contact structure, the storage node contact structure including a contact plug, a metal silicide layer and contact pads; wherein, the contact plug is located between adjacent bit lines, and the upper surface of the contact plug is lower than the upper surface of the bit line; the metal silicide layer is located on the upper surface of the contact plug, and there is an air gap between the metal silicide layer and the bit line; the contact pad is located on the metal silicide layer, and partially extends between the metal silicide layer and the bit line, and is located above the air gap.

14. The semiconductor structure according to claim 13, characterized in that, The semiconductor structure also includes: A first dielectric layer is located on the surface of the bit line and between the bit line and the memory node contact structure; The second dielectric layer is located on the surface of the first dielectric layer, between the first dielectric layer and the storage node contact structure, and below the air gap.

15. The semiconductor structure according to claim 14, characterized in that, The first dielectric layer includes a silicon nitride layer, the second dielectric layer includes a silicon oxide layer, and the metal silicide layer includes a cobalt silicide layer.

16. The semiconductor structure according to claim 14, characterized in that, The upper surface of the contact plug is flush with the upper surface of the second dielectric layer, and the metal silicide layer is located on the upper surface of the contact plug.

17. The semiconductor structure according to claim 14, characterized in that, The upper surface of the contact plug is higher than the upper surface of the second dielectric layer, and the metal silicide layer covers the surface of the contact plug located above the second dielectric layer.

18. The semiconductor structure according to any one of claims 14 to 17, characterized in that, The contact pads include: An adhesion layer is located on the surface of the bit line after the removal of the partial sidewall, and on the surface of the metal silicide layer, and extends partially between the metal silicide layer and the bit line; A conductive pad layer is located on the surface of the adhesion layer.

19. The semiconductor structure according to claim 18, characterized in that, The adhesion layer includes a titanium nitride layer, and the pad conductive layer includes a metal layer.

20. The semiconductor structure according to claim 13, characterized in that, The height of the air gap is 20% to 80% of the height of the gap between the metal silicide layer and the bit line.

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