Semiconductor structure and preparation method thereof

Abstract

The present application provides a semiconductor structure and a method for manufacturing the same, relating to the field of semiconductor technology. The semiconductor structure includes a substrate having a first doped region therein; an active pillar group disposed within the first doped region, the active pillar group including four active pillars arranged in an array, at least one of the active pillars having a notch disposed therein, the notch being oriented toward a row centerline and / or a column centerline of the active pillar group. The present application provides a notch on at least one active pillar, thereby increasing the distance between a bottom wall of the notch, which is concave toward the center of the active pillar, and another active pillar in the same row or column. This increases the migration path of electrons between the notch and a surface directly opposite the notch, reduces the risk of leakage between the notched active pillar and another active pillar in the same row or column, and improves the performance of the semiconductor structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] Dynamic random access memory (DRAM) is a semiconductor memory that can write and read data randomly at high speed and is widely used in data storage devices or apparatuses.

[0003] Dynamic random access memory typically includes multiple active areas arranged in an array and transistors disposed within each active area. The transistors include vertically arranged active pillars and gates surrounding the active pillars. As dynamic random access memory develops toward greater integration, the distance between adjacent active pillars becomes increasingly smaller, leading to leakage between adjacent active pillars and degrading the performance of the semiconductor structure. Summary of the Invention

[0004] In view of the above problems, embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, which are used to prevent leakage between adjacent active pillars and improve the performance of the semiconductor structure.

[0005] In order to achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0006] A first aspect of an embodiment of the present application provides a method for preparing a semiconductor structure, comprising:

[0007] a substrate having a first doped region therein;

[0008] An active pillar group is disposed in the first doping region, the active pillar group including four active pillars arranged in an array, at least one of the active pillars is provided with a notch, the notch facing a row center line and / or a column center line of the active pillar group.

[0009] In some embodiments, each of the active pillars includes a first pillar and a second pillar connected to the first pillar;

[0010] In two active pillars in the same row, the second pillar is arranged on a side of the first pillar facing the other first pillar.

[0011] In some embodiments, in two active pillars in the same column, the second pillar is disposed at an end of the first pillar away from the other first pillar, and the notches disposed on the two diagonally opposite active pillars face oppositely.

[0012] In some embodiments, there are multiple active pillar groups, and the multiple active pillar groups are arranged in an array in the substrate.

[0013] In some embodiments, along a direction perpendicular to the substrate, each of the active pillars includes a channel region and a source region and a drain region respectively disposed at two ends of the channel region.

[0014] In some embodiments, the active pillar group further includes a channel connection region, and each active pillar includes a drain region, a channel region, and a source region stacked sequentially from bottom to top along a direction perpendicular to the substrate;

[0015] In each of the active pillar groups, the drain regions of the active pillars are connected to each other through the channel connection region, the channel regions are connected to the channel connection region, and the channel connection region is in contact with the substrate.

[0016] In some embodiments, the device further includes a plurality of first bit lines and a plurality of second bit lines, wherein the plurality of first bit lines and the plurality of second bit lines are alternately arranged along a first direction, and the first bit lines and the second bit lines extend along a second direction, and the first direction intersects the second direction;

[0017] Along the first direction, each of the active pillar groups includes a first surface and a second surface arranged opposite to each other; the first bit line is arranged on the first surface and connects the drain regions of each active pillar located on the same column corresponding to the first surface; the second bit line is arranged on the second surface and connects the drain regions of each active pillar located on the same column corresponding to the second surface.

[0018] In some embodiments, the invention further includes a plurality of first word lines and a plurality of second word lines, wherein the plurality of first word lines and the plurality of second word lines are alternately arranged along the second direction, and the first word lines and the second word lines extend along the first direction;

[0019] Along the second direction, each of the active pillar groups includes a third surface and a fourth surface arranged opposite to each other; the first word line is arranged on the third surface and connects the channel regions of each active pillar located on the same row corresponding to the third surface; the second word line is arranged on the fourth surface and connects the channel regions of each active pillar located on the same row corresponding to the fourth surface.

[0020] In some embodiments, a plurality of isolation structures are further included, each of the isolation structures is disposed in a region surrounded by a plurality of active pillars in each active pillar group, and a bottom surface of the isolation structure is higher than a top surface of the drain region.

[0021] In some embodiments, a capacitor is disposed on each of the active pillars.

[0022] A second aspect of the embodiments of the present application provides a method for preparing a semiconductor structure, comprising the following steps:

[0023] providing a substrate having a first doped region;

[0024] An active pillar group is formed in the first doping region. The active pillar group includes four active pillars arranged in an array. At least one of the active pillars is provided with a notch. The notch faces a row center line and / or a column center line of the active pillar group.

[0025] In some embodiments, the step of forming an active pillar group in the first doped region includes:

[0026] Providing a mask, the mask comprising a rectangular first mask area and four second mask areas, the four second mask areas being respectively arranged at vertex corners of the first mask area, and each second mask area wraps around a vertex corner of the first mask area;

[0027] Using the mask as a mask, etching the substrate not blocked by the mask to form columns in the first doped region, wherein the columns include a first column and four second columns, wherein the cross-section of the first column is rectangular, with a plane parallel to the substrate as a cross-section, and the four second columns are respectively arranged at the vertex corners of the first column, and each second column wraps around the vertex corner of the first column;

[0028] Removing a portion of the thickness of the first columnar body to form a filling hole in the first columnar body, and each of the remaining second columnar bodies constitutes an intermediate columnar body;

[0029] forming an isolation structure in the filling hole, wherein a top surface of the isolation structure is flush with a top surface of the middle column;

[0030] Ion implantation is performed on the top surface of each intermediate column to form a source region on the top surface of the intermediate column. The intermediate column with the source region formed thereon constitutes an active column, and four active columns constitute an active column group.

[0031] In some embodiments, there are a plurality of pillars, and a plurality of the pillars are arranged in an array within the substrate.

[0032] In some embodiments, after the step of using the mask as a mask and before the step of removing a portion of the thickness of the first columnar body, the preparation method further includes:

[0033] forming a first dielectric layer covering each of the pillars on the substrate, wherein the top surface of the first dielectric layer is flush with the top surface of the pillars;

[0034] forming a plurality of first mask strips extending along the second direction on the first dielectric layer, wherein the plurality of first mask strips are spaced apart along the first direction, and first openings are formed between adjacent first mask strips, wherein the first openings expose the first dielectric layer between two adjacent columns of the columnar bodies;

[0035] removing a portion of the first dielectric layer exposed in the first opening to form a first groove, wherein the first groove exposes a first surface and a second surface of the active pillar group that are oppositely arranged along a first direction;

[0036] Performing ion implantation on the first surface and the second surface to form a second doped region in the second column, wherein the type of doping ions in the second doped region is different from the type of doping ions in the first doped region, and the second doped region is used to form a drain region;

[0037] removing the first mask strip;

[0038] forming a second dielectric layer in the first groove, wherein a top surface of the second dielectric layer is lower than a top surface of the columnar body;

[0039] forming a third dielectric layer on the second dielectric layer, wherein a top surface of the third dielectric layer is flush with a top surface of the columnar body;

[0040] forming second mask strips extending along the first direction on the third dielectric layer, wherein a plurality of the second mask strips are spaced apart along the second direction, and second openings are formed between adjacent second mask strips, wherein the second openings expose the third dielectric layer between two adjacent rows of the columnar bodies;

[0041] removing the third dielectric layer exposed in the second opening to form a second groove, wherein the second groove exposes a third surface and a fourth surface of the active pillar group that are oppositely arranged along the second direction;

[0042] Ion implantation is performed on the third surface and the fourth surface to form a third doping region in the second column. The type of doping ions in the third doping region is different from the type of doping ions in the second doping region and is the same as the type of doping ions in the first doping region. The third doping region is used to form a channel region.

[0043] In some embodiments, after the step of performing ion implantation on exposed surfaces opposite to each other of the second columns adjacent to each other along the first direction and before the step of removing the first mask strips, the preparation method further includes:

[0044] A first bit line and a second bit line are formed in the first groove, and the first bit line and the second bit line both extend along the second direction. The first bit line is connected to the drain region of the column corresponding to the first surface exposed in the first groove, and the second bit line is connected to the drain region of the column corresponding to the second surface exposed in the first groove.

[0045] In some embodiments, after the step of performing ion implantation on the exposed surfaces opposite to the second columns along the second direction, the preparation method further comprises:

[0046] forming a first word line and a second word line in the second groove, wherein the first word line and the second word line both extend along the first direction, and the first word line is connected to the channel region of the pillar corresponding to the third surface exposed in the second groove, and the second word line is connected to the channel region of the pillar corresponding to the fourth surface exposed in the first groove;

[0047] The second mask strip is removed.

[0048] In some embodiments, the step of providing a substrate comprises:

[0049] providing a substrate;

[0050] forming a first protective layer and a mask layer having a mask pattern on the substrate;

[0051] Ion doping is performed on the substrate to form a first doping region in the substrate. The substrate having the first doping region constitutes the base.

[0052] In some embodiments, after the step of removing a portion of the first dielectric layer exposed within the first opening and before the step of performing ion implantation on the exposed surfaces opposite to the second columns adjacent to each other along the first direction, the preparation method includes:

[0053] A second protective layer is formed on the second column exposed in the first groove, and the second protective layer is used to protect the second column.

[0054] In some embodiments, after the step of removing the third dielectric layer exposed in the second opening to form the second groove and before the step of performing ion implantation on the surface opposite to the second column exposed along the second direction, the preparation method further includes:

[0055] A third protective layer is formed on the second column exposed in the second groove, and the third protective layer is used to protect the second column.

[0056] In some embodiments, after the step of performing ion implantation on the third surface and the fourth surface and before the step of forming the first word line and the second word line in the second groove, the preparation method further includes:

[0057] A gate oxide layer is formed on the channel region.

[0058] In the semiconductor structure and preparation method provided in the embodiments of the present application, by providing a notch on at least one active column, the distance between the bottom wall of the notch that is recessed toward the center of the active column and another active column on the same row or column is increased, thereby increasing the migration path of electrons between the notch and the surface directly opposite the notch, reducing the risk of leakage between the active column provided with the notch and another active column on the same row or column, and improving the performance of the semiconductor structure.

[0059] In addition to the technical problems solved by the embodiments of the present application, the technical features that constitute the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor structure and the preparation method thereof provided by the embodiments of the present application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0061] Figure 1 A schematic diagram of a semiconductor structure provided in an embodiment of the present application;

[0062] Figure 2 for Figure 1 The main view;

[0063] Figure 3 for Figure 2 Cross-sectional view in the AA direction;

[0064] Figures 4 to 9 Schematic diagram of the structure of each active column;

[0065] Figure 10 A process flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0066] Figure 11 A schematic structural diagram of a substrate in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0067] Figure 12 A three-dimensional diagram of a mask used in a method for preparing a semiconductor structure according to an embodiment of the present application;

[0068] Figure 13 A top view of a mask in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0069] Figure 14 A schematic diagram of a structure for forming a columnar body in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0070] Figure 15 A schematic structural diagram of forming a first sub-dielectric layer in the method for preparing a semiconductor structure provided in an embodiment of the present application;

[0071] Figure 16 A schematic structural diagram of forming a second sub-dielectric layer in the method for preparing a semiconductor structure provided in an embodiment of the present application;

[0072] Figure 17 A schematic structural diagram of forming a first mask strip in the method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0073] Figure 18 A schematic structural diagram of forming a first groove in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0074] Figure 19 A schematic diagram of a structure for forming a first bit line and a second bit line in a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0075] Figure 20 A schematic structural diagram of forming a first mask strip in the method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0076] Figure 21 A schematic diagram of a structure for removing a first mask strip in a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0077] Figure 22 A schematic structural diagram of forming a second dielectric layer in the method for preparing a semiconductor structure provided in an embodiment of the present application;

[0078] Figure 23 A schematic structural diagram of forming a third dielectric layer in the method for preparing a semiconductor structure provided in an embodiment of the present application;

[0079] Figure 24 A schematic structural diagram of forming a second mask strip in the method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0080] Figure 25A schematic structural diagram of forming a first word line and a second word line in a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0081] Figure 26 A schematic structural diagram of forming a fourth dielectric layer in the method for preparing a semiconductor structure provided in an embodiment of the present application;

[0082] Figure 27 A schematic structural diagram of forming a mask block in the method for preparing a semiconductor structure provided in an embodiment of the present application;

[0083] Figure 28 A schematic diagram of a structure for forming a filling hole in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0084] Figure 29 A schematic structural diagram of an isolation structure formed in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0085] Figure 30 A schematic structural diagram of forming a mask layer in the method for preparing a semiconductor structure provided in an embodiment of the present application;

[0086] Figure 31 A three-dimensional diagram of a mask layer provided in an embodiment of the present application;

[0087] Figure 32 This is a schematic structural diagram of forming an active pillar group in the method for preparing a semiconductor structure provided in an embodiment of the present application.

[0088] Reference numerals:

[0089] 10: substrate; 11: first doped region; 20: active pillar group; 21: active pillar; 211: first pillar; 212: second pillar; 213: source region; 214: drain region; 215: channel region; 216: channel connection region; 22: notch; 23: first surface; 24: second surface; 25: third surface; 26: fourth surface; 27: mask; 271: first mask region; 272: second mask region; 30: column; 31: first column; 32: second column; 33: middle column; 40: : first dielectric layer; 41: first sub-dielectric layer; 42: second sub-dielectric layer; 43: first groove; 50: first mask stripe; 60: first opening; 70: first bit line; 80: second bit line; 90: second dielectric layer; 100: third dielectric layer; 110: second mask stripe; 120: second opening; 130: second groove; 140: first word line; 150: second word line; 160: fourth dielectric layer; 170: mask block; 180: filling hole; 190: isolation structure; 200: mask layer; 210: mask opening. DETAILED DESCRIPTION

[0090] As described in the background technology, there is a leakage problem between the active pillars of the semiconductor structure in the related art. The inventors have found that the reason for this problem is that the distance between adjacent active pillars is relatively short, resulting in a shorter transmission path for electrons from one active pillar to another active pillar, which in turn causes leakage between adjacent active pillars.

[0091] In response to the above-mentioned technical problems, in an embodiment of the present application, a notch is provided on at least one active column, so that the distance between the bottom wall of the notch which is concave toward the center of the active column and another active column on the same row or column is increased, thereby increasing the migration path of electrons between the notch and the surface opposite the notch, reducing the risk of leakage between the active column with the notch and another active column on the same row or column, and improving the performance of the semiconductor structure.

[0092] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0093] This embodiment does not limit the semiconductor structure. The semiconductor structure will be described below using a dynamic random access memory (DRAM) as an example, but this embodiment is not limited thereto. The semiconductor structure in this embodiment may also be other structures.

[0094] like Figure 1 As shown, the semiconductor structure provided by the embodiment of the present application may include a substrate 10 and an active column group 20, wherein the substrate 10 may serve as a supporting component of the semiconductor structure, for supporting the active column group 20 arranged on the substrate 10, wherein, wherein, the substrate 10 may be made of a semiconductor material, and the semiconductor material may be one or more of silicon, germanium, a silicon-germanium compound, and a silicon-carbon compound.

[0095] like Figure 2 As shown, the substrate 10 may have a first doped region 11 therein, and the first doped region may serve as an array region, wherein the array region is used to form a semiconductor device, for example, to form a transistor or a capacitor structure.

[0096] Illustratively, an active pillar group 20 is provided in the first doping region 11 , wherein the active pillar group 20 includes four active pillars 21 in an array. For example, the four active pillars 21 may be arranged in a matrix, that is, the four active pillars 21 may be arranged in two rows and two columns.

[0097] At least one active pillar 21 is provided with a notch 22 , and the notch 22 faces the row centerline and / or column centerline of the active pillar group 20 , that is, the notch faces the area surrounded by the four active pillars 21 .

[0098] It should be noted that, in this embodiment, the row center line can be understood as the center line between the first row of active pillars and the second row of active pillars, and the column center line can be understood as the center line between the first column of active pillars and the second column of active pillars.

[0099] This embodiment increases the distance between the bottom wall of the notch that is recessed toward the center of the active column and another active column in the same row or column by providing a notch on at least one active column, thereby increasing the migration path of electrons between the notch and the surface directly opposite the notch, reducing the risk of leakage between the active column with the notch and another active column in the same row or column, and improving the performance of the semiconductor structure.

[0100] In this embodiment, at least one active pillar 21 is provided with a notch 22 , which can be understood as one active pillar 21 being provided with a notch 22 , or two active pillars 21 being provided with notches 22 , or three active pillars 21 being provided with notches 22 , or all four active pillars 21 being provided with notches.

[0101] When an active pillar is provided with a notch, e.g. Figure 4 As shown, the notch 22 can be set on the right side of the first active pillar 21 in the first row, and the notch 22 can be oriented toward the column center line, for example, the notch 22 is oriented toward the second active pillar 21 in the first row; for example, Figure 5 As shown, the notch 22 may also be provided on the lower side of the first active pillar 21 in the first row, and the notch 22 may face the second active pillar 21 in the first column; furthermore, as shown Figure 6 As shown, the notch 22 can also be provided at the top corner of the first active pillar 21 in the first row facing the center of the area surrounded by the four active pillars 21 , and the notch is simultaneously facing the row center line and the column center line of the active pillar group.

[0102] When two active pillars 21 are provided with notches 22, the two notches 22 can be provided on two adjacent active pillars 21 and can be provided at intervals. When provided on two adjacent active pillars 21, the two notches 22 can be provided symmetrically, for example, Figure 7 As shown, one notch 22 may be provided on the first active pillar 21 in the first row, and another notch 22 may be provided on the second active pillar 21 in the first row, and the two notches 22 may be symmetrically provided with respect to the column center line.

[0103] When the three active pillars are provided with notches, the arrangement of the notches is similar to the above-mentioned arrangement, and is not listed here one by one in this embodiment.

[0104] When the notches 22 are provided on all four active pillars 21 , the notches 22 are provided in the following manner.

[0105] like Figure 8 As shown, each active pillar 21 includes a first pillar 211 and a second pillar 212 connected to the first pillar 211 , wherein the first pillar 211 may extend along a column direction, and the second pillar 212 may extend along a row direction.

[0106] In two active pillars 21 in the same row, the second pillar 212 is arranged on a side of the first pillar 211 facing the other first pillar 211, for example, Figure 8 As shown, the second pillar 212 of the first active pillar 21 in the first row is disposed on the right side of the first pillar 211 , and the second pillar 212 of the second active pillar 21 in the first row is disposed on the left side of the first pillar 211 .

[0107] It should be noted that, in this embodiment, the second pillar 212 can be disposed in the middle of the first pillar 211 so that the cross section of the active pillar 21 is T-shaped, or can be disposed at both ends of the first pillar 211 .

[0108] For example, Figure 9 As shown, in the two active pillars 21 in the same column, the second pillar 212 is arranged at one end of the first pillar 211 away from the other first pillar 211, and the notches 22 arranged on the two diagonally located active pillars 21 face opposite each other, so that the cross-sectional shape of the active pillar 21 is L-shaped.

[0109] Continue to refer Figure 9 The second column 212 of the first active column 21 in the first column is arranged at the upper end of the first column 211 of the active column 21, and the second column 212 of the second active column 21 in the first column is arranged at the lower end of the first column 211 of the active column 21. In addition, the arrangement of the first active column 21 and the second active column 21 in the second column are respectively the same as the arrangement of the first active column 21 and the second active column 21 in the first column, and this embodiment will not be described in detail here.

[0110] by Figure 9Taking the shown orientation as an example, if the electrons in the B region of the first active column 21 in the first row are to be transferred to the second active column in the first row, the length of the transmission path is L1. Compared with the transmission path L2 of the electrons in the C region to the second active column in the first row, the transmission path of the electrons in the B region is increased, thereby reducing the leakage risk between two adjacent active columns in the same row and improving the performance of the semiconductor structure.

[0111] In addition, if the electrons in the C region of the first active column 21 are to be transferred to the second active column in the first column, the length of the transmission path is L3. Compared with the transmission path L4 of the electrons in the B region to be transferred to the second active column in the first row, the transmission path of the electrons in the C region is increased, thereby reducing the leakage risk between two adjacent active columns in the same column and improving the performance of the semiconductor structure.

[0112] In this embodiment, a notch 22 is provided on each active pillar 21 so that the cross-sectional shape of the active pillar 21 is L-shaped, and the L-shaped opening is arranged toward the center of the active pillar group 20. This can reduce the leakage risk between adjacent active pillars in the same row and the leakage risk between adjacent active pillars in the same column, thereby improving the performance of the semiconductor structure.

[0113] Continue to refer Figure 1 The number of active pillar groups 20 may be multiple, and the multiple active pillar groups 20 may be arranged in an array in the substrate 10 . For example, the multiple active pillar groups 20 may be arranged in a rectangular array in the substrate.

[0114] In some embodiments, as Figure 3 As shown, along the direction perpendicular to the substrate 10, each active pillar 21 includes a channel region 215 and a source region 213 and a drain region 214 respectively arranged at both ends of the channel region. For example, each active pillar 21 includes a drain region 214, a channel region 215 and a source region 213 stacked in sequence from bottom to top along the direction perpendicular to the substrate 10.

[0115] Each active pillar group 20 further includes a channel connection region 216 . The drain regions 214 of each active pillar group 20 are connected to each other through the channel connection region 216 . The channel region 215 is connected to the channel connection region 216 . The channel connection region 216 is in contact with the substrate 10 .

[0116] In this embodiment, the drain regions 214 of each active pillar 21 are connected through a channel connection region 216, wherein the channel connection region 216 is used to connect the VBB voltage, so that the voltage of the drain region 214 of each active pillar 21 is the same and equal to the VBB voltage, thereby ensuring the critical voltage stability of the semiconductor structure and reducing the floating body effect.

[0117] In some embodiments, as Figure 3 As shown, the semiconductor structure further includes a plurality of first bit lines 70 and a plurality of second bit lines 80, which are alternately arranged along a first direction, and the first bit lines 70 and the second bit lines 80 extend along a second direction, and the first direction intersects the second direction.

[0118] The first direction is Figure 1 The X direction in the second direction is Figure 2 in the Y direction.

[0119] Along the first direction, each active pillar group 20 includes a first surface 23 and a second surface 24 arranged opposite to each other; the first bit line 70 is arranged on the first surface 23 and connects the drain regions 214 of each active pillar 21 located on the same column corresponding to the first surface 23; the second bit line 80 is arranged on the second surface 24 and connects the drain regions 214 of each active pillar 21 located on the same column corresponding to the second surface 24.

[0120] In this embodiment, the first bit line and the second bit line are arranged at the front and rear sides of the active pillar group, and the inner side of each active pillar in the active pillar group is connected to the VBB voltage, thereby reducing the floating body effect.

[0121] In some embodiments, as Figure 2 As shown, the semiconductor structure further includes a plurality of first word lines 140 and a plurality of second word lines 150 , which are alternately arranged along the second direction and extend along the first direction.

[0122] Along the second direction, each active pillar group 20 includes a third surface 25 and a fourth surface 26 arranged opposite to each other; the first word line 140 is arranged on the third surface 25 and connects the channel regions 215 of each active pillar 21 located on the same row corresponding to the third surface 25; the second word line 150 is arranged on the fourth surface 26 and connects the channel regions 215 of each active pillar 21 located on the same row corresponding to the fourth surface 26.

[0123] In this embodiment, the first bit line and the second bit line are arranged on the left and right sides of the active pillar group, so that the inner side of each active pillar in the active pillar group is connected to the VBB voltage, thereby reducing the floating body effect.

[0124] In some embodiments, the semiconductor structure further includes a plurality of isolation structures 190. Each isolation structure 190 is disposed within a region enclosed by the plurality of active pillars 21 in each active pillar group 20, and a bottom surface of the isolation structure 190 is higher than a top surface of the drain region 214. Furthermore, the bottom surface of the isolation structure 190 is also lower than a top surface of the channel region 215.

[0125] In this embodiment, the active pillars in the same active pillar group are connected together through the isolation structure, which can reduce the floating body effect.

[0126] In some embodiments, a capacitor (not shown) is disposed on each active pillar 21 , and a lower electrode layer of the capacitor is connected to the source region of the active pillar.

[0127] like Figure 10 As shown, the method for preparing a semiconductor structure provided in an embodiment of the present application includes the following steps:

[0128] Step S100: providing a substrate having a first doped region.

[0129] For example, Figure 11 As shown, the substrate 10 serves as a supporting component of the dynamic random access memory, and is used to support other components arranged thereon, wherein the substrate 10 has a first doping region 11, and the first doping region 11 may include an array region, and the array region is used to form a semiconductor device, for example, to form a transistor or a capacitor structure.

[0130] When forming the first doping region 11, the following method may be used:

[0131] First, a substrate is provided, wherein the material of the substrate may include silicon oxide.

[0132] Next, a first protection layer and a mask layer having a mask pattern are formed on the substrate.

[0133] For example, a first protective layer can be formed on a substrate through a deposition process, and then a photoresist layer of a certain thickness can be formed on the first protective layer through a coating process. The photoresist layer is then patterned by exposure, development or etching to form a mask layer having a mask pattern, wherein the mask pattern may include a mask opening.

[0134] Then, the substrate is ion doped using ion implantation technology. For example, doping ions can be implanted into the mask opening using ion implantation technology, so that the doping ions enter the substrate exposed in the mask opening to form a first doping region 11. The substrate having the first doping region 11 constitutes the base 10.

[0135] It should be noted that, in this embodiment, the doping ions in the first doping region may be P-type ions or N-type ions.

[0136] Step S200 : forming an active pillar group in the first doping region, wherein the active pillar group includes four active pillars arranged in an array, and at least one active pillar is provided with a notch, which faces a row center line and / or a column center line of the active pillar group.

[0137] Exemplarily: Step S210: providing a mask, the mask including a rectangular first mask area and multiple second mask areas, the four second mask areas are respectively set at the vertex positions of the first mask area, and each second mask area wraps the vertex position of the first mask area.

[0138] like Figure 12 and Figure 13 As shown, with the direction parallel to the substrate 10 as the cross section, the cross-sectional shape of the first mask area 271 is rectangular, the cross-sectional shape of the second mask area 272 is L-shaped, and the opening of the L-shaped second mask area 272 is toward the center of the first mask area 271.

[0139] Step S220: Using the mask as a mask, etching the substrate that is not blocked by the mask to form a column in the first doping region, wherein the column includes a first column and four second columns. The cross-section of the first column is a rectangle with a plane parallel to the substrate as the cross-section, and the four second columns are respectively arranged at the top corners of the first column, and each second column wraps the top corner of the first column.

[0140] In this embodiment, the mask 27 can be a positive photoresist layer. When the mask 27 is exposed or developed, the substrate 10 not blocked by the mask 27 will be etched away, and the retained substrate 10 constitutes a columnar body 30, and the columnar body 30 is located in the first doping region.

[0141] The columnar body 30 includes a first columnar body 31 and four second columnar bodies 32. With a plane parallel to the base 10 as a cross section, the cross-sectional shape of the first columnar body 31 is a rectangle. The four second columnar bodies 32 are respectively arranged at the top corners of the first columnar body 31, and each second columnar body 32 wraps around the top corner of the first columnar body 31.

[0142] It should be noted that, in this embodiment, the number of mask plates 27 can be one or more. When the number of mask plates 27 is one, a columnar body 30 will be formed in the substrate 10 accordingly; when the number of mask plates 27 is multiple, multiple mask plates 27 are used as masks to form multiple columns 30 in the substrate 10, and the multiple columns 30 are arranged in an array in the substrate 10.

[0143] For example, Figure 14 As shown, there are four columns 30 , which are arranged in two rows and two columns on the substrate 10 .

[0144] In some embodiments, after the step of using the mask as a mask and before the step of removing a portion of the thickness of the first column, the method for preparing the semiconductor structure further includes:

[0145] like Figure 15 and Figure 16 As shown, a first dielectric layer 40 covering each column 30 is formed on the substrate 10 , and the top surface of the first dielectric layer 40 is flush with the top surface of the column 30 .

[0146] For example, a first dielectric layer 40 may be formed on the substrate 10 by using a deposition process, wherein the first dielectric layer wraps around the side surfaces of each columnar body 30 .

[0147] The first dielectric layer 40 can be formed by a single deposition process or by two deposition processes, for example, Figure 16 As shown, the first dielectric layer 40 may include a first sub-dielectric layer 41 and a second sub-dielectric layer 42. For example, the first sub-dielectric layer 41 may be formed on the substrate 10 by a deposition process, and then the second sub-dielectric layer 42 may be formed on the first sub-dielectric layer 41 by another deposition process. The top surface of the second sub-dielectric layer 42 is flush with the top surface of the columnar body 30.

[0148] The materials of the first sub-dielectric layer 41 and the second sub-dielectric layer 42 can be the same or different. For example, the etching rate of the first sub-dielectric layer 41 is lower than the etching rate of the second sub-dielectric layer 42. In this way, the first sub-dielectric layer 41 can serve as an etching stop layer. When a partial thickness of the first dielectric layer 40 is subsequently etched, the thickness of the etched first dielectric layer 40 can be accurately controlled.

[0149] like Figure 17 As shown, after the first dielectric layer 40 is formed, a plurality of first mask strips 50 extending along the second direction are formed on the first dielectric layer 40. The plurality of first mask strips 50 are spaced apart along the first direction, and first openings 60 are formed between adjacent first mask strips 50. The first openings 60 expose the first dielectric layer 40 between two adjacent columns 30.

[0150] For example, a photoresist layer with a certain thickness can be formed on the first dielectric layer 40 by a coating process, and then the photoresist layer is patterned to form a plurality of first mask stripes 50 and openings between adjacent first mask stripes 50 in the photoresist layer.

[0151] In this embodiment, the first direction can be Figure 17 The X direction shown is the row direction; the second direction can be Figure 17 The Y direction shown is the column direction.

[0152] like Figure 18 As shown, a portion of the first dielectric layer 40 exposed in the first opening 60 is removed to form a first groove 43 . The first groove 43 exposes the first surface 23 and the second surface 24 of the active pillar group 20 that are oppositely disposed along the first direction.

[0153] For example, an etching solution or an etching gas may be used to remove the second sub-dielectric layer 42 exposed in the first opening 60 , so as to form a first groove 43 in the first dielectric layer 40 .

[0154] Along the first direction, the active pillar group 20 has a first surface 23 and a second surface 24 , wherein one first groove 43 may expose the first surface 23 of one of two adjacent active pillar groups 20 and the second surface 24 of the other active pillar group 20 .

[0155] Continue to refer Figure 18 After the first groove 43 is formed, ion implantation technology can be used to implant ions into the first surface 23 and the second surface 24 to form a second doped region in the second column. The type of doping ions in the second doped region is different from the type of doping ions in the first doped region 11. The second doped region is used to form a drain region.

[0156] It should be understood that the doping ions in the second doping region are different from the doping ions in the first doping region 11. For example, the doping ions in the first doping region 11 are P-type ions, and accordingly, the doping ions in the second doping region are N-type ions; for another example, the doping ions in the first doping region 11 are N-type ions, and accordingly, the doping ions in the second doping region are P-type.

[0157] In some embodiments, after removing a portion of the first dielectric layer to expose the first opening, and before performing ion implantation on the exposed surfaces opposite to the adjacent second columns along the first direction, the preparation method includes:

[0158] A second protective layer is formed on the second column 32 exposed in the first groove 43 , and is used to protect the second column to prevent damage to the first surface 23 and the second surface 24 . The material of the second protective layer may include:

[0159] After the second doping region is formed, the second protective layer is removed.

[0160] Afterwards, if Figure 19 As shown, a first bit line 70 and a second bit line 80 are formed in the first groove 43. The first bit line 70 and the second bit line 80 both extend along the second direction. The first bit line 70 is connected to the drain region of the columnar body 30 corresponding to the first surface 23 exposed in the first groove 43, and the second bit line 80 is connected to the drain region of the columnar body 30 corresponding to the second surface 24 exposed in the first groove 43.

[0161] For example, a bit line conductive layer can be first deposited in the first groove 43, and the bit line conductive layer fills the first groove 43, and the top surface of the bit line conductive layer is flush with the top surface of the columnar body, and then the bit line conductive layer is etched back. The retained bit line conductive layer constitutes the first bit line 70 and the second bit line 80, wherein the material of the first bit line 70 and the second bit line 80 may include tungsten.

[0162] In this embodiment, the first bit line and the second bit line are respectively arranged on the left and right sides of the column. Compared with the technical solution in the related art of arranging the bit line at the bottom of the column, the problem of unstable critical voltage of the component caused by the floating body effect can be reduced.

[0163] After the first word line and the second word line are formed, Figure 20 As shown, the first mask strip is removed using a cleaning solution.

[0164] After the first mask strip is removed, first, Figure 21 As shown, a second dielectric layer 90 is formed in the first groove by a deposition process. The top surface of the second dielectric layer 90 is lower than the top surface of the column 30. The material of the second dielectric layer 90 may include silicon oxide.

[0165] Afterwards, if Figure 22 As shown, a third dielectric layer 100 is formed on the second dielectric layer 90 by a deposition process. The top surface of the third dielectric layer 100 is flush with the top surface of the columnar body 30 . The material of the third dielectric layer 100 can be the same as or different from that of the second dielectric layer 90 .

[0166] In this embodiment, the second dielectric layer and the third dielectric layer are formed independently of each other in the first groove, so as to facilitate the subsequent etching back of the third dielectric layer.

[0167] like Figure 23 As shown, after the third dielectric layer 100 is formed, a second mask strip 110 extending along the first direction can be formed on the third dielectric layer 100. A plurality of second mask strips 110 are arranged at intervals along the second direction, and second openings 120 are formed between adjacent second mask strips 110. The second openings 120 expose the third dielectric layer 100 between two adjacent rows of columns.

[0168] like Figure 24 As shown, the third dielectric layer 100 exposed in the second opening 120 is removed by etching solution or etching gas to form a second groove 130 . The second groove 130 exposes the third surface 25 and the fourth surface 26 of the active pillar group that are oppositely arranged along the second direction.

[0169] Continue to refer Figure 24Ions are implanted into the third surface 25 and the fourth surface 26 using ion implantation technology to form a third doping region in the second column 32. The type of doping ions in the third doping region is different from the type of doping ions in the second doping region, and is the same as the type of doping ions in the first doping region. The third doping region is used to form a channel region.

[0170] It should be noted that when the doping ions in the first doping region are P-type ions and the doping ions in the third doping region are P-type ions, that is, the doping ions in the channel region are P-type ions, this embodiment uses the second dielectric layer 90 to protect the second doping region that has been formed on the columnar body, preventing the doping ions used to form the third doping region from penetrating into the second doping region, thereby improving the performance of the semiconductor structure.

[0171] After the step of removing the third dielectric layer exposed in the second opening to form the second groove, and before the step of performing ion implantation on the surface opposite to the second column exposed along the second direction, the method for preparing the semiconductor structure further includes:

[0172] A third protective layer is formed on the second column 32 exposed in the second groove 130 . The third protective layer is used to protect the second column 32 from damage to the third surface and the fourth surface. The material of the third protective layer may include:

[0173] After the third doping region is formed, the third protection layer is removed.

[0174] Afterwards, continue to refer to Figure 24 A first word line 140 and a second word line 150 are formed in the second groove 130. The first word line 140 and the second word line 150 both extend along the first direction. The first word line 140 connects the channel region of the column 30 corresponding to the third surface 25 exposed in the second groove 130, and the second word line 150 connects the channel region of the column 30 corresponding to the fourth surface 26 exposed in the first groove 43.

[0175] Illustratively, a word line conductive layer can be formed in the second groove 130, which fills the second groove 130, and the top surface of the word line conductive layer is aligned with the top surface of the column. Then, the word line conductive layer is etched back to form a first word line 140 and a second word line 150 spaced apart in the second groove 130, wherein the materials of the first word line 140 and the second word line 150 include titanium nitride and polysilicon.

[0176] In this embodiment, the first word line and the second word line are respectively arranged on both sides of the column.

[0177] like Figure 25 As shown, after the first word line 140 and the second word line 150 are formed, the second mask strip 110 is removed using a cleaning solution.

[0178] It should be noted that, after the step of performing ion implantation on the third surface and the fourth surface and before the step of forming the first word line and the second word line in the second groove, the method for preparing the semiconductor structure further includes:

[0179] A gate oxide layer is formed on the channel region by using an atomic layer deposition process, wherein the material of the gate oxide layer may have a high dielectric constant, for example, the material of the gate oxide layer includes aluminum oxide.

[0180] Step S300: removing a portion of the thickness of the first columnar body, and each of the remaining second columns constitutes a middle active column.

[0181] For example, Figure 26 As shown, a fourth dielectric layer 160 is deposited in the second groove 130 , and the top surface of the fourth dielectric layer 160 is flush with the top surface of the column 30 .

[0182] like Figure 27 As shown, a plurality of mask blocks 170 are formed on the fourth dielectric layer 160 , and the projection of each mask block 170 on the fourth dielectric layer 160 covers each first column 31 , and the mask block 170 may be a negative photoresist.

[0183] like Figure 28 As shown, after the mask block 170 is formed, the first columnar body 31 partially blocked by the mask block 170 is removed to form a filling hole 180. The bottom of the filling hole 180 is the upper surface of the first sub-dielectric layer 41. Each second columnar body 32 is retained to form an intermediate columnar body 33.

[0184] like Figure 29 As shown, an isolation structure 190 is formed in the filling hole 180 by a deposition process, and a top surface of the isolation structure 190 is flush with a top surface of the middle column 33 .

[0185] like Figure 29 and Figure 31 As shown, after the isolation structure 190 is formed, a mask layer 200 is formed on the fourth dielectric layer 160 . The mask layer 200 has a plurality of mask openings 210 . Each mask opening 210 is L-shaped, and each mask opening 210 exposes a middle column 33 .

[0186] Then, if Figure 30 As shown, ion implantation is performed on the top surface of the middle column 33 to form a source region on the top surface of the middle column 33. The middle column with the source region formed thereon constitutes an active column 21. Four active columns 21 constitute an active column group 20, and the structure is as shown in FIG. Figure 32 shown.

[0187] In the active column group prepared in the above manner in this embodiment, a notch is provided on each active column, so that the cross-sectional shape of the active column is L-shaped, and the L-shaped openings are all arranged toward the center of the active column group, that is, the leakage risk between adjacent active columns in the same row can be reduced, and the leakage risk between adjacent active columns in the same column can also be reduced, thereby improving the performance of the semiconductor structure.

[0188] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0189] In the description of this specification, reference to terms such as "one embodiment", "some embodiments", "illustrative embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application.

[0190] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any suitable manner in any one or more embodiments or examples.

[0191] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor structure, characterized in that include: a substrate having a first doped region therein; an active pillar group disposed in the first doped region, the active pillar group comprising four active pillars arranged in an array, at least one of the active pillars being provided with a notch, the notch being oriented toward a row centerline and / or a column centerline of the active pillar group and extending in a direction perpendicular to the substrate, each of the active pillars comprising a channel region and a source region and a drain region respectively disposed at opposite ends of the channel region; A plurality of isolation structures are provided, each of the isolation structures is arranged in a region surrounded by a plurality of active pillars in each active pillar group, and a bottom surface of the isolation structure is higher than a top surface of the drain region.

2. The semiconductor structure according to claim 1, wherein: Each of the active pillars includes a first pillar and a second pillar connected to the first pillar; In two active pillars in the same row, the second pillar is arranged on a side of the first pillar facing the other first pillar.

3. The semiconductor structure according to claim 2, wherein: In the two active pillars in the same column, the second pillar is arranged at an end of the first pillar away from the other first pillar, and the notches arranged on the two diagonally opposite active pillars face oppositely.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: There are multiple active pillar groups, and the multiple active pillar groups are arranged in an array in the substrate.

5. The semiconductor structure according to claim 1, wherein: The active pillar group further includes a channel connection region, and each active pillar includes a drain region, a channel region, and a source region stacked sequentially from bottom to top along a direction perpendicular to the substrate; In each of the active pillar groups, the drain regions of the active pillars are connected to each other through the channel connection region, the channel regions are connected to the channel connection region, and the channel connection region is in contact with the substrate.

6. The semiconductor structure according to claim 5, wherein: Also included are a plurality of first bit lines and a plurality of second bit lines, wherein the plurality of first bit lines and the plurality of second bit lines are alternately arranged along a first direction, and the first bit lines and the second bit lines extend along a second direction, and the first direction intersects the second direction; Along the first direction, each of the active pillar groups includes a first surface and a second surface arranged opposite to each other; the first bit line is arranged on the first surface and connects the drain regions of each active pillar located on the same column corresponding to the first surface; the second bit line is arranged on the second surface and connects the drain regions of each active pillar located on the same column corresponding to the second surface.

7. The semiconductor structure according to claim 6, wherein: Also included are a plurality of first word lines and a plurality of second word lines, wherein the plurality of first word lines and the plurality of second word lines are alternately arranged along a second direction, and the first word lines and the second word lines extend along the first direction; Along the second direction, each of the active pillar groups includes a third surface and a fourth surface arranged opposite to each other; the first word line is arranged on the third surface and connects the channel regions of each active pillar located on the same row corresponding to the third surface; the second word line is arranged on the fourth surface and connects the channel regions of each active pillar located on the same row corresponding to the fourth surface.

8. The semiconductor structure according to claim 1, wherein: A capacitor is provided on each of the active pillars.

9. A method for preparing a semiconductor structure, characterized in that: The steps include: providing a substrate having a first doped region; forming an active pillar group in the first doping region, the active pillar group including four active pillars arranged in an array, at least one of the active pillars being provided with a notch, the notch being oriented toward a row centerline and / or a column centerline of the active pillar group; The step of forming an active pillar group in the first doping region includes: Providing a mask, the mask comprising a rectangular first mask area and four second mask areas, the four second mask areas being respectively arranged at vertex corners of the first mask area, and each second mask area wraps around a vertex corner of the first mask area; Using the mask as a mask, etching the substrate not blocked by the mask to form columns in the first doped region, wherein the columns include a first column and four second columns, wherein the cross-section of the first column is rectangular, with a plane parallel to the substrate as a cross-section, and the four second columns are respectively arranged at the vertex corners of the first column, and each second column wraps around the vertex corner of the first column; Removing a portion of the thickness of the first columnar body to form a filling hole in the first columnar body, and each of the remaining second columnar bodies constitutes an intermediate columnar body; forming an isolation structure in the filling hole, wherein a top surface of the isolation structure is flush with a top surface of the middle column; Ion implantation is performed on the top surface of each intermediate column to form a source region on the top surface of the intermediate column. The intermediate column with the source region formed thereon constitutes an active column, and four active columns constitute an active column group.

10. The method for preparing a semiconductor structure according to claim 9, wherein: There are a plurality of pillars, and a plurality of the pillars are arranged in an array in the base.

11. The method for preparing a semiconductor structure according to claim 10, wherein: After the step of using the mask as a mask and before the step of removing a portion of the thickness of the first columnar body, the preparation method further includes: forming a first dielectric layer covering each of the pillars on the substrate, wherein the top surface of the first dielectric layer is flush with the top surface of the pillars; forming a plurality of first mask strips extending along the second direction on the first dielectric layer, wherein the plurality of first mask strips are spaced apart along the first direction, and first openings are formed between adjacent first mask strips, wherein the first openings expose the first dielectric layer between two adjacent columns of the columnar bodies; removing a portion of the first dielectric layer exposed in the first opening to form a first groove, wherein the first groove exposes a first surface and a second surface of the active pillar group that are oppositely arranged along a first direction; Performing ion implantation on the first surface and the second surface to form a second doped region in the second column, wherein the type of doping ions in the second doped region is different from the type of doping ions in the first doped region, and the second doped region is used to form a drain region; removing the first mask strip; forming a second dielectric layer in the first groove, wherein a top surface of the second dielectric layer is lower than a top surface of the columnar body; forming a third dielectric layer on the second dielectric layer, wherein a top surface of the third dielectric layer is flush with a top surface of the columnar body; forming second mask strips extending along the first direction on the third dielectric layer, wherein a plurality of the second mask strips are spaced apart along the second direction, and second openings are formed between adjacent second mask strips, wherein the second openings expose the third dielectric layer between two adjacent rows of the columnar bodies; removing the third dielectric layer exposed in the second opening to form a second groove, wherein the second groove exposes a third surface and a fourth surface of the active pillar group that are oppositely arranged along the second direction; Ion implantation is performed on the third surface and the fourth surface to form a third doping region in the second column. The type of doping ions in the third doping region is different from the type of doping ions in the second doping region and is the same as the type of doping ions in the first doping region. The third doping region is used to form a channel region.

12. The method for preparing a semiconductor structure according to claim 11, wherein: After the step of performing ion implantation on exposed surfaces of the second columns adjacent to each other along the first direction and facing away from each other, and before the step of removing the first mask strips, the preparation method further comprises: A first bit line and a second bit line are formed in the first groove, and the first bit line and the second bit line both extend along the second direction. The first bit line is connected to the drain region of the column corresponding to the first surface exposed in the first groove, and the second bit line is connected to the drain region of the column corresponding to the second surface exposed in the first groove.

13. The method for preparing a semiconductor structure according to claim 11, wherein: After the step of performing ion implantation on the exposed surfaces opposite to the second columns along the second direction, the preparation method further comprises: forming a first word line and a second word line in the second groove, wherein the first word line and the second word line both extend along the first direction, and the first word line is connected to the channel region of the pillar corresponding to the third surface exposed in the second groove, and the second word line is connected to the channel region of the pillar corresponding to the fourth surface exposed in the first groove; The second mask strip is removed.

14. The method for preparing a semiconductor structure according to any one of claims 9 to 13, wherein: The step of providing a substrate comprises: providing a substrate; forming a first protective layer and a mask layer having a mask pattern on the substrate; Ion doping is performed on the substrate to form a first doping region in the substrate. The substrate having the first doping region constitutes the base.

15. The method for preparing a semiconductor structure according to claim 11, wherein: After the step of removing a portion of the first dielectric layer exposed in the first opening and before the step of performing ion implantation on the exposed surfaces opposite to the second columns adjacent to each other along the first direction, the preparation method includes: A second protective layer is formed on the second column exposed in the first groove, and the second protective layer is used to protect the second column.

16. The method for preparing a semiconductor structure according to claim 15, wherein: After the step of removing the third dielectric layer exposed in the second opening to form a second groove, and before the step of performing ion implantation on the surface opposite to the second column exposed along the second direction, the preparation method further includes: A third protective layer is formed on the second column exposed in the second groove, and the third protective layer is used to protect the second column.

17. The method for preparing a semiconductor structure according to claim 16, wherein: After the step of performing ion implantation on the third surface and the fourth surface and before the step of forming the first word line and the second word line in the second groove, the preparation method further includes: A gate oxide layer is formed on the channel region.

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