Resistive random access memory device and method of manufacturing the same

Abstract

The present application provides a resistive random access memory device and a manufacturing method thereof, wherein the resistive random access memory device comprises a dielectric layer above a substrate, a first electrode above the dielectric layer, wherein the first electrode is a columnar body, a second electrode covering sidewalls and a top surface of the first electrode, and a variable resistance layer between the top surface of the first electrode and the second electrode, between the sidewalls of the first electrode and the second electrode, and between the second electrode and the dielectric layer.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a memory device and a manufacturing method thereof, and more particularly to a resistive random access memory (RRAM) and a manufacturing method thereof. BACKGROUND

[0002] Resistive random access memory is a kind of non-volatile memory which has been widely studied in recent years, and has the advantages of fast operation speed and low power consumption. When a resistive random access memory cell performs a set (SET) operation, a variable resistance layer between two electrodes will form a conductive filament and present a conductive state, at which time the variable resistance layer is converted from a high resistance state (HRS) to a low resistance state (LRS). When the RRAM cell performs a reset (RESET) operation, a negative bias is applied to the resistive random access memory, the conductive filament is broken and presents a non-conductive state, at which time the variable resistance layer is converted from LRS to HRS. However, if the conductive filament generated in the variable resistance layer is insufficient, it will result in insufficient current flow in the low resistance state (LRS). SUMMARY

[0003] Embodiments of the present application provide a resistive random access memory cell and a manufacturing method thereof, which can increase the conductive filament in the variable resistance layer and improve the current flow in the low resistance state (LRS).

[0004] According to an embodiment of the present application, a resistive random access memory device includes a dielectric layer above a substrate, a first electrode above the dielectric layer, wherein the first electrode is a columnar body, a second electrode covering a sidewall and a top surface of the first electrode, and a variable resistance layer between the top surface of the first electrode and the second electrode, between the sidewall of the first electrode and the second electrode and between the second electrode and the dielectric layer.

[0005] According to an embodiment of the present application, a method of fabricating a resistive random access memory device, comprising: forming a dielectric layer over a substrate; forming a first electrode material layer over the dielectric layer; patterning the first electrode material layer to form a first electrode; forming a variable resistance layer over a top surface and sidewalls of the first electrode and the dielectric layer; forming a second electrode material layer over the variable resistance layer; and patterning the second electrode material layer and the variable resistance layer to form a second electrode and a variable resistance layer; and the variable resistance layer is sandwiched between the top surface of the first electrode and the second electrode, between the sidewalls of the first electrode and the second electrode and between the second electrode and the dielectric layer.

[0006] Based on the above, the resistive random access memory unit and the method of fabricating the same can increase the number of conductive wires in the variable resistance layer, and improve the current in the low resistance state. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figures 1A-1G is a cross-sectional view of a method of fabricating a resistive random access memory according to an embodiment of the present application;

[0008] Figure 2A and Figure 2B is a top view of various resistive random access memories according to embodiments of the present application;

[0009] Figure 3 is a partial perspective view of a resistive random access memory unit according to an embodiment of the present application;

[0010] Figure 4 shows Figure 3 is a partial enlarged view of DETAILED DESCRIPTION

[0011] Reference will now be made in detail to exemplary embodiments of the present application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the drawings and the description to refer to the same or like parts.

[0012] Please refer to Figure 1AA substrate 100 is provided. The substrate 100 may be a semiconductor substrate, such as doped or undoped bulk silicon, or an active layer of a silicon-on-insulator (SOI) substrate. A device layer 102 may be formed on the substrate 100. The device layer 102 may include active devices or passive devices. Active devices include, for example, transistors, diodes, etc. Passive devices include, for example, capacitors, resistors, inductors, etc. Transistors may be N-type metal-oxide-semiconductor (NMOS) transistors, P-type metal-oxide-semiconductor (PMOS) transistors, or complementary metal-oxide-semiconductor (CMOS) devices. Transistors may be planar transistors, fin field-effect transistors (FinFETs), nanowire transistors, etc. The device layer 102 may be formed using any suitable method.

[0013] Please refer to Figure 1A A metal interconnect structure 112 is formed on device layer 102. The metal interconnect structure 112 can be formed from alternating layers of dielectric and conductive materials, and can be formed via any suitable process (e.g., deposition, damascene, dual damascene, etc.). The metal interconnect structure 112 may include dielectric layers 104, 110 and metal interconnects 107 formed in the multilayer dielectric layer 104. The metal interconnects 107 are electrically connected to device layer 102. The metal interconnects 107 may include plugs 105 and wires 106, etc. The materials of plugs 105 and wires 106 include a barrier layer (or adhesive layer) and a metal layer formed on the barrier layer. The barrier layer is, for example, a composite layer of titanium, titanium nitride, tantalum, tantalum nitride, or combinations thereof. The metal layer is, for example, tungsten or copper.

[0014] exist Figures 1A-1G The diagram only shows a single dielectric layer 104, a single plug 105, and a single conductor 106. However, the metal interconnect structure 112 may include multiple dielectric layers 104, multiple plugs 105, and multiple conductors 106. The dielectric layers 104 separate adjacent conductors 106. The conductors 106 can be connected to each other via plugs 105, and the conductors 106 can be connected to the device layer 102 via plugs 105. In some embodiments, the metal interconnect structure 112 further includes a stop layer 108. The stop layer 108 may be disposed between the dielectric layers 104 and 110. The material of the stop layer 108 is different from the materials of the dielectric layers 104 and 110, for example, nitrogen-doped silicon carbide (NDC), silicon nitride, silicon oxynitride, silicon carbide, or a combination thereof. The stop layer 108 may be formed by, for example, chemical vapor deposition. The dielectric layer 110 may be a planarized layer planarized by a chemical mechanical polishing process.

[0015] Please refer to Figure 1AA barrier material layer 120 is formed over the dielectric layer 110. The barrier material layer 120 can be a nitrogen-containing dielectric material layer, such as silicon nitride. The barrier material layer 120 can be formed by a chemical vapor deposition process. The barrier material layer 120 can block diffusion of the metal (e.g., copper) in the conductive line 106 into a film layer formed thereover.

[0016] Please refer to Figure 1B A via 114 is formed in the barrier material layer 120, the dielectric layer 110, and the stop layer 108 to electrically connect the conductive line 106. The via 114 can be formed by a photolithography and etching process. A conductive material layer is formed over the barrier material layer 120 and in the via 114. The conductive material layer includes a metal layer and a barrier layer (or adhesion layer) over the metal layer. The barrier layer can be titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof. The metal layer can be tungsten. A planarization process, such as a chemical mechanical polishing process, is then performed to remove the conductive material layer over the barrier material layer 120. In some embodiments, a top surface of the via 114 is coplanar with a top surface of the barrier material layer 120.

[0017] Please refer to Figure 1C A first electrode material layer 122 is formed over the barrier material layer 120. The first electrode material layer 122 can be titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), titanium tungsten (TiW) alloy, platinum (Pt), iridium (Ir), ruthenium (Ru), titanium (Ti), tungsten (W), tantalum (Ta), aluminum (Al), zirconium (Zr), hafnium (Hf), nickel (Ni), copper (Cu), cobalt (Co), iron (Fe), gadolinium (Gd), molybdenum (Mo), graphite, or a combination thereof.

[0018] Please refer to Figure 1D A photolithography and etching process is performed to pattern the first electrode material layer 122 to form a first electrode 122a that is electrically connected to the via 114. The first electrode 122a can be a columnar body, such as a cylindrical body or a hexahedral body (as shown in Figure 3 and Figure 4 ). A top surface of the first electrode 122a can have a top view that is a circle, a rectangle with rounded corners, or the like, as shown in Figure 2A and Figure 2B , respectively. The top surface of the first electrode 122a can have other various shapes, such as an ellipse or the like.

[0019] Please refer to Figure 1EA variable resistance material layer 124 is formed on the top surface and sidewalls of the first electrode 122a and the blocking material layer 120. In some embodiments, the variable resistance material layer 124 is a conformal layer conformally covering the top surface and sidewalls of the first electrode 122a and the blocking material layer 120. In some embodiments, the blocking material layer 120 is a planar layer, and thus, the bottom surface of the variable resistance material layer 124 is coplanar with the bottom surface of the first electrode 122a. The material of the variable resistance material layer 124 includes a metal oxide, such as hafnium oxide (Hf02), tantalum oxide (Ta205), titanium oxide (Ti02), magnesium oxide (MgO), nickel oxide (NiO), niobium oxide (Nb205), aluminum oxide (AI2O3), vanadium oxide (V205), tungsten oxide (W03), zinc oxide (ZnO), or cobalt oxide (CoO).

[0020] Referring to Figure 1F A second electrode material layer 126 is formed on the variable resistance material layer 124. The second electrode material layer 126 is, for example, titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (TiAIN), titanium tungsten (TiW) alloy, platinum (Pt), iridium (Ir), ruthenium (Ru), titanium (Ti), tungsten (W), tantalum (Ta), aluminum (Al), zirconium (Zr), hafnium (Hf), nickel (Ni), copper (Cu), cobalt (Co), iron (Fe), gadolinium (Gd), molybdenum (Mo), graphite, or a combination thereof. The second electrode material layer 126 can be a single layer or a double layer. In some embodiments, the second electrode material layer 126 is a double layer, in which the upper layer can be titanium nitride or tantalum nitride, and the lower layer can be iridium. The thickness H2 of the second electrode material layer 126 can be greater than, equal to, or less than the thickness H1 of the first electrode 122a. The second electrode material layer 126 can have a planar surface (as shown), or be conformal to the variable resistance material layer 124 (not shown). Figure 1E

[0021] Referring to Figure 1F A photolithography and etching process is performed to pattern the second electrode material layer 126, the variable resistance material layer 124, and the blocking material layer 120 to form a second electrode 126a, a variable resistance layer 124a, and a blocking pad 120a. In some embodiments, the second electrode 126a, the variable resistance layer 124a, and the blocking pad 120a have trimmed sidewalls.

[0022] Referring to Figure 1G ​A spacer 128 is formed on the sidewalls of the second electrode 126a, the variable resistance layer 124a, and the blocking pad 120a. The spacer 128 includes a dielectric material layer containing nitrogen, such as silicon nitride. The spacer 128 and the blocking pad 120a can include the same material. The spacer 128 is formed by, for example, forming a spacer material layer to cover the sidewalls of the second electrode 126a, the variable resistance layer 124a, and the blocking pad 120a, and the surface of the dielectric layer 110, and then performing an anisotropic etching process.

[0023] At this point, the resistive random access memory 150 is formed. The resistive random access memory 150 has the spacer 128 and the blocking pad 120a covering the sidewalls and the bottom surface of the variable resistance layer 124a, respectively, and the spacer 128 extending upward to cover the lower sidewalls of the second electrode 126. In some embodiments, the spacer 128 covers 1 / 2 to 2 / 3 of the sidewalls of the second electrode 126. The spacer 128 and the blocking pad 120a can jointly block the diffusion of water vapor, metal atoms (such as copper atoms), or oxygen into the variable resistance layer 124a.

[0024] Referring to Figure 1G and Figure 3 The first electrode 122a of the resistive random access memory 150 of the embodiments of the present application is a columnar body. The variable resistance layer 124a is sandwiched between the top surface of the first electrode 122a and the second electrode 126a, and between the sidewalls of the first electrode 122a and the second electrode 126a. Moreover, the variable resistance layer 124a is located between the bottom surface of the second electrode 126a and the blocking pad 120a. The variable resistance layer 124a can be separated from the dielectric layer 110 by a non-zero distance through the blocking pad 120a to avoid contacting the dielectric layer 110, thereby preventing the diffusion of oxygen in the dielectric layer 110 to the variable resistance layer 124a.

[0025] Referring to Figure 1G and Figure 4When a SET operation is performed, a positive voltage is applied to the resistive random access memory 150, and oxygen ions in the variable resistance layer 124a are attracted away by the positive voltage to generate oxygen vacancies, thus forming a conductive filament 130 and presenting a conductive state, at which time the variable resistance layer is converted from a high resistance state (HRS) to a low resistance state (LRS). When a RESET operation is performed, a negative bias voltage is applied to the resistive random access memory 150, and the oxygen ions return to the variable resistance layer 124a, causing the conductive filament 130 to break and present a non-conductive state, at which time the variable resistance layer is converted from the LRS to the HRS. In the embodiment of the present application, since the first electrode 122a is in the form of a columnar body, and the variable resistance layer 124a covers the top surface and the sidewall of the columnar body, a plurality of conductive filaments 130 can be formed in the variable resistance layer 124a on the top surface and the sidewall of the first electrode 122a.

[0026] The structure of the resistive random access memory of the embodiment of the present application can form conductive filaments in more areas, thus increasing the current flow in the low resistance state of the resistive random access memory unit.

[0027] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A resistive random access memory device, characterized in that, The resistive random access memory device includes: Dielectric layer, located above the substrate; and The first electrode is a columnar body located above the dielectric layer; The second electrode covers the sidewall and top surface of the first electrode; A variable resistance layer is sandwiched between the top surface of the first electrode and the second electrode, between the sidewall of the first electrode and the second electrode, and located between the second electrode and the dielectric layer; and Spacers, at least covering the sidewalls of the variable resistance layer.

2. The resistive random access memory device according to claim 1, wherein the top surface of the second electrode is a circle and a rectangle with rounded bevels.

3. The resistive random access memory device according to claim 1, wherein the bottom surface of the second electrode is annular.

4. The resistive random access memory device according to claim 1, wherein the bottom surface of the variable resistance layer is coplanar with the bottom surface of the first electrode.

5. The resistive random access memory device according to claim 1, wherein the variable resistance layer is separated from the dielectric layer by a non-zero distance.

6. The resistive random access memory device according to claim 5, further comprising: A barrier pad is located on the dielectric layer to separate the bottom surface of the variable resistance layer from the dielectric layer.

7. The resistive random access memory device of claim 6, wherein the blocking pad comprises a nitrogen-containing dielectric material layer.

8. The resistive random access memory device of claim 7, wherein the material of the nitrogen-containing dielectric layer comprises silicon nitride.

9. The resistive random access memory device of claim 6, wherein the spacer further extends to cover the lower sidewall of the second electrode and the sidewall of the barrier pad.

10. The resistive random access memory device of claim 1, wherein the spacer comprises a nitrogen-containing dielectric material layer.

11. The resistive random access memory device of claim 10, wherein the material of the nitrogen-containing dielectric layer comprises silicon nitride.

12. The resistive random access memory device of claim 6, wherein the spacer and the barrier pad comprise the same material.

13. A method for manufacturing a resistive random access memory device, characterized in that, The manufacturing method includes: A dielectric layer is formed above the substrate; A first electrode material layer is formed above the dielectric layer; The first electrode material layer is patterned to form the first electrode; A variable resistance material layer is formed on the top surface and sidewalls of the first electrode and above the dielectric layer; A second electrode material layer is formed on the variable resistance material layer; The second electrode material layer and the variable resistance material layer are patterned to form the second electrode and the variable resistance layer, wherein... The second electrode covers the sidewall and top surface of the first electrode; The variable resistance layer is sandwiched between the top surface of the first electrode and the second electrode, between the sidewall of the first electrode and the second electrode, and located between the second electrode and the dielectric layer; and Spacers are formed on the sidewalls of the variable resistance layer.

14. The method of manufacturing a resistive random access memory device according to claim 13, further comprising: Before forming the first electrode material layer, a barrier material layer is formed on the dielectric layer; as well as After patterning the second electrode material layer and the variable resistance material layer, the barrier material layer is patterned to form a barrier pad.

15. The method of manufacturing a resistive random access memory device according to claim 14, further comprising: The spacer is formed on the sidewall of the second electrode and the blocking pad.

16. The method of manufacturing a resistive random access memory device according to claim 15, wherein the spacer and the barrier material layer comprise the same material.

17. The method of manufacturing a resistive random access memory device according to claim 15, wherein the spacer and the barrier material layer comprise a nitrogen-containing dielectric material layer.

18. The method of manufacturing a resistive random access memory device according to claim 17, wherein the material of the nitrogen-containing dielectric material layer comprises silicon nitride.

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