Target layout optimization method

Abstract

The present invention provides a target layout optimization method, comprising: performing OPC correction on a first metal layer pattern using a standard model to obtain a first OPC pattern; simulating the first OPC pattern using a process window model to obtain a simulated pattern, and marking a bridge pattern and a broken line pattern therefrom; selecting a first pattern edge where the first metal layer contacts the bridge pattern and moving it a first distance to obtain a second metal layer pattern; selecting a second pattern edge where the second metal layer pattern contacts the broken line pattern and moving it a second distance to obtain a first target pattern; selecting a third pattern edge where the first target pattern contacts the bridge pattern and moving it a first distance in an inner direction of the pattern to obtain a third metal layer pattern; selecting a fourth pattern edge where the third metal layer pattern contacts the broken line pattern and moving it a second distance in an outer direction of the pattern to obtain a second target pattern; performing OPC correction on the second target pattern based on a standard model and a process window model to obtain a second OPC pattern.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a target layout optimization method. Background Art

[0002] The optimization of metal target graphics is one of the key steps in the optical proximity correction of the metal layer. In order to improve the photolithography process window of the metal layer in the lithography process, a large number of selective size optimizations are applied to the layout correction process. The traditional metal layer target size optimization is a rule-based optimization. By collecting the silicon wafer sizes of graphics of different sizes and pitches, the photolithography process windows of different graphics are calculated to determine the minimum required target size under different pitches, and based on this, the metal layer layout target size optimization rules are formulated. The metal layer layout target optimization is performed based on the target optimization rules, and then the model-based OPC correction processing is performed to obtain the final mask template graphics.

[0003] The rule-based metal layer target size optimization is based on one-dimensional (1D) size, while the actual metal layer layout graphics contain a large number of two-dimensional (2D) graphics. It is not accurate to optimize the target size based on this. In addition, for one-dimensional graphics, the surrounding environment of the actual layout is quite different from the strict test graphics. There will be large deviations when optimizing the target graphics based on the results obtained from the strict test graphics. Therefore, in the process of optimizing the target graphics of the actual metal layer layout, in order to ensure sufficient process windows, the target size is usually over-adjusted to avoid defects such as bridges or pinches in the photolithography process. However, over-adjusting the target size not only affects the electrical performance of the product, but also causes the metal layer to have poor coverage of the through-hole layer, which in turn affects the connectivity of the upper and lower layers, thereby affecting the product yield. Figure 1 The figure shows an example of a conventional metal layer target after adjustment. From the initial figure 110 to the target figure 120, the through-hole figure 130 is partially covered. Therefore, the OPC correction is performed using the target figure 120. The simulation figure 140 shows that the coverage of the metal layer on the through-hole figure 130 is reduced, as shown in FIG. Figure 2 shown. Summary of the invention

[0004] The purpose of the present invention is to provide a target layout optimization method, which can optimize a better target layout pattern and improve the coverage of the metal layer pattern on the through-hole pattern.

[0005] In order to achieve the above object, the present invention provides a target layout optimization method, comprising:

[0006] Inputting a first metal layer pattern and a through hole pattern corresponding to the first metal layer pattern;

[0007] Performing a first OPC correction on the first metal layer pattern using a standard model to obtain a first OPC pattern;

[0008] Simulating the first OPC pattern using a process window model to obtain a simulated pattern, and marking a bridge pattern and a disconnection pattern from the simulated pattern according to a bridge specification and a disconnection specification;

[0009] Selecting a first pattern edge where the first metal layer contacts the bridge pattern, and moving the first pattern edge toward the inside of the bridge pattern by a first distance to obtain a second metal layer pattern;

[0010] Selecting a second pattern edge of the second metal layer pattern that contacts the broken line pattern, and moving the second pattern edge toward the outside of the broken line pattern by a second distance to obtain a first target pattern;

[0011] Selecting a third pattern edge where the first target pattern contacts the bridge pattern, and moving the third pattern edge toward the inside of the bridge pattern by a first distance to obtain a third metal layer pattern;

[0012] Selecting a fourth pattern edge of the third metal layer pattern in contact with the broken line pattern, and moving the fourth pattern edge toward the outside of the broken line pattern by a second distance to obtain a second target pattern; and

[0013] The second target pattern is subjected to OPC correction based on the standard model and the window process model to obtain a second OPC pattern.

[0014] Optionally, in the target layout optimization method, the number of times the first OPC correction is performed on the first metal layer pattern using a standard model is 3 to 6 times.

[0015] Optionally, in the target layout optimization method, the bridging specification is the minimum value allowed between the simulation graphic lines.

[0016] Optionally, in the target layout optimization method, the bridging graphic includes: a graphic in which the distance between the lines of the simulation graphic is less than or equal to the bridging specification.

[0017] Optionally, in the target layout optimization method, the line break specification is the minimum value allowed for the line size of the simulation graphic.

[0018] Optionally, in the target layout optimization method, the broken line graphic includes: a graphic whose simulation graphic size is less than or equal to the broken line specification.

[0019] Optionally, in the target layout optimization method, the bridging graphics and the broken line graphics are both polygons.

[0020] Optionally, in the target layout optimization method, the calculation formula of the first distance includes:

[0021]

[0022] Wherein, Sx is the minimum value of the pattern spacing in the bridge pattern, Sb is the bridge specification, and Cx is the vertical distance between the first pattern edge or the third pattern edge and the through-hole pattern inside the first metal layer in contact.

[0023] Optionally, in the target layout optimization method, the calculation formula of the second distance includes:

[0024]

[0025] Among them, Sy is the minimum value of the graphic size in the broken line graphic, Sp is the broken line specification, Dy is the vertical spacing between the second graphic edge and the adjacent second metal layer graphic, or Dy is the vertical spacing between the fourth graphic edge and the adjacent third metal graphic, and Ds is the minimum graphic spacing specified by the design rules.

[0026] Optionally, in the target layout optimization method, OPC correction is performed on the second target graphic based on the standard model and the process window model for 8 to 12 times.

[0027] The target layout optimization method provided by the present invention includes: inputting a first metal layer pattern and a through-hole pattern corresponding to the first metal layer pattern; performing a first OPC correction on the first metal layer pattern using a standard model to obtain a first OPC pattern; simulating the first OPC pattern using a process window model to obtain a simulation pattern, and marking a bridge pattern and a disconnection pattern from the simulation pattern according to a bridge specification and a disconnection specification; selecting a first pattern edge where the first metal layer contacts the bridge pattern, and moving a first distance to obtain a second metal layer pattern; selecting a second pattern edge where the second metal layer contact the disconnection pattern, and moving a second distance to obtain a first target pattern; selecting a third pattern edge where the first target pattern contacts the bridge pattern, and moving the third pattern edge toward the inside of the bridge pattern, and moving the first distance to obtain a third metal layer pattern; selecting a fourth pattern edge where the third metal layer contact the disconnection pattern, and moving the fourth pattern edge toward the outside of the disconnection pattern, and moving the second distance to obtain a second target pattern; performing OPC correction on the second target pattern based on the standard model and the window process model to obtain a second OPC pattern. The present invention optimizes a better target layout pattern and improves the coverage of the metal layer pattern to the through-hole pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 and Figure 2It is a schematic diagram of the layout of the metal layer pattern and the through-hole pattern in the prior art.

[0029] Figure 3 is a flow chart of a target layout optimization method according to an embodiment of the present invention;

[0030] Figures 4 to 9 is a schematic diagram of a layout optimization of an embodiment of the present invention;

[0031] In the figure: 110-initial graphic, 120-to target graphic, 130-through-hole graphic, 140-simulation graphic, M0-first metal layer graphic, M1-first OPC graphic, V0-through-hole graphic, B1-bridge graphic, B2-broken line graphic, Eb-first graphic edge, Ep1-second graphic edge, Epx-third graphic edge, T1-first target graphic, Ep2-fourth graphic edge, M2-second OPC graphic. DETAILED DESCRIPTION

[0032] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0033] Hereinafter, the terms "first", "second", etc. are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological sequence. It is to be understood that these terms used in this manner are interchangeable where appropriate. Similarly, if the method described herein includes a series of steps, the order of these steps presented herein is not necessarily the only order in which these steps can be performed, and some of the steps described may be omitted and / or some other steps not described herein may be added to the method.

[0034] Please refer to Figure 3 The present invention provides a target layout optimization method, comprising:

[0035] S11: inputting a first metal layer pattern and a through hole pattern corresponding to the first metal layer pattern;

[0036] S12: performing a first OPC correction on the first metal layer pattern using a standard model to obtain a first OPC pattern;

[0037] S13: simulating the first OPC pattern using a process window model to obtain a simulated pattern, and marking a bridge pattern and a disconnection pattern from the simulated pattern according to a bridge specification and a disconnection specification;

[0038] S14: selecting a first pattern edge where the first metal layer contacts the bridge pattern, and moving the first pattern edge toward the inside of the bridge pattern by a first distance to obtain a second metal layer pattern;

[0039] S15: selecting a second pattern edge where the second metal layer pattern contacts the broken line pattern, and moving the second pattern edge toward the outside of the broken line pattern by a second distance to obtain a first target pattern;

[0040] S16: selecting a third graphic edge where the first target graphic contacts the bridge graphic, and moving the third graphic edge toward the inside of the bridge graphic by a first distance to obtain a third metal layer graphic;

[0041] S17: selecting a fourth pattern edge where the third metal layer pattern contacts the broken line pattern, and moving the fourth pattern edge toward the outside of the broken line pattern by a second distance to obtain a second target pattern; and

[0042] S18: performing OPC correction on the second target pattern based on the standard model and the process window model to obtain a second OPC pattern.

[0043] In step S11, please refer to Figure 4 , input the first metal layer pattern M0 and the through-hole pattern V0 corresponding to the first metal layer pattern. The input first metal layer pattern M0 refers to the original metal layer pattern of the layout. The original metal layer here can be the first metal layer in the layout. There are through-hole patterns above and below the metal layer pattern, and the through-hole image connects multiple metal layer patterns. Therefore, the metal layer pattern needs to have a good coverage rate with the through-hole pattern. Therefore, it is necessary to continuously simulate and correct to find the best target layout pattern, and use this target layout pattern for wafer etching, so as to achieve the best device performance.

[0044] In step S12, please refer to Figure 5 , the first metal layer pattern M0 is subjected to the first OPC correction using the standard model to obtain the first OPC pattern M1, and the number of times the first metal layer pattern M0 is subjected to the first OPC correction using the standard model is 3 to 6 times. 3 to 6 times are typical preferred numbers, among which 4 times can be selected, and other numbers can also be used in other embodiments of the present invention. The standard model refers to a model under normal conditions, which is equivalent to that the simulation parameters will not change, for example, the exposure energy and exposure focal length are fixed.

[0045] In step S13, please refer to Figure 6 and Figure 7 , the first OPC pattern M1 is simulated using a process window model to obtain a simulated pattern, and a bridge pattern B1 and a broken line pattern B2 are marked therefrom.

[0046] Next, please refer to Figure 6 Execute step S14, select the first graphic edge Eb where the first metal layer graphic M0 and the bridge graphic B1 are in contact, and move the first graphic edge Eb toward the inner direction of the bridge graphic, the moving distance is the first distance, to obtain the second metal layer graphic. In step S14, the first graphic edge where the first metal layer and the bridge graphic are in contact can be found, and the first graphic edge can be one edge or two edges or more. The first graphic edge found is moved along the direction of the first metal layer by the first distance. The first graphic edge is actually the edge of the first metal layer, so after the first graphic edge is moved, the first metal layer becomes the second metal layer.

[0047] Next, please refer to Figure 7 and Figure 8 , execute step S15, select the second graphic edge Ep1 of the second metal layer graphic in contact with the broken wire graphic B2, and move the second distance toward the outside direction of the broken wire graphic B2 to obtain the first target graphic T1. In step S15, select the second graphic edge of the second metal layer graphic in contact with the broken wire graphic, and move the second distance to obtain the first target graphic.

[0048] Next, step S16 is performed: selecting a third pattern edge where the first target pattern contacts the bridge pattern, and moving the third pattern edge toward the inside of the bridge pattern by a first distance to obtain a third metal layer pattern.

[0049] The calculation formula for the first distance includes:

[0050]

[0051] Wherein, Sx is the minimum value of the simulated pattern spacing in the bridge pattern, Sb is the bridge specification, and Cx is the vertical distance between the first pattern edge or the third pattern edge and the contacted through-hole pattern inside the first metal layer.

[0052] Next, step S17 is performed: selecting a fourth pattern edge where the third metal layer pattern contacts the broken line pattern, and moving the fourth pattern edge toward the outside of the broken line pattern by a second distance to obtain a second target pattern.

[0053] The calculation formula for the second distance includes:

[0054]

[0055] Among them, Sy is the minimum value of the simulated graphic size in the broken line graphic, Sp is the broken line specification, Dy is the vertical spacing between the second graphic edge and the adjacent second metal layer graphic, or Dy is the vertical spacing between the fourth graphic edge and the adjacent third metal graphic, and Ds is the minimum graphic spacing specified by the design rules.

[0056] Next, please refer to Fig. 9, execute step S18, perform OPC correction on the second target pattern based on the standard model and the process window model to obtain the second OPC pattern M2, and the second OPC pattern M2 is the final optimized target layout pattern. In step S18, the second target pattern M2 is OPC-corrected 8 to 12 times based on the standard model and the process window model. The standard model is simulated first, and then the process window model is simulated. The two are regarded as a cycle, and the total number of cycles is preferably 8 to 12 times, for example 10 times. Of course, in other embodiments of the present invention, other numbers can also be selected.

[0057] In summary, in the target layout optimization method provided in the embodiment of the present invention, a better target layout pattern is optimized, and the coverage rate of the metal layer pattern on the through-hole pattern is improved.

[0058] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. A target layout optimization method, characterized in that: include: Inputting a first metal layer pattern and a through hole pattern corresponding to the first metal layer pattern; Performing a first OPC correction on the first metal layer pattern using a standard model to obtain a first OPC pattern; Simulating the first OPC pattern using a process window model to obtain a simulated pattern, and marking a bridge pattern and a disconnection pattern from the simulated pattern according to a bridge specification and a disconnection specification; Selecting a first pattern edge where the first metal layer contacts the bridge pattern, and moving the first pattern edge toward the inside of the bridge pattern by a first distance to obtain a second metal layer pattern; Selecting a second pattern edge of the second metal layer pattern that contacts the broken line pattern, and moving the second pattern edge toward the outside of the broken line pattern by a second distance to obtain a first target pattern; Selecting a third pattern edge where the first target pattern contacts the bridge pattern, and moving the third pattern edge toward the inside of the bridge pattern by a first distance to obtain a third metal layer pattern; Selecting a fourth pattern edge where the third metal layer pattern contacts the broken line pattern, and moving the fourth pattern edge toward the outside of the broken line pattern by a second distance to obtain a second target pattern; as well as The second target pattern is subjected to OPC correction based on the standard model and the process window model to obtain a second OPC pattern.

2. The target layout optimization method according to claim 1, characterized in that: The first OPC correction is performed 3 to 6 times on the first metal layer pattern using a standard model.

3. The target layout optimization method according to claim 1, characterized in that: The bridge specification is the minimum value allowed between the analog graphic lines.

4. The target layout optimization method according to claim 3, characterized in that: The bridge pattern includes: a pattern in which the distance between the lines of the simulation pattern is less than or equal to the bridge specification.

5. The target layout optimization method according to claim 1, characterized in that: The line breaking specification is the minimum value allowed for the line size of the simulation graphic.

6. The target layout optimization method according to claim 5, characterized in that: The disconnection pattern includes: a pattern whose size of the simulation pattern is smaller than or equal to the disconnection specification.

7. The target layout optimization method according to claim 1, characterized in that: The bridge pattern and the broken line pattern are both polygonal.

8. The target layout optimization method according to claim 1, characterized in that: The calculation formula of the first distance includes: Wherein, Sx is the minimum value of the pattern spacing in the bridge pattern, Sb is the bridge specification, and Cx is the vertical distance between the first pattern edge or the third pattern edge and the through-hole pattern inside the first metal layer in contact.

9. The target layout optimization method according to claim 1, characterized in that: The calculation formula of the second distance includes: Among them, Sy is the minimum value of the graphic size in the broken line graphic, Sp is the broken line specification, Dy is the vertical spacing between the second graphic edge and the adjacent second metal layer graphic, or Dy is the vertical spacing between the fourth graphic edge and the adjacent third metal graphic, and Ds is the minimum graphic spacing specified by the design rules.

10. The target layout optimization method according to claim 1, characterized in that: The OPC correction is performed 8 to 12 times on the second target pattern based on the standard model and the process window model.

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