Memory fault processing method and computer device

Abstract

The embodiment of the application provides a memory fault processing method and computer equipment, and relates to the technical field of memory. In the method, after determining a plurality of fault events of the memory, the plurality of fault events are divided into at least two fault groups according to physical positions of the plurality of fault events, and the influence degree of the fault events in a target fault group on the memory is predicted. Since the influence degree of the target fault group is positively correlated with the repair value of the physical position where the target fault group is located, and the fault influence degree meets a preset condition, the repair value of the physical position where the target fault group is located is higher. Based on this, the physical position where the target fault group located and the influence degree meet the preset condition is determined as a to-be-repaired position, which can ensure that the necessity of repair is higher, and therefore, unnecessary repair operations and problems of wasting storage resources and fault repair resources of the memory can be avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory, and particularly relates to a memory fault processing method and a computer device. BACKGROUND

[0002] Memory is an essential component in a computer device. During use, the memory has a certain probability of failure. The memory failure includes correct error (CE) level failure and uncorrect error (UCE) level failure. When the memory has UCE level failure, the computer device usually has system failure, for example, system downtime.

[0003] In the related art, in order to improve the reliability of the memory and avoid system failure caused by serious failure of the memory, when the number of times of CE level failure of a chip grain of the memory reaches a threshold, the chip grain is isolated. However, since the correlation between the number of times of CE level failure and the severity of the memory failure is not clear, this processing method may have unnecessary repair operations, which wastes the storage resources and failure repair resources of the memory. Repairing the physical position with a high number of times of CE level failure usually cannot effectively reduce the risk of memory failure. SUMMARY

[0004] Embodiments of the present application provide a memory fault processing method and a computer device, which can effectively reduce the risk of memory failure and avoid wasting the storage resources of the memory.

[0005] To achieve the above object, embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, a memory fault processing method is provided. The method comprises: determining a plurality of failure events of a memory; dividing the plurality of failure events into at least two failure groups according to physical positions of the plurality of failure events; the at least two groups include a target failure group; predicting an influence degree of the failure events in the target failure group on the memory; and determining a physical position of the failure events in the target failure group as a to-be-repaired position when the influence degree meets a first preset condition.

[0007] In the scheme, after a plurality of fault events of the memory are determined, the plurality of fault events are divided into at least two fault groups according to physical positions of the plurality of fault events, and an influence degree of the fault events in a target fault group on the memory is predicted. Since the influence degree of the fault events in the target fault group on the memory is positively correlated with repair values of the physical positions of the fault events in the target fault group, that is, the greater the influence degree of the target fault group is, the greater the repair value of the physical position of the target fault group is, and when the influence degree satisfies a first preset condition, the repair value of the physical position of the target fault group is higher. Based on this, the physical position of the target fault group in which the fault events satisfy the first preset condition is determined as the to-be-repaired position, which can ensure that the repair necessity of the physical position of the target fault group is higher, thereby avoiding unnecessary repair operations and problems of wasting storage resources and fault repair resources of the memory, and repairing the physical position of the memory with higher repair necessity can effectively reduce the risk of the memory failure, for example, the risk of UCE-level failure, thereby helping to effectively avoid system failure of the computer device.

[0008] In a possible implementation, the influence degree of the fault events in the target fault group on the memory is predicted by predicting a first fault severity of the memory according to the fault events in a non-target fault group of the at least two fault groups, and determining the influence degree of the fault events in the target fault group on the memory according to the first fault severity of the memory. The higher the first fault severity of the memory is, the lower the influence degree of the fault events in the target fault group on the memory is.

[0009] In the implementation, the first fault severity predicted according to the fault events in the non-target fault group is the fault severity of the memory after the physical position of the target fault group is repaired. Based on this, the higher the first fault severity is, the lower the influence degree of the fault events in the target fault group on the memory is, and the lower the repair value is. In other words, even if the physical position of the target fault group is repaired, the fault severity of the memory can be reduced very limitedly. Therefore, determining the influence degree of the fault events in the target fault group on the memory according to the first fault severity of the memory can help to more accurately indicate the repair value of the physical position of the target fault group in the target fault group, thereby helping to ensure that the physical position of the target fault group is determined as the to-be-repaired position when the repair value of the physical position of the target fault group is higher. In this way, unnecessary repair operations and problems of wasting storage resources and fault repair resources of the memory can be more effectively avoided.

[0010] In another possible implementation, the degree of influence of the fault event in the target fault group on the memory is predicted by: predicting a first fault severity of the memory according to the fault events in the non-target fault group of the at least two fault groups; predicting a second fault severity of the memory according to the plurality of fault events; and determining the degree of influence of the fault event in the target fault group on the memory according to a difference between the second fault severity of the memory and the first fault severity of the memory, wherein the smaller the difference is, the lower the degree of influence of the fault event in the target fault group on the memory is.

[0011] In this implementation, the first fault severity predicted according to the fault events in the non-target fault group is the fault severity of the memory after the physical location where the fault event in the target fault group is located is repaired, and the second fault severity predicted according to the fault events in the plurality of fault groups is the fault severity of the memory when the physical location where the fault event in the target fault group is located is not repaired. Based on this, the difference between the second fault severity and the first fault severity is the degree of influence of the fault event in the target fault group on the memory. Therefore, determining the degree of influence of the fault event in the target fault group on the memory according to the difference between the second fault severity and the first fault severity helps to improve the accuracy of the degree of influence, so that the degree of influence of the target fault group can more accurately indicate the repair value of the physical location where the fault event in the target fault group is located, thereby helping to ensure that the physical location where the fault event in the target fault group is located is determined as the to-be-repaired location when the repair value of the physical location is high, so that unnecessary repair operations can be more effectively avoided, and the problem of wasting storage resources and fault repair resources of the memory can be avoided.

[0012] In another possible implementation, when the degree of influence meets the first preset condition, the physical location where the fault event in the target fault group is located is determined as the to-be-repaired location, including: when the degree of influence meets the first preset condition and the second fault severity meets a second preset condition, the physical location where the fault event in the target fault group is located is determined as the to-be-repaired location.

[0013] In the implementation, since the second fault severity is predicted according to the fault events in the plurality of fault groups, the current actual fault severity of the memory is equivalent to the second fault severity, and the second fault severity satisfies the second preset condition, so that the physical location of the fault event in the target fault group is determined as the to-be-repaired location only when the current actual fault severity of the memory is relatively severe, so as to perform fault repair on the memory, and the to-be-repaired location is not determined when the current actual fault severity of the memory is relatively slight, that is, the fault repair is not performed on the memory. In this way, the limited fault repair resources can be reasonably utilized, overuse of the fault repair resources is avoided, and the utilization rate of the fault repair resources is improved.

[0014] In another possible implementation, the second fault severity is predicted according to the plurality of fault events, including: inputting the plurality of fault events into a fault prediction model to obtain the second fault severity output by the fault prediction model.

[0015] In the implementation, since the fault prediction model is pre-trained, the second fault severity is predicted according to the plurality of fault events and the fault prediction model, without the need for user participation in calculation and data processing. This not only helps to improve the prediction speed, but also avoids artificial errors caused by user operation, and further helps to improve the accuracy of the predicted second fault severity.

[0016] In another possible implementation, the first fault severity is predicted according to the fault events in the non-target fault group of the at least two fault groups, including: inputting the fault events in the non-target fault group of the at least two fault groups into a fault prediction model to obtain the first fault severity output by the fault prediction model.

[0017] In the implementation, since the fault prediction model is pre-trained, the first fault severity is predicted according to the fault events in the non-target fault group and the fault prediction model, without the need for user participation in calculation and data processing. This not only helps to improve the prediction speed, but also avoids artificial errors caused by user operation, and further helps to improve the accuracy of the predicted first fault severity.

[0018] In another possible implementation, the plurality of fault events are divided into the at least two fault groups according to the physical locations of the plurality of fault events, including: dividing the plurality of fault events into the at least two fault groups according to the physical locations of the plurality of fault events and the granularity of the physical locations repaired by a fault repair manner; and wherein the fault repair manner is of the same type as a fault repair manner to be used by the to-be-repaired location.

[0019] In the implementation, the plurality of fault events are grouped according to the physical locations of the plurality of fault events and the granularity of the physical locations repaired by the fault repair manners, which helps to establish the correlation between the physical locations of the fault events in the target fault group and the fault repair manners, for example, the granularity of the physical locations repaired by the fault repair manners is a memory row, and the physical locations of the fault events in the target fault group belong to the same memory row. Based on this, after determining that the physical locations of the fault events in the target fault group are the to-be-repaired locations, if the to-be-repaired locations are repaired by the fault repair manner used for grouping, the adaptability between the to-be-repaired locations and the fault repair manner is improved.

[0020] In another possible implementation, the method further includes: sending a fault repair request, the fault repair request being used to request to repair the to-be-repaired locations.

[0021] In the implementation, by sending the fault repair request, the fault repair of the to-be-repaired locations is requested, so as to reduce the risk of future memory faults, for example, the risk of UCE-level faults, and further avoid system faults caused by memory faults.

[0022] In another possible implementation, the method further includes: outputting fault processing information, the fault processing information including the identification of the to-be-repaired locations.

[0023] In the implementation, by outputting the fault processing information, for example, voice output or text output, the user can know the number of to-be-repaired physical locations and the specific locations in the memory, so as to help the user to timely master the fault conditions of the memory.

[0024] In another possible implementation, the plurality of fault events include a first fault event, and the first fault event includes fault time information, fault location information, and fault correction difficulty information of the memory fault indicated by the first fault event.

[0025] In the implementation, the first fault event includes the fault time information, the fault location information and the fault correction difficulty information, so that the fault severity of the memory can be predicted based on multiple dimensions such as the fault time, the fault location and the fault correction difficulty, and the accuracy of the prediction result is improved. Since the multiple fault events indicate multiple historical faults of the memory, in terms of the fault time, the shorter the time interval of the multiple historical faults, that is, the higher the occurrence frequency, the greater the influence on the fault severity of the memory. In terms of the fault location, if the fault locations (such as the physical addresses) of the multiple historical faults present a certain concentration, such as the multiple historical faults occurring in the same memory cell, the same memory row or the same memory column, the greater the influence on the fault severity of the memory. In terms of the repair difficulty, the greater the fault correction difficulty of the multiple historical faults, the greater the influence on the fault severity of the memory. Therefore, the fault severity of the memory is predicted according to the fault time, the fault location and the fault correction difficulty of the historical faults of the memory, and the accuracy of the fault severity prediction is improved.

[0026] In a second aspect, a memory fault processing apparatus is provided, which includes functional units for performing any of the methods provided in the first aspect, and each of the functional units performs an action by hardware or by hardware executing corresponding software. For example, the memory fault processing apparatus can include a processing unit and a prediction unit. The processing unit is configured to determine multiple fault events of a memory, and divide the multiple fault events into at least two fault groups according to physical locations of the multiple fault events. The at least two groups include a target fault group. The prediction unit is configured to predict an influence degree of the fault events in the target fault group on the memory. The processing unit is further configured to determine a physical location of the fault events in the target fault group as a to-be-repaired location when the influence degree meets a first preset condition.

[0027] In a third aspect, a computer device is provided, which includes a processor, an out-of-band controller and a memory. The processor is in communication connection with the memory, and the processor is also in communication connection with the out-of-band controller. The out-of-band controller is configured to determine multiple fault events of the memory, divide the multiple fault events into at least two fault groups according to physical locations of the multiple fault events, and predict an influence degree of the fault events in a target fault group on the memory. When the influence degree meets a first preset condition, the out-of-band controller is configured to determine a physical location of the fault events in the target fault group as a to-be-repaired location.

[0028] Optionally, the out-of-band controller is specifically configured to: predict a first fault severity of the memory according to the fault events in the non-target fault group of the at least two fault groups; and determine the influence degree of the fault events in the target fault group on the memory according to the first fault severity of the memory; wherein the higher the first fault severity of the memory is, the lower the influence degree of the fault events in the target fault group on the memory is.

[0029] Optionally, the out-of-band controller is specifically configured to: predict a first fault severity of the memory according to the fault events in the non-target fault group of the at least two fault groups; predict a second fault severity of the memory according to the plurality of fault events; and determine the influence degree of the fault events in the target fault group on the memory according to a difference between the second fault severity of the memory and the first fault severity of the memory; wherein the smaller the difference is, the lower the influence degree of the fault events in the target fault group on the memory is.

[0030] Optionally, the out-of-band controller is specifically configured to: determine the physical location of the fault events in the target fault group as the to-be-repaired location when the influence degree meets a first preset condition and the second fault severity meets a second preset condition.

[0031] Optionally, the out-of-band controller is specifically configured to: divide the plurality of fault events into the at least two fault groups according to the physical locations of the plurality of fault events and a granularity of physical locations repaired by the fault repair manners of the plurality of fault events; wherein the fault repair manner is of the same type as the type of the fault repair manner to be used for the to-be-repaired location.

[0032] Optionally, the out-of-band controller is further configured to: send a fault repair request, the fault repair request being used to request to repair the to-be-repaired location.

[0033] Optionally, the out-of-band controller is further configured to: output fault processing information, the fault processing information including an identifier of the to-be-repaired location.

[0034] Optionally, the plurality of fault events include a first fault event, and the first fault event includes fault time information, fault location information, and fault correction difficulty information of a memory fault indicated by the first fault event.

[0035] In a fourth aspect, a computer device is provided, including: a processor and a memory, the processor being connected with the memory. The memory is configured to store computer execution instructions, and the processor executes the computer execution instructions stored in the memory, thereby realizing any one of the methods provided in the first aspect.

[0036] In a fifth aspect, a chip is provided, including: a processor and an interface circuit; the interface circuit is configured to receive code instructions and transmit the code instructions to the processor; the processor is configured to run the code instructions to execute any one of the methods provided in the first aspect.

[0037] In a sixth aspect, a computer-readable storage medium is provided, which stores computer-executable instructions that, when executed on a computer, cause the computer to perform any of the methods provided in the first aspect.

[0038] In a seventh aspect, a computer program product is provided, which includes computer-executable instructions that, when executed on a computer, cause the computer to perform any of the methods provided in the first aspect.

[0039] The technical effects brought by the implementation manners of the second aspect to the seventh aspect can be referred to the technical effects brought by the implementation manners of the first aspect, and will not be described here. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 An architecture diagram of a computer device provided by an embodiment of the present application is provided.

[0041] Figure 2 A schematic diagram of a memory provided by an embodiment of the present application is provided.

[0042] Figure 3 A flowchart of a memory fault processing method provided by an embodiment of the present application is provided.

[0043] Figure 4 A schematic diagram of a memory provided by an embodiment of the present application is provided.

[0044] Figure 5 A flowchart of another memory fault processing method provided by an embodiment of the present application is provided.

[0045] Figure 6 A schematic diagram of a prediction impact degree provided by an embodiment of the present application is provided.

[0046] Figure 7 A flowchart of another memory fault processing method provided by an embodiment of the present application is provided.

[0047] Figure 8 A schematic diagram of a memory fault processing apparatus provided by an embodiment of the present application is provided. DETAILED DESCRIPTION

[0048] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

[0049] In the description of the present application, unless otherwise specified, " / " represents that the objects before and after the correlation are in an "or" relationship, for example, A / B can represent A or B; "and / or" in the present application is only a description of the correlation of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent: A exists alone, A and B exist together, and B exists alone, where A, B can be singular or plural.

[0050] In addition, in the description of the present application, unless otherwise specified, "multiple" means two or more than two. "At least one of the following" or the like means any combination of the items, including any combination of single item or multiple items. For example, at least one of a, b, or c can represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, c can be single or multiple.

[0051] In addition, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, "first", "second" and the like are used to distinguish the same items or similar items with basically the same function and effect. The skilled in the art can understand that "first", "second" and the like do not limit the quantity and execution order, and "first", "second" and the like do not necessarily mean different. At the same time, in the embodiments of the present application, "exemplary" or "for example" means to represent as an example, illustration or explanation. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the use of "exemplary" or "for example" is intended to present the relevant concept in a specific manner, for understanding.

[0052] First, the application scenario of the embodiments of the present application is exemplarily introduced. Memory is an essential component in computer equipment. In the use process, there is a certain probability that memory failure will occur, including correct error (CE) level failure and uncorrectable error (UCE) level failure. Since the programs of computer equipment are running in memory, if the memory fails and is not repaired, for example, UCE level failure occurs, it will cause the program running in the memory to crash, and even cause the server to have system failure, such as system downtime, etc. Once this happens, it will bring serious loss.

[0053] With the increasing of the frequency of the memory, the density of the particle is getting larger and larger, and the capacity is also getting larger and larger, and the probability of failure of the memory is also getting larger and larger, at present, the memory failure has become one of the most serious problems in the data center. Therefore, it is necessary to improve the reliability of the memory as much as possible to avoid the problems such as memory crash, system restart, memory physical damage and the like.

[0054] Based on this, the memory maintenance strategy is that for CE level failure, the error correction method such as parity, error checking and correction (ECC) configured by the computer device is used for self-repair, and for UCE level failure, the method of pre-isolation is used for processing, so as to guarantee the normal operation of the computer device.

[0055] In the related art, when the UCE level failure is pre-isolated, the chip particle of the memory is usually isolated when the number of CE level failures of the chip particle reaches a threshold. However, since the correlation between the number of CE level failures and the severity of the memory failure is not clear, this processing method may generate unnecessary repair operations, resulting in waste of memory storage resources and failure repair resources, and repairing the physical position with a high number of CE level failures usually cannot effectively reduce the risk of memory failure.

[0056] Therefore, the embodiments of the present application provide a memory failure processing method, after determining a plurality of failure events of the memory, the plurality of failure events are divided into at least two failure groups according to the physical positions of the plurality of failure events, and the influence degree of the failure events in the target failure group on the memory is predicted. Since the influence degree of the failure events in the target failure group on the memory is positively correlated with the repair value of the physical position of the failure events in the target failure group, that is, the greater the influence degree of the target failure group, the greater the repair value of the physical position of the target failure group, and when the failure influence degree meets a first preset condition, the repair value of the physical position of the failure events in the target failure group is higher. Based on this, the physical position of the failure events in the target failure group meeting the first preset condition is determined as the to-be-repaired position, which can ensure that the repair necessity of the physical position of the failure events in the target failure group is higher, so as to avoid unnecessary repair operations and the problem of waste of memory storage resources and failure repair resources. Moreover, repairing the physical position with higher repair necessity on the memory can effectively reduce the risk of memory failure, such as UCE level failure, thereby helping to effectively avoid system failure of the computer device.

[0057] Secondly, the system architecture of the embodiments of the present application is exemplarily introduced.

[0058] As Figure 1 shown, it is a schematic diagram of a computer device in the embodiments of the present application. The computer device comprises a central processing unit (CPU), an out-of-band controller and a memory.

[0059] The CPU runs a processor firmware and an operating system (OS) management unit.

[0060] For example, the OS management unit can be a system management unit provided by the OS, or a device management agent installed in the OS, and the embodiments of the present application do not limit this.

[0061] For example, the processor firmware (also referred to as processor firmware program) can be firmware, basic input output system (BIOS), management engine (ME), microcode or intelligent management unit (IMU) and the like. It should be noted that the embodiments of the present application do not limit the specific form of the processor firmware, and the above is only an exemplary description. In the following embodiments, only the processor firmware is taken as BIOS for example.

[0062] The out-of-band controller can perform remote maintenance and management on the computer device through a dedicated data channel. The out-of-band controller is a controller completely independent of the CPU, and communicates with the basic input output system (BIOS) and the operating system OS (or the OS management unit) in the CPU through the out-of-band management interface of the computer device.

[0063] For example, the out-of-band controller can include a management unit of the running state of the computer device, a management system in the management chip outside the processor, a baseboard management controller (BMC) of the computer device, a system management module (SMM) and the like. It should be noted that the embodiments of the present application do not limit the specific form of the out-of-band controller, and the above is only an exemplary description. In the following embodiments, only the out-of-band controller is taken as BMC for example.

[0064] It should be noted that the computer device has different names for BMC, such as BMC, iLO and iDRAC. Whether it is called BMC, iLO or iDRAC, it can be understood as BMC in the embodiments of the present application.

[0065] In some embodiments, the out-of-band controller includes a fault management module, a fault location module, and a fault handling module.

[0066] The fault management module collects memory fault events and stores them in the out-of-band controller's cache. These memory fault events can be sent to the fault management unit by the processor firmware or by the OS management unit. It should be noted that this application embodiment does not limit the source of the fault events collected by the fault management unit.

[0067] The fault location module is used to group cache fault events of the out-of-band controller, predict the impact of each group of fault events on memory, and determine the physical location of the group whose impact meets preset conditions as the fault risk area.

[0068] The fault handling module is used to perform operations such as alarming, repairing, and isolating faulty risk areas to reduce the risk of memory failure.

[0069] The following, combined with Figure 2 An example of the structure of memory is provided.

[0070] Memory, also known as internal memory or main memory, is the memory slot installed on the motherboard of a computer device. Figure 2 In (not shown), memory and memory controller ( Figure 2 (Not shown in the diagram) communicate via memory channels. Memory has at least one memory rank, such as... Figure 2 The diagram shows memory columns 0 and 1. Each memory column is located on a face of the memory, and each memory column includes at least one sub-rank. Each memory column or sub-rank includes multiple memory chips (devices), such as... Figure 2 The memory chips shown are 00, 01, etc. Each memory chip is divided into multiple memory bank groups, and each memory bank group includes multiple memory banks, such as... Figure 2 The storage arrays shown are 0, 1, etc. Each storage array is divided into multiple storage cells, each storage cell has a row address and a column address, and each storage cell includes one or more bits. Figure 2 (Not shown in the image). In one partitioning method, memory can be divided from the upper level to the lower level into memory chips, memory array groups, memory arrays, memory rows / columns, memory cells, and bits.

[0071] It should be noted that the system architecture and application scenarios described in the embodiments of the present application are used to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those skilled in the art can know that with the evolution of system architecture and the appearance of new business scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0072] For ease of understanding, the memory fault processing method provided by the present application is exemplarily introduced below in combination with the drawings, and the memory fault processing method is applicable to Figure 1 the computer device shown in the drawings.

[0073] Figure 3 is a flowchart of a memory fault processing method according to an exemplary embodiment. Exemplarily, the memory fault processing method includes the following S301-S306.

[0074] S301: The out-of-band controller determines a plurality of fault events of the memory.

[0075] Among them, the fault event and the memory fault are in a one-to-one correspondence, and one fault event is used to indicate one memory fault.

[0076] Optionally, the fault event can be a CE level fault event and / or a UCE level fault event.

[0077] Among the plurality of fault events, a part of the fault events can be CE level fault events, and another part of the fault events can be UCE level fault events.

[0078] Optionally, the plurality of fault events includes a first fault event, and the first fault event includes fault time information, fault location information and fault correction difficulty information of the memory fault indicated by the first fault event. Among them, the first fault event can be any one of the plurality of fault events.

[0079] The fault time information is used to indicate the occurrence time of the memory fault indicated by the first fault event.

[0080] The fault location information is used to indicate the physical location of the memory fault indicated by the first fault event. For example, the fault location information can include at least one of processor identification (CPU ID), channel identification (Channel ID), memory identification (DimmID), memory column identification (Rank ID), memory chip identification (Device ID), storage array group identification (BankGruop ID), storage array identification (Bank ID), row address, and column address.

[0081] The fault correction difficulty information is used to indicate a correction difficulty of the memory fault indicated by the first fault event. For example, the correction difficulty of the first fault event can be determined based on a parity check result recorded in a register after the memory fault indicated by the first fault event is corrected by the ECC correction method. For example, the correction difficulty is determined according to the number of 1s in the parity check result of the ECC correction method, where the smaller the number of 1s, the fewer the bit flips in the data, and thus the smaller the repair difficulty. Conversely, the greater the fault correction difficulty. In some embodiments, after the CPU detects that the memory has a fault (such as fault a), the CPU collects the fault time information, the fault location information, and the fault correction difficulty information of fault a, and then encapsulates the collected information to obtain a fault event a corresponding to fault a, and sends the fault event a to the out-of-band controller. After receiving the fault event a, the out-of-band controller stores the fault event a, for example, in a local cache.

[0082] In some embodiments, when the number of fault events stored by the out-of-band controller reaches a preset threshold, the out-of-band controller starts to perform S301 described above. For example, the preset threshold can be 20, 50, etc. It should be noted that the present application does not limit the specific value of the preset threshold.

[0083] In some other embodiments, the out-of-band controller performs S301 described above at a preset period. For example, the preset period can be 1 day, 7 days, etc. It should be noted that the present application does not limit the length of the preset period.

[0084] S302: The out-of-band controller divides the plurality of fault events into at least two fault groups according to physical locations of the plurality of fault events.

[0085] The fault event and the physical location are in a one-to-one correspondence, that is, one fault event corresponds to one physical location. The physical location corresponding to the fault event can be determined according to the fault location information included in the fault event.

[0086] It should be noted that the physical locations corresponding to different fault events can be the same or different, and the present application does not limit this.

[0087] Optionally, the at least two fault groups include a first fault group, and the first fault group includes at least one fault event. The first fault group can be any one of the at least two fault groups.

[0088] It should be noted that the number of fault events included in different fault groups can be equal or unequal, and the present application does not limit this.

[0089] Optionally, S302 comprises: dividing, by the out-of-band controller, the plurality of fault events into at least two fault groups according to physical locations where the plurality of fault events are located based on the division granularity.

[0090] For example, if the division granularity is a memory row, the plurality of fault events are grouped according to memory rows where the plurality of fault events are located, and if the division granularity is a storage array, the plurality of fault events are grouped according to storage arrays where the plurality of fault events are located.

[0091] The division granularity can be pre-determined or randomly selected.

[0092] Optionally, the division granularity is any one of a memory chip, a storage array group, a storage array, a storage row / storage column, and a storage cell. Optionally, S302 comprises: dividing, according to physical locations where the plurality of fault events are located and a granularity of physical locations repaired by a fault repair manner of the plurality of fault events, the plurality of fault events into at least two fault groups; wherein the fault repair manner is of a same type as a fault repair manner to be used for a to-be-repaired location.

[0093] In some embodiments, the fault repair manner comprises a cell repair, a row repair, a column repair, and an array repair.

[0094] The granularity of physical locations repaired by the cell repair is a storage cell. The granularity of physical locations repaired by the row repair is a memory row. The granularity of physical locations repaired by the column repair is a memory column. The granularity of physical locations repaired by the array repair is a storage array.

[0095] In some embodiments, the plurality of fault events are divided into at least two fault groups according to physical locations where the plurality of fault events are located based on a granularity of physical locations repaired by a fault repair manner of the plurality of fault events.

[0096] For example, if the fault repair manner of the plurality of fault events is the row repair, i.e., the granularity of physical locations repaired by the fault repair manner is the memory row, the plurality of fault events are grouped according to memory rows where the plurality of fault events are located.

[0097] In one example, the plurality of fault events are divided into at least two fault groups based on a pre-determined granularity of physical locations repaired by a fault repair manner of the plurality of fault events.

[0098] For example, before S302 is performed, the fault repair manner of the plurality of fault events is determined by a human, and if the determined fault repair manner is the row repair, the plurality of fault events are grouped according to physical locations where the plurality of fault events are located based on a granularity of physical locations repaired by the row repair, i.e., the memory row.

[0099] In another example, the plurality of failure events are divided into at least two failure groups according to the physical locations of the plurality of failure events based on the granularity of the physical locations repaired by any one of the failure repair manners.

[0100] For example, after determining the plurality of failure events of the memory, a failure repair manner is randomly selected, such as the randomly selected failure repair manner is array repair, and the plurality of failure events are grouped according to the physical locations of the plurality of failure events based on the granularity of the physical locations repaired by the array repair.

[0101] In yet another example, the plurality of failure events are divided into at least two failure groups according to the physical locations of the plurality of failure events based on the granularity of the physical locations repaired by each of the failure repair manners respectively.

[0102] For example, the plurality of failure events are divided into at least two failure groups according to the physical locations of the plurality of failure events based on the granularity of the physical locations repaired by the cell repair first. Then, the plurality of failure events are divided into at least two failure groups according to the physical locations of the plurality of failure events based on the granularity of the physical locations repaired by the row repair. Then, the plurality of failure events are divided into at least two failure groups according to the physical locations of the plurality of failure events based on the granularity of the physical locations repaired by the column repair. Finally, the plurality of failure events are divided into at least two failure groups according to the physical locations of the plurality of failure events based on the granularity of the physical locations repaired by the array repair.

[0103] There are various implementation manners for how to divide the plurality of failure events into at least two failure groups according to the physical locations of the plurality of failure events, which are exemplarily described below by way of example 1 to example 4.

[0104] Example 1: the plurality of failure events are divided into at least two failure groups according to the storage cells where the plurality of failure events are located.

[0105] In which, different failure events in the same failure group are located in the same storage cell, and failure events in different failure groups are located in different storage cells.

[0106] As shown in FIG. 1, a schematic diagram of a storage array of the memory is shown, and the storage array includes a plurality of storage cells. In which, row i is used to represent the ith row, i = 1, …, 8. Column j is used to represent the jth column, j = 1, …, 8. Figure 4 It should be noted that the number of storage cells included in the storage array is not limited in the embodiments of the present application,

[0107] and the number of storage cells shown in FIG. 1 is only exemplary. Figure 3

[0108] ​The following describes mode 1 by taking multiple fault events including fault event 1, …, fault event 6 as an example.

[0109] As shown in Figure 3 , the storage unit where fault event 1 and fault event 2 are located is row 1 column 2, the storage unit where fault event 3 is located is row 1 column 3, the storage unit where fault event 4 is located is row 3 column 3, the storage unit where fault event 5 is located is row 3 column 6, and the storage unit where fault event 6 is located is row 6 column 2.

[0110] On this basis, if multiple fault events are grouped based on the storage units where the multiple fault events are located, fault event 1 and fault event 2 are located in the same storage unit and belong to the same fault group, for example, fault group 1. Fault event 3, fault event 4, fault event 5, and fault event 6 are located in different storage units, for example, belong to fault group 2, fault group 3, and fault group 5, and fault group 6 in turn.

[0111] Among them, fault group 1, …, fault group 6 are different fault groups.

[0112] Mode 2: Based on the memory rows where multiple fault events are located, the multiple fault events are divided into at least two fault groups.

[0113] Among them, different fault events in the same fault group are located in the same memory row, and fault events in different fault groups are located in different memory rows.

[0114] As shown in Figure 3 , fault event 1, fault event 2, and fault event 3 are located in row 1, fault event 4 and fault event 5 are located in row 3, and fault event 6 is located in row 6.

[0115] On this basis, if multiple fault events are grouped based on the memory rows where the multiple fault events are located, fault event 1, fault event 2, and fault event 3 are located in the same row and belong to the same fault group, for example, fault group 1. Fault event 4 and fault event 5 are located in the same row and belong to the same fault group, for example, fault group 2. Fault event 6 belongs to the same fault group, for example, fault group 3.

[0116] Among them, fault group 1, …, fault group 3 are different fault groups.

[0117] Mode 3: Based on the memory columns where multiple fault events are located, the multiple fault events are divided into at least two fault groups.

[0118] Among them, different fault events in the same fault group are located in the same memory column, and fault events in different fault groups are located in different memory columns.

[0119] As shown in Figure 3As shown, fault event 1, fault event 2, and fault event 6 are located in column 2, fault event 3 and fault event 4 are located in column 3, and fault event 5 is located in column 5.

[0120] On this basis, if the plurality of fault events are grouped based on the memory columns in which the plurality of fault events are located, fault event 1, fault event 2, and fault event 6 are located in the same column and belong to the same fault group, for example, fault group 1. Fault event 3 and fault event 4 are located in the same column and belong to the same fault group, for example, fault group 2. Fault event 5 belongs to a fault group, for example, fault group 3.

[0121] Among them, fault group 1, …, fault group 3 are different fault groups.

[0122] Method 4: Based on the storage arrays in which the plurality of fault events are located, the plurality of fault events are divided into at least two fault groups.

[0123] Among them, different fault events in the same fault group are located in the same storage array, and fault events in different fault groups are located in different storage arrays.

[0124] Hereinafter, taking the plurality of fault events including fault event 1, …, fault event 6, and fault event N as an example, method 4 is described. Among them, fault event N and fault event 1 are located in different storage arrays.

[0125] As shown, Figure 3 fault event 1, …, fault event 6 are located in the same storage array, and fault event N and fault event 1 are located in different storage arrays. On this basis, if the plurality of fault events are grouped based on the storage arrays in which the plurality of fault events are located, fault event 1, …, fault event 6 are located in the same storage array and belong to the same fault group, for example, fault group 1. Fault event N belongs to a fault group, for example, fault group 2.

[0126] Among them, fault group 1 and fault group 2 are different fault groups.

[0127] S303: The out-of-band controller predicts the degree of influence of the fault events in the target fault group on the memory.

[0128] Among them, the degree of influence on the memory includes the degree of influence on the memory that has failed. For example, it can be the degree of influence on the memory that has failed at the UCE level.

[0129] It should be noted that the at least two groups in S302 include the target fault group. Among them, the target fault group can be any one of the at least two fault groups.

[0130] In some embodiments, the out-of-band controller predicts the impact of the failure events in the target failure group on the memory failure according to the failure events in a non-target failure group of the at least two failure groups.

[0131] It should be noted that how the out-of-band controller predicts the impact of the failure events in the target failure group on the memory failure according to the failure events in a non-target failure group of the at least two failure groups will be described below in the embodiments shown in Figure 3 and Figure 5 , and will not be described here again.

[0132] In some other embodiments, the out-of-band controller predicts the impact of the failure events in the target failure group on the memory failure according to the failure events in the target failure group.

[0133] In some embodiments, the prediction result can be a probability value of the memory failure. At this time, the size of the impact of the failure events in the target failure group on the memory failure (hereinafter referred to as the impact of the target failure group) is determined according to the size of the probability value.

[0134] In some other embodiments, the prediction result can be a health degree value of the memory. At this time, the size of the impact of the target failure group is determined according to the size of the health degree value.

[0135] It should be noted that how the size of the impact of the target failure group is determined according to the size of the health degree value or the probability value will be described below in the embodiments shown in Figure 7 , Figure 5 , and will not be described here again.

[0136] S304: The out-of-band controller determines that the physical location of the failure events in the target failure group is the to-be-repaired location if the impact meets the first preset condition.

[0137] In some embodiments, if the prediction result is the probability value of the memory failure, the size relationship between the probability value and a preset probability threshold can be used to determine whether the impact meets the first preset condition.

[0138] In some other embodiments, if the prediction result is the health degree value of the memory, the size relationship between the health degree value and a preset health degree threshold can be used to determine whether the impact meets the first preset condition.

[0139] It should be noted that how the size relationship between the probability value or the health degree value and the preset threshold is used to determine whether the impact meets the first preset condition will be described below in the embodiments shown in Figure 6 , Figure 5 , and will not be described here again.

[0140] In the above embodiments, after determining the plurality of fault events occurred in the memory, the plurality of fault events are divided into at least two fault groups according to the physical positions of the plurality of fault events, and the influence degree of the fault events in the target fault group on the failure of the memory is predicted. Since the influence degree of the fault events in the target fault group on the failure of the memory is positively correlated with the repair value of the physical position of the fault events in the target fault group, that is, the greater the influence degree of the target fault group, the greater the repair value of the physical position of the target fault group. When the influence degree meets the first preset condition, the repair value of the physical position of the fault events in the target fault group is higher. Based on this, the physical position of the fault events in the target fault group meeting the first preset condition is determined as the to-be-repaired position, which can ensure that the repair necessity of the physical position of the fault events in the target fault group is higher. Therefore, unnecessary repair operations can be avoided, and the problems of wasting storage resources and fault repair resources of the memory can be avoided. Moreover, the physical position with higher repair necessity on the memory is repaired, which can effectively reduce the risk of failure of the memory, for example, the risk of UCE-level failure, thereby helping to effectively avoid system failure of the computer device.

[0141] Optionally, S305: The out-of-band controller sends a fault repair request, and the fault repair request is used to request to repair the to-be-repaired position.

[0142] The fault repair request can include the identifier of the to-be-repaired position. The identifier of the to-be-repaired position can be the fault position information of the fault events in the target fault group, such as a processor identifier (CPU ID), a channel identifier (Channel ID), a memory identifier (Dimm ID), a memory column identifier (Rank ID), a memory chip identifier (Device ID), a storage array group identifier (Bank Group ID), a storage array identifier (Bank ID), a row address, a column address, and the like.

[0143] In some embodiments, the out-of-band controller sends a fault repair request to the CPU, for example, a request to repair the to-be-repaired position to an OS management unit running in the CPU.

[0144] The repair of the to-be-repaired position includes various implementation manners, which are exemplarily described below by two possible implementation manners.

[0145] In a possible implementation, the to-be-repaired location is repaired based on the hot spare memory in the computer device. For example, when a row repair is used for the to-be-repaired location, a memory row in the hot spare memory is used to replace the memory row in which the to-be-repaired location is located. In this way, after the repair, if the to-be-written data needs to be written into the memory row in which the to-be-repaired location is located, the to-be-written data can be written only into the memory row used for replacement in the hot spare memory, or the to-be-written data can be written into both the memory row in which the to-be-repaired location is located and the memory row used for replacement in the hot spare memory.

[0146] In another possible implementation, the to-be-repaired location is repaired. For example, when a row repair is used for the to-be-repaired location, the memory row in which the to-be-repaired location is located is isolated, so that, after the repair, the to-be-written data will not be written into the memory row in which the to-be-repaired location is located.

[0147] Optionally, the fault repair request includes a fault repair manner. In this way, after the CPU receives the fault repair request, the to-be-repaired location can be repaired according to the fault repair manner in the fault repair request.

[0148] The following takes a row repair as an example to illustrate how the CPU repairs the to-be-repaired location.

[0149] For example, the to-be-repaired location is the memory row 6 shown in FIG. 6, in some embodiments, the CPU can isolate the memory row 6 as a whole, and then the memory will not store data in the memory row 6, which means that the memory row 6 is not used. In other embodiments, the CPU can replace the memory row 6, for example, using the memory row 8 to replace the memory row 6, and then the memory will store the data that should be stored in the memory row 6 in the memory row 8. Figure 6 It should be noted that the embodiments of the present application do not limit the specific repair form of the to-be-repaired location, which can be isolated as a whole or replaced.

[0150] In the above embodiments, the fault repair request is sent to request to repair the to-be-repaired location, thereby reducing the risk of future memory failure, for example, the risk of UCE-level failure, and avoiding system failure caused by memory failure.

[0151] Optionally, the out-of-band controller outputs fault handling information, and the fault handling information includes an identifier of the to-be-repaired location.

[0152] It should be noted that the related description about the identifier of the to-be-repaired location can be referred to the above S305, which will not be described here.

[0153]

[0154] ​In some embodiments, the out-of-band controller outputs the fault handling information to the terminal device, for example, in voice or in text.

[0155] In one example, the out-of-band controller sends the fault handling information to the terminal device for display. In another example, the fault handling information sends the fault handling information to the terminal device for voice play.

[0156] In the above embodiments, the fault handling information is output, for example, in voice or in text, to alert the user of the physical locations to be repaired, so that the user can understand the number of physical locations to be repaired and the specific locations in the memory, thereby helping the user to timely grasp the fault condition of the memory.

[0157] The above, combined with Figure 4 An implementation scheme of the memory fault handling method is introduced. The following, combined with Figure 3 introduced Figure 5 A specific implementation of the scheme shown in is introduced. Specifically, it is Figure 2 A specific implementation of S303 in the scheme shown in is introduced.

[0158] Figure 3 is a flowchart of a memory fault handling method according to an exemplary embodiment. Exemplary, the memory fault handling method includes the following S501-S507.

[0159] S501-S502: Refer to the above S301-S302.

[0160] S503: The out-of-band controller predicts the first fault severity of the memory according to the fault events in the non-target fault group of the at least two fault groups.

[0161] In some embodiments, the first fault severity is a probability value of the memory failure, and the greater the probability value, the greater the probability of the memory failure, and vice versa, the smaller the probability of the failure.

[0162] Since the probability value of the memory failure is predicted according to the fault events in the non-target fault group, it is equivalent to the case where the physical location of the fault event in the target fault group is repaired, or in other words, it has no effect on the memory failure. The probability value of the memory failure is obtained. At this time, if the probability value is large, it means that the physical location of the fault event in the target fault group will not reduce the probability of the memory failure even if it is repaired, which means that the repair value of the physical location of the fault event in the target fault group is low.

[0163] In some embodiments, the prediction result is a health value of the memory. For example, the greater the health value, the greater the probability of failure of the memory, and vice versa.

[0164] It should be noted that the trend between the health value and the probability of failure is not limited in the embodiments of the present application. In the following, the greater the health value, the greater the probability of failure of the memory is taken as an example for illustration.

[0165] Since the health value of the memory is predicted according to the failure events in the non-target failure group, it is equivalent to the case that the physical location of the failure events in the target failure group is repaired, or in other words, the case that it has no effect on the failure of the memory. At this time, if the health value is large, it means that the repair of the physical location of the failure events in the target failure group will not reduce the health value of the memory, which means that the repair value of the physical location of the failure events in the target failure group is low.

[0166] In the following, the way 2 in S302 is taken as an example to illustrate S503.

[0167] As shown above, the failure event 1, the failure event 2 and the failure event 3 belong to the failure group 1, the failure event 4 and the failure event 5 belong to the failure group 2, and the failure event 6 belongs to the failure group 3. In the case that the failure group 1 is the target failure group (hereinafter referred to as the target failure group 1), the failure group 2 and the failure group 3 are non-target failure groups (hereinafter referred to as the non-target failure group 1), and the first failure severity of the memory is predicted according to the failure events in the failure group 2 and the failure group 3. In the case that the failure group 2 is the target failure group (hereinafter referred to as the target failure group 2), the failure group 1 and the failure group 3 are non-target failure groups (hereinafter referred to as the non-target failure group 2), and the first failure severity of the memory is predicted according to the failure events in the failure group 1 and the failure group 3. In the case that the failure group 3 is the target failure group (hereinafter referred to as the target failure group 3), the failure group 1 and the failure group 2 are non-target failure groups (hereinafter referred to as the non-target failure group 3), and the first failure severity of the memory is predicted according to the failure events in the failure group 1 and the failure group 2.

[0168] From the above, it can be seen that in the case that the plurality of failure events are divided into at least two failure groups, the target failure group in the embodiments of the present application can be any one of the at least two failure groups.

[0169] Optionally, S503 comprises: obtaining the first failure severity of the memory output by the failure prediction model according to the failure events in the non-target failure group and the failure prediction model.

[0170] The following, according to the fault events in the non-target fault group and the fault prediction model, the implementation process of the first fault severity of the fault prediction model output is exemplarily illustrated.

[0171] In some embodiments, as shown in Figure 5 The process of obtaining the first fault severity of the memory is illustrated by taking the target fault group 1 as an example. First, the feature extraction is performed on the fault event 4, the fault event 5 and the fault event 6 (i.e. the fault events in the non-target fault group 1), to obtain the feature vector of the non-target fault group, and then the feature vector of the non-target fault group is input into the fault prediction model to obtain the first fault severity of the memory output by the fault prediction model (hereinafter referred to as the first fault severity 1).

[0172] It can be understood that for the target fault group 2, the first fault severity 2 of the memory can be obtained according to the fault events in the non-target fault group 2. For the target fault group 3, the first fault severity 3 of the memory can be obtained according to the fault events in the non-target fault group 3.

[0173] It should be noted that the process of obtaining the first fault severity 2 and the first fault severity 3 of the memory is the same as the process of obtaining the first fault severity 1, which will not be described here.

[0174] When performing feature extraction, the extracted features include one or more of the number of fault events occurring in the recent preset time length, the number of row faults occurring in the recent preset time length, the number of column faults occurring in the recent preset time length, the shortest interval time between two fault events in the recent preset time length, the average number of burst error of parity bits in the recent preset time length, and the maximum value of the nearest distance of bit error of parity bits in the recent preset time length.

[0175] The first preset time length can be 6 minutes, 6 hours, 120 hours, etc. It should be noted that the specific value of the preset time length is not limited in the embodiments of the present application.

[0176] For example, the number of fault events occurring in the recent preset time length can be one or more of the number of CE-level fault events occurring in the recent 6 minutes, the number of CE-level fault events occurring in the recent 6 hours, the number of CE-level fault events occurring in the recent 120 hours, and the number of UCE-level fault events occurring in the recent 120 hours.

[0177] The number of row failures occurring in the recent preset time period can be the number of row failures occurring in the recent 120 hours. Wherein, a row failure is defined as at least two failure events occurring in the same memory row in the recent 24 hours.

[0178] The number of column failures occurring in the recent preset time period can be the number of column failures occurring in the recent 120 hours. Wherein, a column failure is defined as at least two failure events occurring in the same memory column in the recent 24 hours.

[0179] The minimum interval time of N failure events in the failure events occurring in the recent preset time period can be the minimum time interval between two failure events separated by 3 failure events in the failure events occurring in the recent 120 hours.

[0180] The average number of burst errors of parity bits in the failure events occurring in the recent preset time period can be the average number of burst errors of parity bits in the failure events occurring in the recent 120 hours.

[0181] The maximum value of the nearest distance of bit errors of parity bits in the failure events occurring in the recent preset time period can be the maximum value of the nearest distance of bit errors of parity bits in the failure events occurring in the recent 120 hours.

[0182] It should be noted that one parity bit includes 8 burst bits, one burst bit includes 4 bit bits, and one parity bit includes 32 bit bits. Wherein, the value of a bit bit is 1 indicating an error, and the value of a bit bit is 0 indicating normal (i.e. no error). If there is at least one 1 in a burst bit, the burst bit is an error.

[0183] For example, the nearest distance of error bit in parity bit is the nearest distance of bit bit with value 1 in parity bit. For example, the parity bit is 0011 00000001 0001 0000 0000 0000 0000, and the nearest distance is 1 (i.e. the distance between the 3rd and 4th bits from left to right).

[0184] For example, the feature vector of the non-target failure can be a 3-dimensional vector (1, 0, 1), wherein each element corresponds to a feature index, for example, from left to right, the first element is used to indicate the failure time, the second element is used to indicate the failure address, and the third element is used to indicate the failure correction difficulty.

[0185] It should be noted that the embodiments of the present application do not limit the dimension of the feature vector.

[0186] It should be noted that the embodiments of the present application do not limit the specific type of feature extractor, and other types of feature extractors in related technologies can also be used.

[0187] Before performing S503, the initial model needs to be trained to obtain the fault prediction model. The training process of the initial model is exemplarily illustrated through S1-S3 as follows.

[0188] S1: Obtain at least one training sample and at least one sample label of the at least one training sample.

[0189] The training sample and the sample label are in a one-to-one correspondence, that is, one training sample corresponds to one sample label.

[0190] The training sample and the sample label are illustrated by taking at least one training sample as training sample a and the sample label a of the training sample a as an example.

[0191] The training sample a includes a plurality of historical fault events of the memory a, and the sample label a is used to indicate whether the memory a has occurred UCE level fault or not.

[0192] S2: Iteratively train the initial model based on the training sample and the sample label.

[0193] Optionally, the initial model can be a random forest model, an extreme gradient boosting (XGBoost) model, a convolutional neural network (CNN) model, a long short-term memory (LSTM) model, a gradient boosting decision tree (GBDT) model, etc.

[0194] It should be noted that the implementation process of S2 is the same as the principle of the training process of the model in related technologies, which will not be described here.

[0195] S3: In the case that the initial model meets the model convergence condition, the initial model meeting the model convergence condition is determined as the fault prediction model.

[0196] It should be noted that the implementation process of S3 is the same as the principle of the training process of the model in related technologies, which will not be described here.

[0197] S504: determining an influence degree of the target fault group on the memory according to the first fault severity of the memory.

[0198] The influence degree on the memory includes an influence degree of the memory having a fault. For example, the influence degree of the memory having a fault can be an influence degree of the memory having a UCE-level fault.

[0199] The higher the first fault severity of the memory is, the lower the influence degree of the target fault group is.

[0200] Hereinafter, S504 is described by taking the first fault severity as a probability value of the memory having a fault as an example.

[0201] In some embodiments, the first fault severity of the memory is determined as the influence degree of the target fault group, that is, the probability value of the memory having a fault is determined as the influence degree of the fault event in the target fault group on the memory having a fault.

[0202] Based on this, the greater the probability value of the memory having a fault is, the lower the influence degree of the target fault group is, and the lower the repair value of the physical location where the fault event in the target fault group is located is. Conversely, the higher the influence degree of the target fault group is, and the higher the repair value of the physical location where the fault event in the target fault group is located is.

[0203] In other embodiments, the probability value of the memory having a fault is 100% if the physical location where the fault event in the target fault group is located is not repaired, and based on this, a difference between the probability value 100% and the predicted probability value of the memory having a fault is determined as the influence degree of the target fault group.

[0204] Based on this, the greater the probability value of the memory having a fault is, the smaller the difference is, the lower the influence degree of the target fault group is, and the lower the repair value of the physical location where the fault event in the target fault group is located is. Conversely, the higher the influence degree of the target fault group is, and the higher the repair value of the physical location where the fault event in the target fault group is located is.

[0205] It should be noted that when the first fault severity is a health degree value of the memory, the principle of determining the influence degree of the target fault group is the same as that when the first fault severity is a probability value of the memory having a fault, which is not described here.

[0206] It should be noted that S503 to S504 can be regarded as a specific implementation manner of S303.

[0207] S505: determining the physical location where the fault event in the target fault group is located as a to-be-repaired location when the influence degree meets a first preset condition.

[0208] The following describes S505 by taking the first failure severity as the probability value of memory failure as an example.

[0209] In some embodiments, if the impact degree is the first probability value (e.g., the first failure severity in S504), the impact degree satisfying the first preset condition includes that the first probability value is less than or equal to a first preset probability threshold.

[0210] Since the greater the first probability value is, the smaller the impact degree of the target failure group on the memory is. Conversely, the smaller the first probability value is, the greater the impact degree of the target failure group on the memory is. Therefore, the impact degree of the target failure group satisfying the first preset condition is that the first probability value is less than or equal to the first preset probability threshold.

[0211] For example, the first preset probability threshold is 40%, the first probability value of the target failure group 1 is 35%, the first probability value of the target failure group 2 is 65%, and the first probability value of the target failure group 3 is 39%. The target failure group 1 and the target failure group 3 satisfy the first preset condition, and the target failure group 2 does not satisfy the first preset condition. Based on this, the physical locations of the failure events in the target failure group 1 and the target failure group 3 are determined as the to-be-repaired locations, and the physical locations of the failure events in the target failure group 2 are not determined as the to-be-repaired locations. In other embodiments, the impact degree is the second probability value (e.g., the difference value in S504), and the impact degree satisfying the first preset condition includes that the second probability value is greater than or equal to a second preset probability threshold.

[0212] Since the greater the second probability value is, the greater the impact degree of the target failure group on the memory is. Therefore, the impact degree of the target failure group satisfying the first preset condition is that the second probability value is greater than or equal to the second preset probability threshold.

[0213] For example, the second preset probability threshold is 60%, the impact degree of the target failure group 1 is 65%, the impact degree of the target failure group 2 is 35%, and the impact degree of the target failure group 3 is 61%. The target failure group 1 and the target failure group 3 satisfy the first condition, and the target failure group 2 does not satisfy the first preset condition. Based on this, the physical locations of the failure events in the target failure group 1 and the target failure group 3 are determined as the to-be-repaired locations, and the physical locations of the failure events in the target failure group 2 are not determined as the to-be-repaired locations. In yet other embodiments, the impact degree satisfying the first preset condition includes that the impact degree of the target failure group is greater than the impact degree of a non-target failure group.

[0214] The impact degree of the non-target failure group is determined according to the failure events in the target failure group.

[0215] For example, the influence degree of the target fault group 1 is 65%, and the influence degree of the non-target fault group 1 is 30%. The influence degree of the target fault group 2 is 35%, and the influence degree of the non-target fault group 2 is 65%. The influence degree of the target fault group 3 is 61%, and the influence degree of the non-target fault group 3 is 35%. Based on this, the influence degree of the target fault group 1 is greater than the influence degree of the non-target fault group 1, and therefore, the influence degree of the target fault group 1 meets the first preset condition. The influence degree of the target fault group 2 is less than the influence degree of the non-target fault group 2, and therefore, the influence degree of the target fault group 2 does not meet the first preset condition. The influence degree of the target fault group 3 is greater than the influence degree of the non-target fault group 3, and therefore, the influence degree of the target fault group 3 meets the first preset condition.

[0216] In some other embodiments, the influence degree meeting the first preset condition comprises that the ranking of the influence degree of the target fault group in the plurality of influence degrees of the plurality of fault groups is greater than or equal to a preset ranking threshold.

[0217] For example, the influence degree of the target fault group 1 is 65%, the influence degree of the target fault group 2 is 35%, and the influence degree of the target fault group 3 is 61%. The target fault group 1, the target fault group 2, and the target fault group 3 are ranked according to the influence degree, for example, ranked in the order of the influence degree from large to small, and the ranking result is the target fault group 1, the target fault group 2, and the target fault group 3. If the preset ranking threshold is 2, the influence degree of the target fault group ranked as the first or the second meets the first preset condition, that is, the target fault group 1 and the target fault group 3 meet the first preset condition, and the target fault group 2 does not meet the first preset condition.

[0218] Of course, the target fault group 1, the target fault group 2, and the target fault group 3 can also be ranked in the order of the influence degree from small to large. If the preset ranking threshold is 2, the influence degree of the target fault group ranked as the second or the third meets the first preset condition.

[0219] Optionally, the preset ranking threshold can be determined according to the number of the plurality of fault groups and / or the number of the to-be-repaired positions of the predicted repair. It should be noted that the specific value of the preset ranking threshold is not limited in the embodiments of the present application.

[0220] It should be noted that when the first fault severity is the health degree value of the memory, the principle of determining that the influence degree meets the preset condition is the same as that when the first fault severity is the probability value of the memory failure, which will not be described here.

[0221] S506-S507: Refer to S305-S306 described above.

[0222] In the above embodiment, the first failure severity predicted according to the failure events in the non-target failure group is equivalent to the failure severity of the memory after the physical location where the failure events in the target failure group are repaired. Based on this, the higher the first failure severity is, the lower the impact of the failure events in the target failure group on the memory is, and the lower the repair value is. In other words, even if the physical location where the failure events in the target failure group are repaired, the failure severity of the memory that can be reduced is very limited. Therefore, according to the first failure severity of the memory, the impact of the failure events in the target failure group on the memory is determined, which helps to more accurately indicate the repair value of the physical location where the failure events in the target failure group are located, and further helps to ensure that when the repair value of the physical location where the failure events in the target failure group are located is high, it is determined as the to-be-repaired location. In this way, unnecessary repair operations can be more effectively avoided, and the problem of wasting memory storage resources and failure repair resources can be avoided.

[0223] The above, in combination with Figure 6 , introduces Figure 5 a specific implementation mode of S303 in the scheme shown in the figure. The following, in combination with Figure 3 introduce Figure 7 another specific implementation mode of S303 in the scheme shown in the figure, and a specific implementation mode of S304.

[0224] Figure 3 is a flowchart of a memory failure processing method according to an example embodiment. The example memory failure processing method includes the following S701-S708.

[0225] S701-S702: refer to the above S301-S302.

[0226] S703: refer to the above S503.

[0227] S704: predicting a second failure severity according to the plurality of failure events and the failure prediction model.

[0228] If it is said that the first failure severity predicted according to the failure events in the non-target failure group is equivalent to the failure severity of the memory after the physical location where the failure events in the target failure group are repaired. Then, according to the second failure severity predicted according to the failure events in the plurality of failure groups, it is equivalent to the failure severity of the memory when the physical location where the failure events in the target failure group are not repaired.

[0229] It should be noted that the implementation principle of S704 is the same as that of S503, and therefore, for the implementation process and related description of S704, reference can be made to the above S503, which will not be described in detail here.

[0230] S705: determining the influence degree of the target fault group on the memory according to the difference between the second fault severity of the memory and the first fault severity of the memory.

[0231] The influence degree on the memory includes the influence degree on the memory failure. For example, it can be the influence degree on the memory to occur UCE level failure.

[0232] Hereinafter, only taking the first fault severity and the second fault severity as the probability value of the memory failure as an example, S705 is described.

[0233] In some embodiments, the difference (i.e. the difference) between the first fault severity and the first fault severity is determined as the influence degree of the target fault group.

[0234] Since the second fault severity is the fault severity of the memory when the physical location of the fault event in the target fault group is not repaired, and the first fault severity is the fault severity of the memory when the physical location of the fault event in the target fault group is repaired, the difference is caused by the fault event in the target fault group.

[0235] Based on this, the smaller the difference, the lower the influence degree of the target fault group, and the lower the repair value of the physical location of the fault event in the target fault group. Conversely, the influence degree of the target fault group is higher, and the repair value of the physical location of the fault event in the target fault group is higher.

[0236] Hereinafter, S705 is exemplarily described by taking mode 2 in S302 as an example.

[0237] As shown above, fault event 1, fault event 2 and fault event 3 belong to fault group 1, fault event 4 and fault event 5 belong to fault group 2, and fault event 6 belongs to fault group 3.

[0238] For example, based on the fault events in fault group 1, fault group 2 and fault group 3, the predicted second fault severity is 0.7.

[0239] If the first fault severity 1 predicted based on the fault events in fault group 2 and fault group 3 is 0.6, the influence degree of target fault group 1 is 0.1 (i.e. 0.7-0.6).

[0240] If the first failure severity 2 predicted based on the failure events in failure group 1 and failure group 3 is 0.35, the impact degree of the target failure group 2 is 0.35 (i.e. 0.7-0.35).

[0241] If the first failure severity 3 predicted based on the failure events in failure group 1 and failure group 2 is 0.55, the impact degree of the target failure group 3 is 0.15 (i.e. 0.7-0.35).

[0242] In some embodiments, the first failure severity and the second failure severity are predicted based on respective failure prediction methods, so that the two different failure severities of the memory can be compared in the same dimension, which helps to improve the accuracy of the impact degree of the target failure group determined based on the first failure severity and the second failure severity.

[0243] In addition, the first failure severity and the second failure severity are in the same data form, for example, when the first failure severity is a probability value of the memory failure, the second failure severity should also be a probability value of the memory failure.

[0244] It should be noted that when the first failure severity and the second failure severity are health values of the memory, the principle of determining the impact degree of the failure event in the target failure group on the memory is the same as that when the first failure severity and the second failure severity are probability values of the memory failure, which will not be described here.

[0245] It should be noted that S703 to S705 can be regarded as another specific implementation manner of S303.

[0246] S706: The out-of-band controller determines that the physical location of the failure event in the target failure group is the to-be-repaired location when the impact degree meets the first preset condition and the second failure severity meets the second preset condition.

[0247] Hereinafter, S706 will be described only by taking the first failure severity and the second failure severity as probability values of the memory failure as an example.

[0248] In some embodiments, the impact degree meeting the first preset condition includes that the impact degree of the target failure group is greater than or equal to a third preset probability threshold.

[0249] In some other embodiments, the impact degree meeting the first preset condition includes that the impact degree of the target failure group is greater than the impact degree of a non-target failure group.

[0250] In yet some other embodiments, the impact degree meeting the first preset condition includes that the ranking of the impact degree of the target failure group in the multiple impact degrees of the multiple failure groups is greater than or equal to a preset ranking threshold.

[0251] It should be noted that the detailed description of the influence degree satisfying the first preset condition can refer to S505, and will not be described here.

[0252] In some embodiments, the second fault severity satisfying the second preset condition comprises the second fault severity being greater than or equal to a fourth preset probability threshold.

[0253] For example, as shown in S705, the second fault severity of the memory is 0.7, the influence degree of the target fault group 2 is 0.35, the third preset probability threshold is 0.3, and the fourth preset probability threshold is 0.6. Since the second fault severity is greater than the fourth preset probability threshold, and the influence degree of the target fault group 2 is greater than the third preset probability threshold, the physical location of the fault event in the target fault group is determined as the to-be-repaired location.

[0254] S707-S708: Refer to S305-S306 described above.

[0255] In the above embodiments, the first fault severity predicted according to the fault events in the non-target fault group is equivalent to the fault severity of the memory after the physical location of the fault event in the target fault group is repaired, and the second fault severity predicted according to the fault events in the plurality of fault groups is equivalent to the fault severity of the memory when the physical location of the fault event in the target fault group is not repaired. Based on this, the difference between the second fault severity and the first fault severity is the influence degree of the fault event in the target fault group on the memory. Therefore, according to the difference between the second fault severity and the first fault severity, the influence degree of the fault event in the target fault group on the memory is determined, which helps to improve the accuracy of the influence degree, so that the influence degree of the target fault group can more accurately indicate the repair value of the physical location of the fault event in the target fault group, and further help to ensure that when the repair value of the physical location of the fault event in the target fault group is high, it is determined as the to-be-repaired location. In this way, unnecessary repair operations can be more effectively avoided, and the problem of wasting memory storage resources and fault repair resources can be avoided.

[0256] The above describes the solutions provided by the embodiments of the present application from the method aspect. To implement the above functions, the memory fault processing apparatus comprises hardware structures and / or software modules corresponding to the functions. Those skilled in the art should easily realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is implemented in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solutions. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0257] The embodiments of the present application can divide the functional modules of the memory fault processing apparatus according to the above method. For example, the memory fault processing apparatus can comprise functional modules corresponding to each function, or two or more functions can be integrated into one processing module. The integrated module can be implemented in the form of hardware or software functional module. It should be noted that the division of modules in the embodiments of the present application is illustrative, and is only a logical functional division. Actual implementation can have another division manner.

[0258] For example, Figure 7 A possible structure diagram of the memory fault processing apparatus (denoted as memory fault processing apparatus 800) involved in the above embodiments is shown, which comprises a processing unit 801 and a prediction unit 802. The processing unit 801 is configured to determine a plurality of fault events of the memory. For example, Figure 8 S301 shown, Figure 3 S501 shown, and Figure 5 S701 shown. The processing unit 801 is further configured to divide the plurality of fault events into at least two fault groups according to physical positions of the plurality of fault events, wherein the at least two groups comprise a target fault group. For example, Figure 7 S302 shown, Figure 3 S502 shown, and Figure 5 S702 shown. The prediction unit 802 is configured to predict an influence degree of the fault events in the target fault group on the memory. For example, Figure 7 S303 shown, Figure 3 S503-S504 shown, and Figure 5 S703-S705 shown. The processing unit 801 is further configured to determine a physical position where the fault events in the target fault group occur as a to-be-repaired position in a case where the influence degree satisfies a first preset condition. For example, Figure 7 S304 shown, Figure 3S505 is shown, and Figure 5 Figure 7 S706 is shown.

[0259] Optionally, the prediction unit 802 is specifically configured to predict a first fault severity of the memory according to the fault events in the non-target fault group of the at least two fault groups; determine the influence degree of the fault events in the target fault group on the memory according to the first fault severity of the memory; the higher the first fault severity of the memory, the lower the influence degree of the fault events in the target fault group on the memory.

[0260] Optionally, the prediction unit 802 is specifically configured to predict a first fault severity of the memory according to the fault events in the non-target fault group of the at least two fault groups; predict a second fault severity of the memory according to the plurality of fault events; determine the influence degree of the fault events in the target fault group on the memory according to a difference between the second fault severity of the memory and the first fault severity of the memory; wherein the smaller the difference, the lower the influence degree of the fault events in the target fault group on the memory.

[0261] Optionally, the processing unit 801 is specifically configured to determine the physical location of the fault events in the target fault group as the to-be-repaired location when the influence degree meets the first preset condition and the second fault severity meets the second preset condition.

[0262] Optionally, the prediction unit 802 is specifically configured to input the plurality of fault events into a fault prediction model to obtain a second fault severity output by the fault prediction model.

[0263] Optionally, the prediction unit 802 is specifically configured to input the fault events in the non-target fault group of the at least two fault groups into a fault prediction model to obtain a first fault severity output by the fault prediction model.

[0264] Optionally, the processing unit 801 is specifically configured to divide the plurality of fault events into at least two fault groups according to the physical locations of the plurality of fault events and the granularity of the physical locations repaired by the fault repair methods; wherein the fault repair method is of the same type as the fault repair method to be used for the to-be-repaired location.

[0265] Optionally, the processing unit 801 is further configured to send a fault repair request, the fault repair request being used to request to repair the to-be-repaired location.

[0266] Optionally, the processing unit 801 is further configured to output fault processing information, the fault processing information including an identifier of the to-be-repaired location.

[0267] Optionally, the plurality of failure events comprises a first failure event, and the first failure event comprises failure time information, failure location information and failure correction difficulty information of the memory failure indicated by the first failure event.

[0268] The specific description of the above optional mode can be referred to the foregoing method embodiments, and will not be described here. In addition, the explanation and beneficial effect description of any one of the above provided memory failure processing apparatus 800 can be referred to the corresponding method embodiments, and will not be described here.

[0269] The embodiment of the present application further provides a computer device, which comprises a processor and a memory, the processor is connected with the memory, the memory stores computer execution instructions, and the processor realizes the data processing method in the foregoing embodiment when executing the computer execution instructions. The embodiment of the present application does not make any limitation to the specific form of the computer device. For example, the computer device can be a terminal apparatus or a network device. The terminal apparatus can be referred to as a terminal, a user equipment (UE), a terminal device, an access terminal, a user unit, a user station, a mobile station, a remote station, a remote terminal, a mobile device, a user terminal, a wireless communication device, a user agent or a user apparatus, etc. The terminal apparatus can be a mobile phone, an augmented reality (AR) device, a virtual reality (VR) device, a tablet computer, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a personal digital assistant (PDA), etc. The network device can be a server, etc. The server can be one physical or logical server, or two or more physical or logical servers sharing different responsibilities, and cooperating with each other to realize the functions of the server.

[0270] The embodiment of the present application further provides a computer readable storage medium, which stores a computer program, and when the computer program runs on a computer, the computer program makes the computer execute the method executed by any one of the computer devices provided above.

[0271] The explanation and beneficial effect description of the related content in any one of the above provided computer readable storage medium can be referred to the corresponding embodiments, and will not be described here.

[0272] The embodiments of the present application further provide a chip. The chip integrates a control circuit and one or more ports for implementing the functions of the computer device. Optionally, the functions supported by the chip can refer to the above, and will not be described here. Those skilled in the art can understand that all or part of the steps of the above-mentioned embodiments can be instructed by a program to relevant hardware to complete. The program can be stored in a computer readable storage medium. The storage medium mentioned above can be a read-only memory, a random access memory, etc. The above-mentioned processing unit or processor can be a central processing unit, a general-purpose processor, an application specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA) or other programmable logic device, a transistor logic device, a hardware component or any combination thereof.

[0273] The embodiments of the present application further provide a computer program product containing instructions, which, when executed on a computer, cause the computer to perform any of the methods in the above embodiments. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, all or part of the processes or functions according to the embodiments of the present application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another, for example, the computer instructions can be transferred from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode. The computer readable storage medium can be any available medium that can be accessed by a computer or data storage device including one or more servers, data centers, etc. integrated with the medium. The available medium can be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as an SSD), etc.

[0274] It should be noted that the above-mentioned devices for storing computer instructions or computer programs provided by the embodiments of the present application, such as but not limited to the above-mentioned memory, computer readable storage medium and communication chip, etc., all have non-volatility (non-transitory).

[0275] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions according to the embodiments of the present application are generated. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions can be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be transmitted from one website site, computer, server or data center to another website site, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode. The computer readable storage medium can be any available medium that can be accessed by a computer or data storage device including one or more servers, data centers, etc. integrated with the medium. The available medium can be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)), etc.

[0276] Although the present application is described herein in conjunction with various embodiments, it is understood that other variations of the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from an inspection of the drawings, the disclosure, and the appended claims. The word "comprising" does not exclude other components or steps not listed in the claims, "a" or "an" does not exclude a plurality, and a single processor or other unit can fulfill the functions of several means recited in the claims. Means-plus-function or step-plus-function clauses are used where for procedural or logical operations, the recitation of means or steps in a claim is intended to encompass both implementations of the means or steps in addition to the corresponding structure or acts for performing the recited functions. The means-plus-function clauses are intended to cover both the structure and the functions of the means described.

[0277] Although the present application is described herein in conjunction with various embodiments, it is understood that other variations of the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from an inspection of the drawings, the disclosure, and the appended claims. The word "comprising" does not exclude other components or steps not listed in the claims, "a" or "an" does not exclude a plurality, and a single processor or other unit can fulfill the functions of several means recited in the claims. Means-plus-function or step-plus-function clauses are used where for procedural or logical operations, the recitation of means or steps in a claim is intended to encompass both implementations of the means or steps in addition to the corresponding structure or acts for performing the recited functions. The means-plus-function clauses are intended to cover both the structure and the functions of the means described.

Claims

1. A memory failure handling method, characterized by, The method comprises: determining a plurality of fault events occurring in the memory; dividing the plurality of fault events into at least two fault groups according to physical locations of the plurality of fault events; the at least two groups include a target fault group; predicting a first fault severity of the memory according to fault events in a non-target fault group of the at least two fault groups; determining an influence degree of the fault events in the target fault group on the memory according to the first fault severity of the memory; wherein the higher the first fault severity of the memory is, the lower the influence degree of the fault events in the target fault group on the memory is; or predicting a first fault severity of the memory according to fault events in a non-target fault group of the at least two fault groups; predicting a second fault severity of the memory according to the plurality of fault events; determining an influence degree of the fault events in the target fault group on the memory according to a difference between the second fault severity of the memory and the first fault severity of the memory; wherein the smaller the difference is, the lower the influence degree of the fault events in the target fault group on the memory is; in a case where the influence degree meets a first preset condition, determining a physical location of the fault events in the target fault group as a to-be-repaired location.

2. The method of claim 1, wherein, The case where the influence degree meets the first preset condition and the physical location of the fault events in the target fault group is determined as the to-be-repaired location comprises: in a case where the influence degree meets the first preset condition and a second fault severity meets a second preset condition, the physical location of the fault events in the target fault group is determined as the to-be-repaired location.

3. The method according to claim 1 or 2, characterized in that, The dividing of the plurality of fault events into at least two fault groups according to physical locations where the plurality of fault events occur comprises: dividing the plurality of fault events into at least two fault groups according to physical locations where the plurality of fault events occur and granularity of physical locations repaired by a fault repair mode; wherein the fault repair mode is of a same type as a fault repair mode to be used for the to-be-repaired location.

4. The method according to claim 1 or 2, characterized in that, The method further comprises: sending a fault repair request, the fault repair request being used for requesting repair of the to-be-repaired location.

5. The method according to claim 1 or 2, characterized in that, The method further comprises: outputting fault processing information, the fault processing information including an identifier of the to-be-repaired location.

6. The method of claim 1 or 2, wherein the plurality of fault events include a first fault event, and the first fault event includes fault time information, fault location information, and fault correction difficulty information of a memory fault indicated by the first fault event.

7. A computer device, comprising: comprise a processor, an out-of-band controller, and a memory; the processor is in communication connection with the memory, and the processor is also in communication connection with the out-of-band controller; the out-of-band controller is configured to determine a plurality of fault events occurring in the memory; the out-of-band controller is further configured to divide the plurality of fault events into at least two fault groups according to physical locations of the plurality of fault events; the at least two groups include a target fault group; The out-of-band controller is further configured to predict a first severity of the memory according to the fault events in the non-target fault group of the at least two fault groups; According to the first severity of the memory, determine the influence degree of the fault events in the target fault group on the memory; wherein the higher the first severity of the memory, the lower the influence degree of the fault events in the target fault group on the memory; or, according to the fault events in the non-target fault group of the at least two fault groups, predict the first severity of the memory; according to the plurality of fault events, predict a second severity of the memory; according to the difference between the second severity of the memory and the first severity of the memory, determine the influence degree of the fault events in the target fault group on the memory; wherein the smaller the difference, the lower the influence degree of the fault events in the target fault group on the memory; The out-of-band controller is further configured to determine the physical location of the fault events in the target fault group as a to-be-repaired location if the influence degree meets a first preset condition.

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