Display panel and display device

Abstract

The present invention discloses a display panel and a display device, wherein when a pixel circuit in the display panel works in a data writing stage, a clock pulse frequency of a clock signal is a first frequency F1; when the pixel circuit works in a holding stage, N stages are provided, and in at least one of the N stages, the clock pulse frequency of the clock signal is a second frequency F2, where F1>F2>0. Thus, on the one hand, the power consumption of the display panel is saved, and on the other hand, when the clock signal is kept at a constant potential for a long time, the transistor of the driving circuit is prevented from being in the same state for a long time, thereby causing the problem of unstable output signal.

Description

[0001] This application is a divisional application with the application date of September 14, 2021, application number 202111076370.X, and the name of the invention being “Display panel and display device”. Technical Field

[0002] The present invention belongs to the field of display technology, and in particular relates to a display panel and a display device. Background Art

[0003] At present, display panels have penetrated into all aspects of people's daily lives. For example, display panels are used as display interaction modules of various devices for users to watch accordingly. When the display panel is running, the pixel circuit of the display panel is controlled by the driving circuit. However, due to factors such as leakage current, the output signal of the driving circuit is unstable. Summary of the invention

[0004] Embodiments of the present invention provide a display panel and a display device, which can avoid the problem of unstable output signals of a driving circuit due to factors such as leakage current.

[0005] On one hand, the present application provides a display panel, including:

[0006] A pixel circuit, the pixel circuit comprising a driving transistor;

[0007] A driving circuit, the driving circuit is used to provide a control signal for the pixel circuit;

[0008] A clock signal line, used to provide a clock signal to the driving circuit;

[0009] A data refresh cycle of the pixel circuit includes a data writing phase and a holding phase, and the holding phase includes N phases arranged in sequence, N≥1; wherein,

[0010] When the pixel circuit works in the data writing stage, the clock pulse frequency of the clock signal is the first frequency F1;

[0011] When the pixel circuit operates in the holding phase, in at least one phase among the N phases, the clock pulse frequency of the clock signal is the second frequency F2;

[0012] F1>F2>0.

[0013] Another aspect of the present application provides a display device, comprising the above-mentioned display panel.

[0014] Compared with the prior art, in the display panel and display device provided by the embodiments of the present application, when the pixel circuit works in the holding stage, it includes N stages. In at least one stage of the N stages, the clock pulse frequency of the clock signal is F2, and F2 is greater than 0, and F2 is less than the clock pulse frequency F1 of the clock signal in the data writing stage. Therefore, when the pixel circuit is working, the clock signal can maintain a certain pulse frequency output, avoiding the transistor of the driving circuit from being kept in the same state for a long time, and then causing the problem of unstable output signal due to leakage current and other factors. On the other hand, the clock pulse frequency of the clock signal when the pixel circuit works in the holding stage is lower, saving power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments of the present invention are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 The present invention is a schematic diagram of an optional circuit structure of a pixel circuit and a switch element in a display panel.

[0017] Figure 2 The present invention is a schematic diagram of an optional circuit structure of a driving circuit in a display panel.

[0018] Figure 3 It is a schematic diagram of the clock frequency of the clock signal when the pixel circuit is in different working stages in an embodiment of the display panel of the present invention.

[0019] Figure 4 It is a schematic diagram of the clock frequency of the clock signal when the pixel circuit is in different working stages in another embodiment of the display panel of the present invention.

[0020] Figure 5 It is a schematic diagram of the clock frequency of the clock signal when the pixel circuit is in different working stages in an optional example of the display panel of the present invention.

[0021] Figure 6 It is a schematic diagram of the clock frequency of the clock signal when the pixel circuit is in different working stages in another optional example of the display panel of the present invention.

[0022] Figure 7 It is a schematic diagram of the clock frequency of the clock signal when the pixel circuit is in different working stages in another embodiment of the display panel of the present invention.

[0023] Figure 8It is a schematic diagram of the clock frequency of the clock signal when the pixel circuit is in different working stages in another embodiment of the display panel of the present invention.

[0024] Fig. 9 It is a circuit structure diagram of a driving circuit and a pixel circuit in another embodiment of a display panel of the present invention.

[0025] Fig.10 FIG. 1 is a schematic diagram of a display device according to an embodiment of the present invention.

[0026] In the accompanying drawings: pixel circuit 10, light emitting element 20, driving transistor T0, driving module 11, light emitting control module 12, data writing module 14, compensation module 15, reset module 16, initialization module 17, first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, driving circuit 21, data signal Vdata, first scan signal S1, second scan signal S2, third scan signal S3, fourth scan signal S4, reset signal Vref, light emitting control signal EM, initialization signal Vini, first driving circuit 211, second driving circuit 212, clock signal, clock signal CK, first clock signal CK1, second clock signal CK2. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0028] It should be noted that the terms "upper", "lower", "left", "right", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on this patent. The terms "first" and "second" are only used for the convenience of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features. "Multiple" means two or more, unless otherwise clearly and specifically defined. In addition, terms such as "horizontal", "vertical", and "overhanging" do not mean that the components are required to be absolutely horizontal or overhanging, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0029] It should also be noted that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0030] In order to illustrate the technical solution of the present application, a detailed description is given below in conjunction with specific drawings and embodiments.

[0031] With the development of display technology, display panels are widely used in electronic devices such as mobile phones, televisions, notebooks and computers. Figure 1 , which shows an optional circuit structure schematic diagram of a pixel circuit 10 and a light-emitting element 20 in a display panel. The display panel may include a pixel circuit 10 and a light-emitting element 20.

[0032] The light-emitting element 20 may be a LED (Light-Emitting Diode), an OLED (Organic Electroluminescence Display) or others.

[0033] The pixel circuit 10 can be used to provide a driving current for the light emitting element 20 of the display panel. The pixel circuit 10 can also be connected to a data signal line (not shown). The data signal line can be used to provide a data signal Vdata for the pixel circuit 10 .

[0034] The pixel circuit 10 may include a driving module 11, and the driving module 11 may include a driving transistor T0, and the gate of the driving transistor T0 receives the data signal Vdata written by the data signal line. When the pixel circuit 10 provides a driving current for the light-emitting element 20, the driving transistor T0 actually serves as a core component of the pixel circuit 10 to generate the driving current.

[0035] The driving transistor T0 may be an oxide semiconductor transistor, in particular, an IGZO (Indium Gallium Zinc Oxide) transistor, or a silicon transistor, in particular, an LTPS (Low Temperature Poly-Silicon) transistor, or others.

[0036] Please continue to see Figure 1In addition to the driving transistor T0 , the pixel circuit 10 may also include a light emitting control module 12 , a data writing module 14 , a compensation module 15 , a reset module 16 and an initialization module 17 .

[0037] The light emitting control module 12 can be used to selectively allow the light emitting element 20 to enter the light emitting stage; the light emitting control module 12 can include a third transistor T3 and a fourth transistor T4. The control terminals of the third transistor T3 and the fourth transistor T4 are connected to a light emitting control signal line (not shown) for receiving a light emitting control signal EM.

[0038] When the light-emitting control signal line outputs a valid pulse (i.e., the light-emitting control signal EM), the third transistor T3 and the fourth transistor T4 are turned on to drive the light-emitting element 20 to enter the light-emitting stage, and the driving current flows into the light-emitting element 20. When the light-emitting control signal line outputs an invalid pulse, the third transistor T3 and the fourth transistor T4 are turned off to disconnect the path for the driving current to flow into the light-emitting element 20.

[0039] The data writing module 14 can be used to selectively provide a data signal Vdata to the driving transistor T0; the data writing module 14 can include a first transistor T1. The drain of the first transistor T1 can be connected to the source of the driving transistor T0, the source of the first transistor T1 can be connected to the data signal line, and can receive the data signal Vdata, and the control end of the first transistor T1 can be connected to the first scanning signal line, and can be used to receive the first scanning signal S1, and the first scanning signal S1 can control the opening and closing of the first transistor T1.

[0040] The compensation module 15 can be connected between the gate of the driving transistor T0 and the drain of the driving transistor T0, and the compensation module 15 can be used to compensate for the threshold voltage of the driving transistor T0. The compensation module 15 can include a second transistor T2, and the control end of the second transistor T2 is connected to the second scanning signal line, and can receive the second scanning signal S2, and the second scanning signal S2 can control the second transistor T2 to turn on or off.

[0041] The reset module 16 can be connected between the reset signal terminal and the gate of the driving transistor T0, and the reset module 16 can be used to provide a reset signal Vref for the gate of the driving transistor T0. The reset module 16 can include a fifth transistor T5, the source of the fifth transistor T5 can be connected to the reset signal terminal, and can be used to receive the reset signal Vref, and the gate of the fifth transistor T5 is connected to the third scan signal line, and can be used to receive the third scan signal S3.

[0042] Initialization module 17, which can be connected between the initialization signal terminal and the light emitting element 20, can be used to selectively provide the initialization signal Vini to the light emitting element 20. The control terminal of the initialization module 17 can be connected to the fourth scanning signal line to receive the fourth scanning signal S4.

[0043] Optionally, the initialization module 17 may include a seventh transistor T7, the source of the seventh transistor T7 is connected to the initialization signal terminal, the drain of the seventh transistor T7 is connected to the light emitting element 20, and the gate of the seventh transistor T7 is connected to the fourth scanning signal line. When the initialization module 17 is turned on, the pixel circuit 10 enters the initialization stage.

[0044] It is understandable that based on Figure 1 The optional circuit structure of the pixel circuit 10 and the light emitting element 20 of the display panel is shown. In order to enable the pixel circuit 10 to provide driving current to the light emitting element 20 in an orderly manner, a driving circuit is also required in the display panel. Figure 1 and Figure 2 ,in Figure 2 A schematic diagram of an optional driving circuit structure provided for an embodiment of a display panel of the present application.

[0045] See also Figure 1 and Figure 2 It can be known that a driving circuit 21 may be further provided in the display panel, and the driving circuit 21 may be used to provide a control signal for the pixel circuit 10. The driving circuit 21 includes a plurality of transistors, and some transistors in the driving circuit 21 may be connected to the clock signal line, for example, some transistors may include transistors M5, M6, etc.

[0046] The clock signal line can be used to provide a clock signal CK to the driving circuit 21. As one of the signals received by the driving circuit 21, the clock signal CK can be output at a clock pulse frequency or at a constant potential.

[0047] Optionally, in an embodiment of the present application, a data writing cycle of the display panel may include S frame refresh images, S>0, and may include a data writing frame and a holding frame. The data writing frame may include a data writing phase; the holding frame does not include a data writing phase, and may include a holding phase, that is, a data refresh cycle of the pixel circuit 10 may include a data writing phase and a holding phase.

[0048] In the data writing stage, the data signal line can write the data signal Vdata to the gate of the driving transistor T0, at which time the data writing module 14, the driving module 11 and the compensation module 15 can be turned on, and the data signal Vdata is written to the gate of the driving transistor T0. In the holding stage, the data signal line does not write the data signal Vdata to the gate of the driving transistor T0.

[0049] It should be noted that when the pixel circuit 10 is in the holding stage, the driving circuit 21 provides an invalid pulse signal to the pixel circuit 10 to control the corresponding transistor to turn off, but when the holding stage is long, the driving circuit 21 will continue to output the same signal for a long time.

[0050] On the one hand, if the clock signal CK is output at a clock pulse frequency of F1 during the holding phase, and since the driving circuit 21 outputs the same signal during the holding phase, the jump of the clock signal CK cannot cause the jump of the output signal of the driving circuit 21. Therefore, the clock signal CK will jump at a higher frequency F1, resulting in greater power consumption.

[0051] On the other hand, if the clock signal CK is maintained at a constant potential during the holding phase, when the holding phase is long, the driving circuit 21 will continue to output the same signal for a long time, which will cause the transistors in the driving circuit 21 to accumulate leakage current, thereby causing the output signal to shift and the transistor output of the driving circuit 21 to be unstable.

[0052] It should be noted that when the output signal of the driving circuit 21 is offset to a certain extent, the transistors in some pixel circuits 10 that were originally turned off will gradually tend to be turned on, and then the leakage current of these transistors will increase rapidly, causing the potential of the transistors to change. Because the function of the pixel circuit 10 is to generate the driving current required by the light-emitting element 20, when the leakage current of the transistors therein is too large, it may cause the driving current to change, thereby causing uneven light emission on the display panel and flickering when grayscale switching occurs.

[0053] Therefore, in order to solve the above problem, in this embodiment, the holding phase of the pixel circuit 10 includes N phases arranged in sequence, where N≥1. Figures 1 to 3 ,in, Figure 3 is a comparison diagram of clock pulse frequencies when the pixel circuit 10 works at different stages, Figure 3 When the pixel circuit 10 works in the data writing stage, the clock pulse frequency of the clock signal CK is the first frequency F1; when the pixel circuit 10 works in the holding stage, in at least one stage among the N stages, the clock pulse frequency of the clock signal CK is the second frequency F2, F1>F2>0.

[0054] It can be understood that when the pixel circuit 10 operates in the data writing stage, the first frequency F1 of the clock pulse signal is greater than the clock pulse frequency F2 of at least one stage when the pixel circuit 10 operates in the holding stage, that is, relative to the data writing stage of the pixel circuit 10, a frequency reduction setting is performed in at least one stage when the pixel circuit 10 is in the holding stage, which saves power consumption compared to the jump of the higher first frequency F1.

[0055] At the same time, when the frequency reduction is set, it is ensured that the second frequency F2 after the reduction is greater than 0, which can avoid the problem that when the second frequency F2 is 0, the clock signal CK does not jump, resulting in the transistor of the driving circuit 21 being in the same state for a long time, and the output signal of the driving circuit 21 is unstable due to factors such as leakage current. That is, the uneven light emission of the display panel and the flickering problem when grayscale switching caused by this are avoided.

[0056] Therefore, in the embodiment of the present application, when the pixel circuit 10 works in the holding stage, in at least one stage among the N stages, the clock pulse frequency of the clock signal CK is F2, and F2 is greater than 0, and F2 is less than the clock pulse frequency F1 of the clock signal CK in the data writing stage. Therefore, when the pixel circuit 10 works in the holding stage, the clock signal CK can maintain a certain pulse frequency output, avoiding the problem that the transistor of the driving circuit 21 remains in the same state for a long time, and the output signal of the driving circuit 21 is unstable due to factors such as leakage current. On the other hand, the clock pulse frequency of the clock signal CK in the holding stage is also lower, saving power consumption.

[0057] Please continue to see Figures 1 to 3 In a data refresh cycle of the pixel circuit 10 of the display panel, the time length of the clock pulse frequency of the clock signal CK being the first frequency F1 can be set to T1, and the time length of the clock pulse frequency of the clock signal CK being the second frequency F2 can be set to T2, where T1 is less than T2.

[0058] It is understandable that when the pixel circuit 10 works in the holding stage for a long time, it means that the display panel works in a low-frequency state. When the display panel is in a low-frequency state, it is necessary to ensure that the clock signal CK has a certain pulse, so that some transistors in the driving circuit 21 can maintain normal operation, avoid leakage current for a long time, and cause the output signal of the driving circuit 21 to be unstable. At the same time, the frequency of the clock signal CK needs to be low to reduce power consumption.

[0059] Therefore, the clock signal CK can be maintained at the second frequency F2 for a longer period of time. It is necessary for the clock signal CK to maintain the first frequency F1 in the data writing stage, but when the pixel circuit 10 works in the holding stage, the clock signal CK does not have to maintain the first frequency F1. Therefore, the time length T2 that the clock signal CK maintains at the second frequency F2 can be set to be greater than the time length T1 that the clock signal CK maintains at the first frequency F1, so that the time length T1 of the first frequency F1 is not too long, which helps to reduce the power consumption of the display panel.

[0060] Based on the above analysis, it can be known that when the pixel circuit 10 works in the holding stage, the clock signal CK does not need to maintain a higher clock signal frequency. On the contrary, when the clock signal CK is at a relatively low clock signal frequency, maintaining pulse jumping can play a better role in reducing power consumption and stabilizing the output signal of the driving circuit 21.

[0061] However, when the clock signal CK is working normally, that is, when the pixel circuit 10 is working in the data writing stage, the clock signal frequency of the clock signal CK is the first frequency F1, and its clock signal frequency (that is, the first frequency F1) is a very high frequency. If the first frequency F1 is suddenly changed and reduced to a lower frequency, it will cause the state of the transistor in the driving circuit 21 to be unstable.

[0062] For this purpose, please also refer to Figure 1 , Figure 2 as well as Figure 4 In the present application, a transition phase can also be set to solve the problem that the state of the transistor in the driving circuit 21 may be unstable due to a sudden change in the frequency of the clock signal. Specifically, on the basis that the first frequency F1 is greater than the second frequency F2, and the second frequency F2 is greater than 0, the N phases in which the pixel circuit 10 works in the holding phase also include at least one phase, in which the clock pulse frequency of the clock signal CK is the third frequency F3, and F2>F3≥0.

[0063] The implementation process of the transition stage can be that the clock signal CK is first reduced from a high clock pulse frequency (i.e., the first frequency F1) to a medium clock pulse frequency (i.e., the second frequency F2), and after maintaining it for a period of time, it is then reduced from the medium clock pulse frequency (i.e., the second frequency F2) to a lower clock pulse frequency (i.e., the third frequency F3), so that the clock signal frequency transitions smoothly, and the state of the transistor of the driving circuit 21 can also transition smoothly, thereby avoiding the problem of transistor instability.

[0064] For an alternative example, see Figure 1 , Figure 2 as well as Figure 4, it can be that when the pixel circuit 10 works in the holding stage, in the i-th stage among N stages, the clock pulse frequency of the clock signal CK is the second frequency F2, and in the j-th stage among N stages, the clock signal CK is the third frequency F3; wherein, 1≤i<j≤N.

[0065] It is understandable that in order to prevent the problem of unstable state of transistors in the driving circuit 21 caused by sudden changes in the frequency of the clock signal, the clock pulse frequency should maintain a smooth transition from high to low frequency, and the timing corresponding to the clock pulse frequency should also follow this rule. That is, when the pixel circuit 10 works in N stages, from the first stage to the Nth stage, the clock pulse frequency shows an overall decreasing trend in the number of stages occupied by the corresponding different stages, thereby improving the stability of the transistors in the pixel circuit 10.

[0066] For example, see Figure 1 , Figure 5 and Figure 6 , which shows a schematic diagram of the optional relationship between the phase numbers and the clock pulse frequency of the N phases when the pixel circuit 10 works in the holding phase. Figure 5 In the equation, i=1, j=N-3, that is, Figure 6 Here i=2, j=N-3.

[0067] Please continue to see Figures 1 to 4 , it is also possible that within a data refresh cycle of the pixel circuit 10, on the basis of setting the clock pulse frequency of the clock signal CK to at least include the first frequency F1, the second frequency F2, and the third frequency F3, the time length T1 when the clock pulse frequency of the clock signal CK is the first frequency F1 is set to be shorter than the time length T2 when the clock pulse frequency is the second frequency F2. The time length T2 when the clock pulse frequency of the clock signal CK is the second frequency F2 is set to be shorter than the time length T3 when the clock pulse frequency of the clock signal CK is the third frequency F3.

[0068] That is, in this example, the time length of the clock pulse frequency is set for a single data refresh cycle. The time length T1 of the first frequency F1, the time length T2 of the second frequency F2, and the time length T3 of the third frequency F3 can be set to increase successively. This can ensure that the clock pulse frequency of the clock signal CK transitions more smoothly and that the stage with a lower clock pulse frequency can be maintained for a longer time, which is beneficial to saving power consumption.

[0069] In another optional example, within a data refresh cycle of the pixel circuit 10, the difference between the time length T1 when the clock pulse frequency of the clock signal CK is the first frequency F1 and the time length T2 when the clock pulse frequency is the second frequency F2 is set to d1, and the difference between the time length T2 when the clock pulse frequency of the clock signal CK is the second frequency F2 and the time length T3 when the clock pulse frequency of the clock signal CK is the third frequency F3 is set to d2, where d1 is less than d2.

[0070] Expressed in mathematical terms, d1=T2-T1, d2=T3-T2, and d1<d2. It can be understood that, based on the above analysis, the first frequency F1 is set to ensure the normal operation of the pixel circuit 10 in the data writing phase, the second frequency F2 is set to ensure a smooth transition of the clock pulse frequency, and the third frequency F3 is set to reduce the power consumption of the display panel. By setting d1 to be less than d2, each clock pulse frequency can better perform its respective function.

[0071] It should also be noted that, within a data refresh cycle of the pixel circuit 10, on the basis of setting the clock pulse frequency of the clock signal CK to at least include the first frequency F1, the second frequency F2 and the third frequency F3, when F3>0, the ratio between the clock pulse frequency F1 when the pixel circuit 10 is working in the data writing stage and the clock pulse frequency of at least one stage in the N stages when the pixel circuit 10 is working in the holding stage is set to d3; the clock pulse frequencies of two different stages in the N stages when the pixel circuit 10 is working in the holding stage can also be compared, that is, the ratio between the second frequency F2 and the third frequency F3 is set to d4, and d3=F1 / F2≤d4=F2 / F3 exists.

[0072] It can be understood that because the clock pulse frequency F1 of the clock signal CK is very high when the pixel circuit 10 operates in the data writing stage, and when the pixel circuit 10 operates in the holding stage, the clock pulse frequency (including the second frequency F2 and the third frequency F3) of the clock signal CK in at least one of the N stages is relatively low.

[0073] Therefore, if d3=F1 / F2=d4=F2 / F3, it is possible that F1-F2, that is, the difference between the clock pulse frequency F1 of the clock signal CK when the pixel circuit 10 works in the data writing stage, and the clock pulse frequency F2 of at least one stage in the N stages when the pixel circuit 10 works in the holding stage, will be much larger than F2-F3, that is, much larger than the difference between the different clock pulse frequencies of two different stages in the N stages when the pixel circuit 10 works in the holding stage.

[0074] That is, when the pixel circuit 10 works in the data writing stage, the clock pulse frequency F1 of the clock signal CK drops to the second frequency F2 when the pixel circuit 10 works in the holding stage, and the difference is relatively large in at least one stage of the N stages.

[0075] Therefore, the present application defines d3=F1 / F2≤d4=F2 / F3, which can make d3=F1 / F2 smaller, so that the difference between the first frequency F1 and the second frequency F2 is not too large, avoiding the problem that the difference between the first frequency F1 and the second frequency F2 is too large and easily leads to the unstable state of the transistor. That is, such a setting is conducive to ensuring a smooth transition of the transistor state and improving the stability of the driving circuit 21.

[0076] When the pixel circuit 10 works in the holding stage, in at least one stage of the N stages, the clock pulse frequency of the clock signal CK is the third frequency F3=0, and the third frequency has no pulse change. Therefore, when the pixel circuit 10 works in the holding stage, the clock signal CK corresponding to the third frequency is a constant voltage signal. At this time, it can be set that at least one transistor controlled by the clock signal CK in the driving circuit 21 is in an on state under the control of the constant voltage signal.

[0077] Furthermore, in order to avoid the problem that a large amount of leakage current accumulates on the transistors controlled by the clock signal CK when the pixel circuit 10 works in the holding stage, thereby causing the output of the driving circuit 21 to be unstable, when the clock signal CK is a constant voltage signal, the constant voltage signal can be set to a voltage that controls these transistors to remain in an on state, thereby ensuring that even if the state of the driving circuit 21 is refreshed, the accumulation of charges in a local area can be avoided to cause the output signal to be unstable.

[0078] Please see Figure 1 , Figure 2 and Figure 7 ,in Figure 7 In another embodiment of the display panel of the present application, when the pixel circuit 10 works in the holding stage, the clock pulse frequency of the clock signal CK is optionally changed. In this embodiment, the N stages include N1 stages and N2 stages arranged in sequence, the N1 stage includes the second frequency stage and the third frequency stage arranged in sequence, and the N2 stage includes the second frequency stage and the third frequency stage arranged in sequence.

[0079] In the second frequency stage, the clock pulse frequency of the clock signal CK is the second frequency F2, and in the third frequency stage, the clock pulse frequency of the clock signal CK is the third frequency F3.

[0080] Such an arrangement enables the pixel circuit 10 to work in N stages of the holding stage, and the clock pulse frequency of the clock signal CK first drops from the first frequency F1 to the second frequency F2, then drops to the third frequency F3, maintains the third frequency F3 for a period of time, then rises to the second frequency F2, and then drops to the third frequency F3.

[0081] This can prevent the frequency of the clock signal CK from being too low when it is kept at a low frequency (i.e., the third frequency F3) for a long time, resulting in a large leakage current generated by the transistor for a long time, thereby causing the output signal of the driving circuit 21 to shift, resulting in an increase in the off-state leakage current of the transistor in the pixel circuit 10, thereby causing uneven display of the display panel or flickering when the grayscale changes.

[0082] On this basis, please also refer to Figure 1 , Figure 2 and Figure 8 , a first frequency stage may be included between the N1 stage and the N2 stage. In the first frequency stage, the clock pulse frequency of the clock signal CK is a first frequency F1.

[0083] It can be understood that the first frequency F1 is a very high frequency. Such a setting can enable the third frequency F3 to switch to a high frequency again, or when the third frequency F3 switches to the first frequency F1 and then drops down, the first frequency F1 can be used to pull the change of the transistor, which can better avoid the accumulation of leakage current on the transistor.

[0084] Please continue to see Figure 1 and Figure 2 In another optional example of the present application, the data refresh frequency of the pixel circuit 10 includes a first data refresh frequency F11 and a second data refresh frequency F22, wherein F11>F22.

[0085] When the pixel circuit 10 operates at the first data refresh frequency F11, the holding phase includes X1 second frequency phases and Y1 third frequency phases, and when the pixel circuit 10 operates at the second data refresh frequency F22, the holding phase includes X2 second frequency phases and Y2 third frequency phases; wherein X1<X2, and / or Y1<Y2;

[0086] In the second frequency stage, the clock pulse frequency of the clock signal CK is the second frequency F2. In the third frequency voltage stage, the clock pulse frequency of the clock signal CK is the third frequency F3.

[0087] It should be noted that the first data refresh frequency F11 is a relatively low frequency, such as 10 Hz, and the second data refresh frequency F22 is a low frequency, such as 1 Hz. When the second data refresh frequency F22 is compared with the first data refresh frequency F11, the holding phase of the pixel circuit 10 is longer, and at this time, the problem of unstable output signal of the driving circuit 21 is more serious.

[0088] Therefore, by setting more second frequency stages or third frequency stages at the second data refresh frequency F22, the frequency change of the clock signal CK is more frequent at the second data refresh frequency F22, thereby avoiding the problem of unstable output signal of the driving circuit 21 caused by holding time too long.

[0089] Please continue to see Figure 1 , Figure 2 In another optional example of the display panel of the present application, the data refresh frequency of the pixel circuit 10 includes a first data refresh frequency F11 and a second data refresh frequency F22, and F11>F22.

[0090] When the pixel circuit 10 operates at the first data refresh frequency F11, during a holding phase, the clock pulse frequency of the clock signal CK is at the second frequency F2 for a time length of L1; when the pixel circuit 10 operates at the second data refresh frequency F22, during a holding phase, the clock pulse frequency of the clock signal CK is at the second frequency F2 for a time length of L2; wherein, L1<L2.

[0091] It can be understood that when the pixel circuit 10 operates at the second data refresh frequency F22, the relatively high frequency second data refresh frequency F22 is maintained longer than the clock signal CK, which can avoid the problem of unstable output signal of the driving circuit 21 caused by the clock signal CK maintaining the lower frequency F33 for a long time.

[0092] In addition, when the pixel circuit 10 operates at the first data refresh frequency F11, during a holding phase, the clock pulse frequency of the clock signal CK is the third frequency F3 for a time length of L3; when the pixel circuit 10 operates at the second data refresh frequency F22, during a holding phase, the clock pulse frequency of the clock signal CK is the third frequency F3 for a time length of L4; wherein, |L1-L3|>|L2-L4|.

[0093] It is understandable that, as mentioned above, in a holding phase, the clock pulse frequency of the clock signal CK is kept at the third frequency F3 for a longer time, so when the second data refresh frequency F22 is lower, the time of the second frequency F2 should also be longer. Thus, when the frequency is low, the time occupied by the second frequency F2 is longer, and relatively, the time occupied by the third frequency F3 can be shorter, so |L1-L3|>|L2-L4| can be set.

[0094] For an alternative example, see Figure 1 and Figure 2 Specifically, the source or drain of the first transistor T1 included in the pixel circuit 10 is connected to the gate of the driving transistor T0; wherein,

[0095] The driving circuit 21 may be used to provide a control signal for the first transistor T1 .

[0096] The gate of the driving transistor T0 is connected to the driving circuit 21 to provide a control signal to the pixel circuit 10 , thereby ensuring that the gate potential of the driving transistor T0 is stable.

[0097] For another alternative example, see Figure 1 , Figure 2 and Fig. 9 The pixel circuit 10 may include a first transistor T1 and a second transistor T2 , wherein a source or a drain of the first transistor T1 is connected to a gate of the driving transistor T0 , and a source or a drain of the second transistor T2 is connected to a source or a drain of the driving transistor T0 .

[0098] The driving circuit 21 may include a first driving circuit 211 and a second driving circuit 212. The first driving circuit 211 is used to provide a control signal (ie, a first scanning signal S1) for the first transistor T1, and the second driving circuit 212 is used to provide a control signal (ie, a second scanning signal S2) for the second transistor T2.

[0099] The clock signal line may also include a first clock signal line, which provides a first clock signal CK1 for the first driving circuit 211, and a second clock signal line which provides a second clock signal CK2 for the second driving circuit 212; wherein, when the pixel circuit 10 operates in the holding stage, the length of time that the clock pulse frequency of the first clock signal CK1 is the second frequency F2 is greater than the length of time that the clock pulse frequency of the second clock signal CK2 is the second frequency F2.

[0100] It should be noted that the gate of the driving transistor T0 is used to write the data signal Vdata, and the data signal Vdata is a crucial factor in generating the driving current. Therefore, whether the gate potential of the driving transistor T0 is stable is an important factor affecting the brightness of the light emitting element 20.

[0101] In order to fully ensure the stability of the gate potential of the driving transistor T0, the first clock signal CK1 is set to a longer time length when it is at the higher second frequency F2, thereby avoiding the problem that the first clock signal CK1 is at the low third frequency F3 for too long, which causes the output signal of the driving transistor T0 to change, and further causes the first transistor T1 to not be completely turned off when in the off state, resulting in a large leakage current affecting the gate potential of the driving transistor T0.

[0102] The second transistor T2 does not write a signal to the gate of the driving transistor T0. In some cases, when the pixel circuit 10 works in the holding stage, the second transistor T2 is turned on, that is, the output signal of the second driving circuit 212 will jump, and the time for maintaining the same signal output will not be too long.

[0103] On this basis, when the pixel circuit 10 is operating in the holding stage, the time length of the clock pulse frequency of the first clock signal CK1 being the third frequency F3 can be set to be shorter than the time length of the clock pulse frequency of the second clock signal CK2 being the third frequency F3. In this way, the time length of the first clock signal CK1 being at the third frequency F3 can be relatively short, so as to ensure that the off state of the first transistor T1 is completely turned off.

[0104] Combined with the above Figures 1 to 9 , describes in detail the display panel of the embodiment of the present invention. On this basis, the embodiment of the present application also protects a display device, see Fig.10 , Fig.10 is an optional schematic diagram of the display device, and the display device may also be at least one of a wearable device, a camera, a mobile phone, a tablet computer, a display screen, a television, and a vehicle-mounted display terminal. The display device includes the display panel provided in the above embodiment, so the display device has all the beneficial effects of the above display panel.

[0105] In addition, the term "and / or" in this article is only a description of the association relationship between the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0106] It should be understood that in the embodiment of the present invention, "B corresponding to A" means that B is associated with A, and B can be determined according to A. However, it should also be understood that determining B according to A does not mean determining B only according to A, and B can also be determined according to A and / or other information.

[0107] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A display panel, characterized in that: include: A driving circuit and a pixel circuit, wherein the driving circuit is used to provide a control signal for the pixel circuit; A clock signal line, used to provide a clock signal to the driving circuit; A data refresh cycle of the pixel circuit includes a data writing phase and a holding phase, and the holding phase includes N phases arranged in sequence, N≥1; wherein, When the pixel circuit operates in the data writing phase, the clock pulse frequency of the clock signal is a first frequency F1; When the pixel circuit operates in the holding phase, in at least one phase of the N phases, the clock pulse frequency of the clock signal is the second frequency F2, and the N phases also include at least one phase in which the clock pulse frequency of the clock signal is the third frequency F3; wherein, F1>F2>F3≥0.

2. The display panel according to claim 1, characterized in that: When the pixel circuit operates in the holding stage, in the i-th stage among the N stages, the clock pulse frequency of the clock signal is the second frequency F2, and in the j-th stage among the N stages, the clock pulse frequency of the clock signal is the third frequency F3, wherein 1≤i≤N, 1≤j≤N.

3. The display panel according to claim 2, characterized in that: 1≤i<j≤N.

4. The display panel according to claim 1, characterized in that: In one of the data refresh cycles, the time length during which the clock pulse frequency of the clock signal is the first frequency F1 is shorter than the time length during which the clock pulse frequency of the clock signal is the second frequency F2.

5. The display panel according to claim 1, characterized in that: In one of the data refresh cycles, the time length during which the clock pulse frequency of the clock signal is the second frequency F2 is shorter than the time length during which the clock pulse frequency of the clock signal is the third frequency F3.

6. The display panel according to claim 1, characterized in that: In one of the data refresh cycles, the difference between the length of time when the clock pulse frequency of the clock signal is the first frequency F1 and the length of time when the clock pulse frequency of the clock signal is the second frequency F2 is smaller than the difference between the length of time when the clock pulse frequency of the clock signal is the second frequency F2 and the length of time when the clock pulse frequency of the clock signal is the third frequency F3.

7. The display panel according to claim 1, characterized in that: When F3>0, F1 / F2≤F2 / F3.

8. The display panel according to claim 1, characterized in that: When F3=0, the clock signal is a constant voltage signal.

9. The display panel according to claim 8, characterized in that: The driving circuit includes at least one transistor controlled by the clock signal, and the constant voltage signal controls the at least one transistor to be in an on state.

10. The display panel according to claim 1, characterized in that: The N stages include N1 stages and N2 stages arranged in sequence, the N1 stage includes a second frequency stage and a third frequency stage arranged in sequence, and the N2 stage includes a second frequency stage and a third frequency stage arranged in sequence; In the second frequency stage, the clock pulse frequency of the clock signal is the second frequency F2, and in the third frequency stage, the clock pulse frequency of the clock signal is the third frequency F3.

11. The display panel according to claim 10, characterized in that: A first frequency stage is included between the N1 stage and the N2 stage. In the first frequency stage, the clock pulse frequency of the clock signal is the first frequency F1.

12. The display panel according to claim 1, characterized in that: The data refresh frequency of the pixel circuit includes a first data refresh frequency F11 and a second data refresh frequency F22, F11>F22; When the pixel circuit operates at the first data refresh frequency F11, in one of the holding phases, the time length of the clock pulse frequency of the clock signal being the second frequency F2 is L1; when the pixel circuit operates at the second data refresh frequency F22, in one of the holding phases, the time length of the clock pulse frequency of the clock signal being the second frequency F2 is L2; When the pixel circuit operates at the first data refresh frequency F11, in one of the holding phases, the time length of the clock pulse frequency of the clock signal being the third frequency F3 is L3; when the pixel circuit operates at the second data refresh frequency F22, in one of the holding phases, the time length of the clock pulse frequency of the clock signal being the third frequency F3 is L4; wherein, |L1-L3|>|L2-L4|.

13. The display panel according to claim 1, characterized in that: The data refresh frequency of the pixel circuit includes a first data refresh frequency F11 and a second data refresh frequency F22, F11>F22; When the pixel circuit operates at the first data refresh frequency F11, the holding phase includes X1 second frequency phases and Y1 third frequency phases; when the pixel circuit operates at the second data refresh frequency F22, the holding phase includes X2 second frequency phases and Y2 third frequency phases; wherein, X1<X2, and / or, Y1<Y2; In the second frequency stage, the clock pulse frequency of the clock signal is the second frequency F2, and in the third frequency stage, the clock pulse frequency of the clock signal is the third frequency F3.

14. The display panel according to claim 1, characterized in that: The pixel circuit includes a driving transistor and a first transistor, wherein a source or a drain of the first transistor is connected to a gate of the driving transistor; wherein, The driving circuit is used for providing a control signal to the first transistor.

15. The display panel according to claim 1, characterized in that: The pixel circuit includes a driving transistor and a first transistor and a second transistor, wherein a source or a drain of the first transistor is connected to a gate of the driving transistor, and a source or a drain of the second transistor is connected to a source or a drain of the driving transistor; The driving circuit comprises a first driving circuit and a second driving circuit, the first driving circuit is used to provide a control signal for the first transistor, and the second driving circuit is used to provide a control signal for the second transistor; The clock signal line includes a first clock signal line and a second clock signal line, the first clock signal line provides a first clock signal for the first driving circuit, and the second clock signal line provides a second clock signal for the second driving circuit; wherein, When the pixel circuit operates in the holding phase, the length of time that the clock pulse frequency of the first clock signal is the second frequency F2 is greater than the length of time that the clock pulse frequency of the second clock signal is the second frequency F2.

16. The display panel according to claim 15, characterized in that: When the pixel circuit operates in the holding phase, the length of time that the clock pulse frequency of the first clock signal is the third frequency F3 is shorter than the length of time that the clock pulse frequency of the second clock signal is the third frequency F3.

17. A display device, characterized in that: A display panel comprising any one of claims 1-16.

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