Display substrate, driving method, display panel and display device

Abstract

The present application discloses a display substrate, a driving method, a display panel, and a display device, relating to the field of display technology. The display substrate can improve the problem of insulation breakdown between signal lines of a display panel during long-term use, reduce display defects, and thereby improve the service life and reliability of the display panel. The display substrate includes: a plurality of pixel circuits; a plurality of first scan drive circuits electrically connected to the pixel circuits; clock signal lines, including a first clock signal line and a second clock signal line, the first clock signal line and the second clock signal line being electrically connected to different first scan drive circuits, respectively; the first clock signal line, the second clock signal line, and the first scan drive circuit are arranged on the same side of the pixel circuit, and the first clock signal line and the second clock signal line are arranged on different sides of the first scan drive circuit, respectively.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display substrate, a driving method, a display panel, and a display device. Background Art

[0002] With the continuous development of display technology, higher requirements are being placed on the service life and reliability of display panels. However, the existing display panel drive circuit design is prone to insulation breakdown between signal lines after long-term use, resulting in poor display performance and thus affecting the service life and reliability of the display panel. Summary of the Invention

[0003] The embodiments of the present application provide a display substrate, a driving method, a display panel, and a display device, which can improve the problem of insulation layer breakdown between signal lines of the display panel under long-term use, reduce display defects, and thereby improve the service life and reliability of the display panel.

[0004] According to a first aspect of an embodiment of the present application, a display substrate is provided, comprising:

[0005] a plurality of pixel circuits;

[0006] a plurality of first scan driving circuits electrically connected to the pixel circuits;

[0007] a clock signal line, comprising a first clock signal line and a second clock signal line, wherein the first clock signal line and the second clock signal line are electrically connected to different first scan driving circuits respectively;

[0008] The first clock signal line, the second clock signal line and the first scan driving circuit are arranged on the same side of the pixel circuit, and the first clock signal line and the second clock signal line are respectively arranged on different sides of the first scan driving circuit.

[0009] In some embodiments, the clock signal transmitted by the first clock signal line and the clock signal transmitted by the second clock signal line have different timings.

[0010] In some embodiments, the clock signal transmitted by the first clock signal line and the clock signal transmitted by the second clock signal line have opposite timings.

[0011] In some embodiments, when the timing of the clock signal transmitted by the first clock signal line is a high-level signal period, the timing of the clock signal transmitted by the second clock signal line is a low-level signal period;

[0012] In a case where the timing of the clock signal transmitted by the first clock signal line is a low-level signal period, the timing of the clock signal transmitted by the second clock signal line is a high-level signal period.

[0013] In some embodiments, the first clock signal line includes a first sub-signal line to an nth sub-signal line, and the second clock signal line includes an n+1th sub-signal line to a 2nth sub-signal line, where n is a natural number greater than 1;

[0014] The first to 2n sub-signal lines are electrically connected to different first scan driving circuits respectively;

[0015] The clock signal transmitted by the first sub-signal line is opposite in timing to the clock signal transmitted by the (n+1)th sub-signal line, and the clock signal transmitted by the nth sub-signal line is opposite in timing to the clock signal transmitted by the (2n)th sub-signal line.

[0016] In some embodiments, the first clock signal line and the second clock signal line are disposed opposite to each other with respect to the first scan driving circuit.

[0017] In some embodiments, the display substrate further includes:

[0018] substrate layer;

[0019] a first metal layer, wherein the clock signal line is provided on the first metal layer;

[0020] a second metal layer, the first metal layer being disposed between the substrate layer and the second metal layer;

[0021] an insulating layer, disposed between the first metal layer and the second metal layer, the insulating layer comprising a first through hole;

[0022] The first scan driving circuit is electrically connected to the corresponding clock signal line through an input lead, the input lead is provided in the second metal layer, and the input lead is electrically connected to the corresponding clock signal line through the first through hole.

[0023] In some embodiments, the second clock signal line is provided between the first scan driving circuit and the pixel circuit;

[0024] The first scan driving circuits in cascade are electrically connected to each other via cascade signal lines, the cascade signal lines are used to transmit a reset signal or a frame start signal, and the cascade signal lines are provided on the second metal layer;

[0025] The input lead includes a first section of input lead and a second section of input lead, the first section of input lead and the second section of input lead are electrically connected through a first jumper line, the first jumper line is set on the first metal layer, and the orthographic projection of the first jumper line on the substrate layer intersects with the orthographic projection of the cascade signal line on the substrate layer.

[0026] In some embodiments, the first scan driving circuit is electrically connected to the pixel circuit via an output lead, the output lead is provided on the first metal layer, and the output lead includes a first section of output lead and a second section of output lead;

[0027] The first output lead and the second output lead are electrically connected via a second jumper line, the second jumper line is arranged on the second metal layer, and the orthographic projection of the second jumper line on the substrate layer intersects with the orthographic projection of the second clock signal line on the substrate layer.

[0028] In some embodiments, the display substrate further includes:

[0029] a first auxiliary electrode, disposed on the first metal layer, the first auxiliary electrode being connected in parallel with the adjacent clock signal line, the first auxiliary electrode being used to receive the same clock signal as the parallel clock signal line; and / or,

[0030] A second auxiliary electrode is arranged on the second metal layer, the second auxiliary electrode is connected in parallel with the corresponding clock signal line through a second through hole, the second through hole is arranged on the insulating layer, and the orthographic projection of the second auxiliary electrode on the substrate layer at least partially overlaps with the orthographic projection of the parallel clock signal line on the substrate layer.

[0031] In some embodiments, the display substrate further includes:

[0032] a block electrode disposed on the second metal layer, the block electrode covering and filling the first through-hole, the block electrode being electrically connected to the input lead, the block electrode being electrically connected to the clock signal line through the first through-hole, and an orthographic projection of the block electrode on the substrate layer falling within an orthographic projection of the electrically connected clock signal line on the substrate layer;

[0033] In the case where the display substrate includes the second auxiliary electrode, the orthographic projection of the second auxiliary electrode on the substrate layer falls within the orthographic projection of the parallel clock signal line on the substrate layer;

[0034] The circumference of the block electrode surrounds at least two of the second auxiliary electrodes.

[0035] In some embodiments, one of the block electrodes covers at least two of the first through holes; and / or,

[0036] One second auxiliary electrode covers at least two second through holes; and / or,

[0037] The distance between adjacent block electrodes and the second auxiliary electrodes is smaller than the distance between adjacent clock signal lines.

[0038] In some embodiments, when the display substrate includes the first auxiliary electrode, the clock signal line corresponds to the first auxiliary electrode in a one-to-one manner; and / or,

[0039] In the case where the display substrate includes the second auxiliary electrodes, one clock signal line corresponds to at least two second auxiliary electrodes, and the second auxiliary electrodes connected in parallel to the same clock signal line are discontinuous.

[0040] In some embodiments, the display substrate further includes:

[0041] Display driver circuit;

[0042] a driving signal lead, provided on the first metal layer, wherein the display driving circuit is electrically connected to the clock signal line via the driving signal lead;

[0043] The third auxiliary electrode is provided on the second metal layer. The third auxiliary electrode is connected in parallel with the corresponding driving signal lead through a third through hole. The third through hole is provided on the insulating layer.

[0044] In some embodiments, the display substrate further includes:

[0045] An electrostatic protection structure, wherein the clock signal line is electrically connected to the electrostatic protection structure through an electrostatic lead, the electrostatic lead is arranged on the second metal layer, and the electrostatic lead is electrically connected to the clock signal line through a fourth through hole, and the fourth through hole is arranged on the insulating layer.

[0046] In some embodiments, the electrostatic protection structure includes a first electrostatic protection structure and a second electrostatic protection structure, and the first electrostatic protection structure and the second electrostatic protection structure are respectively arranged on different sides of the pixel circuit;

[0047] The clock signal line includes a first end and a second end, the first end is electrically connected to the drive signal lead and the first electrostatic protection structure respectively, and the second end is electrically connected to the second electrostatic protection structure;

[0048] In the length extension direction of the clock signal line, the first auxiliary electrode does not extend beyond the first end and the second end.

[0049] In some embodiments, all of the clock signal lines have the same line width; and / or,

[0050] The clock signal lines located on the same side of the first scan driving circuit have the same line spacing.

[0051] In some embodiments, the display substrate further includes:

[0052] a common electrode, disposed between the second clock signal line and the pixel circuit, wherein the second clock signal line is disposed between the first scan drive circuit and the pixel circuit;

[0053] The distance between the common electrode and the nearest second clock signal line is greater than the distance between adjacent second clock signal lines.

[0054] In some embodiments, the display substrate further includes:

[0055] a plurality of second scan driving circuits electrically connected to the pixel circuit, wherein the first scan driving circuit and the second scan driving circuit are respectively arranged on different sides of the pixel circuit;

[0056] The clock signal line further includes a third clock signal line and a fourth clock signal line, wherein the third clock signal line and the fourth clock signal line are electrically connected to different second scan driving circuits respectively, and the clock signal transmitted by the third clock signal line has a different timing sequence from the clock signal transmitted by the fourth clock signal line;

[0057] The third clock signal line, the fourth clock signal line and the second scan driving circuit are arranged on the same side of the pixel circuit, and the third clock signal line and the fourth clock signal line are respectively arranged on different sides of the second scan driving circuit.

[0058] In some embodiments, the second clock signal line is provided between the first scan driving circuit and the pixel circuit, the fourth clock signal line is provided between the second scan driving circuit and the pixel circuit, and the plurality of pixel circuits are arranged in an array;

[0059] Each scan driving circuit is electrically connected to a row of pixel circuits, and the scan driving circuit includes the first scan driving circuit and the second scan driving circuit;

[0060] The first clock signal line and the third clock signal line are respectively electrically connected to the pixel circuits in the same row, and the second clock signal line and the fourth clock signal line are respectively electrically connected to the pixel circuits in the same row; or, the first clock signal line and the third clock signal line are respectively electrically connected to the pixel circuits in different rows, and the second clock signal line and the fourth clock signal line are respectively electrically connected to the pixel circuits in different rows.

[0061] A second aspect of the embodiments of the present application provides a method for driving a display substrate, which is applied to the display substrate according to the first aspect. The method includes:

[0062] transmitting clock signals to the first clock signal line and the second clock signal line respectively,

[0063] And, transmitting a frame start signal to the first first scan driving circuit to scan and drive the electrically connected pixel circuits based on the clock signal and the frame start signal.

[0064] In some embodiments, the method for driving the display substrate further includes:

[0065] The high level amplitude and the low level amplitude of the clock signal are adjusted to reduce the voltage difference between the clock signals with line crossing.

[0066] In some implementations, adjusting the high level amplitude and the low level amplitude of the clock signal to reduce the voltage difference between the clock signals having line crossings includes:

[0067] The high level signal of the clock signal is lowered, and the low level signal transmitted to the scan driving circuit is increased.

[0068] According to a third aspect of the embodiments of the present application, a display panel is provided, comprising:

[0069] The display substrate as described in the first aspect.

[0070] According to a fourth aspect of the embodiments of the present application, a display device is provided, including:

[0071] The display panel as described in the third aspect.

[0072] In a display substrate provided by an embodiment of the present application, a first clock signal line, a second clock signal line, and a first scan driver circuit are arranged on the same side of a pixel circuit, and the first clock signal line and the second clock signal line are arranged on different sides of the first scan driver circuit. This reduces the number of intersections between the clock signal lines and the input terminals of the first scan driver circuit, i.e., the number of clock signal intersections. This reduces the occurrence of film breakdown due to clock signal intersections, thereby reducing defects caused by film breakdown. Furthermore, the clock signal transmitted by the first clock signal line and the clock signal transmitted by the second clock signal line are arranged to have different timings, i.e., the clock signal transmitted by the clock signal lines on both sides of the first scan driver circuit have different timings. This reduces the timing differences between the clock signals on the same side of the first scan driver circuit, reducing the number of clock signal intersections while also reducing the duration of large voltage differences at clock signal intersections. The shortened duration of the maximum voltage difference at clock signal intersections reduces the probability of insulation breakdown at the clock signal intersections. Combined with the reduced number of clock signal intersections, this significantly reduces the occurrence of insulation breakdown, further improving the yield, service life, and reliability of the display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] Figure 1 A schematic structural diagram of a display substrate provided in an embodiment of the present application;

[0074] Figure 2 A schematic diagram of a clock signal timing provided in an embodiment of the present application;

[0075] Figure 3 A schematic partial structural diagram of a display substrate provided in an embodiment of the present application;

[0076] Figure 4 A schematic partial structural diagram of another display substrate provided in an embodiment of the present application;

[0077] Figure 5 A schematic partial structural diagram of another display substrate provided in an embodiment of the present application;

[0078] Figure 6 A schematic partial structural diagram of a display substrate provided in an embodiment of the present application;

[0079] Figure 7 A schematic cross-sectional view of a display substrate along line BB provided in an embodiment of the present application;

[0080] Figure 8 A schematic partial structural diagram of another display substrate provided in an embodiment of the present application;

[0081] Figure 9 A partial design layout of a display substrate provided in an embodiment of the present application;

[0082] Figure 10 A schematic partial structural diagram of another display substrate provided in an embodiment of the present application;

[0083] Figure 11 A schematic partial structural diagram of another display substrate provided in an embodiment of the present application;

[0084] Figure 12 A connection design layout of a first electrostatic protection structure provided in an embodiment of the present application;

[0085] Figure 13 A connection design layout of a second electrostatic protection structure provided in an embodiment of the present application;

[0086] Figure 14 A schematic flow chart of a method for driving a display substrate provided in an embodiment of the present application;

[0087] Figure 15 A schematic structural block diagram of a display panel provided in an embodiment of the present application;

[0088] Figure 16 A schematic structural block diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0089] In order to better understand the technical solutions provided by the embodiments of this specification, the technical solutions of the embodiments of this specification are described in detail below through the accompanying drawings and specific embodiments. It should be understood that the embodiments of this specification and the specific features in the embodiments are detailed descriptions of the technical solutions of the embodiments of this specification, rather than limitations on the technical solutions of this specification. In the absence of conflict, the embodiments of this specification and the technical features in the embodiments can be combined with each other.

[0090] In this article, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also include elements inherent to such process, method, article or equipment. In the absence of further restrictions, the elements defined by the statement "comprising a ..." do not exclude the presence of other identical elements in the process, method, article or equipment comprising the elements. The term "two or more" includes two or more than two cases.

[0091] With the continuous development of display technology, higher requirements are being placed on the service life and reliability of display panels. However, the existing display panel drive circuit design is prone to insulation breakdown between signal lines after long-term use, resulting in poor display performance and thus affecting the service life and reliability of the display panel.

[0092] In view of this, the embodiments of the present application provide a display substrate, a driving method, a display panel and a display device, which can improve the problem of insulation layer breakdown between signal lines of the display panel under long-term use, reduce display defects, and thereby improve the service life and reliability of the display panel.

[0093] In a first aspect of an embodiment of the present application, a display substrate is provided. The display substrate may include a substrate layer in the thickness direction of the display substrate. The substrate layer may be flexible or rigid. Exemplarily, a display panel may be composed of a display substrate combined with other film layers or substrate structures. For example, a liquid crystal display panel may include an array substrate and a color filter substrate. The display substrate may serve as the array substrate. A liquid crystal layer may be disposed between the color filter substrate and the display substrate. Pixel circuits and pixel electrodes may be disposed on the display substrate. The pixel circuits are used to drive the pixel electrodes. The pixel electrodes may generate an electric field, causing the liquid crystal molecules to rotate and transmit light under the action of the electric field, thereby displaying an image. Exemplarily, if the display panel is an organic light-emitting display panel, the substrate layer of the display substrate may be provided with pixel circuits and light-emitting devices. The pixel circuits drive the light-emitting devices to emit light. An encapsulation layer may be disposed on the light-emitting devices. The encapsulation layer may protect the light-emitting devices and block water and oxygen corrosion outside the display substrate. A polarizer or a color filter may also be disposed on the display substrate. The polarizer may be used to reduce glare, and the color filter may be used to reduce color shift. The display substrate may also include other film layers, which are not listed here.

[0094] Figure 1 This is a schematic structural diagram of a display substrate provided in an embodiment of the present application. Figure 1 As shown, the display substrate includes clock signal lines, which are arranged on both sides of the display area AA of the display substrate. A scan driving circuit is also arranged between the display area AA of the display substrate and the clock signal lines, which are respectively represented as GOA1, GOA2, ... GOA12, .... For example, Figure 2 A clock signal timing diagram provided in an embodiment of the present application. Figure 2 As shown, the timing of the clock signal transmitted by the first clock signal line 110 is different from that of the clock signal transmitted by the second clock signal line 120. The timing of the first clock signal CLK1, the second clock signal CLK2 and the third clock signal CLK3 are all different from the timing of the fourth clock signal CLK4, the fifth clock signal CLK5 and the third clock signal CLK3. The input lines of the clock signal input to the scan driving circuit may cross, such as Figure 1 As shown in the dotted box, the intersection of clock signals of different timings will generate a voltage difference. The longer the pressure difference lasts, the more likely the film layer will break down. The film layer breakdown can easily lead to a short circuit in the signal line, resulting in poor display.

[0095] Figure 3 This is a schematic partial structural diagram of a display substrate provided in an embodiment of the present application. Figure 3 As shown, the display substrate provided by the embodiment of the present application includes: a clock signal line 100, a plurality of first scanning drive circuits 200 and a plurality of pixel circuits 300. The display substrate includes a display area AA and a non-display area NA, the clock signal line 100 and the plurality of first scanning drive circuits 200 are arranged in the non-display area NA, and the pixel circuit 300 is arranged in the display area AA. The pixel circuit 300 is used to drive the pixel to transmit light or emit light to realize picture display. Exemplarily, in an organic light-emitting display substrate, the pixel circuit 300 can be 2T1C, that is, 2 TFTs (thin film transistors) and a storage capacitor, or 7T1C (7 TFTs and a storage capacitor). In a liquid crystal display substrate, the pixel circuit can be one or more TFTs, which are used to drive the pixel electrodes so that the liquid crystal molecules rotate in the electric field formed by the pixel electrodes to achieve transmittance adjustment, so that the light from the backlight source can pass through the display screen. The clock signal line 100 is used to transmit a clock signal to the first scan driver circuit 200. Using the clock signal, the first scan driver circuit 200 can scan the multiple pixel circuits 300 row by row, achieving surface scanning of the pixel circuits 300 within the display area AA. Combined with the data signal, this can realize image display. For example, the multiple pixel circuits 300 can be arranged in an array, with each pixel circuit 300 correspondingly driving the lighting state of a sub-pixel. The clock signal scans the pixel circuits 300 in rows, and the data signal drives the lighting state of the pixels in the column direction to realize image display.

[0096] For example, one or more scan driving circuits transmit scan signals to a row of pixel circuits 300, and the scan driving circuits output scan signals after receiving clock signals. Figure 3 As shown, the clock signal line 100 includes a first clock signal line 110 and a second clock signal line 120, and the first clock signal line 110 and the second clock signal line 120 are respectively electrically connected to different first scan driving circuits 200, and the first clock signal line 110, the second clock signal line 120 and the first scan driving circuit 200 are arranged on the same side of the pixel circuit 300, and the first clock signal line 110 and the second clock signal line 120 are respectively arranged on different sides of the first scan driving circuit 200.

[0097] For example, Figure 3As shown, there are multiple first scan driving circuits 200, and the number of first scan driving circuits 200 is related to the number of rows of pixel circuits 300. The multiple first scan driving circuits 200 can be identified by numbers GOA1, GOA2, GOA3, GOA4, GOA5, GOA6, GOA7, GOA8, GOA9, GOA10, GOA11, GOA12, ... There can be three first clock signal lines 110, which respectively transmit a first clock signal CLK1, a second clock signal CLK2, and a third clock signal CLK3; there can be three second clock signal lines 120, which respectively transmit a fourth clock signal CLK4, a fifth clock signal CLK5, and a third clock signal CLK3. The first clock signal CLK1 is input to GOA1, GOA7..., the second clock signal CLK2 is input to GOA2, GOA8..., the third clock signal CLK3 is input to GOA3, GOA9..., the fourth clock signal CLK4 is input to GOA4, GOA10..., the fifth clock signal CLK5 is input to GOA5, GOA11..., and the third clock signal CLK3 is input to GOA6, GOA12...

[0098] It should be noted that Figure 3 The number of clock signal lines 100 shown is only for illustration, and the number of first scan driving circuits 200 is also for illustration, and is not intended to be a specific limitation of the embodiments of the present application.

[0099] It should be noted that during the display panel's display process, the first scan driver circuit 200 continuously receives clock signals, i.e., clock signals are input into the first scan driver circuit and output scan signals to the corresponding connected pixel circuits 300. Different clock signal lines 100 intersect with the connection lines at the input terminals of different first scan driver circuits 200. Due to the different timings of the different clock signals, there is a voltage difference between the clock signals of the intersecting connection lines. During long signal transmission, the intersections with large voltage differences are prone to breakdown of the insulating film layer. This breakdown can cause short circuits in the connection lines, resulting in line failures and ultimately display failures in the display panel. For example, the high level amplitude of the clock signal is generally around 18V, and the low level amplitude is generally around -15V. The maximum voltage difference can reach twice the scan time of each row of pixel circuits. Analysis of 75 display anomalies and non-defective displays from a certain display product, resulting from long-term use, revealed that nearly 80% of the cases were caused by signal pull between different clock signal lines. Focused ion beam analysis revealed that ESD (electrostatic discharge) breakdown caused the short circuit between two metal layers. This indicates that when the product is used for a long time, the large voltage difference between the clock signals breaks down the insulating film layer between the two metal layers.

[0100] To address the above issues, the display substrate provided in the embodiment of the present application sets the first clock signal line 110, the second clock signal line 120 and the first scan driving circuit 200 on the same side of the pixel circuit 300, and the first clock signal line 110 and the second clock signal line 120 are set on different sides of the first scan driving circuit 200, which can reduce the number of intersections between the clock signal line 100 and the input end of the first scan driving circuit 200, that is, the number of crossings of the clock signal can be reduced. For example, Figure 3 As shown, the first clock signal CLK1, the second clock signal CLK2 and the third clock signal CLK3 have signal intersections on one side of the input end of the first scan driving circuit 200, and the fourth clock signal CLK4, the fifth clock signal CLK5 and the sixth clock signal CLK6 do not have any signal intersections with the first clock signal CLK1, the second clock signal CLK2 and the third clock signal CLK3, so the crossing of the clock signals is reduced by half, which can reduce the occurrence of film breakdown caused by the clock signal crossing points and reduce the defects caused by film breakdown.

[0101] In addition, the timing of the clock signal transmitted by the first clock signal line 110 is different from that of the clock signal transmitted by the second clock signal line 120, that is, the timing of the clock signals transmitted by the clock signal lines on both sides of the first scan driving circuit 200 is different, which can reduce the timing difference between the clock signals on the same side of the first scan driving circuit 200, and at the same time reduce the number of clock signal crossings, it can also reduce the duration of the large voltage difference at the clock signal crossing point. For example, Figure 2As shown, for clock signals transmitted on the same side of the first scan driver circuit 200, within a single cycle T, the maximum voltage difference between the first clock signal CLK1 and the second clock signal CLK2 lasts for 1 / 3 of the cycle, the maximum voltage difference between the first clock signal CLK1 and the third clock signal CLK3 lasts for 2 / 3 of the cycle, and the maximum voltage difference between the second clock signal CLK2 and the third clock signal CLK3 lasts for 1 / 3 of the cycle, none of which lasts for a full cycle T. If the first clock signal CLK1 and the fourth clock signal CLK4 are arranged on the same side of the first scan driver circuit 200, the maximum voltage difference at the intersection of the first clock signal CLK1 and the fourth clock signal CLK4 is always present, that is, it remains at the maximum voltage difference of the clock signals throughout the entire cycle T, and the probability of insulation layer breakdown is maximized. Shortening the duration of the maximum voltage difference at the clock signal intersection can reduce the probability of insulation layer breakdown at the clock signal intersection. Combined with reducing the number of clock signal intersections, this can significantly reduce the occurrence of insulation layer breakdown, further improving the yield, service life, and reliability of the display substrate. It should be noted that the periods of the first clock signal CLK1 , the second clock signal CLK2 , the third clock signal CLK3 , the fourth clock signal CLK4 , the fifth clock signal CLK5 and the sixth clock signal CLK6 are all T.

[0102] In some embodiments, reference Figure 3 , the first clock signal line 110 and the second clock signal line 120 are arranged relative to each other with respect to the first scan driving circuit 200; the timing of the clock signal transmitted by the first clock signal line 110 is opposite to the timing of the clock signal transmitted by the second clock signal line 120. When the timing of the clock signal transmitted by the first clock signal line 110 is a high-level signal period, the timing of the clock signal transmitted by the second clock signal line 120 is a low-level signal period; when the timing of the clock signal transmitted by the first clock signal line 110 is a low-level signal period, the timing of the clock signal transmitted by the second clock signal line 120 is a high-level signal period. It is easy to understand that the high-level value of the high-level signal period is greater than the low-level value of the low-level signal period. For example, the high-level value is +18V and the low-level value is -15V.

[0103] In some embodiments, the first clock signal line 100 includes a first sub-signal line to an nth sub-signal line, and the second clock signal line 120 includes an n+1th sub-signal line to a 2nth sub-signal line, where n is a natural number greater than 1; the first sub-signal line to the 2nth sub-signal line are electrically connected to different first scan driving circuits 200, respectively; the clock signal transmitted by the first sub-signal line is opposite in timing to the clock signal transmitted by the n+1th sub-signal line, and the clock signal transmitted by the nth sub-signal line is opposite in timing to the clock signal transmitted by the 2nth sub-signal line.

[0104] Exemplary, reference Figure 2 and Figure 3 , n=3, the first sub-signal line transmits the first clock signal CLK1, the second sub-signal line transmits the second clock signal CLK2, the third sub-signal line transmits the third clock signal CLK3, the fourth sub-signal line transmits the fourth clock signal CLK4, the fifth sub-signal line transmits the fifth clock signal CLK5, and the sixth sub-signal line transmits the sixth clock signal CLK6. The timing of the first clock signal CLK1 is opposite to the timing of the fourth clock signal CLK4, the timing of the second clock signal CLK2 is opposite to the timing of the fifth clock signal CLK5, and the timing of the third clock signal CLK3 is opposite to the timing of the sixth clock signal CLK6.

[0105] In an embodiment of the present application, the timing of the initial and final signals transmitted by the first clock signal line 110 and the second clock signal line 120 are set to be opposite. When the timing is opposite, the voltage difference of the clock signals in the entire cycle is sustained to the maximum. The clock signals with opposite timing are set on both sides of the first scan driving circuit 200. This can avoid the crossing of the clock signals with the longest duration of the maximum voltage difference. The duration of the maximum voltage difference of the clock signals on the same side of the first scan driving circuit 200 does not occupy the entire cycle. The duration of the maximum voltage difference at the signal intersection can be shortened, and the breakdown of the insulating layer at the clock signal intersection can be minimized to the greatest extent, thereby improving the yield, service life and reliability of the display substrate.

[0106] Exemplarily, the peripheral side of the first scan driving circuit 200 can be divided into four plane areas. Figure 3 What is shown is only the case where the first clock signal line 110 and the second clock signal line 120 are respectively located on two opposite sides of the first scan driving circuit 200 . They can also be respectively located on two adjacent sides, which is not specifically limited in the embodiment of the present application.

[0107] In some embodiments, Figure 4 This is a schematic partial structural diagram of another display substrate provided in an embodiment of the present application. Figure 4As shown, the display substrate provided in an embodiment of the present application further includes: a plurality of second scan driving circuits 400, the second scan driving circuits 400 being electrically connected to the pixel circuits 300, and the first scan driving circuits 200 and the second scan driving circuits 400 being respectively arranged on different sides of the pixel circuits 300. The plurality of second scan driving circuits 400 can also be identified by numbers GOA1, GOA2, GOA3, GOA4, GOA5, GOA6, GOA7, GOA8, GOA9, GOA10, GOA11, GOA12, ... The clock signal line 100 further includes a third clock signal line 130 and a fourth clock signal line 140, the third clock signal line 130 and the fourth clock signal line 140 being electrically connected to different second scan driving circuits 400, and the clock signal transmitted by the third clock signal line 130 and the clock signal transmitted by the fourth clock signal line 140 having different timings. The third clock signal line 130, the fourth clock signal line 140 and the second scan driving circuit 400 are arranged on the same side of the pixel circuit 300, and the third clock signal line 130 and the fourth clock signal line 140 are respectively arranged on different sides of the second scan driving circuit 400. It can be understood that the second scan driving circuit 400 is located between the third clock signal line 130 and the fourth clock signal line 140. For example, referring to Figure 4 There can be three third clock signal lines 130, which respectively transmit the first clock signal CLK1, the second clock signal CLK2 and the third clock signal CLK3. There can be three fourth clock signal lines 140, which respectively transmit the fourth clock signal CLK4, the fifth clock signal CLK5 and the sixth clock signal CLK6.

[0108] For example, Figure 4As shown, the second clock signal line 120 is disposed between the first scan driver circuit 200 and the pixel circuit 300, and the fourth clock signal line 140 is disposed between the second scan driver circuit 400 and the pixel circuit 300. A plurality of pixel circuits 300 are arranged in an array; each scan driver circuit is electrically connected to a row of pixel circuits 300. The scan driver circuit includes a first scan driver circuit 200 and a second scan driver circuit 400. The first clock signal line 110 and the third clock signal line 130 are electrically connected to the pixel circuits 300 in the same row, respectively, and the second clock signal line 120 and the fourth clock signal line 140 are electrically connected to the pixel circuits 300 in the same row, respectively. It should be noted that the electrical connection between the clock signal line 100 and the pixel circuit 300 is achieved through the first scan driver circuit 200 and the second scan driver circuit 400. The clock signal is input to the scan driver circuit and then output as a scan signal. The scan signal is input to the pixel circuit 300 to implement the scan driver function. It is easy to understand that the first clock signal CLK1 on both sides of the pixel circuit 300 is input to GOA1, GOA7, ..., the second clock signal CLK2 is input to GOA2, GOA8, ..., the third clock signal CLK3 is input to GOA3, GOA9, ..., the fourth clock signal CLK4 is input to GOA4, GOA10, ..., the fifth clock signal CLK5 is input to GOA5, GOA11, ..., and the third clock signal CLK3 is input to GOA6, GOA12, .... In other words, the pixel circuits 300 in the same row receive scan signals output by the first scan driving circuit 200 and the second scan driving circuit 400 on both sides, respectively. For example, the pixel circuits 300 in the first row receive scan signals converted from the first clock signal CLK1 on both sides. Figure 4 The structure arrangement of the clock signal line 100 and the scan driving circuit shown is a driving circuit design of a double-side driving mode.

[0109] For example, Figure 5 This is a schematic partial structural diagram of another display substrate provided in an embodiment of the present application. Figure 5 As shown, the first clock signal line transmits the first clock signal CLK1, the second clock signal line transmits the second clock signal CLK2, the third clock signal line transmits the third clock signal CLK3, and the fourth clock signal line transmits the fourth clock signal CLK4. The first clock signal line and the third clock signal line are electrically connected to pixel circuits in different rows, that is, the first scan drive circuit connected to the first clock signal line and the second scan drive circuit connected to the third clock signal line are electrically connected to pixel circuits in different rows. The second clock signal line and the fourth clock signal line are electrically connected to pixel circuits in different rows, that is, the first scan drive circuit connected to the second clock signal line and the second scan drive circuit connected to the fourth clock signal line are electrically connected to pixel circuits in different rows. Figure 5The driving circuit design of the display substrate shown is a unilateral driving mode driving circuit design.

[0110] It should be noted that, regardless of the unit driving mode or the bilateral driving mode, the scanning driving circuit on one side of the pixel circuit is located between the two sets of clock signal lines, which can reduce the crossing of the clock signals and shorten the maximum voltage difference duration between the crossed clock signals. It can reduce the poor breakdown of the insulation layer at the intersection of the clock signals under long-term operation, and improve the yield, service life and reliability of the display substrate.

[0111] In some embodiments, Figure 6 A schematic partial structural diagram of a display substrate provided in an embodiment of the present application; Figure 7 A schematic cross-sectional view of a display substrate along BB provided in an embodiment of the present application. Figure 6 and Figure 7 The display substrate further includes: a substrate layer 101, a first metal layer 102, an insulating layer GI, and a second metal layer 103. The clock signal line 100 is provided in the first metal layer 102, the first metal layer 102 is provided between the substrate layer 101 and the second metal layer 103, the insulating layer GI is provided between the first metal layer 102 and the second metal layer 103, the insulating layer GI includes a first through-hole 104, and the first through-hole 104 is a via hole penetrating the insulating layer GI; the first scan driving circuit 200 is electrically connected to the corresponding clock signal line through the input lead 210, the input lead 210 is provided in the second metal layer 103, and the input lead 210 is electrically connected to the corresponding clock signal line through the first through-hole 104.

[0112] For example, the gate electrode of the thin film transistor of the display substrate may be disposed on the first metal layer 102 , and the source electrode and the drain electrode of the thin film transistor may be disposed on the second metal layer 103 .

[0113] In some embodiments, Figure 8 This is a schematic partial structural diagram of another display substrate provided in an embodiment of the present application. Figure 8 As shown, the second clock signal line 120 is provided between the first scan driving circuit 200 and the pixel circuit 300; the cascaded first scan driving circuits 200 are electrically connected via a cascade signal line 230, which is used to transmit a reset signal or a frame start signal. The cascade signal line 230 is provided on the second metal layer 103. It should be noted that Figure 8The cascade signal line 230 shown is used to transmit a reset signal. When the frame start signal is transmitted from top to bottom, the reset signal is transmitted from bottom to top, that is, a top-down row scan of the pixel circuit 300 can be achieved. The number of scan drive circuits spaced apart by the cascade signal line 230 for transmitting the reset signal can be obtained based on the number of pixel circuits and the number of clock signal lines. For example, the cascade signal line for transmitting the frame start signal can be set between the first clock signal line and the first scan drive circuit. For example, Figure 8 As shown, the reset signal of GOA7 is transmitted to GOA3 via the cascade signal line 230, and the reset signal of GOA6 is transmitted to GOA2 via the cascade signal line 230. The cascade signal lines for transmitting the reset signals of GOA1, GOA2, GOA3, GOA4, and GOA5 upward are left floating. Due to the large number of lines, for clarity, the cascade signal lines for GOA7, GOA6, GOA5, and GOA4 to receive the reset signal below are not fully shown.

[0114] refer to Figure 8 The input leads 210 include a first section of input leads 211 and a second section of input leads 212. The first section of input leads 211 and the second section of input leads 212 are electrically connected via a first jumper 213. The first jumper 213 is disposed on the first metal layer 102. The orthographic projection of the first jumper 213 on the substrate layer 101 intersects with the orthographic projection of the cascade signal line 230 on the substrate layer 101. The first scan driver circuit 200 is electrically connected to the pixel circuit 300 via output leads. The output leads are disposed on the first metal layer 102. The output leads include a first section of output leads 221 and a second section of output leads 222. The first section of output leads 221 and the second section of output leads 222 are electrically connected via a second jumper 223. The second jumper 223 is disposed on the second metal layer 103. The orthographic projection of the second jumper 223 on the substrate layer 101 intersects with the orthographic projection of the second clock signal line 120 on the substrate layer. First jumper line 213 and clock signal line are arranged on different metal layers to prevent cross-circuiting between connecting lines formed on the same metal layer. Second jumper line 223 and cascade signal line are arranged on different metal layers to prevent cross-circuiting between connecting lines formed on the same metal layer. Routing signal lines on different metal layers can save wiring space and reduce the bezel of the display substrate.

[0115] refer to Figure 8One end of the first-segment input lead 211 is electrically connected to the clock input terminal of the first scan driving circuit. The other end of the first-segment input lead 211 is electrically connected to one end of the first jumper 213 through the fifth through-hole 106 of the insulating layer. The other end of the first jumper 213 is electrically connected to one end of the second-segment input lead 212 through the fifth through-hole 106 of the insulating layer. The other end of the second-segment input lead 212 is electrically connected to the second clock signal line 120 through the first through-hole 104. One end of the first-segment output lead 221 is electrically connected to the output terminal of the first scan driving circuit 200. The other end of the first-segment output lead 221 is electrically connected to one end of the second jumper 223 through the sixth through-hole 107 of the insulating layer. The other end of the second jumper 223 is electrically connected to one end of the second-segment output lead 222 through the sixth through-hole 107 of the insulating layer. The other end of the second-segment output lead 222 is electrically connected to the pixel circuit 300.

[0116] refer to Figure 8 The non-display area NA of the display substrate is further provided with a common electrode COM, and the common electrode COM is used to input a common voltage signal. The common electrode COM is provided between the second clock signal line 120 and the pixel circuit 300 .

[0117] It should be noted that if Figure 8 As shown, the cascade signal line 230 is electrically connected to the second scan driving circuit through the third jumper line 231. The third jumper line 231 crosses the cascade signal line 230, but due to different layer settings, the third jumper line 231 is set in the first metal layer 102. The third jumper line 231 is used to avoid other cascade signal lines 230.

[0118] In some embodiments, the display substrate further includes a first auxiliary electrode 121, which is disposed on the first metal layer 102, and is connected in parallel with the adjacent clock signal line 100. The first auxiliary electrode 121 is used to receive the same clock signal as the parallel clock signal line 100. For example, referring to Figure 8 , the first auxiliary electrode 121 is connected in parallel with the adjacent second clock signal line 120, because Figure 8 Due to limited schematic space, the parallel locations are not shown. The first auxiliary electrodes 121 are disposed on the same layer as the clock signal lines 100. The parallel connection of the first auxiliary electrodes 121 can reduce the resistance of the clock signal lines 100, thereby reducing the IR drop (voltage drop) of the clock signal lines and improving the stability of the clock signals transmitted by the clock signal lines. In some examples, the clock signal lines 100 correspond one to one with the first auxiliary electrodes, i.e., one first auxiliary electrode 121 is connected in parallel to each clock signal line 100, which can both reduce resistance and reduce wiring space.

[0119] In some embodiments, reference Figure 8The display substrate may further include a second auxiliary electrode 122 disposed on the second metal layer 103. The second auxiliary electrode 122 is connected in parallel with the corresponding clock signal line 100 via a second through-hole 105 disposed in the insulating layer GI. The orthographic projection of the second auxiliary electrode 122 on the substrate layer 101 at least partially overlaps with the orthographic projection of the parallel clock signal line 100 on the substrate layer 101. The second auxiliary electrode 122 and the clock signal line 100 are disposed on different metal layers and connected in parallel via a through-hole in the insulating layer GI, which also serves to reduce the resistance of the clock signal line.

[0120] Exemplarily, one clock signal line 100 corresponds to at least two second auxiliary electrodes 122, and the second auxiliary electrodes 122 connected in parallel to the same clock signal line 100 are discontinuous. One second auxiliary electrode 122 covers at least two second through holes 105, thereby achieving parallel connection between the second auxiliary electrode 122 and the clock signal line. Figure 8 The number of the second auxiliary electrodes 122 shown is only for illustration and is not intended to be a specific limitation of the embodiment of the present application.

[0121] In some embodiments, reference Figure 8 The display substrate further includes a block electrode 214 disposed on the second metal layer 103. The block electrode 214 covers and fills the first through-hole 104. The block electrode 214 is electrically connected to the second-segment input lead 212. The block electrode 214 is electrically connected to the clock signal line 100 through the first through-hole 104. The orthographic projection of the block electrode 214 on the substrate layer 101 falls within the orthographic projection of the electrically connected clock signal line 100 on the substrate layer 101. The orthographic projection of the second auxiliary electrode 122 on the substrate layer 101 falls within the orthographic projection of the parallel clock signal line 100 on the substrate layer 101. The block electrode 214 is surrounded by at least two second auxiliary electrodes 122. The through-holes in the insulating layer GI affect the resistance of the signal line. By disposing a plurality of second through-holes 105 and second auxiliary electrodes 122 around the first through-hole 104, the impact of the first through-hole 104 can be minimized. Figure 8 The arrangement and number of the second through holes 105 and the second auxiliary electrodes 122 shown are merely illustrative and are not intended to be a specific limitation of the present application.

[0122] For example, Figure 8 As shown, one block electrode 214 covers at least two first through holes. The provision of multiple first through holes can enhance the electrical connection stability of the block electrode 214 .

[0123] In some embodiments, the distance between adjacent block electrodes 214 and the second auxiliary electrodes 122 is smaller than the distance between adjacent clock signal lines 100 , so that the influence of the through-hole on the resistance can be averaged.

[0124] For example, Figure 9 This is a partial design layout of a display substrate provided in an embodiment of the present application. Figure 9 As shown, a cascade signal line 230 is provided between the first scan driving circuit 200 and the second clock signal line 120. A common electrode COM is provided on the side of the second clock signal line 120 away from the first scan driving circuit 200. A sixth through hole 107 with an insulating layer is provided between the second clock signal line 120 and the common electrode COM for electrically connecting to the second jumper line 223. The first scan driving circuit 200 and the cascade signal line 230 are both indicated by dashed lines, and the first through hole 104 is indicated by a solid circle.

[0125] In some embodiments, Figure 10 This is a schematic partial structural diagram of another display substrate provided in an embodiment of the present application. Figure 10 As shown, the display substrate further includes a display driving circuit, which may include a driving chip and an FPC (flexible printed circuit). The driving chip is electrically connected to the FPC, and the FPC is electrically connected to the clock signal line via a driving signal lead 500. The driving signal lead 500 is provided on the first metal layer 102.

[0126] like Figure 10 As shown, the first auxiliary electrode 121 is connected in parallel to the corresponding clock signal lines at both ends. Figure 10 The parallel connection method shown uses lines connected on the same metal layer.

[0127] In some embodiments, the display substrate further includes a third auxiliary electrode, which is disposed on the second metal layer 103. The third auxiliary electrode and the drive signal lead 500 are disposed on different metal layers. The third auxiliary electrode is connected in parallel to the corresponding drive signal lead 500 via a third through hole disposed in the insulating layer. The provision of the third auxiliary electrode can reduce the resistance of the drive signal lead 500, thereby reducing the voltage drop across the drive signal lead 500.

[0128] refer to Figure 10 The display substrate may further include an electrostatic protection structure. The clock signal line 100 is electrically connected to the electrostatic protection structure via an electrostatic lead 600 , which is disposed on the second metal layer 103 . The electrostatic lead 600 is electrically connected to the clock signal line 100 via a fourth through hole disposed on the insulating layer.

[0129] In some embodiments, as Figure 10As shown, the electrostatic protection structure includes a first electrostatic protection structure ESD1 and a second electrostatic protection structure ESD2, which are respectively arranged on different sides of the pixel circuit 300. The clock signal line 100 includes a first end 123 and a second end 124. The first end 123 is electrically connected to the drive signal lead 500 and the first electrostatic protection structure ESD1, respectively, and the second end 124 is electrically connected to the second electrostatic protection structure ESD2. In the direction of the length extension of the clock signal line 100, the first auxiliary electrode 121 does not extend beyond the first end 123 and the second end 124. The electrostatic protection structure can be an electrostatic protection ring structure, which can be formed by connecting multiple diodes to dissipate static electricity and protect the circuits and devices of the display substrate.

[0130] It should be noted that the display substrate also includes a frame start signal line, a high-level signal line, a low-level signal line, an anode signal line, a test signal line, etc., all of which are connected to the drive signal lead 500 and the electrostatic protection structure, and the signals of each signal line come from the display drive circuit.

[0131] The display driving circuit may be provided with a memory and a processor, etc. The memory may be used to store a driving program, the processor may be used to execute the driving program, and the driving program may drive the display of the display substrate.

[0132] In some embodiments, all clock signal lines 100 have the same line width, and the line spacing of clock signal lines 100 on the same side of the first scan driving circuit 200 is the same, so that the resistance between the clock signal lines 100 can be consistent. For example, the line width can be 16 μm and the line spacing can be 9 μm.

[0133] In some embodiments, reference Figure 10 The distance between the common electrode COM and the nearest second clock signal line 120 is greater than the distance between adjacent second clock signal lines 120. This can provide space for the through hole of the second crossover line 223, thereby preventing interference between the common voltage signal and the clock signal. It should be noted that the through hole on the insulating layer between the common electrode COM and the nearest second clock signal line 120 can be centered in the spacing region, i.e., the distance between the through hole and the common electrode COM is equal to the distance from the second clock signal line 120.

[0134] For example, Figure 11 This is a schematic partial structural diagram of another display substrate provided in an embodiment of the present application. Figure 11As shown, the first auxiliary electrode 121 is provided on the same layer as the clock signal line. The first auxiliary electrode 121 can be electrically connected to the clock signal through a parallel connection line 125. The number of parallel connection lines 125 between the first auxiliary electrode 121 and the corresponding parallel clock signal line can be multiple. The parallel connection lines 125 can be provided at both ends of the first auxiliary electrode 121. The second auxiliary electrode 122 and the second through hole 105 can be provided near the parallel connection line 125 between the clock signal line and the first auxiliary electrode 121. The number of the second auxiliary electrodes 122 and the second through hole 105 can be set according to specific needs. Figure 11 This is for illustration only. For example, the number of parallel connection lines 125 between a group of parallel clock signal lines and the first auxiliary electrode 121 can be greater than 1 and less than 10. The number of parallel connection lines 125 being greater than 1 prevents a break in a single parallel connection line 125 from affecting the electrical connection between the clock signal line and the first auxiliary electrode 121. The number of parallel connection lines 125 being less than 10 prevents the clock signal line from being thickened.

[0135] It should be noted that Figure 10 and Figure 11 The connection manner between the clock signal lines and the corresponding parallel-connected first auxiliary electrodes 121 is merely illustrative and other connection manners are also possible, which are not specifically limited in the embodiments of the present application.

[0136] For example, Figure 12 This is a connection design layout of a first electrostatic protection structure provided in an embodiment of the present application. Figure 12 As shown, the first electrostatic protection structure ESD1 is also connected to the frame start signal line STV, and the clock signal line is electrically connected to the first electrostatic protection structure ESD1 through the electrostatic lead 600. The frame start signal line STV, the clock signal line and the common electrode COM are all electrically connected to the drive signal lead 500. The signal lines corresponding to the reset signal TRST, the high level signal VDD, the low level signal VGL and the transmitter start signal are electrically connected to the first electrostatic protection structure ESD1 through the electrostatic lead 600. Figure 12 The third auxiliary electrode is disposed on the second metal layer 103. The third auxiliary electrode and the drive signal lead 500 are disposed on different metal layers. The third auxiliary electrode is connected in parallel to the corresponding drive signal lead 500 via a third through-hole 501, which is disposed in the insulating layer. The provision of the third auxiliary electrode can reduce the resistance of the drive signal lead 500, thereby reducing the voltage drop across the drive signal lead 500.

[0137] refer to Figure 12 The clock signal line 100 is electrically connected to the electrostatic protection structure through the electrostatic lead 600, and the electrostatic lead 600 is set in the second metal layer 103. The electrostatic lead 600 is electrically connected to the clock signal line 100 through the fourth through hole 601, and the fourth through hole 601 is set in the insulating layer.

[0138] For example, Figure 13 This is a connection design layout of a second electrostatic protection structure provided in an embodiment of the present application. Figure 13 As shown, the second electrostatic protection structure ESD2 is electrically connected to the clock signal line through the electrostatic lead 600 .

[0139] A second aspect of the embodiments of the present application provides a method for driving a display substrate, which is applied to the display substrate as described in the first aspect. Figure 14 This is a schematic flow chart of a method for driving a display substrate provided in an embodiment of the present application. Figure 14 As shown, the driving method includes:

[0140] S001: Transmit a clock signal to a first clock signal line and a second clock signal line respectively.

[0141] S002: Transmitting a frame start signal to a first first scan driver circuit to scan and drive the electrically connected pixel circuits based on the clock signal and the frame start signal. The frame start signal is used to turn on an enable transistor of the first first scan driver circuit and is transmitted to subsequent first scan driver circuits via cascade signal lines. The frame start signal is used to initiate row scanning. Driven by the frame start signal and the clock signal, row scanning of the display substrate begins.

[0142] In some examples, the method for driving a display substrate further includes:

[0143] Adjust the high and low level amplitudes of the clock signal to reduce the voltage difference between clock signals where lines cross. Reducing the voltage difference can reduce the possibility of insulation breakdown at the intersection of clock signals, thereby reducing the defects caused by insulation breakdown.

[0144] Exemplarily, the high-level signal of the clock signal may be lowered, and the low-level signal transmitted to the scan driving circuit may be increased.

[0145] According to a third aspect of the present application, a display panel is provided. Figure 15 This is a schematic structural block diagram of a display panel provided in an embodiment of the present application. Figure 15 As shown, the display panel includes the display substrate 1000 as described in the first aspect.

[0146] According to a fourth aspect of the present application, a display device is provided. Figure 16 This is a schematic structural block diagram of a display device provided in an embodiment of the present application. Figure 16 As shown, the display device includes the display panel 2000 as described in the third aspect.

[0147] It should be noted that the display device can be a smart phone, a laptop computer, a television, a tablet computer or other displays, and is not specifically limited in the embodiments of the present application.

[0148] The display driving circuit of the display substrate may include a memory and a processor. The memory may store a computer program, and the processor may execute the computer program to implement the display substrate driving method described in the second aspect.

[0149] It should be noted that, in the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0150] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-readable program code.

[0151] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0152] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0153] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0154] An embodiment of the present application further provides a computer program product, which includes computer software instructions. When the computer software instructions are executed on a processing device, the processing device executes a process of a method for driving a display substrate.

[0155] A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, a process or function according to an embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. A computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or data center that includes one or more available media integrations. Available media may be magnetic media (e.g., floppy disk, hard disk, tape), optical media (e.g., DVD), or semiconductor media (e.g., solid-state disk (SSD)), etc.

[0156] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0157] In the several embodiments provided in this application, it should be understood that the disclosed devices, apparatuses and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.

[0158] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0159] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0160] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0161] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

[0162] Although the preferred embodiments of this specification have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of this specification.

[0163] Obviously, those skilled in the art may make various changes and modifications to this specification without departing from the spirit and scope of this specification. Thus, if such changes and modifications fall within the scope of the claims of this specification and their equivalents, this specification is intended to include such changes and modifications.

Claims

1. A display substrate, characterized in that: include: a plurality of pixel circuits; a plurality of first scan driving circuits electrically connected to the pixel circuits; a clock signal line, comprising a first clock signal line and a second clock signal line, wherein the first clock signal line and the second clock signal line are electrically connected to different first scan driving circuits respectively; The first clock signal line, the second clock signal line and the first scan driving circuit are arranged on the same side of the pixel circuit, and the first clock signal line and the second clock signal line are respectively arranged on different sides of the first scan driving circuit.

2. The display substrate according to claim 1, wherein: The timing of the clock signal transmitted by the first clock signal line is different from the timing of the clock signal transmitted by the second clock signal line.

3. The display substrate according to claim 2, wherein: The timing of the clock signal transmitted by the first clock signal line is opposite to that of the clock signal transmitted by the second clock signal line.

4. The display substrate according to claim 3, wherein: In a case where the timing of the clock signal transmitted by the first clock signal line is a high-level signal period, the timing of the clock signal transmitted by the second clock signal line is a low-level signal period; In a case where the timing of the clock signal transmitted by the first clock signal line is a low-level signal period, the timing of the clock signal transmitted by the second clock signal line is a high-level signal period.

5. The display substrate according to claim 3, wherein: The first clock signal line includes a first sub-signal line to an nth sub-signal line, and the second clock signal line includes an n+1th sub-signal line to a 2nth sub-signal line, where n is a natural number greater than 1; The first to 2n sub-signal lines are electrically connected to different first scan driving circuits respectively; The clock signal transmitted by the first sub-signal line is opposite in timing to the clock signal transmitted by the (n+1)th sub-signal line, and the clock signal transmitted by the nth sub-signal line is opposite in timing to the clock signal transmitted by the (2n)th sub-signal line.

6. The display substrate according to claim 1, wherein: The first clock signal line and the second clock signal line are arranged opposite to each other with respect to the first scan driving circuit.

7. The display substrate according to claim 6, wherein: Also includes: substrate layer; a first metal layer, wherein the clock signal line is provided on the first metal layer; a second metal layer, the first metal layer being disposed between the substrate layer and the second metal layer; an insulating layer, disposed between the first metal layer and the second metal layer, the insulating layer comprising a first through hole; The first scan driving circuit is electrically connected to the corresponding clock signal line through an input lead, the input lead is provided in the second metal layer, and the input lead is electrically connected to the corresponding clock signal line through the first through hole.

8. The display substrate according to claim 7, wherein: The second clock signal line is provided between the first scan driving circuit and the pixel circuit; The first scan driving circuits in cascade are electrically connected to each other via cascade signal lines, the cascade signal lines are used to transmit a reset signal or a frame start signal, and the cascade signal lines are provided on the second metal layer; The input lead includes a first section of input lead and a second section of input lead, the first section of input lead and the second section of input lead are electrically connected through a first jumper line, the first jumper line is set on the first metal layer, and the orthographic projection of the first jumper line on the substrate layer intersects with the orthographic projection of the cascade signal line on the substrate layer.

9. The display substrate according to claim 7, wherein: The first scan driving circuit is electrically connected to the pixel circuit via an output lead, the output lead is provided on the first metal layer, and the output lead includes a first section of output lead and a second section of output lead; The first output lead and the second output lead are electrically connected via a second jumper line, the second jumper line is arranged on the second metal layer, and the orthographic projection of the second jumper line on the substrate layer intersects with the orthographic projection of the second clock signal line on the substrate layer.

10. The display substrate according to claim 7, wherein: Also includes: a first auxiliary electrode, disposed on the first metal layer, the first auxiliary electrode being connected in parallel with the adjacent clock signal line, and the first auxiliary electrode being used to receive the same clock signal as the parallel clock signal line; and / or, A second auxiliary electrode is arranged on the second metal layer, the second auxiliary electrode is connected in parallel with the corresponding clock signal line through a second through hole, the second through hole is arranged on the insulating layer, and the orthographic projection of the second auxiliary electrode on the substrate layer at least partially overlaps with the orthographic projection of the parallel clock signal line on the substrate layer.

11. The display substrate according to claim 10, wherein: Also includes: a block electrode disposed on the second metal layer, the block electrode covering and filling the first through-hole, the block electrode being electrically connected to the input lead, the block electrode being electrically connected to the clock signal line through the first through-hole, and an orthographic projection of the block electrode on the substrate layer falling within an orthographic projection of the electrically connected clock signal line on the substrate layer; In the case where the display substrate includes the second auxiliary electrode, the orthographic projection of the second auxiliary electrode on the substrate layer falls within the orthographic projection of the parallel clock signal line on the substrate layer; The circumference of the block electrode surrounds at least two of the second auxiliary electrodes.

12. The display substrate according to claim 11, wherein: One of the block electrodes covers at least two of the first through holes; and / or, One second auxiliary electrode covers at least two second through holes; and / or, The distance between adjacent block electrodes and the second auxiliary electrodes is smaller than the distance between adjacent clock signal lines.

13. The display substrate according to claim 10, wherein: In the case where the display substrate includes the first auxiliary electrodes, the clock signal lines correspond to the first auxiliary electrodes in a one-to-one manner; and / or, In the case where the display substrate includes the second auxiliary electrodes, one clock signal line corresponds to at least two second auxiliary electrodes, and the second auxiliary electrodes connected in parallel to the same clock signal line are discontinuous.

14. The display substrate according to claim 10, wherein: Also includes: Display driver circuit; a driving signal lead, provided on the first metal layer, wherein the display driving circuit is electrically connected to the clock signal line via the driving signal lead; The third auxiliary electrode is provided on the second metal layer. The third auxiliary electrode is connected in parallel with the corresponding driving signal lead through a third through hole. The third through hole is provided on the insulating layer.

15. The display substrate according to claim 14, wherein: Also includes: An electrostatic protection structure, wherein the clock signal line is electrically connected to the electrostatic protection structure through an electrostatic lead, the electrostatic lead is arranged on the second metal layer, and the electrostatic lead is electrically connected to the clock signal line through a fourth through hole, and the fourth through hole is arranged on the insulating layer.

16. The display substrate according to claim 15, wherein: The electrostatic protection structure includes a first electrostatic protection structure and a second electrostatic protection structure, wherein the first electrostatic protection structure and the second electrostatic protection structure are respectively arranged on different sides of the pixel circuit; The clock signal line includes a first end and a second end, the first end is electrically connected to the drive signal lead and the first electrostatic protection structure respectively, and the second end is electrically connected to the second electrostatic protection structure; In the length extension direction of the clock signal line, the first auxiliary electrode does not extend beyond the first end and the second end.

17. The display substrate according to claim 1, wherein All the clock signal lines have the same line width; and / or, The clock signal lines located on the same side of the first scan driving circuit have the same line spacing.

18. The display substrate according to claim 1, wherein Also includes: a common electrode, disposed between the second clock signal line and the pixel circuit, wherein the second clock signal line is disposed between the first scan drive circuit and the pixel circuit; The distance between the common electrode and the nearest second clock signal line is greater than the distance between adjacent second clock signal lines.

19. The display substrate according to any one of claims 1 to 18, characterized in that: Also includes: a plurality of second scan driving circuits electrically connected to the pixel circuit, wherein the first scan driving circuit and the second scan driving circuit are respectively arranged on different sides of the pixel circuit; The clock signal line further includes a third clock signal line and a fourth clock signal line, wherein the third clock signal line and the fourth clock signal line are electrically connected to different second scan driving circuits respectively, and the clock signal transmitted by the third clock signal line has a different timing sequence from the clock signal transmitted by the fourth clock signal line; The third clock signal line, the fourth clock signal line and the second scan driving circuit are arranged on the same side of the pixel circuit, and the third clock signal line and the fourth clock signal line are respectively arranged on different sides of the second scan driving circuit.

20. The display substrate according to claim 19, wherein The second clock signal line is provided between the first scan driving circuit and the pixel circuit, the fourth clock signal line is provided between the second scan driving circuit and the pixel circuit, and the plurality of pixel circuits are arranged in an array; Each scan driving circuit is electrically connected to a row of pixel circuits, and the scan driving circuit includes the first scan driving circuit and the second scan driving circuit; The first clock signal line and the third clock signal line are respectively electrically connected to the pixel circuits in the same row, and the second clock signal line and the fourth clock signal line are respectively electrically connected to the pixel circuits in the same row; or, the first clock signal line and the third clock signal line are respectively electrically connected to the pixel circuits in different rows, and the second clock signal line and the fourth clock signal line are respectively electrically connected to the pixel circuits in different rows.

21. A method for driving a display substrate, characterized in that: Applied to the display substrate according to any one of claims 1 to 20, the driving method comprises: transmitting clock signals to the first clock signal line and the second clock signal line respectively, And, transmitting a frame start signal to a first first scan driving circuit to scan and drive the electrically connected pixel circuits based on the clock signal and the frame start signal.

22. The method for driving a display substrate according to claim 21, wherein: Also includes: The high level amplitude and the low level amplitude of the clock signal are adjusted to reduce the voltage difference between the clock signals with line crossing.

23. The method for driving a display substrate according to claim 22, wherein: The adjusting the high level amplitude and the low level amplitude of the clock signal to reduce the voltage difference between the clock signals having line crossings includes: The high level signal of the clock signal is lowered, and the low level signal transmitted to the scan driving circuit is increased.

24. A display panel, characterized in that: include: The display substrate according to any one of claims 1 to 20.

25. A display device, characterized in that: include: The display panel as claimed in claim 24.

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