A multi-beam phased transmitting circuit with amplitude weighting

Abstract

The present invention discloses a multi-beam phased transmitting circuit with amplitude weighting, belonging to the field of circuits, which includes a signal source and a plurality of power amplifier circuits. The signal source transmits a positive low-voltage driving signal and a negative low-voltage driving signal to each power amplifier circuit respectively. The time interval τ between two adjacent positive low-voltage driving signals and between two adjacent negative low-voltage driving signals is the delay time between two power amplifier circuits obtained according to the phased angle. The multi-beam phased transmitting circuit with amplitude weighting of the present invention adopts technologies such as changing the duty cycle to adjust the amplitude of the transmitted signal, full-bridge power amplifier and impedance matching, thereby realizing a multi-beam phased circuit with amplitude weighting, realizing phased transmission, and improving the main-to-side lobe ratio.

Description

Technical Field

[0001] The present invention relates to the technical field of circuits, and particularly to a multi-beam phased transmission circuit with amplitude weighting. Background Art

[0002] A multi-beam sounding instrument is an efficient seabed topographic mapping device. It can give the water depth values of dozens or even hundreds of seabed measurement points in a vertical plane perpendicular to the navigation direction in one measurement, or a full-coverage water depth strip of a certain width; therefore, it can accurately and quickly measure the size, shape, and height changes of underwater targets within a certain width along the route, and thus more precisely depict the accurate characteristics of the seabed topography.

[0003] The function of a multi-beam phased transmission circuit is to amplify the phased signal given by an external signal source, drive the transmitting transducer, and precisely control the phases of the transmitting elements of the transmitting transducer, so that the acoustic signal transmitted by the transmitting transducer obtains directivity in a predetermined direction. For a transmitting system, having directivity means that the transmitted energy can be concentrated in a certain direction. In this way, first, a smaller transmitted power can be used to detect targets at a farther distance, and second, the direction of the transmitted directivity can be changed according to the change of roll, so that the acoustic signal of the transmitting array maintains directivity in the direction perpendicular to the horizontal plane. Summary of the Invention

[0004] The purpose of the present invention is to provide a multi-beam phased transmission circuit with amplitude weighting to solve the problems in the background art.

[0005] To solve the above technical problems, the present invention provides a multi-beam phased transmission circuit with amplitude weighting, which includes a signal source and a plurality of power amplifier circuits. The signal source transmits a positive low-voltage driving signal and a negative low-voltage driving signal to each power amplifier circuit respectively; the time interval τ between two adjacent positive low-voltage driving signals and between two adjacent negative low-voltage driving signals is the delay time between two power amplifier circuits obtained according to the phased angle.

[0006] The power amplifier circuit includes an optocoupler isolation circuit, a gate circuit, a driving circuit, a full-bridge power amplifier, an impedance matching circuit, and a first transducer element connected in sequence. The optocoupler isolation circuit plays a role in signal isolation. The gate circuit raises the level of the phased signal of the external circuit. The driving circuit is used to drive the full-bridge circuit. The impedance matching circuit performs tuning matching and impedance matching.

[0007] In an embodiment, the optocoupler isolation circuit includes a dual-channel optocoupler chip HCPL2630, resistors R1 to R4, and capacitors C1 to C2.

[0008] The first Anode terminal of the dual-channel optocoupler chip HCPL2630 is connected to the signal source signal A+, the first Cathode terminal is grounded through the resistor R1, the second Cathode terminal is connected to the signal source signal A-, the second Anode terminal is grounded through the resistor R2, the VCC terminal is connected to the first ends of the resistors R3 and R4, the first output terminal is connected to the external signal GA1+ through the second end of the resistor R3, the second output terminal is connected to the external signal GA1-, and the GND terminal is grounded;

[0009] The second end of the resistor R3 is grounded through the capacitor C1, and the second end of the resistor R4 is grounded through the capacitor C2.

[0010] In one embodiment, the resistors R3 and R4 are pull-up circuits, and the capacitors C1 and C2 are used for filtering.

[0011] In one embodiment, the gate circuit includes NOT gates N4_1D and N4_1E, AND gates N1_1C and N1_1D, resistors R6 and R7, and capacitors C6 and C7;

[0012] The input terminals of the NOT gates N4_1D and N4_1E are respectively connected to the external signals GA1+ and GA1-, and the two output terminals are respectively connected to one input terminal of the AND gates N1_1C and N1_1D; the other input terminals of the AND gates N1_1C and N1_1D are respectively connected to the external signals GA1- and GA1+, and the two output terminals respectively output drive signals HIN1 and LIN1;

[0013] One end of the resistor R6 is connected to the output terminal of the AND gate N1_1C, and the other end is grounded; one end of the resistor R7 is connected to the output terminal of the AND gate N1_1D, and the other end is grounded; the capacitors C6 and C7 are respectively in parallel with the resistors R6 and R7.

[0014] In one embodiment, the resistors R6 and R7 are respectively pull-down resistors, and the capacitors C6 and C7 play a filtering role.

[0015] In one embodiment, the drive circuit includes a drive chip IR2110, resistors R9 to R11, capacitors C3 to C5, and diodes V1 to V2;

[0016] One end of the capacitors C3 and C4 is grounded, and the other end is connected to a 15V voltage; the positive pole of the diode V1 is connected to the 15V voltage, the negative pole is connected to the VB terminal of the drive chip IR2110 and one end of the capacitor C5, the other end of the capacitor C5 is connected to the negative pole of the diode V2, and the positive pole of the diode V2 is connected to the VSS terminal of the drive chip IR2110;

[0017] The LO terminal of the drive chip IR2110 is connected to the resistor R9, the VS terminal is connected to the resistor R10, and the HO terminal is connected to the resistor R11.

[0018] In one embodiment, the full-bridge power amplifier includes diodes V5 to V8, resistors R15 to R18, and NMOS transistors V9 to V12;

[0019] The drain terminals of NMOS transistor V9, NMOS transistor V11, the negative electrodes of diode V5 and diode V7 are connected together, and the drain terminals of NMOS transistor V10, NMOS transistor V12, the positive electrodes of diode V6 and diode V8 are connected together; the source terminal of NMOS transistor V9 is connected to the source terminal of NMOS transistor V10, and the source terminal of NMOS transistor V11 is connected to the source terminal of NMOS transistor V12;

[0020] Both ends of resistor R15 are respectively connected to the gate terminal and the source terminal of NMOS transistor V9, both ends of resistor R17 are respectively connected to the gate terminal and the source terminal of NMOS transistor V11, both ends of resistor R16 are respectively connected to the gate terminal and the drain terminal of NMOS transistor V10, and both ends of resistor R18 are respectively connected to the gate terminal and the drain terminal of NMOS transistor V12;

[0021] The negative electrode of diode V6 is connected to the positive electrode of diode V5, and the negative electrode of diode V8 is connected to the positive electrode of diode V7.

[0022] In one embodiment, the NMOS transistors V9, V10, V11, and V12 form a full-bridge power amplifier, the resistors R15, R16, R17, and R18 are the leakage resistors of the field-effect transistors, and the diodes V5, V6, V7, and V8 form a protection circuit for four field-effect transistors.

[0023] In one embodiment, the impedance matching circuit includes an inductor L1, resistors R33 to R34, a capacitor C21, diodes V5 to V6, and a transducer Y1;

[0024] The first end of resistor R34 is connected to the first end of inductor L1, the second end of resistor R34 is simultaneously connected to the first end of resistor R33, the positive electrode of diode V5, and the negative electrode of diode V6, and the second end of resistor R33, the negative electrode of diode V5, and the positive electrode of diode V6 are connected together;

[0025] One end of capacitor C21 is connected to the second end of inductor L1, the other end is connected to the first end of transducer Y1, and the second end of transducer Y1 is connected to the second end of inductor L1.

[0026] In one embodiment, the inductor L1 and the capacitor C21 form an impedance matching circuit, the resistors R33, R34, and diodes V5, V6 form an emission indication circuit, and during normal emission, the two LED lights of diodes V5 and V6 flash, and the higher the emission peak-to-peak value, the brighter the indicator light.

[0027] A multi-beam phased transmitting circuit with amplitude weighting provided by the present invention can further improve the directivity of the transmitting array after amplitude weighting, mainly by improving the relative amplitude of the main lobe and side lobe, that is, obtaining the lowest side lobe under the requirement of a given main lobe width, thereby reducing the target signal intensity measured by the side lobe, which is beneficial to reducing the influence of the side lobe in subsequent signal processing and obtaining high-quality target signals. The multi-beam phased transmitting circuit with amplitude weighting of the present invention adopts technologies such as changing the duty cycle to adjust the amplitude of the transmitting signal, full-bridge power amplification, and impedance matching, thereby realizing a multi-beam phased circuit with amplitude weighting, realizing phased transmission, and improving the main lobe-to-side lobe ratio. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 FIG. is a schematic structural diagram of a multi-beam phased transmitting circuit with amplitude weighting provided by the present invention.

[0029] Figure 2 FIG. is a schematic diagram of two signals given by a signal source.

[0030] Figure 3 FIG. is a schematic diagram of amplitude weighting.

[0031] Figure 4 FIG. is a schematic structural diagram of an optocoupler isolation circuit.

[0032] Figure 5 FIG. is a schematic structural diagram of a gate circuit.

[0033] Figure 6 FIG. is a schematic structural diagram of a drive circuit.

[0034] Figure 7 FIG. is a schematic structural diagram of a full-bridge circuit.

[0035] Figure 8 FIG. is a schematic structural diagram of an impedance matching circuit. DETAILED DESCRIPTION OF THE INVENTION

[0036] The following further describes in detail a multi-beam phased transmitting circuit with amplitude weighting proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the embodiments of the present invention.

[0037] The present invention provides a multi-beam phased transmitting circuit with amplitude weighting.

[0038] The system block diagram of the multi-beam phased transmitting circuit is as Figure 1As shown. The signal source generates twenty phased signals and supplies them to the power amplifier circuit. Here, the signal source selects the XC95288XL-7TQ144I chip of the XC9500XL 3.3V ISP series from Xilinx. It is a 3.3V low-voltage and high-efficiency CPLD, and its internal resources and the number of IOs can meet the normal requirements.

[0039] The optocoupler isolation circuit plays a role in signal isolation. Since the subsequent circuit is a high-voltage and high-power circuit, while the signal source is a low-voltage circuit, the one-way transmission of the signal can be realized through the optocoupler isolation circuit, enabling electrical isolation between the subsequent circuit and the signal source, reducing the interference of the subsequent circuit to the signal source during high-power transmission, and thus making the signal source work stably.

[0040] The gate circuit in the power amplifier circuit is composed of a NOT gate and an AND gate. One of its functions is to raise the level of the phased signal of the external circuit, and the other is to prevent the two signals entering the driving device from being high at the same time, thus preventing the full-bridge power amplifier from being misconducted.

[0041] The drive circuit is used to drive the power amplification transistor. The IR2110 driver produced by IR Company of the United States is adopted in the present invention, which has the advantages of small size and fast speed.

[0042] Considering the volume, a transformer is not used, so the full-bridge power amplifier form is selected in the power amplifier form. Considering the working current and working voltage, four IRF640 chips are selected to form the full-bridge power amplifier.

[0043] The impedance matching circuit has very important functions: one is tuning and matching, that is, adjusting the impedance of the transducer through the impedance matching circuit to make the transducer as close as possible to the pure resistance state and reduce the reactive component; the other is impedance matching, that is, changing the impedance of the transducer to make it impedance-matched with the power supply to ensure that the transducer obtains the maximum electric power. Considering that the impedance of the transducer is capacitive and to prevent the transducer from short-circuiting and causing damage to the instrument, a series inductor and a parallel capacitor are used for matching.

[0044] The functions of the charging circuit and the discharging circuit are to use the electrolytic capacitor charging circuit to store energy for the power amplifier circuit to use, and use the discharging circuit to quickly release the residual energy in the electrolytic capacitor after the instrument is turned off.

[0045] In actual use, due to the reason of pitching, if phased emission is not adopted, then the directivity direction of the emission array will change with the pitching angle θ at this time. Therefore, if it is desired that the directivity of the emission array does not change, it is necessary to use phased emission to form an emission beam in the opposite direction of the θ angle. Then the time difference τ between the (i + 1)-th element and the i-th element for emission is:

[0046] τ = d × sinθ / c (1.1)

[0047] where d is the spacing between array elements, and c is the propagation speed of sound waves in water. When the time difference τ is positive, the (i + 1)-th array element emits with a delay compared to the i-th array element; when τ is negative, the (i + 1)-th array element emits ahead of the i-th array element.

[0048] For an equally spaced linear array with N array elements, the time difference τ by which the emission waveform of the i-th array element should lag or lead that of the 1st array element i is:

[0049]

[0050] where τ i is lag when it is positive and lead when it is negative; d is the spacing between array elements, and c is the propagation speed of sound waves in water.

[0051] In the present invention, twenty array elements are adopted, the array element spacing is 0.024 m, the phased array angle range is from -7.5° to 7.5° (with each increment of 0.75° being a phased array angle, a total of 21 phased array angles). Taking the phased array angle of 0.75° as an example, the time difference between the (i + 1)-th array element and the i-th array element for emission is:

[0052] τ = d × sinθ / c = 0.024 × sin0.75 / 1500 = 209 (ns)

[0053] As Figure 2 shown, since a full-bridge power amplifier is used, there are two signals corresponding to each power amplifier circuit, and the two signals cannot be high simultaneously. Figure 2 In it, A1+ and A1- are the first low-voltage drive signals of the power amplifier given by the signal source, A2+ and A2- are the second low-voltage drive signals of the power amplifier. The time interval τ between A1+ and A2+ as well as between A1- and A2- is the delay time between the two power amplifier circuits obtained according to the phased array angle. Taking the phased array angle of 0.75° as an example, τ is 209 ns at this time. Figure 2 In it, b is the period time corresponding to the emission frequency, and the peak-to-peak voltage applied across the transducer is determined by adjusting the pulse magnitude of a, i.e., the duty cycle of the low-voltage drive signal.

[0054] In the case of an equally spaced linear array, the most commonly used amplitude weighting method is Dolph-Chebyshev weighting. According to the formula, the weighting value corresponding to each of the 20 power amplifier circuits can be calculated, and then the ratio of the emission peak-to-peak values between each path can be obtained, so as to determine the duty cycle of each path. After obtaining the delay between each path according to the phased array angle, amplitude-weighted phased emission can be achieved by changing the duty cycle of each path. Still taking the two paths just mentioned as an example, as Figure 3As shown, the time intervals τ between A1+ and A2+ and between A1- and A2- are the same as before, achieving a phase control angle of 0.75°. At this time, by adjusting the duty cycles of A2+ and A2-, the transmission energy is increased, so that the transmission peak-to-peak value of the first power amplifier circuit is also larger than that of the second power amplifier circuit, thereby achieving amplitude weighting.

[0055] Since each power amplifier circuit corresponds to a pair of signals, taking the first path as an example, they are A1+ and A1- respectively. Therefore, a dual-channel optocoupler chip HCPL2630 is adopted. As Figure 4 shown in the structural schematic diagram of the optocoupler isolation circuit, it includes a dual-channel optocoupler chip HCPL2630, resistors R1 to R4, and capacitors C1 to C2. The first Anode terminal of the dual-channel optocoupler chip HCPL2630 is connected to the signal source signal A+, the first Cathode terminal is grounded through resistor R1, the second Cathode terminal is connected to the signal source signal A-, the second Anode terminal is grounded through resistor R2, the VCC terminal is connected to the first ends of resistors R3 and R4, the first output terminal is connected to the external signal GA1+ through the second end of resistor R3, the second output terminal is connected to the external signal GA1-, and the GND terminal is grounded. The second end of resistor R3 is grounded through capacitor C1, and the second end of resistor R4 is grounded through capacitor C2. Resistors R3 and R4 are pull-up circuits, and capacitors C1 and C2 achieve filtering. Through this optocoupler isolation circuit, the signal source signals A1+, A1- and GA1+, GA1- are not grounded together, thereby reducing the interference of the subsequent circuit on the signal source.

[0056] The gate circuit is as Figure 5 shown, including NOT gates N4_1D and N4_1E, AND gates N1_1C and N1_1D, resistors R6 and R7, and capacitors C6 and C7. The input terminals of NOT gates N4_1D and N4_1E are respectively connected to the external signals GA1+ and GA1-, and the two output terminals are respectively connected to one input terminal of AND gates N1_1C and N1_1D; the other input terminals of AND gates N1_1C and N1_1D are respectively connected to the external signals GA1- and GA1+, and the two output terminals respectively output drive signals HIN1 and LIN1. One end of resistor R6 is connected to the output terminal of AND gate N1_1C, and the other end is grounded; one end of resistor R7 is connected to the output terminal of AND gate N1_1D, and the other end is grounded; capacitors C6 and C7 are respectively in parallel with resistors R6 and R7. The resistors R6 and R7 are pull-down resistors respectively, and the capacitors C6 and C7 play a filtering role.

[0057] The drive signal HIN1 is obtained by passing GA1+ through a NOT gate and then ANDing it with GA1-, and the drive signal LIN1 is obtained by passing GA1- through a NOT gate and then ANDing it with GA1+. This ensures that regardless of the levels of the external signals GA1+ and GA1-, the drive signals HIN1 and LIN1 supplied to the full-bridge power amplifier will not both be high at the same time, thus avoiding device damage caused by mis-conduction of the paired transistors. During normal driving and Figure 3 as shown, at this time, the waveform of HIN1 obtained by passing the external signal GA1+ through a NOT gate and then ANDing it with GA1- is the same as the external signal GA1-; the waveform of LIN1 obtained by passing the external signal GA1- through a NOT gate and then ANDing it with GA1+ is the same as GA1+. If the external signals GA1+ and GA1- are both high for some unknown reason, after passing through the gate circuit, the drive signals HIN1 and LIN1 are both low, so that the power amplifier transistors are not conducting, which plays a protective role.

[0058] For the full-bridge power amplifier, the principles of the left and right drive circuits are exactly the same. The principle of the left drive circuit is as Figure 6 shown, including the drive chip IR2110, resistors R9 to R11, capacitors C3 to C5, and diodes V1 to V2. One end of capacitors C3 and C4 is grounded, and the other end is connected to a 15V voltage; the positive pole of diode V1 is connected to the 15V voltage, and the negative pole is connected to the VB terminal of the drive chip IR2110 and one end of capacitor C5. The other end of capacitor C5 is connected to the negative pole of diode V2, and the positive pole of diode V2 is connected to the VSS terminal of the drive chip IR2110. The LO terminal of the drive chip IR2110 is connected to resistor R9, the VS terminal is connected to resistor R10, and the HO terminal is connected to resistor R11.

[0059] The left and right drive circuits receive the positive half-cycle pulse signal HIN1 and the negative half-cycle pulse signal LIN1 transmitted from the gate circuit, and output the drive signals RH, RV, and RL. When the HIN1 signal is valid, the RH signal output by the left drive circuit and the LL signal (not shown in the figure) of the right drive circuit are valid; when the LIN1 signal is valid, the RL signal output by the left drive circuit and the LH signal (not shown in the figure) of the right drive circuit are valid.

[0060] The full-bridge power amplifier is as Figure 7As shown, it includes diodes V5 to V8, resistors R15 to R18, and NMOS transistors V9 to V12. The drain terminals of NMOS transistor V9, NMOS transistor V11, the negative electrodes of diode V5 and diode V7 are connected together. The drain terminals of NMOS transistor V10, NMOS transistor V12, the positive electrodes of diode V6 and diode V8 are connected together. The source terminal of NMOS transistor V9 is connected to the source terminal of NMOS transistor V10, and the source terminal of NMOS transistor V11 is connected to the source terminal of NMOS transistor V12. The two ends of resistor R15 are respectively connected to the gate terminal and the source terminal of NMOS transistor V9, the two ends of resistor R17 are respectively connected to the gate terminal and the source terminal of NMOS transistor V11, the two ends of resistor R16 are respectively connected to the gate terminal and the drain terminal of NMOS transistor V10, and the two ends of resistor R18 are respectively connected to the gate terminal and the drain terminal of NMOS transistor V12. The negative electrode of diode V6 is connected to the positive electrode of diode V5, and the negative electrode of diode V8 is connected to the positive electrode of diode V7. Among them, NMOS transistors V9, V10, V11, and V12 constitute a full-bridge power amplifier circuit. Resistors R15, R16, R17, and R18 are the leakage resistors of the field-effect transistors. Diodes V5, V6, V7, and V8 constitute the protection circuit of the four field-effect transistors.

[0061] The on / off of the full-bridge power amplifier is controlled by the RL, RH, LL, and LH signals output by the driving chip IR2110. Among them, the RH and LH signals have the same form, and the RL and LL signals have the same form. When RH and LH are high and RL and LL are low, NMOS transistors V9 and V12 are turned on, and NMOS transistors V10 and V11 are turned off. The current flows from the positive electrode of the transducer to the negative electrode, forming the positive half-cycle of emission. When RL and LL are high and RH and LH are low, NMOS transistors V9 and V12 are turned off, and NMOS transistors V10 and V11 are turned on. The current flows from the negative electrode of the transducer to the positive electrode, forming the negative half-cycle of emission.

[0062] The impedance matching circuit is as Figure 8 As shown, it includes inductor L1, resistors R33 to R34, capacitor C21, diodes V5 to V6, and transducer Y1. The first end of resistor R34 is connected to the first end of inductor L1. The second end of resistor R34 is simultaneously connected to the first end of resistor R33, the positive electrode of diode V5, and the negative electrode of diode V6. The second end of resistor R33, the negative electrode of diode V5, and the positive electrode of diode V6 are connected together. One end of capacitor C21 is connected to the second end of inductor L1, and the other end is connected to the first end of transducer Y1. The second end of transducer Y1 is connected to the second end of inductor L1. Among them, inductor L1 and capacitor C21 constitute the impedance matching circuit. Resistors R33, R34, and diodes V5, V6 constitute the emission indication circuit. During normal emission, it can be seen that the two LED lights of diodes V5 and V6 flash. The higher the emission peak value, the brighter the indicator light.

[0063] The functions of the impedance matching circuit are as follows: First, tuning and matching, that is, adjusting the impedance of the transducer through the impedance matching circuit to make the transmitting load as close to the pure resistance state as possible and reduce the reactive component; Second, impedance matching, that is, changing the impedance of the transducer circuit to achieve impedance matching with the power supply to ensure that the transducer obtains the maximum electric power. At the same time, the series-parallel matching circuit can also prevent the instrument from being damaged due to the short circuit of the transducer.

[0064] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention according to the above disclosure are within the scope of protection of the claims.

Claims

1. A multi-beam phased transmitting circuit with amplitude weighting, characterized in that It includes a signal source and several power amplifier circuits. The signal source transmits a positive low-voltage driving signal and a negative low-voltage driving signal to each power amplifier circuit respectively; the time intervals between adjacent positive low-voltage driving signals and between adjacent negative low-voltage driving signals are the delay times between two power amplifier circuits obtained according to the phase control angles; The power amplifier circuit includes an optocoupler isolation circuit, a gate circuit, a drive circuit, a full-bridge power amplifier, an impedance matching circuit, and a first transducer element connected in sequence. The optocoupler isolation circuit plays a role in signal isolation. The gate circuit raises the level of the phase control signal of the external circuit. The drive circuit is used to drive the full-bridge power amplifier. The impedance matching circuit performs tuning matching and impedance matching. The optocoupler isolation circuit includes a dual-channel optocoupler chip HCPL2630, resistors R1 to R4, and capacitors C1 to C2. The first Anode terminal of the dual-channel optocoupler chip HCPL2630 is connected to the signal source signal A+. The first Cathode terminal is grounded through resistor R1. The second Cathode terminal is connected to the signal source signal A-. The second Anode terminal is grounded through resistor R2. The VCC terminal is connected to the first ends of resistors R3 and R4. The first output terminal is connected to the external signal GA1+ through the second end of resistor R3. The second output terminal is connected to the external signal GA1-. The GND terminal is grounded. The second end of resistor R3 is grounded through capacitor C1. The second end of resistor R4 is grounded through capacitor C2. The gate circuit includes NOT gates N4_1D and N4_1E, AND gates N1_1C and N1_1D, resistors R6 and R7, and capacitors C6 and C7. The input terminals of NOT gates N4_1D and N4_1E are respectively connected to the external signals GA1+ and GA1-. The two output terminals are respectively connected to one input terminal of AND gates N1_1C and N1_1D. The other input terminals of AND gates N1_1C and N1_1D are respectively connected to the external signals GA1- and GA1+. The two output terminals respectively output drive signals HIN1 and LIN1. One end of resistor R6 is connected to the output terminal of AND gate N1_1C, and the other end is grounded. One end of resistor R7 is connected to the output terminal of AND gate N1_1D, and the other end is grounded. Capacitors C6 and C7 are respectively in parallel with resistors R6 and R7.

2. The multi-beam phased transmission circuit with amplitude weighting according to claim 1, wherein The resistors R3 and R4 are pull-up circuits, and the capacitors C1 and C2 achieve filtering.

3. The multi-beam phased transmitting circuit with amplitude weighting according to claim 1, characterized in that, The resistors R6 and R7 are respectively pull-down resistors, and the capacitors C6 and C7 play a filtering role.

4. The multi-beam phased transmission circuit with amplitude weighting according to claim 1, characterized in that The drive circuit includes a drive chip IR2110, resistors R9 to R11, capacitors C3 to C5, and diodes V1 to V2. One ends of capacitors C3 and C4 are grounded, and the other ends are connected to a 15V voltage. The positive electrode of diode V1 is connected to the 15V voltage, and the negative electrode is connected to the VB terminal of drive chip IR2110 and one end of capacitor C5. The other end of capacitor C5 is connected to the negative electrode of diode V2. The positive electrode of diode V2 is connected to the VSS terminal of drive chip IR2110. The LO terminal of drive chip IR2110 is connected to resistor R9, the VS terminal is connected to resistor R10, and the HO terminal is connected to resistor R11.

5. The multi-beam phased emission circuit with amplitude weighting according to claim 1, characterized in that The full-bridge power amplifier includes diodes V5 to V8, resistors R15 to R18, and NMOS transistors V9 to V12. The drain terminal of NMOS transistor V9, the drain terminal of NMOS transistor V11, the negative electrode of diode V5, and the negative electrode of diode V7 are connected; the drain terminal of NMOS transistor V10, the drain terminal of NMOS transistor V12, the positive electrode of diode V6, and the positive electrode of diode V8 are connected; the source terminal of NMOS transistor V9 is connected to the source terminal of NMOS transistor V10, and the source terminal of NMOS transistor V11 is connected to the source terminal of NMOS transistor V12; Both ends of resistor R15 are respectively connected to the gate terminal and the source terminal of NMOS transistor V9, both ends of resistor R17 are respectively connected to the gate terminal and the source terminal of NMOS transistor V11, both ends of resistor R16 are respectively connected to the gate terminal and the drain terminal of NMOS transistor V10, and both ends of resistor R18 are respectively connected to the gate terminal and the drain terminal of NMOS transistor V12; The negative electrode of diode V6 is connected to the positive electrode of diode V5, and the negative electrode of diode V8 is connected to the positive electrode of diode V7.

6. The multi-beam phased emission circuit with amplitude weighting according to claim 5, characterized in that The NMOS transistors V9, V10, V11, and V12 form a full-bridge power amplifier. The resistors R15, R16, R17, and R18 are the leakage resistors of the field-effect transistors. The diodes V5, V6, V7, and V8 form a protection circuit for the four field-effect transistors.

7. The multi-beam phased emission circuit with amplitude weighting according to claim 1, characterized in that, The impedance matching circuit includes inductor L1, resistors R33 to R34, capacitor C21, diodes V5 to V6, and transducer Y1; The first end of resistor R34 is connected to the first end of inductor L1. The second end of resistor R34 is simultaneously connected to the first end of resistor R33, the positive electrode of diode V5, and the negative electrode of diode V6. The second end of resistor R33, the negative electrode of diode V5, and the positive electrode of diode V6 are connected; One end of capacitor C21 is connected to the second end of inductor L1, the other end is connected to the first end of transducer Y1, and the second end of transducer Y1 is connected to the second end of inductor L1.

8. The multi-beam phased transmitting circuit with amplitude weighting according to claim 7, characterized in that, The inductor L1 and the capacitor C21 form an impedance matching circuit. The resistors R33, R34, diodes V5, and V6 form a transmission indication circuit. During normal transmission, the two LED lights of diodes V5 and V6 flash. The higher the transmission peak-to-peak value, the brighter the indicator lights.

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