Thin film transistor, manufacturing method thereof, array substrate and display device

Abstract

The application provides a thin film transistor and a preparation method thereof, an array substrate and a display device, and belongs to the technical field of display, and can solve the problems that the existing conductor treatment can cause the active layer to lose the semiconductor performance or the TFT channel length to be unevenly distributed on the substrate. The preparation method of the thin film transistor comprises the step of forming a via hole on one side of the conductor region adjacent to the semiconductor region, the via hole can prevent the conductor region from diffusing to the semiconductor region, and the middle part of the active layer can be prevented from being diffused to form a conductor.

Description

[0001] This application is a divisional application of application No. 201910024065.2, filed on January 10, 2019, entitled "Thin Film Transistor and Preparation Method Thereof, Array Substrate and Display Device".

[0002] 10, the title of which is "Thin Film Transistor and Preparation Method Thereof, Array Substrate and Display Device". TECHNICAL FIELD

[0003] The present application belongs to the technical field of display, and particularly relates to a thin film transistor and a preparation method thereof, an array substrate and a display device. BACKGROUND

[0004] With the continuous increase in the size of display, amorphous silicon thin film transistors have problems of insufficient electron mobility and poor uniformity. In order to solve the above problems, oxide semiconductor materials such as IGZO, ITZO and IZO are used to replace amorphous silicon as an active layer.

[0005] In the preparation of a thin film transistor (TFT), in order to ensure that the source and drain (S / D) in the TFT have good contact with IGZO, reduce the S / D overlap impedance and improve the performance of the TFT, the edge of the active layer where the source and drain contact is subjected to conductorization treatment.

[0006] The inventors have found that the existing conductorization treatment of the edge of the active layer cannot avoid the problem of conductorization diffusion, which will cause the middle part of the active layer to be diffused to form a conductor, losing the semiconductor performance or causing poor uniformity of the TFT channel length on the substrate. SUMMARY

[0007] The present application provides a thin film transistor and a preparation method thereof, an array substrate and a display device to solve the problems that the existing conductorization treatment causes the active layer to lose the semiconductor performance or the TFT channel length to have poor uniformity on the substrate.

[0008] The technical solution adopted by the present application to solve the technical problem is as follows:

[0009] A preparation method of a thin film transistor, comprising the steps of forming an oxide active layer and a source and a drain on a substrate, wherein the oxide active layer comprises a conductorization region and a semiconductor region connected to each other, and the source and the drain are electrically connected to the conductorization region.

[0010] The method further comprises the step of forming a via hole on the side of the conductorization region adjacent to the semiconductor region.

[0011] Optionally, the formation of the oxide active layer specifically comprises the following steps:

[0012] forming a pattern of oxide semiconductor material on a substrate, the pattern of oxide semiconductor material comprising a conductorized region and a semiconductor region connected to the conductorized region, and a via located on a side of the conductorized region adjacent to the semiconductor region;

[0013] conducterizing the oxide semiconductor material of the conductorized region to form an oxide active layer.

[0014] Optionally, the conducterizing the conductorized region comprises hydrogenating or deoxidizing the oxide semiconductor material of the conductorized region using ion bombardment.

[0015] Optionally, the forming the oxide active layer, and the source and drain electrodes specifically comprises the following steps:

[0016] forming the oxide active layer over the substrate;

[0017] forming a gate insulating layer on the substrate after the above steps are completed;

[0018] forming a gate electrode on the substrate after the above steps are completed;

[0019] forming an interlayer insulating layer on the substrate after the above steps are completed;

[0020] forming the source and drain electrodes on the substrate after the above steps are completed.

[0021] Optionally, the via comprises a sidewall, wherein a sidewall distal from the semiconductor region is a first sidewall; the source and drain electrodes cover at least part of the first sidewall.

[0022] The present application also provides a thin film transistor comprising a substrate, an oxide active layer disposed over the substrate, and source and drain electrodes, the oxide active layer comprising a conductorized region and a semiconductor region connected to the conductorized region, the source and drain electrodes being electrically connected to the conductorized region; wherein the conductorized region is provided with a via on a side proximal to the semiconductor region.

[0023] Optionally, the conductorized region is formed by hydrogenating or deoxidizing the same oxide semiconductor material as the semiconductor region.

[0024] Optionally, the conductorized region forms a side surface at the via, wherein a side surface distal from the semiconductor region is a first side surface; the source and drain electrodes cover at least part of the first side surface.

[0025] Optionally, the thin film transistor is of a top gate type.

[0026] The present application also provides an array substrate comprising the above thin film transistor.

[0027] The present invention also provides a display device comprising the array substrate described above. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the thin-film transistor structure according to Embodiment 1 of the present invention;

[0029] Figure 2 This is a schematic flowchart of the thin-film transistor according to Embodiment 2 of the present invention;

[0030] Figure 3 This is a schematic diagram of the active layer formation of a thin-film transistor according to Embodiment 2 of the present invention;

[0031] Figure 4 This is a schematic diagram showing the formation of the source and drain of the thin-film transistor in Embodiment 2 of the present invention;

[0032] Figure 5 This is a schematic diagram of a thin-film transistor according to Embodiment 3 of the present invention;

[0033] Figure 6 This is a schematic diagram of another structure of the thin-film transistor according to Embodiment 3 of the present invention;

[0034] The reference numerals in the figures are as follows: 1. Substrate; 11. Protective layer; 12. Buffer layer; 2. Oxide active layer; 21. Conductive region; 22. Semiconductor region; 23. Via; 3. Source and drain; 4. Gate insulating layer; 5. Gate electrode; 6. Interlayer insulating layer; 7. Photoresist. Detailed Implementation

[0035] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] Example 1:

[0037] This embodiment provides a method for fabricating a thin-film transistor, such as... Figure 1 As shown, the method includes the steps of forming an oxide active layer 2 on a substrate 1, as well as a source, a drain, and a gate insulating layer, wherein the oxide active layer 2 includes a connected conductive region 21 and a semiconductor region 22, and the source and drain are electrically connected to a first conductive region 211 of the conductive region 21; the method further includes the step of forming a via between the first conductive region 211 and the second conductive region 212 of the conductive region 21, that is, the step of forming a via 23 on the side of the conductive region 21 adjacent to the semiconductor region 22; and the step of forming a gate insulating layer above the active layer 2, the gate insulating layer being used to provide a gate.

[0038] The preparation method of the thin film transistor of the embodiment includes the step of forming a via 23 on the side of the conductorized region 21 adjacent to the semiconductor region 22, which can prevent the conductorized region 21 from diffusing to the semiconductor region 22, can avoid the middle part of the active layer from being diffused to form a conductor, and is adjacent to the conductorized region 21 on both sides, thereby improving the uniformity of the via 23.

[0039] Embodiment 2

[0040] The embodiment provides a preparation method of a thin film transistor, as shown in the figure, including the following preparation steps: Figures 2-4

[0041] Optionally, S01, a patterned protective layer 11 is formed on a substrate 1, and a buffer layer 12 covering the protective layer 11; wherein the substrate 1 can be made of transparent materials such as glass and is pre-cleaned. The buffer layer 12 can be a single-layer structure or a laminated structure of multiple sub-layers, and the buffer layer 12 can be formed of silicon oxide or silicon nitride. Specifically, the buffer layer 12 can be formed by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, electron cyclotron resonance chemical vapor deposition or sputtering.

[0042] S02, forming an oxide active layer 2 on the substrate 1 after the above steps; wherein the oxide active layer 2 includes a conductorized region 21 and a semiconductor region 22 connected; specifically, S02 includes:

[0043] S02a, using a one-step patterning process, forming an oxide semiconductor material and a pattern including a via 23 on the substrate 1 after the above steps, the pattern of the oxide semiconductor material includes a conductorized region 21 and a semiconductor region 22 connected, the conductorized region 21 includes a first conductorized region 211 and a second conductorized region 212, and the via 23 is arranged between the first conductorized region 211 and the second conductorized region 212, and the via 23 is located on the side of the conductorized region 21 adjacent to the semiconductor region 22; specifically, as shown in the figure, a layer of photoresist 7 can be formed on the oxide semiconductor material, the photoresist 7 is exposed and developed, and then dry etching is performed to form a pattern including an active layer and a via 23. Figure 3

[0044] S02b, the oxide semiconductor material of the conductorized region 21 is subjected to a conductorization treatment to obtain an oxide active layer 2.

[0045] As an optional solution of the embodiment, the conductorization treatment of the conductorized region 21 includes hydrogenation or deoxidation of the oxide semiconductor material of the conductorized region 21 by ion bombardment.

[0046] ​​In this embodiment, the via 23 is formed first and then the conductorization is performed, which can avoid the diffusion of hydrogen atoms in the conductorization process to a greater extent. The via 23 can be formed by one-step mask of the active layer.

[0047] As a preferred scheme of this embodiment, the first conductorization region 211 is formed with a first sidewall close to the source and drain 3 and a second sidewall close to the second conductorization region 212, wherein the first sidewall and the second sidewall jointly form the via 23; and the source and drain 3 cover at least part of the first sidewall.

[0048] In this way, the overlap contact area of the source and drain with the side of the via 23 of the conductorization region 21 is increased, which is more conducive to the transmission of electrons.

[0049] S03, forming a gate insulating layer 4 on the substrate 1 after the above steps; specifically, the gate insulating layer 4 can be formed above the active layer by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, electron cyclotron resonance chemical vapor deposition or sputtering.

[0050] S04, forming a gate 5 on the substrate 1 after the above steps; the gate 5 can be formed by at least one of molybdenum, molybdenum-niobium alloy, aluminum, aluminum-neodymium alloy, titanium or copper. Specifically, the gate metal electrode film can be formed by sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition or electron cyclotron resonance chemical vapor deposition.

[0051] S05, forming an interlayer insulating layer 6 on the substrate 1 after the above steps; the interlayer insulating layer 6 can be formed by silicon oxide, silicon nitride, hafnium oxide or aluminum oxide.

[0052] S06, forming a source and drain 3 on the substrate 1 after the above steps, the source and drain 3 are electrically connected to the first conductorization region 211 of the conductorization region 21. The source and drain are formed by at least one of molybdenum, molybdenum-niobium alloy, aluminum, aluminum-neodymium alloy, titanium or copper. As shown in the figure, a layer of photoresist 7 can be formed on the above conductive material layer, the photoresist 7 is exposed and developed, and then etched to form a pattern including the source and drain 3. Figure 4

[0053] ​The method for fabricating a thin-film transistor in this embodiment includes forming a via 23 on one side of the conductive region adjacent to the semiconductor region 22 before conductor formation. This via 23 prevents the conductive region 21 from diffusing into the semiconductor region 22, effectively avoiding the formation of a conductor in the middle of the active layer. Furthermore, both sides of the via 23 are adjacent to the conductive region 21, improving the uniformity of the via fabrication. During subsequent SD bonding, the source and drain 3 cover at least a portion of the first sidewall of the via 23, effectively increasing the contact area and reducing bonding impedance, thus improving conductivity. The TFT fabricated using this method exhibits good uniformity.

[0054] The accompanying drawings for this embodiment show, for illustrative purposes only, the size and thickness of each structural layer. In the manufacturing process, the projected area of ​​each structural layer on the substrate 1 can be the same or different, and the required projected area of ​​each structural layer can be achieved through etching. At the same time, the structure shown in the drawings is not limited to the geometry of each structural layer. For example, it can be a rectangle as shown in the drawings, or it can be a trapezoid, or other shapes formed by etching, which can also be achieved through etching.

[0055] Example 3:

[0056] This embodiment provides a thin-film transistor, such as Figure 5 As shown, it includes a substrate 1, an active oxide layer 2 disposed above the substrate 1, and a source, a drain 3, and a gate insulating layer 4. The active oxide layer 2 includes a conductive region 21 and a semiconductor region 22 connected together. The conductive region 21 includes a first conductive region 211 and a second conductive region 212. The source and drain 3 are electrically connected to the first conductive region 211 of the conductive region 21. A via 23 is provided between the first conductive region 211 and the second conductive region 212, that is, a via 23 is provided on the side of the conductive region 21 closer to the semiconductor region 22. A gate insulating layer 4 is formed above the active layer 2, and the gate insulating layer 4 is used to house the gate 5.

[0057] In this embodiment, a via 23 is provided on one side of the conductive region 21 adjacent to the semiconductor region 22. Since the second conductive region 212 is located close to the semiconductor region 22, the via 23 is positioned between the first conductive region 211 and the second conductive region 212. This via 23 prevents the conductive region 21 from diffusing into the semiconductor region 22, thus avoiding the formation of a conductor in the middle of the active layer. Furthermore, the via 23 is adjacent to the conductive region 21 on both sides, improving the uniformity of the via fabrication. Additionally, since the width of the first conductive region 211 is not equal to the width of the second conductive region 212, the width of the first conductive region 211 can optionally be greater than the width of the second conductive region 212. This further reduces the impact of the second conductive region 212 on the middle of the active layer.

[0058] As an optional embodiment, the conductor region 21 is formed by hydrogenating or deoxidizing the same oxide semiconductor material as the semiconductor region 22.

[0059] This embodiment provides a hydrogenation or deoxidation method for conductor formation. Similar vias 23 can be set using other conductor formation methods. It should be noted that forming vias 23 before conductor formation can largely avoid the diffusion of hydrogen atoms during the conductor formation process. In addition, vias 23 can also be formed in one step with the active layer mask.

[0060] In one embodiment, the thin-film transistor is a top-gate type. A gate insulating layer 4 is disposed above the oxide active layer 2, and a gate 5 is disposed above the gate insulating layer 4.

[0061] In one embodiment, such as Figure 5 and Figure 6 As shown, the gate insulating layer 4 includes an edge portion 41 that is not covered by the gate 5. Specifically, since the gate 5 is located on top of the gate insulating layer 4, and neither side of the gate 5 completely covers the gate insulating layer 4, the edge portion 41 is formed on both sides of the gate insulating layer 4. The edge portion 41 can reduce the influence of the second conductive region 212 on the middle of the active layer 2, and can also prevent the gate 5 from overlapping with the second conductive region 212.

[0062] In one embodiment, the edge portion 41 includes a flat portion that contacts the gate 5 and a sloped surface away from the gate 5. Specifically, the top of the gate insulating layer 4 is a flat structure for contacting the gate 5, while both sides of the gate insulating layer 4 are sloped structures, that is, the edge portion 41 includes a flat portion that contacts the gate 5 and a sloped surface away from the gate 5, making the process of this application simple and easy to implement.

[0063] In one embodiment, the thin-film transistor further includes a first insulating layer that fills the via 23. The first insulating layer includes a third side surface at the location of the via 23, the third side surface extending into the via 23 to fill the via 23. The first insulating layer may be an interlayer insulating layer 6 disposed above the gate 5. Because the first insulating layer partially fills the via 23, leakage current can be effectively reduced.

[0064] In one embodiment, the first insulating layer covers at least a portion of the edge 41, the first conductive region 211, or the second conductive region 212. Specifically, the first insulating layer has through-holes to expose the first conductive region 211 for drain 3 connection, meaning the first insulating layer covers at least a portion of the edge 41 or the first conductive region 211; or the first insulating layer has through-holes to expose the second conductive region 212 for drain 3 connection, meaning the first insulating layer covers at least a portion of the edge 41 or the second conductive region 212. Since the first insulating layer (interlayer insulating layer 6) partially fills the through-holes 23, leakage current can be effectively reduced.

[0065] This embodiment uses a top-gate thin-film transistor as an example for specific explanation. Other bottom-gate thin-film transistors can also adopt a similar scheme, which will not be described in detail here.

[0066] In one embodiment, such as Figure 6 As shown, the semiconductorized region 21 forms a side surface at the via 23, wherein the side surface away from the semiconductorized region 21 is a first side surface; the source and drain 3 cover at least a portion of the first side surface. That is, Figure 6 The scheme shown is equivalent to increasing the overlap contact area between the source / drain electrodes and the side of the via 23 of the conductor region 21, which is more conducive to electron transmission.

[0067] In one embodiment, such as Figure 6 As shown, the gate 5 does not overlap with the first conductive region 211. The gate 5 does not overlap with the second conductive region 212. Since the gate 5 is disposed above the gate insulating layer 4, and a first insulating layer is also disposed on the gate 5, the first insulating layer partially fills the via 23, so that the gate 5 does not overlap with either the first conductive region 211 or the second conductive region 212, thereby significantly reducing parasitic capacitance.

[0068] In one embodiment, such as Figure 6 As shown, the gate 5 and the via 23 do not overlap. Since the gate 5 is covered by the first insulating layer, the gate 5 and the via 23 do not overlap, thereby improving the uniformity of the channel fabrication.

[0069] Example 4:

[0070] This embodiment provides an array substrate, including the thin-film transistors described above.

[0071] Example 5:

[0072] The embodiment provides a display device comprising the array substrate.

[0073] It can be understood that the above embodiments are only exemplary embodiments for illustrating the principles of the present application, and the present application is not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and essence of the present application, and these modifications and improvements are also considered as the protection scope of the present application.

Claims

1. A thin-film transistor, characterized in that, The thin-film transistor includes a substrate, an active layer, a source, a drain, a gate, and a gate insulating layer disposed above the substrate. The active layer includes a conductive region and a semiconductor region connected together. The conductive region includes a first conductive region connected to the source and drain and a second conductive region connected to the semiconductor region. A via is disposed between the first conductive region and the second conductive region. The thin-film transistor also includes a first insulating layer that fills the via and is in direct contact with the gate.

2. The thin-film transistor according to claim 1, characterized in that, The gate insulating layer includes an edge portion not covered by the gate.

3. The thin-film transistor according to claim 2, characterized in that, The edge portion includes a flat portion that contacts the gate and a sloped surface that is away from the gate.

4. The thin-film transistor according to claim 2, characterized in that, The first insulating layer covers at least a portion of the edge or a portion of the first conductive region or a portion of the second conductive region.

5. The thin-film transistor according to claim 1, characterized in that, The thin-film transistor is a top-gate type.

6. The thin-film transistor according to claim 1, characterized in that, The active layer material is an oxide semiconductor material.

7. An array substrate, characterized in that, Includes the thin-film transistor according to any one of claims 1-6.

8. A display device, characterized in that, Includes the array substrate as described in claim 7.

9. A display device as claimed in claim 8, characterized in that, The display device is an OLED panel.

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