Dcdc converter, method of dcdc conversion, and electronic device

Abstract

The application discloses a DCDC converter, a DCDC conversion method and an electronic device, which can provide a dynamically controlled load threshold and distinguish a load threshold when entering a light load mode and a load threshold when exiting the light load mode. The DCDC converter comprises an error amplification module, a pulse width modulation wave generation module and a cross cycle module. The cross cycle module is used to obtain an input voltage, an output voltage and a sampling voltage, and outputs a high cross cycle signal when the sampling voltage is greater than a second reference voltage, so as to turn off the pulse width modulation wave generation module, thereby reducing the frequency of the pulse width modulation wave output by the pulse width modulation wave generation module. The pulse width modulation wave generation module is used to output a forced duty cycle to raise the output voltage when the control signal is high, thereby raising the sampling voltage, and the raising amplitude is related to the input voltage and the output voltage, so that the sampled voltage is greater than the second reference voltage.

Description

Technical Field

[0001] This application relates to the field of DC-DC converters, specifically to a DC-DC converter, a DC-DC conversion method, and an electronic device. Background Technology

[0002] In recent years, with the rise of various battery-powered wearable devices and IoT devices, more demands have been placed on power chips, requiring them to have higher efficiency and longer battery life. For example, in wearable devices, sensor devices are used for relatively short periods, and the system is often under light load or even no load. Therefore, efficiency under extremely light loads is particularly important for these devices, as it directly affects the device's battery life.

[0003] DC-DC converters are commonly used as power supply devices in these types of electronic products. DC-DC converters have high conversion efficiency and are controlled using PWM (Pulse Width Modulation). PWM control offers advantages such as a fixed operating frequency, low output voltage ripple, good stability, and mature control methods. However, because the power transistors in the converter must be turned on and off in each switching cycle, the switching losses of the power transistors are relatively large, resulting in lower overall efficiency of the converter under light load or standby conditions.

[0004] In existing technologies, PFM (Frequency Control Module) and PSM (Period-Switching Modulation) control methods are commonly used to prevent the efficiency of DC-DC converters from decreasing when switching from heavy load to light load. The essence of both PFM and PSM control methods is to reduce the actual switching frequency, thereby improving efficiency under light load conditions.

[0005] In PSM control mode, the DC-DC converter enters PSM mode under light load. The criterion for entering PSM mode is that the low-time of the pulse width modulation wave of the control DC-DC product becomes longer. After entering PSM mode, the output PWM wave skips some clock cycles, thereby reducing the switching frequency and improving the operating efficiency under light load.

[0006] Current PSM control methods still have many problems to be solved. For example, after entering PSM mode, the load threshold does not change with external conditions, which makes it impossible to enter light load mode at some conversion ratios, and the load threshold for exiting light load mode varies greatly. At some conversion ratios, a very heavy load is required to exit light load mode, which affects efficiency.

[0007] For example, in a BOOST system, it is impossible to enter light load mode when the input voltage Vin is low, while it is easier to enter light load mode when the input voltage Vin is high. However, the light load current threshold required to exit light load mode is too high. In addition, the existing PSM control method does not precisely control the output voltage ripple. The output voltage ripple is small, the operating frequency in light load mode is not low enough, and the operating efficiency is low. Summary of the Invention

[0008] In view of this, this application provides a DC-DC converter, a DC-DC conversion method, and an electronic device, which can provide dynamically controlled load thresholds and distinguish between load thresholds when entering a light load mode and load thresholds when exiting a light load mode.

[0009] This application provides a DC-DC converter, including an error amplification module for acquiring a sampling voltage and a first reference voltage, and outputting an error amplification value based on the difference between the sampling voltage and the first reference voltage, wherein the sampling voltage is sampled from the output voltage of the DC-DC converter;

[0010] A pulse width modulation wave generation module is connected to the error amplification module and is used to output a pulse width modulation wave according to the error amplification value;

[0011] A cross-cycle module, connected to the pulse width modulation wave generation module, is used to acquire the pulse width modulation wave, input voltage, output voltage and sampling voltage, so as to output a high control signal when the low duration of the pulse width modulation wave is greater than a first preset duration, and output a high cross-cycle signal when the sampling voltage is greater than a second reference voltage.

[0012] The pulse width modulation wave generation module is used to output a forced duty cycle to raise the output voltage when the control signal is high, so that the sampled voltage is greater than the second reference voltage, and to turn off when the cross-cycle signal is high, thereby reducing the frequency of the pulse width modulation wave output by the pulse width modulation wave generation module.

[0013] Optionally, the cross-cycle module includes: a first comparison unit, configured to acquire and compare the sampled voltage and the second reference voltage, and generate a cross-cycle signal based on the comparison result; and a load threshold control unit, connected to the first comparison unit to acquire the cross-cycle signal, the load threshold control unit also being connected to the pulse width modulation wave generation module, and configured to acquire the input voltage to form the control signal based on the cross-cycle signal, the pulse width modulation wave and the input voltage.

[0014] Optionally, the load threshold control unit includes: a first subunit connected to the output of the first comparison unit, used to generate a first signal based on the cross-cycle signal output by the first comparison unit; a second subunit connected to the output of the first subunit to obtain the first signal, and connected to the output of the pulse width modulation wave generation module to obtain the pulse width modulation wave, wherein the second subunit generates a second signal based on the pulse width modulation wave, and generates the control signal based on the first signal and the second signal.

[0015] Optionally, the first sub-unit includes: a first switch for receiving the cross-cycle signal via a first inverter, wherein the first switch is closed when the cross-cycle signal is low and open when it is high; a second switch for receiving the cross-cycle signal and closing when the cross-cycle signal is high and opening when it is low; and a first charging / discharging circuit connected to the first and second switches and changing the first signal according to the opening and closing states of the first and second switches.

[0016] Optionally, the first charging and discharging circuit includes: a first current source, with its two ends connected to the first switch and the second switch respectively; a first capacitor, with its upper and lower plates connected to the first and second terminals of the second switch respectively, and the upper plate of the first capacitor connected to the first current source; a first hysteresis inverter, connected to the upper plate of the first capacitor to obtain the voltage of the upper plate of the first capacitor and output a hysteresis-inverted signal of the voltage of the upper plate of the first capacitor; and a first buffer, connected to the output terminal of the hysteresis inverter, which outputs a high first signal when the hysteresis-inverted signal is higher than a toggling threshold, and outputs a low first signal when the hysteresis-inverted signal is lower than the toggling threshold.

[0017] Optionally, the first current source includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, and a fifth PMOS transistor, wherein: the gate of the first PMOS transistor receives the input voltage of the DC-DC converter, and its source is grounded through a first switch and a first resistor connected in sequence; the source of the second PMOS transistor is connected to the drain of the first PMOS transistor, the drain is used to receive the output voltage, and its gate is connected to the drain of the first PMOS transistor and to the gates of the third PMOS transistor and the fourth PMOS transistor; the source of the third PMOS transistor is connected to the first terminal of the second switch, and its drain is used to receive the output voltage; the drain of the fourth PMOS transistor is used to receive the output voltage, and its source is connected to the drain of the fifth PMOS transistor; the source of the fifth PMOS transistor is connected to the upper plate of the first capacitor, and its gate is connected to the output terminal of the first hysteresis inverter; the second terminal of the second switch and the lower plate of the first capacitor are both grounded.

[0018] Optionally, the second subunit includes: a first delay unit, used to receive the pulse width modulation wave and delay the pulse width modulation wave for the first preset duration; a first OR gate, used to receive the output voltage of the first delay unit and to receive the pulse width modulation wave and perform a logical OR operation on the output voltage of the first delay unit and the pulse width modulation wave, thereby outputting the second signal; and a second charging and discharging circuit, connected to the output terminal of the first OR gate and connected to the output terminal of the first subunit, used to output the control signal according to the first signal and the second signal.

[0019] Optionally, the second charging and discharging circuit includes: a third switch and a fourth switch, used to receive the second signal and close when the second signal is high and open when the second signal is low; a fifth switch, one end of which is connected to the output terminal of the output module, and the other end is grounded through a second resistor and the third switch connected in sequence, and the fifth switch receives the first signal, closes when the first signal is high and opens when the first signal is low; a second current source, the first end of which is connected to the output terminal of the output module, and the second end of which is connected to the first end of the fourth switch through a controllable current source, and the current direction is from the first end to the second end; a controllable current source, the first end of which is connected to the second end of the second current source and the connection point of the second resistor and the fifth switch, the second end of which is grounded through the fourth switch, and the current direction of the controllable current source is from the first end to the second end, and the current magnitude is a multiple of the input voltage; a second capacitor, the upper plate of which is connected to the connection point of the second current source and the controllable current source, and the lower plate of which is grounded; and a second hysteresis inverter, the input end of which is connected to the upper plate of the second capacitor, and the output end of which is used to output the control signal.

[0020] Optionally, the pulse width modulation wave generation module includes: a selection unit, used to receive the error amplification value, the control signal, and a third reference voltage, and selectively output one of the error amplification value and the third reference voltage as a selection result according to the control signal; and a second comparison unit, connected to the output terminal of the selection unit, and receiving a sawtooth wave source, used to compare the selection result with the sawtooth wave provided by the sawtooth wave source to form the pulse width modulation wave.

[0021] Optionally, the selection unit is configured to output the third reference voltage when the control signal is high, and to output the error amplification value when the control signal is low.

[0022] Optionally, the aforementioned DC-DC converter further includes an output module, comprising: a logic circuit including a second OR gate, a first AND gate, a second buffer, and a third buffer, wherein the first input terminal of the second OR gate is connected to the output terminal of the pulse width modulation wave generation module to receive the pulse width modulation wave, the second input terminal is used to connect to the output terminal of the third buffer, and the output terminal is connected to the input terminal of the second buffer; the first input terminal of the first AND gate is used to connect to the output terminal of the second buffer, the second input terminal is connected to the output terminal of the pulse width modulation wave generation module to receive the pulse width modulation wave, and the output terminal is connected to the input terminal of the third buffer; and a power stage circuit connected to the output terminal of the logic circuit for acquiring the input voltage and outputting the output voltage according to the signal output by the logic circuit and the input voltage.

[0023] Optionally, the power stage circuit includes: a PMOS power transistor, with its gate connected to the output terminal of the second buffer, its source connected to the input voltage via an inductor, and its drain used to output the output voltage; and an NMOS power transistor, with its gate connected to the output terminal of the third buffer, its source grounded, and connected to the drain of the PMOS power transistor via a third capacitor, and the drain of the NMOS power transistor connected to the source of the PMOS power transistor.

[0024] This application provides a DC-DC conversion method, comprising the following steps: providing a pulse width modulation wave to regulate the output voltage; raising the output voltage when the low duration of the pulse width modulation wave is greater than a first preset duration; and lowering the frequency of the pulse width modulation wave according to the raised output voltage.

[0025] Optionally, providing the pulse width modulated wave includes the following steps: comparing a sampled voltage with a first reference voltage, and outputting an error amplification value between the sampled voltage and the first reference voltage, wherein the sampled voltage is sampled from the output voltage; comparing the error amplification value with a sawtooth wave, and outputting the pulse width modulated wave according to the comparison result.

[0026] Optionally, raising the output voltage includes the following steps: when the low duration of the pulse width modulation wave is greater than a first preset duration, providing a third reference voltage, the third reference voltage being higher than the valley value of the sawtooth wave and lower than the peak value of the sawtooth wave; comparing the third reference voltage with the sawtooth wave, outputting a forced duty cycle, and raising the output voltage according to the forced duty cycle.

[0027] Optionally, when reducing the frequency of the pulse width modulation wave based on the increased output voltage, the method includes the following steps: providing a second reference voltage; comparing the sampled voltage of the output voltage with the second reference voltage, and outputting a high-level cross-cycle signal when the sampled voltage is greater than the second reference voltage; stopping the output of the pulse width modulation wave based on the high-level cross-cycle signal, thereby reducing the frequency of the pulse width modulation wave.

[0028] This application provides an electronic device that includes any of the aforementioned DC-DC converters.

[0029] The DC-DC converter, DC-DC conversion method, and electronic device in this application have dynamic load threshold control for entering and exiting light load mode. The thresholds for entering and exiting light load mode are designed separately and dynamically controlled. Through cross-cycle operation, the output voltage ripple is precisely controlled, the operating frequency is reduced, and most of the working modules in the non-switching state are shut down, thereby achieving extremely high light load mode operating efficiency.

[0030] The DC-DC converter, DC-DC conversion method, and electronic device in this application, through the control of the load threshold control unit, replenish the output voltage with energy when the load becomes lighter, and the energy replenished in a single operation is related to the input voltage. This ensures that the DC-DC converter can enter the light-load cross-cycle mode regardless of whether the input voltage is large or small, thereby improving efficiency. Furthermore, the DC-DC converter, DC-DC conversion method, and electronic device in this application can further reduce power consumption and improve efficiency under light load by shutting down the operating module under light load conditions where the system has no duty cycle output.

[0031] Furthermore, when the system enters the light load cross-cycle mode, by designing the threshold for exiting the light load mode to be related to the input voltage and output voltage, the relationship between the light load current threshold and the input voltage and output voltage can be reduced, thereby reducing the influence of external input voltage and output voltage on the light load exit threshold, and the change in the light load exit current threshold is smaller. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of the structure of the DC-DC converter described in one embodiment of this application;

[0034] Figure 2This is a schematic diagram of the load threshold control unit described in one embodiment of this application;

[0035] Figure 3 This is an implementation circuit diagram of the load threshold control unit described in one embodiment of this application;

[0036] Figure 4 This is a schematic diagram of the circuit structure of the DC-DC converter described in one embodiment of this application;

[0037] Figure 5 This is a schematic diagram of the working waveforms of each signal in the DC-DC converter described in one embodiment of this application;

[0038] Figure 6 This is a schematic diagram of the working waveforms of each signal in the DC-DC converter described in one embodiment of this application;

[0039] Figure 7 This is a flowchart illustrating the steps of a DC-DC conversion method in one embodiment of this application. Detailed Implementation

[0040] The DC-DC converter and the method of DC-DC conversion in this application will be further described below with reference to the accompanying drawings and embodiments.

[0041] Please see Figure 1 This is a schematic diagram of the structure of the DC-DC converter described in one embodiment of this application.

[0042] In this embodiment, the DC-DC converter includes an error amplification module 103, a cross-cycle module 102, and a pulse width modulation wave generation module 101; in some examples, the DC-DC converter may also include an output module 104.

[0043] The error amplification module 103 has two input terminals, used to acquire the sampling voltage VFB and the first reference voltage VREF1, respectively, and to amplify the error between the sampling voltage VFB and the first reference voltage VREF1 to output an error amplification value COMP. The sampling voltage VFB is sampled from the output voltage VOUT of the DC-DC converter. When the sampling voltage VFB is lower than the first reference voltage VREF1, the error amplification value COMP increases, and when the sampling voltage VFB is higher than the first reference voltage VREF1, the error amplification value COMP decreases, thereby realizing voltage regulation of the loop.

[0044] The sampling voltage VFB is obtained by setting a sampling unit. The sampling unit can be two resistors connected to each other, with the upper end of one resistor used to obtain the output voltage VOUT, the lower end of the other resistor used to ground, and the connection point of the two resistors used to output the sampling voltage VFB.

[0045] The cross-cycle module 102 is connected to the pulse width modulation wave generation module 101 and is used to acquire the pulse width modulation wave PWM, so as to output a high control signal CTRL when the low duration of the pulse width modulation wave PWM is greater than a first preset duration.

[0046] The cross-cycle module 102 is also used to acquire the input voltage Vin, the output voltage VOUT, and the sampling voltage VFB, and output a high cross-cycle signal PSM when the sampling voltage VFB is greater than the second reference voltage VREF2, so as to turn off the pulse width modulation wave generation module 101, thereby reducing the frequency of the pulse width modulation wave PWM output by the pulse width modulation wave generation module 101.

[0047] The pulse width modulation (PWM) wave generation module 101 is connected to the error amplification module 103 and is used to output a PWM wave according to the error amplification value COMP. When the control signal CTRL is high, the PWM wave generation module 101 is used to output a forced duty cycle to raise the output voltage VOUT, thereby raising the sampled voltage VFB. The raising amplitude is related to the input voltage Vin and the output voltage VOUT, so that the sampled voltage VFB is greater than the second reference voltage VREF2.

[0048] Since the control signal CTRL is determined by the output voltage VOUT, the input voltage Vin, and the cross-cycle signal PSM, the control signal CTRL changes accordingly when the output voltage VOUT and the input voltage Vin change, thus enabling dynamic control of the control signal CTRL.

[0049] The cross-cycle module 102 acquires the low-time duration of the pulse width modulation (PWM) wave. When the low-time duration is greater than or equal to a first preset duration, it generates a high-time control signal CTRL. This high-time control signal CTRL has a certain delay characteristic, capable of delaying for a second preset duration THOLD. Furthermore, the control signal CTRL enables the PWM wave generation module 101 to output a forced duty cycle, which raises the output voltage VOUT. The sampling voltage VFB increases accordingly, and the increase magnitude is related to the magnitude of the input voltage Vin and the initial value of the output voltage VOUT. When the sampling voltage VFB is higher than the second reference voltage VREF2, the cross-cycle signal PSM output by the first comparison unit 1021 is set high.

[0050] After the high-level cross-cycle signal PSM is provided, the DC-DC converter stops outputting the duty cycle, and the output voltage VOUT stops being pulled high. After the high-level signal stops, since a light load is connected to the output module 104, the output voltage VOUT gradually decreases, and the sampling voltage VFB decreases accordingly. When the sampling voltage VFB is less than or equal to the second reference voltage VREF2, the cross-cycle signal PSM changes from high level to low level, and the pulse width modulation wave generation module 101 resumes generating the duty cycle.

[0051] The control signal CTRL is continuously held high for a third preset duration TSET, which is related to the input voltage Vin. Furthermore, in this embodiment, the third preset duration TSET is sufficiently long, so that the control signal CTRL remains high even after the cross-cycle signal PSM changes from high to low. At this time, the pulse width modulation (PWM) generation module 101 outputs a PWM wave with a forced duty cycle again, the output voltage VOUT is raised again, and the sampling voltage VFB increases accordingly. When the sampling voltage VFB is greater than the second reference voltage VREF2, the cross-cycle signal PSM changes from low to high, the DC-DC converter stops outputting the duty cycle signal, and the output voltage VOUT stops increasing.

[0052] When the DC-DC converter is lightly loaded, the generation of the pulse width modulation (PWM) wave in the DC-DC converter, as described above, oscillates between stopping operation and forced duty cycle.

[0053] When the DC-DC converter switches from light load to heavy load, the output voltage VOUT has already been consumed too much by the heavy load before the cross-cycle signal PSM turns from low to high. Therefore, when the cross-cycle signal PSM is low, the energy provided by the forced duty cycle with a high duration of TSET is insufficient to increase the output voltage VOUT to the point that its sampling voltage VFB is greater than the second reference voltage VREF2. At this time, the cross-cycle signal PSM remains low. After the control signal CTRL is delayed for a third preset duration TSET, the control signal CTRL is also low, and the DC-DC converter jumps out of the cross-cycle mode.

[0054] In this embodiment, the DC-DC converter, under the control of the load threshold control unit 1022, replenishes the output voltage VOUT with energy when the load becomes lighter. The energy replenished in a single operation is related to the input voltage Vin. This ensures that the DC-DC converter can enter the light-load cross-cycle mode regardless of whether the input voltage Vin is large or small, thereby improving efficiency. Furthermore, the DC-DC converter, DC-DC conversion method, and electronic device in this application can further reduce power consumption and improve efficiency under light load by shutting down the working module under light load conditions where the system has no duty cycle output.

[0055] Please see Figure 2 This is a schematic diagram of the load threshold control unit described in one embodiment of this application.

[0056] In this embodiment, the cross-cycle module 102 includes a first comparison unit 1021 and a load threshold control unit 1022. The first comparison unit 1021 is used to acquire and compare the sampled voltage VFB and the second reference voltage VREF2, and generate a cross-cycle signal PSM based on the comparison result. The load threshold control unit 1022 is connected to the first comparison unit 1021 to acquire the cross-cycle signal PSM, and is used to receive the input voltage Vin and output voltage VOUT of the DC-DC converter, and form the control signal CTRL based on the cross-cycle signal PSM, the input voltage Vin, and the output voltage VOUT.

[0057] When the sampled voltage VFB is greater than or equal to the second reference voltage VREF2, the first comparison unit 1021 outputs a high cross-cycle signal PSM, indicating that the duty cycle control system has stopped working; when the sampled voltage VFB is less than the second reference voltage VREF2, it outputs a low cross-cycle signal PSM, indicating that the duty cycle control system has resumed working. By setting the first comparison unit 1021, precise control of the output voltage VOUT ripple can be achieved when the DC-DC converter is in a light load state.

[0058] In practice, because the output voltage VOUT of the DC-DC converter exhibits a hysteresis voltage VHYS under light load conditions, the impact of this hysteresis voltage VHYS needs to be considered in practical applications. Therefore, a low-level cross-cycle signal PSM is only output when the sampling voltage VFB is less than or equal to the difference between the second reference voltage VREF2 and the hysteresis voltage VHYS. Setting a higher VHYS voltage can minimize the operating frequency under light load mode, reducing losses and improving efficiency in light load mode.

[0059] The load threshold control unit 1022 is connected to the first comparison unit 1021 to obtain the cross-cycle signal PSM. The load threshold control unit 1022 is also connected to the pulse width modulation wave generation module 101 and is used to obtain the input voltage Vin in order to form the control signal CTRL based on the cross-cycle signal PSM, the pulse width modulation wave PWM and the input voltage Vin.

[0060] exist Figure 2 In the illustrated embodiment, the load threshold control unit 1022 includes a first subunit 201 and a second subunit 202. The first subunit 201 is connected to the output of the first comparison unit 1021 and is used to generate a first signal CON1 based on the cross-cycle signal PSM output by the first comparison unit 1021. The second subunit 202 is connected to the output of the first subunit 201 to obtain the first signal CON1, and is connected to the output of the pulse width modulation wave generation module 101 to obtain the pulse width modulation wave PWM. The second subunit 202 generates a second signal CON2 based on the pulse width modulation wave PWM, and generates the control signal CTRL based on the first signal CON1 and the second signal CON2.

[0061] Please see Figure 3 This is an implementation circuit diagram of the load threshold control unit described in one embodiment.

[0062] The first subunit 201 includes a first switch K1, a second switch K2, and a first charging / discharging circuit 301. The first switch K1 acquires the cross-cycle signal PSM through an inverter, and the second switch K2 directly acquires the cross-cycle signal PSM. The first switch K1 closes when the cross-cycle signal PSM is low and opens when the cross-cycle signal PSM is high; the second switch K2 closes when the cross-cycle signal PSM is high and opens when it is low.

[0063] The first switch K1 and the second switch K2 are both connected to the first charging and discharging circuit 301. The on / off state of the first switch K1 and the second switch K2 can be used to control the charging and discharging state of the first charging and discharging circuit 301, thereby changing the high and low level of the first signal CON1 output by the first charging and discharging circuit 301.

[0064] exist Figure 3 In the embodiment shown, the first charging and discharging circuit 301 includes: a first current source 302, with its two ends connected to the first switch K1 and the second switch K2 respectively; and a first capacitor C1, with its upper and lower plates connected to the first and second ends of the second switch K2 respectively, and the upper plate connected to the first current source 302.

[0065] The first current source 302 includes a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M3, a fourth PMOS transistor M4, and a fifth PMOS transistor M5. Specifically, the gates of the second PMOS transistor M2, the third PMOS transistor M3, and the fourth PMOS transistor M4 are interconnected and all connected to the source of the second PMOS transistor M2. The drains of all three are used to receive the output voltage VOUT. The source of the third PMOS transistor M3 is grounded through the second switch K2, and the source of the fourth PMOS transistor M4 is grounded through the drain of the fifth PMOS transistor M5 and the first capacitor C1.

[0066] The first charging / discharging circuit 301 further includes a first hysteresis inverter G1. The input terminal of the first hysteresis inverter G1 is connected to the connection point between the second switch K2 and the third PMOS transistor, and also connected to the upper plate of the first capacitor C1. The first hysteresis inverter G1 can output a hysteresis-inverted signal of the voltage obtained at its input terminal.

[0067] When the cross-cycle signal PSM is high, the first switch K1 is open, the second switch K2 is closed, the first capacitor C1 is discharged, the voltage V2 on the upper plate of the first capacitor C1 gradually decreases, and the signal output by the first hysteresis inverter G1 becomes high after the hysteresis time, that is, the first signal CON1 is high.

[0068] When the cross-cycle signal PSM is low, the first switch K1 is closed, the second switch K2 is open, the first current source 302 charges the first capacitor C1, the voltage V2 on the upper plate of the first capacitor gradually increases, and the signal output by the first hysteresis inverter G1 becomes low after the hysteresis time, that is, the first signal CON1 is low.

[0069] In this embodiment, the first charging and discharging circuit 301 further includes a first buffer X1 connected to the output terminal of the first hysteresis inverter G1. When the hysteresis inverted signal output by the first hysteresis inverter G1 is higher than a flip threshold, a first signal CON1 is output high. When the hysteresis inverted signal is lower than the flip threshold, the first signal CON1 is output low.

[0070] The second subunit 202 includes: a first delayer D1, used to receive the pulse width modulation wave PWM and delay the pulse width modulation wave PWM for the first preset duration; and a first OR gate OR1, used to receive the output voltage VOUT of the first delayer D1 and to receive the pulse width modulation wave PWM and perform a logical OR operation on the output voltage VOUT of the first delayer D1 and the pulse width modulation wave PWM, thereby outputting the second signal CON2.

[0071] The circuit consisting of the first delay D1 and the first OR gate OR1 can determine whether the second signal CON2 is high or low based on the low duration of the pulse width modulation (PWM) wave. Specifically, the second signal CON2 is output only when the low duration of the PWM wave lasts for a first preset duration; otherwise, the second signal CON2 is output as high.

[0072] The second subunit 202 further includes a second charging and discharging circuit 303, which is connected to the output terminal of the first OR gate OR1 and the output terminal of the first subunit 201, for outputting the control signal CTRL according to the first signal CON1 and the second signal CON2.

[0073] The second charging / discharging circuit 303 includes a third switch K3 and a fourth switch K4, the on / off states of which are determined by the second signal CON2. Specifically, when the second signal CON2 is high, both the third switch K3 and the fourth switch K4 are closed; when the second signal CON2 is low, both the third switch K3 and the fourth switch K4 are open.

[0074] The second charging / discharging circuit 303 also includes a fifth switch K5. One end of the fifth switch K5 is connected to the output terminal of the output module 104, and the other end is grounded through a second resistor R2 and the third switch K3 connected in sequence. The on / off state of the fifth switch K5 is determined by the first signal CON1; it is closed when the first signal CON1 is high and open when the first signal CON1 is low.

[0075] The second charging / discharging circuit 303 further includes a second current source IB2. The first terminal of the second current source IB2 is connected to the output terminal of the output module 104, and the second terminal is grounded through a controllable current source IB3 and the fourth switch K4 connected in sequence. The current direction of the second current source IB2 is from its first terminal to its second terminal. The current direction of the controllable current source IB3 is from its first terminal connected to the second current source IB2 to its second terminal connected to the fourth switch K4. The magnitude of the current is related to the input voltage Vin and is a multiple of the input voltage Vin.

[0076] The second charging and discharging circuit 303 also includes a second capacitor C2. The upper plate of the second capacitor C2 is connected to the connection point of the second current source IB2 and the controllable current source IB3, and the lower plate is grounded.

[0077] If the low duration of the pulse width modulation (PWM) wave reaches the first preset duration, it is considered that the current DC-DC converter has entered a light load state, the second signal CON2 is low, the third switch K3 and the fourth switch K4 are open, the second current source IB2 charges the second capacitor C2, and the charging current is the current provided by the second current source IB2.

[0078] Otherwise, the second signal CON2 is high, the third switch K3 and the fourth switch K4 are closed, the second capacitor C2 discharges, and the discharge current is the sum of V1 / R2 and the controllable current provided by the controllable current source IB3, where V1 is the voltage of the upper plate of the second capacitor C2 and R2 is the resistance of the second resistor R2.

[0079] When the load on the DC-DC converter becomes light, the third switch K3 and the fourth switch K4 are open for a relatively long time, the second capacitor C2 is continuously charged, and the voltage on the upper plate of the second capacitor C2 gradually increases. When it exceeds the flip threshold of the second hysteresis inverter G2, the output high control signal CTRL is output, which causes the pulse width modulation wave generation module 101 to generate a forced duty cycle signal and provide energy to the output voltage VOUT.

[0080] When the forced duty cycle of the pulse width modulation (PWM) wave causes the second signal CON2 to go high, the third switch K3 and the fourth switch K4 close again, allowing the second capacitor C2 to discharge with a preset current. The preset current is the sum of the ratio of the voltage V1 on the upper plate of the second capacitor to the second resistor R2 and the controllable current provided by the controllable current source IB3.

[0081] When the voltage V1 on the upper plate of the second capacitor C2 is less than the toggling threshold of the second hysteresis inverter G2, a low control signal CTRL is output. At this time, because the error amplification value COMP output by the error amplification module 103 is small, the pulse width modulation wave generation module 101 cannot generate a duty cycle signal normally.

[0082] In this embodiment, by selecting the first delay D1, different second preset durations THOLD are obtained, thereby changing the threshold for determining the low duration of the pulse width modulation (PWM) wave when entering the cross-cycle mode.

[0083] Please see Figure 4 This is a schematic diagram of the structure of the DC-DC converter in one embodiment.

[0084] In this embodiment, the pulse width modulation wave generation module 101 is used to receive the error amplification value COMP, the control signal CTRL and a third reference voltage VR to generate a pulse width modulation wave PWM.

[0085] The pulse width modulation wave generation module 101 includes a selection unit MUX21 with three input terminals, which are respectively used to acquire the error amplification value COMP, the control signal CTRL, and the third reference voltage VR, and selectively output one of the error amplification value COMP and the third reference voltage VR as the selection result according to the control signal CTRL.

[0086] The selection unit outputs the third reference voltage when the control signal CTRL is high, and outputs the error amplification value COMP when the control signal CTRL is low.

[0087] The pulse width modulation (PWM) wave generation module 101 further includes a second comparison unit COMP2. The second comparison unit COMP2 has two input terminals, one of which is connected to the output terminal of the selection unit MUX21, and the other input terminal is used to receive a sawtooth wave RAMP. The second comparison unit COMP2 is used to compare the signal output by the selection unit MUX21 with the sawtooth wave RAMP to form the PWM wave and adjust the output voltage VOUT.

[0088] Therefore, when the control signal CTRL is high, the pulse width modulation (PWM) generation module 101 compares the third reference voltage with the sawtooth wave RAMP to output a PWM. Since the third reference voltage is higher than the valley of the sawtooth wave RAMP but lower than its peak value, the output PWM at this time is a PWM with a forced duty cycle.

[0089] The third reference voltage VR is related to the duty cycle of the pulse width modulation (PWM) wave finally output by the pulse width modulation (PWM) wave generation module 101. If the selection unit outputs the third reference voltage VR, the larger the amplitude of the third reference voltage VR signal, the larger the duty cycle of the output PWM wave; the smaller the amplitude of the third reference voltage VR signal, the smaller the duty cycle of the output PWM wave.

[0090] In this embodiment, when the DC-DC converter enters a light load state, the sampling voltage VFB is small, the error amplification value COMP is small, and the pulse width modulation wave generation module 101 cannot generate a duty cycle before the control signal CTRL has turned high.

[0091] If, after the first preset time period, the pulse width modulation (PWM) waveform output by the DC-DC converter remains low, then Figure 3When the third switch K3 and the fourth switch K4 are disconnected, the second current source IB2 charges the second capacitor, raising the control signal CTRL. This causes the control signal CTRL to be set high, allowing the second comparison unit to compare the third reference voltage VR and the sawtooth wave RAMP, thereby obtaining the forced duty cycle and raising the output voltage VOUT.

[0092] As the load is applied, the output voltage VOUT decreases slowly, and the sampling voltage VFB decreases accordingly. When the sampling voltage VFB is lower than the second reference voltage VREF2, the cross-cycle signal PSM jumps to a low level, and the duty cycle generation system resumes operation.

[0093] Since the high duration of the control signal CTRL can be delayed for at least the third preset duration TSET until the voltage V1 on the upper plate of the second capacitor is less than the toggling threshold of the second hysteresis inverter G2, the duty cycle system will force the generation of a duty cycle signal to raise the output voltage VOUT again, as long as the input voltage Vin is appropriate.

[0094] If the output voltage VOUT cannot be raised sufficiently within the third preset time period TSET, and the sampling voltage VFB cannot be greater than the second reference voltage VREF2 again, the system will exit the cross-cycle mode. At this time, the load current output by the corresponding DC-DC converter is also the current threshold for exiting the light load mode.

[0095] In this embodiment, since the third preset duration TSET is related to Vin, it can offset the influence of the input voltage Vin change on the current load threshold when exiting the cross-cycle mode to a certain extent, thus ensuring the consistency of the current load threshold when exiting the cross-cycle mode.

[0096] The output module 104 includes a logic circuit 401, comprising a second OR gate (OR2), a first AND gate (AND1), a second buffer, and a third buffer. The first input of the second OR gate (OR2) is connected to the output of the pulse width modulation (PWM) generation module 101 to receive the PWM wave. The second input is connected to the output of the third buffer, and the output is connected to the input of the second buffer. The first input of the first AND gate is connected to the output of the second buffer, and the second input is connected to the output of the PWM generation module 101 to receive the PWM wave. The output is connected to the input of the third buffer.

[0097] The output module 104 further includes a power stage circuit 402, which is connected to the output terminal of the logic circuit 401. The output terminal of the logic circuit 401 includes the output terminal of a second buffer and the output terminal of a third buffer. The power stage circuit 402 is used to adjust the output voltage VOUT according to the signal output by the logic circuit 401.

[0098] The power stage circuit 402 includes: a PMOS power transistor, whose gate is connected to the output terminal of the second buffer, whose source is connected to the input voltage Vin through an inductor, and whose drain is used to output the output voltage VOUT; and an NMOS power transistor, whose gate is connected to the output terminal of the third buffer, whose source is grounded and connected to the drain of the PMOS power transistor through a third capacitor, and whose drain is connected to the source of the PMOS power transistor.

[0099] The power stage circuit 402 also includes a capacitor and an inductor. The inductor is positioned between the input voltage and the two power transistors, and the capacitor is positioned between the drain of the PMOS power transistor and the source of the NMOS power transistor.

[0100] The PMOS and NMOS power transistors in the power stage circuit 402 are alternately closed under the control of the pulse width modulation (PWM) wave. Specifically, the PMOS power transistor is closed when the PWM wave is low, and the input voltage Vin is output to the load connected to the output module 104 through the source and drain of the PMOS power transistor.

[0101] Please see Figure 5 , Figure 6 ,in Figure 5 This is a schematic diagram of the operating waveforms of various signals in the DC-DC converter described in one embodiment. Figure 6 This is a schematic diagram of the operating waveforms of various signals in a DC-DC converter according to one embodiment.

[0102] Figure 5 , Figure 6 The structure of the corresponding load threshold control unit 1022 is the same as Figure 3 The embodiments shown are consistent.

[0103] In this embodiment, when the load current is just enough to raise the output voltage VOUT to a level that prevents the sampling voltage VFB from reaching the second reference voltage VREF2, the following formula applies:

[0104]

[0105] Then we have:

[0106]

[0107] Where η is the efficiency of the DC-DC converter, VOUT is the output voltage of the DC-DC converter, VIN is the input voltage of the DC-DC converter, ILOAD is the load current, IL_AVG is the average current of the inductor, COUT is the output capacitor, and VHYS is the hysteresis voltage at the output voltage VOUT terminal in PSM mode.

[0108] The mechanism for generating the third preset duration TSET is as follows:

[0109]

[0110] Where C1 is the capacitance of the second capacitor, R1 is the resistance of the second resistor, k is the mirror ratio of the second PMOS transistor and the third NMOS transistor, VGS_M1 is the gate-source voltage of M1, and VTH is the upper threshold of the second hysteresis inverter G2.

[0111] Since VTH is the product of k1 and the output voltage VOUT, then:

[0112]

[0113] TSET is the third preset duration.

[0114]

[0115] By designing the third preset duration TSET to be related to the input voltage Vin and the output voltage VOUT, the influence of changes in the input voltage Vin on the current load threshold when exiting the cross-cycle mode can be offset to a certain extent, ensuring the consistency of the current load threshold when exiting the cross-cycle mode.

[0116] Please see Figure 7 This is a flowchart illustrating the steps of a DC-DC conversion method in one embodiment. This DC-DC conversion method can be applied to the DC-DC converter described in any of the above embodiments.

[0117] In Figure 7 In the illustrated embodiment, the method includes the following steps:

[0118] Step S401: Provide a pulse width modulation (PWM) waveform to regulate the output voltage VOUT.

[0119] When providing the pulse width modulation (PWM) wave, the following steps are included: comparing the sampled voltage VFB with the first reference voltage VREF1, and outputting the error amplification value COMP between the sampled voltage VFB and the first reference voltage VREF1, wherein the sampled voltage VFB is sampled from the output voltage VOUT; comparing the error amplification value COMP with a sawtooth wave RAMP, and outputting the pulse width modulation (PWM) wave according to the comparison result.

[0120] Step S402: When the low duration of the pulse width modulation (PWM) wave is greater than a first preset duration, the output voltage VOUT is increased. Specifically, when the low duration of the PWM wave is greater than the first preset duration, a third reference voltage is provided, which is higher than the valley value of the sawtooth wave RAMP and lower than the peak value of the sawtooth wave RAMP; the third reference voltage is compared with the sawtooth wave RAMP, a forced duty cycle is output, and the output voltage VOUT is increased according to the forced duty cycle.

[0121] Step S403: Reduce the frequency of the pulse width modulation (PWM) wave according to the increased output voltage VOUT.

[0122] When reducing the frequency of the pulse width modulation (PWM) wave based on the increased output voltage VOUT, the method includes the following steps: providing a second reference voltage VREF2; comparing the sampled voltage VFB of the output voltage VOUT with the second reference voltage VREF2, and outputting a high-level cross-cycle signal PSM when the sampled voltage VFB is greater than the second reference voltage VREF2; stopping the output of the PWM wave based on the high-level cross-cycle signal PSM, thereby reducing the frequency of the PWM wave.

[0123] The DC-DC conversion method generates a high-level control signal CTRL when the low-level duration is greater than or equal to a first preset duration. This high-level control signal CTRL has a certain delay characteristic, capable of delaying the second preset duration THOLD, and enabling the pulse width modulation generation module 101 to output a forced duty cycle. This forced duty cycle raises the output voltage VOUT, and the sampling voltage VFB increases accordingly. The magnitude of the increase is related to the magnitude of the input voltage Vin and the initial value of the output voltage VOUT. When the sampling voltage VFB is higher than the second reference voltage VREF2, the cross-cycle signal PSM output by the first comparison unit 1021 is set high.

[0124] After the high-level cross-cycle signal PSM is provided, the DC-DC converter stops outputting the duty cycle, and the output voltage VOUT stops being pulled high. After the high-level signal stops, since a light load is connected to the output module 104, the output voltage VOUT gradually decreases, and the sampling voltage VFB decreases accordingly. When the sampling voltage VFB is less than or equal to the second reference voltage VREF2, the cross-cycle signal PSM changes from high level to low level, and the pulse width modulation wave generation module 101 resumes generating the duty cycle.

[0125] In this embodiment, the high-delay duration of the control signal CTRL is sufficiently long, so that the control signal CTRL remains high even after the cross-cycle signal PSM changes from high to low. At this time, the pulse width modulation wave generation module 101 outputs a pulse width modulation wave PWM with a forced duty cycle again, the output voltage VOUT is raised again, and the sampling voltage VFB increases accordingly. When the sampling voltage VFB is greater than the second reference voltage VREF2, the cross-cycle signal PSM changes from low to high, the DC-DC converter stops outputting the duty cycle signal, and the output voltage VOUT stops being pulled high.

[0126] When the DC-DC converter is lightly loaded, the generation of the pulse width modulation (PWM) wave in the DC-DC converter, as described above, oscillates between stopping operation and forced duty cycle.

[0127] When the DC-DC converter switches from light load to heavy load, the output voltage VOUT has already been consumed too much by the heavy load before the cross-cycle signal PSM changes from low to high. Therefore, when the cross-cycle signal PSM is low, the energy provided by the forced duty cycle cannot increase the output voltage VOUT to a sufficiently large level. The sampling voltage VFB cannot be greater than the second reference voltage VREF2. The cross-cycle signal PSM remains low. After the control signal CTRL is delayed for a second preset time, the control signal CTRL is also low, and the DC-DC converter exits the cross-cycle mode.

[0128] This application provides an electronic device including the DC-DC converter described in any of the above embodiments.

[0129] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, such as the combination of technical features between embodiments, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A DC-DC converter, characterized in that, include: An error amplification module is used to acquire a sampling voltage and a first reference voltage, and output an error amplification value based on the difference between the sampling voltage and the first reference voltage, wherein the sampling voltage is sampled from the output voltage of the DC-DC converter; A pulse width modulation wave generation module is connected to the error amplification module and is used to output a pulse width modulation wave according to the error amplification value; A cross-cycle module, connected to the pulse width modulation wave generation module, is used to acquire the pulse width modulation wave, input voltage, output voltage and sampling voltage, so as to output a high control signal when the low duration of the pulse width modulation wave is greater than a first preset duration, and output a high cross-cycle signal when the sampling voltage is greater than a second reference voltage. The pulse width modulation wave generation module is used to output a forced duty cycle to raise the output voltage when the control signal is high, so that the sampled voltage is greater than the second reference voltage, and to turn off when the cross-cycle signal is high, thereby reducing the frequency of the pulse width modulation wave output by the pulse width modulation wave generation module. The cross-cycle module includes: a first comparison unit, used to acquire and compare the sampled voltage and the second reference voltage, and generate a cross-cycle signal based on the comparison result; A load threshold control unit is connected to the first comparison unit to obtain the cross-cycle signal. The load threshold control unit is also connected to the pulse width modulation wave generation module and is used to obtain the input voltage to form the control signal based on the cross-cycle signal, the pulse width modulation wave and the input voltage.

2. The DC-DC converter according to claim 1, characterized in that, The load threshold control unit includes: The first subunit is connected to the output of the first comparison unit and is used to generate a first signal based on the cross-cycle signal output by the first comparison unit. The second subunit is connected to the output terminal of the first subunit to obtain the first signal, and connected to the output terminal of the pulse width modulation wave generation module to obtain the pulse width modulation wave. The second subunit generates a second signal based on the pulse width modulation wave, and generates the control signal based on the first signal and the second signal.

3. The DC-DC converter according to claim 2, characterized in that, The first subunit includes: A first switch is used to receive the cross-cycle signal through a first inverter. The first switch is closed when the cross-cycle signal is low and open when it is high. The second switch is used to receive the cross-cycle signal and close when the cross-cycle signal is high and open when it is low. A first charging and discharging circuit is connected to the first switch and the second switch, and changes the first signal according to the opening and closing states of the first switch and the second switch.

4. The DC-DC converter according to claim 3, characterized in that, The first charging and discharging circuit includes: A first current source, with its two ends connected to the first switch and the second switch, respectively; The first capacitor has its upper and lower plates connected to the first and second terminals of the second switch, respectively, and the upper plate of the first capacitor is connected to the first current source. A first hysteresis inverter is connected to the upper plate of the first capacitor to obtain the voltage of the upper plate of the first capacitor and output a hysteresis inverted signal of the voltage of the upper plate of the first capacitor. A first buffer is connected to the output of the hysteresis inverter. When the hysteresis inverted signal is higher than a toggle threshold, it outputs a first signal that is set high. When the hysteresis inverted signal is lower than the toggle threshold, it outputs the first signal that is set low.

5. The DC-DC converter according to claim 4, characterized in that, The first current source includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, and a fifth PMOS transistor, wherein: The gate of the first PMOS transistor receives the input voltage of the DC-DC converter, and the source is grounded through the first switch and a first resistor connected in sequence. The source of the second PMOS transistor is connected to the drain of the first PMOS transistor, the drain is used to receive the output voltage, and the gate is connected to the drain of the first PMOS transistor and the gates of the third PMOS transistor and the fourth NMSO transistor. The source of the third PMOS transistor is connected to the first terminal of the second switch, and the drain is used to receive the output voltage. The drain of the fourth PMOS transistor is used to receive the output voltage, the source is connected to the drain of the fifth PMOS transistor, the source of the fifth PMOS transistor is connected to the upper plate of the first capacitor, and the gate is connected to the output terminal of the first hysteresis inverter. The second terminal of the second switch and the lower plate of the first capacitor are both grounded.

6. The DC-DC converter according to claim 2, characterized in that, The second subunit includes: A first delay unit is used to receive the pulse width modulation wave and delay the pulse width modulation wave for the first preset duration. A first OR gate is configured to receive the output voltage of the first delay and the pulse width modulation wave, and to perform a logical OR operation on the output voltage of the first delay and the pulse width modulation wave to output the second signal. The second charging and discharging circuit is connected to the output terminal of the first OR gate and to the output terminal of the first sub-unit, and is used to output the control signal according to the first signal and the second signal.

7. The DC-DC converter according to claim 6, characterized in that, The second charging and discharging circuit includes: The third and fourth switches are used to receive the second signal and close when the second signal is high and open when the second signal is low. The fifth switch has one end connected to the output terminal of the output module, and the other end grounded through the second resistor and the third switch connected in sequence. The fifth switch receives the first signal, closes when the first signal is high, and opens when the first signal is low. The second current source has its first end connected to the output end of the output module, and its second end connected to the first end of the fourth switch through a controllable current source, with the current flowing from the first end to the second end. A controllable current source has a first end connected to the second end of the second current source and the connection point between the second resistor and the fifth switch. The second end is grounded through the fourth switch, and the current direction of the controllable current source is from the first end to the second end. The magnitude of the current is a multiple of the input voltage. The second capacitor has its upper plate connected to the connection point between the second current source and the controllable current source, and its lower plate grounded. The second hysteresis inverter has its input terminal connected to the upper plate of the second capacitor, and its output terminal is used to output the control signal.

8. The DC-DC converter according to claim 3, characterized in that, The pulse width modulation wave generation module includes: The selection unit is configured to receive the error amplification value, the control signal, and a third reference voltage, and selectively output one of the error amplification value and the third reference voltage as a selection result according to the control signal; The second comparison unit is connected to the output of the selection unit and receives a sawtooth wave source to compare the selection result with the sawtooth wave provided by the sawtooth wave source to form the pulse width modulation wave.

9. The DC-DC converter according to claim 8, characterized in that, The selection unit is configured to output the third reference voltage when the control signal is high, and to output the error amplification value when the control signal is low.

10. The DC-DC converter according to claim 1, characterized in that, It also includes an output module, which includes: The logic circuit includes a second OR gate, a first AND gate, a second buffer, and a third buffer. The first input of the second OR gate is connected to the output of the pulse width modulation wave generation module to receive the pulse width modulation wave. The second input is connected to the output of the third buffer, and the output is connected to the input of the second buffer. The first input terminal of the first AND gate is used to connect to the output terminal of the second buffer, the second input terminal is connected to the output terminal of the pulse width modulation wave generation module to receive the pulse width modulation wave, and the output terminal is connected to the input terminal of the third buffer. A power stage circuit, connected to the output terminal of the logic circuit, is used to acquire the input voltage and output the output voltage based on the signal output by the logic circuit and the input voltage.

11. The DC-DC converter according to claim 10, characterized in that, The power stage circuit includes: The PMOS power transistor has its gate connected to the output terminal of the second buffer, its source connected to the input voltage via an inductor, and its drain used to output the output voltage. The NMOS power transistor has its gate connected to the output of the third buffer, its source grounded, and connected to the drain of the PMOS power transistor via a third capacitor. The drain of the NMOS power transistor is connected to the source of the PMOS power transistor.

12. A method for DC-DC conversion, characterized in that, The method for controlling the DC-DC converter according to any one of claims 1 to 11 to perform DC-DC conversion includes the following steps: Provide pulse width modulation waveforms to regulate the output voltage; The output voltage is raised when the duration of the pulse width modulation wave being lowered is greater than a first preset duration; The frequency of the pulse width modulation wave is reduced according to the increased output voltage.

13. The DC-DC conversion method according to claim 12, characterized in that, Providing the pulse width modulated wave includes the following steps: The sampled voltage is compared with a first reference voltage, and the error amplification value between the sampled voltage and the first reference voltage is output, wherein the sampled voltage is sampled from the output voltage; The error amplification value is compared with a sawtooth wave, and the pulse width modulation wave is output based on the comparison result.

14. The DC-DC conversion method according to claim 13, characterized in that, Raising the output voltage includes the following steps: When the duration of the low position of the pulse width modulation wave is greater than a first preset duration, a third reference voltage is provided, the third reference voltage being higher than the valley value of the sawtooth wave and lower than the peak value of the sawtooth wave; The third reference voltage is compared with the sawtooth wave, a forced duty cycle is output, and the output voltage is increased according to the forced duty cycle.

15. The DC-DC conversion method according to claim 12, characterized in that, When reducing the frequency of the pulse width modulation wave based on the increased output voltage, the following steps are included: Provide a second reference voltage; The sampled voltage of the output voltage is compared with the second reference voltage, and a cross-cycle signal is output high when the sampled voltage is greater than the second reference voltage; The output of the pulse width modulation wave is stopped according to the high-level cross-cycle signal, thereby reducing the frequency of the pulse width modulation wave.

16. An electronic device, characterized in that, Includes the DC-DC converter as described in any one of claims 1 to 11.

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