Method and apparatus for message sending and receiving

Abstract

The present application discloses a method and device for message sending and receiving. The method includes performing endian conversion on a first message in a first channel of a DMA controller to obtain a second message. The first message is received by a port into the first channel, and the first message and the second message are arranged in a first endian and a second endian respectively; transmitting the second message to a central processing unit; performing endian conversion on a third message in a second channel of the DMA controller to obtain a fourth message. The third message is obtained by the central processing unit processing the second message, and the fourth message is arranged in the first endian; transmitting the fourth message to the port for sending. The present application can achieve endian conversion of messages in the channels of the DMA controller, so that there is no need to perform endian conversion in the CPU anymore, which can effectively reduce the performance occupation of the CPU and greatly improve the message sending and receiving efficiency of the CPU.

Description

Technical Field

[0001] This application belongs to the technical field of communication design, and particularly relates to a method and device for packet sending and receiving. Background Art

[0002] DMA (Direct Memory Access) direct memory access is a way for the CPU to interact with peripherals. The interaction between the DMA and the CPU is completed through descriptors, which are stored in a memory with a fixed format. From the perspective of the CPU receiving packets, the DMA stores the packets received from the chip into the specified memory according to the information in the descriptor, and then notifies the CPU. The CPU can parse the information in the specified memory according to the information in the descriptor. In an Ethernet network environment, the sending and receiving of protocol packets between devices are basically completed through the interaction between the CPU and the DMA.

[0003] Currently, there are two different byte orders of CPUs in the market, big-endian and little-endian, while the DMA in the chip often transmits data in big-endian or a fixed byte order. If the byte order of the CPU is inconsistent with that of the DMA, byte order conversion is required. In the prior art, byte order conversion is performed on the CPU side. When more bytes need to be converted, the packet receiving performance of the CPU becomes slower, which brings a great performance bottleneck to the CPU in application scenarios where the CPU needs to efficiently send and receive packets. Summary of the Invention

[0004] The purpose of this application is to provide a method and device for packet sending and receiving to solve the technical problem in the prior art that byte order conversion is performed on the CPU side. When more bytes need to be converted, the packet receiving performance of the CPU becomes slower, which brings a great performance bottleneck to the CPU in application scenarios where the CPU needs to efficiently send and receive packets.

[0005] To achieve the above purpose, a technical solution adopted by this application is:

[0006] A method for packet sending and receiving is provided, including:

[0007] Performing byte order conversion on a first packet in a first channel of a DMA controller to obtain a second packet. The first packet is received from a port to the first channel, and the first packet and the second packet are arranged in a first byte order and a second byte order respectively;

[0008] Transmitting the second packet to a central processing unit;

[0009] Performing byte order conversion on a third packet in a second channel of the DMA controller to obtain a fourth packet. The third packet is obtained by the central processing unit processing the second packet, and the fourth packet is arranged in the first byte order;

[0010] Transmit the fourth message to the port for sending.

[0011] In one or more embodiments, the step of performing endian conversion on the first message in the first channel of the DMA controller to obtain the second message specifically includes:

[0012] Configure multiple endian conversion parameter groups corresponding to multiple eigenvalue for the first channel of the DMA controller, and the endian conversion parameter group is used to describe the conversion method of the endian;

[0013] Allocate an eigenvalue for the first message;

[0014] Based on the eigenvalue index of the first message, index the corresponding endian conversion parameter group to perform endian conversion on the first message.

[0015] In one or more embodiments, the parameter group includes a first parameter, a second parameter, and a third parameter. The first parameter is used to describe whether the endian needs to be converted, the second parameter is used to describe the starting point of the endian conversion, and the third parameter is used to describe the ending point of the endian conversion.

[0016] In one or more embodiments, the step of allocating an eigenvalue for the first message specifically includes:

[0017] Obtain the byte information of the first message, and the byte information is provided by one or more of the access control list, CPU reasonID, and DMA queueID;

[0018] Based on the byte information of the first message, determine whether the first message needs to be converted; if not, allocate a first eigenvalue for the first message, and the value of the first parameter corresponding to the first eigenvalue is used to describe no conversion; if so, then:

[0019] Identify the conversion start position value of the first message, and determine whether the first message needs to be converted to the flag SOP position; if not, identify the conversion end position value of the first message, and allocate a second eigenvalue for the first message. The value of the first parameter corresponding to the second eigenvalue is used to describe that conversion is required, the value of the second parameter corresponding to the second eigenvalue is used to describe the starting point position of the endian conversion, and the value of the third parameter corresponding to the second eigenvalue is used to describe the ending point position of the endian conversion; if so, then:

[0020] Allocate a third eigenvalue to the first message, where the value of the first parameter corresponding to the third eigenvalue is used to describe the conversion required, the value of the second parameter corresponding to the third eigenvalue is used to describe the starting position of the byte order conversion, and the value of the third parameter corresponding to the third eigenvalue is used to describe the position of the byte order conversion to the flag SOP.

[0021] In one or more embodiments, after the step of allocating an eigenvalue to the first message, the following steps are further included:

[0022] Embed the eigenvalue of the first message into the first message.

[0023] In one or more embodiments, the first message includes a data segment and a header segment, and the eigenvalue is embedded in the header segment.

[0024] In one or more embodiments, the step of performing byte order conversion on the third message in the second channel of the DMA controller to obtain a fourth message specifically includes:

[0025] Perform byte order conversion on the third message based on the eigenvalue embedded in the third message.

[0026] To achieve the above object, another technical solution adopted by this application is:

[0027] Provide a device for message sending and receiving, including:

[0028] A first conversion module, configured to perform byte order conversion on a first message in the first channel of a DMA controller to obtain a second message, where the first message is received by a port into the first channel, and the first message and the second message are arranged in a first byte order and a second byte order respectively;

[0029] A first transmission module, configured to transmit the second message to a central processing unit;

[0030] A second conversion module, configured to perform byte order conversion on a third message in the second channel of the DMA controller to obtain a fourth message, where the third message is obtained by the central processing unit processing the second message, and the fourth message is arranged in the first byte order;

[0031] A second transmission module, configured to transmit the fourth message to a port for sending.

[0032] To achieve the above object, yet another technical solution adopted by this application is:

[0033] Provide an electronic device, including at least one processor; and

[0034] A memory that stores instructions which, when executed by the at least one processor, cause the at least one processor to execute the method for message transceiver as described in any of the above embodiments.

[0035] To achieve the above object, another technical solution adopted by this application is:

[0036] Provide a machine-readable storage medium that stores executable instructions which, when executed, cause the machine to execute the method for message transceiver as described in any of the above embodiments.

[0037] Different from the prior art, the beneficial effects of this application are:

[0038] By configuring multiple byte order conversion parameter groups corresponding to multiple eigenvalue in the channels of the DMA controller and assigning eigenvalues to messages in this application, it is possible to perform byte order conversion of messages in the channels of the DMA controller, so that there is no need to perform byte order conversion in the CPU anymore, which can effectively reduce the performance occupation of the CPU and greatly improve the message transceiver efficiency of the CPU. Description of the Drawings

[0039] Figure 1 is a schematic flowchart of an embodiment of the method for message transceiver of this application;

[0040] Figure 2 is Figure 1 a schematic flowchart of an embodiment corresponding to step S100 in

[0041] Figure 3 is Figure 2 a schematic flowchart of an embodiment corresponding to step S102 in

[0042] Figure 4 is a structural block diagram of an embodiment of the device for message transceiver of this application;

[0043] Figure 5 is a structural diagram of an embodiment of the electronic device of this application. Detailed Embodiments

[0044] The following will describe in detail the specific embodiments of the present invention in conjunction with the drawings, but it should be understood that the protection scope of the present invention is not limited by the specific embodiments.

[0045] Unless otherwise clearly stated, in the whole specification and claims, the term "comprising" or its variations such as "including" or "having" etc. will be understood to include the stated elements or components, without excluding other elements or other components.

[0046] In an Ethernet network environment, the sending and receiving of protocol messages between devices are basically completed through the interaction between the central processing unit (CPU) and the direct memory access (DMA) controller.

[0047] Currently, there are two different byte orders of CPUs in the market, big-endian and little-endian, while the DMA controller in the chip often transmits data in big-endian or a fixed byte order. This makes it necessary to perform byte order conversion when the byte order of the DMA controller is different from that of the CPU, so that the interaction operation of the message can be completed between the CPU and the DMA controller.

[0048] In one scenario, the byte order conversion of the message is performed inside the CPU. When the message is transmitted to the inside of the CPU through the DMA controller, the CPU first performs byte order conversion on the message, and then processes the message based on the protocol stack. After the processing is completed, the byte order of the message is converted to the same as that of the DMA controller and sent to the DMA controller for sending. The above interaction process occupies a lot of CPU performance. When more bytes need to be converted, the message receiving performance of the CPU will be slower. In particular, it will bring a great performance bottleneck to the CPU in application scenarios where the CPU needs to efficiently send and receive messages.

[0049] To solve the above problems, the applicant proposes a method that can perform byte order conversion of messages inside the DMA controller, thereby effectively reducing the performance occupation of the CPU and greatly improving the message sending and receiving efficiency of the CPU. Please refer to Figure 1 , Figure 1 which is a schematic flow diagram of an implementation manner of the message sending and receiving method of this application.

[0050] The method includes:

[0051] S100. Perform byte order conversion on the first message in the first channel of the DMA controller to obtain a second message.

[0052] Specifically, the first message is received into the first channel through a port. The port is an import and export for communicating with the outside world, which can be a virtual port or a physical port. The first channel can be understood as the receiving channel of the DMA controller in this implementation manner.

[0053] When the first message is transmitted from the port to the first channel inside the DMA controller, byte conversion is performed in the first channel to generate a second message, where the first message and the second message are arranged in the first byte order and the second byte order respectively.

[0054] The second byte order is the same as the byte order of the CPU for transmitting data, so there is no need to perform byte order conversion in the CPU again, which can effectively reduce the performance occupation of the CPU and greatly improve the message sending and receiving efficiency of the CPU.

[0055] Please refer to Figure 2 , Figure 2 which Figure 1 is a schematic flowchart of an implementation manner corresponding to step S100 in

[0056] In one implementation manner, the steps of performing endian conversion on the first message in the first channel of the DMA controller include:

[0057] S101. Configure multiple endian conversion parameter groups corresponding to multiple feature values for the first channel of the DMA controller.

[0058] Specifically, the endian conversion parameter group is used to describe the endian conversion method. Each endian conversion parameter group represents an endian conversion method. One feature value corresponds to one endian conversion parameter group. That is, it can be understood that when a feature value is obtained, an endian conversion method can be obtained according to the corresponding endian conversion parameter group.

[0059] In an application scenario, the endian conversion parameter group may include a first parameter valid, a second parameter start, and a third parameter end. Among them, the first parameter valid is used to describe whether endian conversion is required. For example, when valid = 0, it may represent that no endian conversion is required. When valid = 1, it may represent that endian conversion is required. The second parameter start is used to describe the starting point of the endian conversion. For example, when start = 1, it may represent starting the endian conversion from the first byte of a segment of bytes. The third parameter end is used to describe the termination point of the endian conversion. For example, when end = 0, it may represent that the endian conversion needs to be performed until the SOP position of the message. When end = 5, it may represent that the endian conversion needs to be performed until the 5th byte.

[0060] It can be understood that through the above three parameters, it can be clearly obtained how to perform endian conversion on a segment of bytes. In other application scenarios, multiple parameters for describing the starting point and termination point of the endian conversion may also be set, or other parameters may also be used, as long as an endian conversion method can be clearly described.

[0061] In an application scenario, the corresponding relationship between the multiple feature values and the multiple endian conversion parameter groups may be stored in the register of the DMA controller. The stored data may be represented as fields of g_{0…n}_valid, g_{0…n}_start, g_{0…n}_end, where 0…n is the feature value, and each parameter corresponding to a feature value has a specific selection value, so as to assign a corresponding endian conversion method to each feature value.

[0062] In other application scenarios, it can also be stored in other positions of other DMA controllers, or stored in a storage module that can be called by the DMA controller, and the effects of this embodiment can be achieved.

[0063] S102. Assign a feature value to the first packet.

[0064] After the first packet enters the first channel, a feature value can be assigned to the first packet inside the first channel based on the correspondence between multiple feature values stored inside the first channel and multiple byte order conversion parameter groups. It can be understood that after the first packet is assigned a feature value, its byte order conversion method can be determined.

[0065] Please refer to FIG. 3. Figure 3 is Figure 2 a schematic flowchart of an embodiment corresponding to step S102 in

[0066] In one embodiment, the step of assigning a feature value to the first packet specifically includes:

[0067] S1021. Obtain the byte information of the first packet.

[0068] In one application scenario, the byte information of the first packet can be provided by an access control list ACL. ACL is an access control technology based on packet filtering. It can filter the data packets on the interface according to the set conditions and allow them to pass or be discarded. The ingress access control list I-ACL (Ingress Access Control List) module or the egress access control list E-ACL (Egress Access Control List) module can be used to obtain the byte information of the packet and match the feature value.

[0069] In other application scenarios, for protocol packets or other custom packet types that go to the CPU, the byte information of the first packet can be provided by the CPU ReasonID in the packet. The CPU ReasonId is carried in the packet header segment for the CPU to identify and determine the reason for reporting the packet, and the byte information can be obtained according to the CPU ReasonId to assign a feature value.

[0070] In addition, the byte information of the first message can also be provided by the DMA QueueId of the message, that is, the DMA queue number. Messages sent to the CPU via DMA need to enter the DMA queue. Each DMA queue corresponds to a queueId. Since there are many messages sent to the CPU and there will be many ReasonIds, some are of high priority, such as PDU protocol messages, and some are of low priority, such as mirror messages. By sending them to the CPU through different queueIds, rate limiting and high / low priority scheduling can be performed for different queueIds. Therefore, the byte information of the message can be obtained according to the queueId and the characteristic value can be assigned.

[0071] S1022. Determine whether the first message needs to be converted.

[0072] Based on the byte information of the first message, first determine whether the first message needs to be converted. If it does not need to be converted, then execute step S1023. If it needs to be converted, then execute step S1024.

[0073] S1023. Assign a first characteristic value to the first message.

[0074] Specifically, the value of the first parameter corresponding to the first characteristic value is used to describe that no conversion is required. In an application scenario, the value of the first parameter corresponding to the first characteristic value can be 0, which means no conversion is required. In this case, there is no need to further analyze the start and end points of the conversion.

[0075] S1024. Identify the conversion start position value of the first message, and determine whether the first message needs to be converted to the flag SOP position.

[0076] When it is determined that the first message needs to be converted, first identify the conversion start position value, and then determine whether to convert to the flag SOP position, that is, whether all the messages after the conversion start position value need to be converted. If not, then execute step S1025. If so, then execute step S1026.

[0077] S1025. Identify the conversion end position value of the first message, and assign a second characteristic value to the first message.

[0078] Specifically, at this time, the first message needs to be partially converted. After identifying the conversion end position value of the first message, the second characteristic value can be assigned to the first message based on the identified conversion start position value and conversion end position value.

[0079] The value of the first parameter corresponding to the second eigenvalue is used to describe the need for conversion. In an application scenario, the value of the first parameter can be 1 to describe the need for conversion; the value of the second parameter corresponding to the second eigenvalue is used to describe the starting position of the endian conversion. For example, the value of the second parameter can be 1 to describe that the endian conversion starts from the first byte position; the value of the third parameter corresponding to the second eigenvalue is used to describe the ending position of the endian conversion. For example, the value of the third parameter can be 5 to describe that the conversion needs to reach the fifth byte position.

[0080] S1026. Assign a third eigenvalue to the first message.

[0081] Specifically, at this time, the first message needs to be converted to the SOP flag position, that is, all the messages after the conversion start position need to be converted. The third eigenvalue can be directly assigned to the first message based on the recognized conversion start position value.

[0082] The value of the first parameter corresponding to the third eigenvalue is used to describe the need for conversion. In an application scenario, the value of the first parameter can be 1 to describe the need for conversion; the value of the second parameter corresponding to the third eigenvalue is used to describe the starting point position of the endian conversion. For example, the value of the second parameter can be 2 to describe that the endian conversion starts from the second byte position; the value of the third parameter corresponding to the third eigenvalue is used to describe the endian conversion to the SOP flag position. In an application scenario, the value of the third parameter can be 0 to describe that the endian conversion needs to reach the SOP flag position.

[0083] S103. Based on the endian conversion parameter group corresponding to the eigenvalue index of the first message, perform endian conversion on the first message.

[0084] Specifically, after the first message is assigned an eigenvalue, according to the endian conversion parameter group corresponding to the eigenvalue index, the endian conversion method of the first message can be obtained, so as to perform endian conversion to obtain the second message.

[0085] S200. Transmit the second message to the central processing unit.

[0086] After the first message undergoes endian conversion, the second message arranged in the second endian is obtained. The second endian is the same as the endian of the CPU to transmit data. Therefore, the second message can be directly transmitted to the central processing unit.

[0087] S300. Perform endian conversion on the third message in the second channel of the DMA controller to obtain the fourth message.

[0088] Specifically, the third message is obtained by the CPU processing the second message. The CPU's processing can be to replace or modify a certain field in the message. After the CPU processes it, the third message can be sent to the second channel of the DMA controller.

[0089] The second channel can be the sending channel of the DMA controller. Since the byte order of the message is not changed during the CPU processing, both the third message and the second message are arranged in the second byte order. However, the DMA controller transmits data in the first byte order. Therefore, it is necessary to restore the byte order of the message to the first byte order within the DMA controller.

[0090] In an application scenario, the byte order of the third message can be adjusted to the first byte order based on the above-mentioned byte order conversion method in the first channel, and the fourth message can be obtained. That is, reconfigure multiple byte order conversion parameter groups corresponding to multiple characteristic values for the second channel; assign a characteristic value to the third message; index the corresponding byte order conversion parameter group based on the characteristic value of the third message to perform byte order conversion on the third message to obtain the fourth message.

[0091] In another application scenario, in order to improve the byte order conversion efficiency of the third message and avoid repeated calculations, the characteristic value assigned to the first message in the first channel can also be reused.

[0092] Specifically, after the above step S102, the characteristic value of the first message can be embedded in the first message. The characteristic value can be transmitted to the CPU following the second message and returned to the second channel of the DMA controller following the third message.

[0093] In the second channel, based on the byte order conversion parameter group indexed by the characteristic value embedded in the third message, a method for converting the byte order of the third message to the first byte order can be obtained, so that the third message can be converted into the fourth message to achieve output transmission within the DMA controller and the port.

[0094] A general message includes a data segment and a PacketHeader header segment set at the head of the data segment. The header segment is not the layer 2 header or layer 3 header in the frame format of network transmission, but a section of data defined by the manufacturer. Its purpose is to carry key information generated during the forwarding of the message in the chip. These key information can be information such as the entry, exit, and queue of the message. In this embodiment, the characteristic value can be embedded in the header segment, so that while not affecting the data in the data segment and byte order conversion, the characteristic value can be transmitted with the message to facilitate restoring the byte order of the message in the second channel.

[0095] S400: Transmit the fourth message to the port for sending.

[0096] After the third message undergoes endian conversion, a fourth message arranged in the first endian is obtained, and the fourth message can be sent out through a port to complete a single send and receive operation of the message.

[0097] It can be understood that in a single send and receive operation of the message, the CPU is only responsible for processing the message, and the endian conversion of the message is performed separately in the first channel and the second channel of the DMA controller, effectively reducing the performance occupancy of the CPU, thereby greatly improving the message sending and receiving efficiency of the CPU.

[0098] This application also provides a device for message sending and receiving. Please refer to Figure 4 , Figure 4 which is a structural block diagram of an embodiment of the device for message sending and receiving in this application.

[0099] The device includes a first conversion module 21, a first transmission module 22, a second conversion module 23, and a second transmission module 24.

[0100] Among them, the first conversion module 21 is used to perform endian conversion on the first message in the first channel of the DMA controller to obtain a second message. The first message is received from the port to the first channel, and the first message and the second message are arranged in the first endian and the second endian respectively.

[0101] The first transmission module 22 is used to transmit the second message to the central processing unit.

[0102] The second conversion module 23 is used to perform endian conversion on the third message in the second channel of the DMA controller to obtain a fourth message. The third message is obtained by the central processing unit processing the second message, and the fourth message is arranged in the first endian.

[0103] The second transmission module 24 is used to transmit the fourth message to the port for sending out.

[0104] In one embodiment, the first conversion module 21 specifically includes a configuration unit 211, an allocation unit 212, and a conversion unit 213. Among them, the configuration unit 211 is used to configure multiple endian conversion parameter groups corresponding to multiple characteristic values for the first channel of the DMA controller. The endian conversion parameter group is used to describe the conversion method of the endian; the allocation unit 212 is used to allocate characteristic values for the first message; the conversion unit 213 is used to index the corresponding endian conversion parameter group based on the characteristic value of the first message to perform endian conversion on the first message.

[0105] As described above with reference to Figures 1 to 2, a method for message sending and receiving according to the embodiments of this specification has been described. The details mentioned in the above description of the method embodiments also apply to the message sending and receiving device of the embodiments of this specification. The above-mentioned message sending and receiving device can be implemented in hardware, or can be implemented by software or a combination of hardware and software.

[0106] Figure 5 shows a hardware structure diagram of an electronic device according to an embodiment of this specification. As Figure 5 shown, the electronic device 30 may include at least one processor 31, a memory 32 (such as a non-volatile memory), a memory 33, and a communication interface 34, and at least one processor 31, the memory 32, the memory 33, and the communication interface 34 are connected together via a bus 35. At least one processor 31 executes at least one computer-readable instruction stored or encoded in the memory 32.

[0107] It should be understood that the computer-executable instructions stored in the memory 32, when executed, cause at least one processor 31 to perform the various operations and functions described above in the various embodiments of this specification in combination with Figures 1 - 2 description.

[0108] In the embodiments of this specification, the electronic device 30 may include, but is not limited to: a personal computer, a server computer, a workstation, a desktop computer, a laptop computer, a notebook computer, a mobile electronic device, a smart phone, a tablet computer, a cellular phone, a personal digital assistant (PDA), a handheld device, a messaging device, a wearable electronic device, a consumer electronic device, and so on.

[0109] According to one embodiment, a program product such as a machine-readable medium is provided. The machine-readable medium may have instructions (i.e., the above-mentioned elements implemented in software form), and when the instructions are executed by the machine, the machine performs the various operations and functions described above in the various embodiments of this specification in combination with Figures 1 - 2 description. Specifically, a system or device equipped with a readable storage medium may be provided, and software program code for implementing the functions of any one of the above-mentioned embodiments is stored on the readable storage medium, and the computer or processor of the system or device reads and executes the instructions stored in the readable storage medium.

[0110] In this case, the program code read from the readable medium itself can implement the functions of any one of the above-mentioned embodiments, so the machine-readable code and the readable storage medium storing the machine-readable code constitute a part of this specification.

[0111] Examples of readable storage media include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD-RW), magnetic tapes, non-volatile memory cards, and ROMs. Optionally, program code can be downloaded from a server computer or the cloud via a communication network.

[0112] Those skilled in the art should understand that various modifications and variations can be made to the above-disclosed embodiments without departing from the essence of the invention. Therefore, the scope of protection of this specification should be defined by the appended claims.

[0113] It should be noted that not all steps and units in the above-mentioned processes and system structure diagrams are necessary, and some steps or units can be ignored according to actual needs. The execution order of each step is not fixed and can be determined according to requirements. The device structures described in the above embodiments can be physical structures or logical structures, that is, some units may be implemented by the same physical entity, or some units may be implemented separately by multiple physical entities, or some components in multiple independent devices may be jointly implemented.

[0114] In the above embodiments, the hardware units or modules can be implemented mechanically or electrically. For example, a hardware unit, module, or processor can include permanent dedicated circuits or logic (such as a dedicated processor, FPGA, or ASIC) to perform corresponding operations. The hardware unit or processor can also include programmable logic or circuits (such as a general-purpose processor or other programmable processors), which can be temporarily set by software to perform corresponding operations. The specific implementation method (mechanical method, or dedicated permanent circuit, or temporarily set circuit) can be determined based on cost and time considerations.

[0115] The specific embodiments described above in conjunction with the accompanying drawings describe exemplary embodiments, but do not represent all embodiments that can be implemented or fall within the scope of protection of the claims. The term "exemplary" used throughout this specification means "serving as an example, instance, or illustration", and does not mean "preferred" or "having advantages" over other embodiments. For the purpose of providing an understanding of the described technology, the specific embodiments include specific details. However, these technologies can be implemented without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described embodiments.

[0116] The foregoing description of the disclosure is provided to enable any person of ordinary skill in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those of ordinary skill in the art, and the generic principles herein can be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for message sending and receiving, characterized in that, Including: Performing endian conversion on a first message within a first channel of a DMA controller to obtain a second message, where the first message is received by a port into the first channel, and the first message and the second message are arranged in a first endian and a second endian respectively; Transmitting the second message to a central processing unit; Performing endian conversion on a third message within a second channel of the DMA controller to obtain a fourth message, where the third message is obtained by the central processing unit processing the second message, and the fourth message is arranged in the first endian; Transmitting the fourth message to the port for sending; Among them, the step of performing endian conversion on the first message within the first channel of the DMA controller to obtain the second message specifically includes: Configuring multiple endian conversion parameter groups corresponding to multiple characteristic values for the first channel of the DMA controller, where the endian conversion parameter groups are used to describe the conversion method of the endian; Allocating a characteristic value for the first message and embedding the characteristic value of the first message into the first message; Based on the characteristic value of the first message, indexing the corresponding endian conversion parameter group to perform endian conversion on the first message.

2. The method according to claim 1, wherein The parameter group includes a first parameter, a second parameter, and a third parameter. The first parameter is used to describe whether the endian needs to be converted, the second parameter is used to describe the starting point of the endian conversion, and the third parameter is used to describe the ending point of the endian conversion.

3. The method according to claim 2, wherein The step of allocating a characteristic value for the first message specifically includes: Obtaining the byte information of the first message, where the byte information is provided by one or more of an access control list, a CPU reason ID, and a DMA queue ID; Based on the byte information of the first message, determining whether the first message needs to be converted; if not, allocating a first characteristic value for the first message, and the value of the first parameter corresponding to the first characteristic value is used to describe no conversion; if so, then: Identifying the conversion start position value of the first message, and determining whether the first message needs to be converted to the flag SOP position; if not, identifying the conversion end position value of the first message, allocating a second characteristic value for the first message, and the value of the first parameter corresponding to the second characteristic value is used to describe the need for conversion, the value of the second parameter corresponding to the second characteristic value is used to describe the starting point position of the endian conversion, and the value of the third parameter corresponding to the second characteristic value is used to describe the ending point position of the endian conversion; if so, then: Allocating a third characteristic value for the first message, and the value of the first parameter corresponding to the third characteristic value is used to describe the need for conversion, the value of the second parameter corresponding to the third characteristic value is used to describe the starting point position of the endian conversion, and the value of the third parameter corresponding to the third characteristic value is used to describe the conversion to the flag SOP position.

4. The method according to claim 1, wherein The first message includes a data segment and a header segment, and the characteristic value is embedded in the header segment.

5. The method according to claim 1, wherein The step of performing endian conversion on the third message within the second channel of the DMA controller to obtain the fourth message specifically includes: Perform endian conversion on the third message based on the eigenvalue embedded in the third message.

6. A device for message sending and receiving, characterized in that, Including: A first conversion module, configured to perform endian conversion on a first message in a first channel of a DMA controller to obtain a second message. The first message is received by a port into the first channel, and the first message and the second message are arranged in a first endian and a second endian respectively. A first transmission module, configured to transmit the second message to a central processing unit. A second conversion module, configured to perform endian conversion on a third message in a second channel of the DMA controller to obtain a fourth message. The third message is obtained by the central processing unit processing the second message, and the fourth message is arranged in the first endian. A second transmission module, configured to transmit the fourth message to the port for sending. Wherein, the performing endian conversion on the first message in the first channel of the DMA controller to obtain the second message specifically includes: Configuring multiple endian conversion parameter groups corresponding to multiple eigenvalues for the first channel of the DMA controller. The endian conversion parameter groups are used to describe the conversion method of the endian. Allocating an eigenvalue to the first message and embedding the eigenvalue of the first message into the first message. Based on the endian conversion parameter group indexed by the eigenvalue of the first message, perform endian conversion on the first message.

7. An electronic device, characterized in that, Including at least one processor; and A memory, the memory stores instructions, when the instructions are executed by the at least one processor, enabling the at least one processor to execute the message sending and receiving method according to any one of claims 1 to 5.

8. A machine-readable storage medium, characterized in that, It stores executable instructions, and when the instructions are executed, enabling the machine to execute the message sending and receiving method according to any one of claims 1 to 5.

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