Multifunctional two-dimensional spin logic gate device and preparation method thereof

Abstract

The application discloses a multifunctional two-dimensional spin logic gate device and a preparation method thereof. The device comprises a substrate layer, a spin electron conduction layer and a logic electrode layer which are sequentially stacked. The logic electrode layer comprises a magnetic control area, a first input area and a second input area which are arranged at intervals in the horizontal direction. The first input area is arranged at the center of the magnetic control area and the second input area. The multifunctional two-dimensional spin logic gate device is switched between the AND gate logic and the NOR gate logic by adjusting the magnetization direction of the magnetic control area. The device has the AND gate logic and the NOR gate logic by arranging the magnetic control area, the first input area and the second input area on the surface of the two-dimensional graphene material and using the material characteristics of the ferromagnetic semimetal and the spin gapless semiconductor. The device does not need to introduce other devices, and the power consumption and delay during the execution of multiple logic operations are reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor materials and devices, and in particular to a multifunctional two-dimensional spin logic gate device and its fabrication method. Background Technology

[0002] As a new generation of "in-memory computing" data storage devices, spin-orbit moment magnetic random access memory (MIM) devices have advantages such as low power consumption, low operating latency, strong radiation resistance, high durability, and non-volatility. The core component of such magnetic "in-memory computing" devices in existing technologies is a magnetic tunnel junction, which typically includes a free layer, a control layer, and a tunneling insulating layer located between them. The magnetic moment of the free layer can freely flip, while the magnetic moment of the control layer is fixed or has high coercivity and is unaffected by external excitation factors such as magnetic fields, current, and temperature. The tunneling insulating layer is composed of insulating materials such as metal oxides.

[0003] Traditional magnetic random access memory (MRAM) units, in addition to magnetic tunnel junctions, require an isolation transistor to store and conduct potentials during read and write operations, thus increasing the complexity and cost of device fabrication and circuit connections. Furthermore, while magnetic tunnel junctions can implement simple logic operations such as AND and OR, XOR operations require cascading multiple devices, significantly increasing power consumption and computational latency, and consequently raising the requirements for device packaging and fabrication processes. Summary of the Invention

[0004] The purpose of this invention is to provide a multifunctional two-dimensional spin logic gate device and its fabrication method, which solves the problem that traditional magnetic random access memory devices are complex and difficult to implement multiple logic operations on a single device.

[0005] To solve the above-mentioned technical problems, the first solution provided by the present invention is: a multifunctional two-dimensional spin logic gate device, comprising a substrate layer, a spin electron conduction layer, and a logic electrode layer stacked sequentially. The logic electrode layer includes a magnetic control region, a first input region, and a second input region arranged at intervals in the horizontal direction. The first input region is located at the center of the magnetic control region and the second input region. The magnetic control region and the second input region are made of ferromagnetic half-metal material, and the first input region is made of spin gapless semiconductor material. By adjusting the magnetization direction of the magnetic control region, the multifunctional two-dimensional spin logic gate device can perform switching between AND gate logic and NOR gate logic.

[0006] The magnetic control area is grounded, and the second input area is connected to an external voltage source.

[0007] Preferably, the substrate layer is composed of silicon and silicon dioxide stacked sequentially, and the silicon dioxide is disposed close to the spin electron conduction layer.

[0008] Preferably, the spin electron conducting layer adopts a two-dimensional graphene material.

[0009] Preferably, the magnetic control region and the second input region both adopt any one of Co2MnGa, CeAlSi and TaAs; and the first input region adopts any one of Mn2Si, Co3Sn2S2, Fe3Sn2 and CoSn.

[0010] When the magnetic control region is subjected to an external magnetic field to make the magnetic moment direction of the magnetic control region downward in the forward bias direction from the magnetic control region to the second input region, the two-dimensional spin logic gate device is configured as an AND gate logic.

[0011] More specifically, when the two-dimensional spin logic gate device is in the AND gate logic, the magnetic moment directions of the first input region and the second input region are both upward, and the two-dimensional spin logic gate device is in a conducting state; otherwise, the two-dimensional spin logic gate device is in a cutoff state.

[0012] When the magnetic control region is subjected to an external magnetic field to make the magnetic moment direction of the magnetic control region upward in the forward bias direction from the magnetic control region to the second input region, the two-dimensional spin logic gate device is configured as an OR-NOT gate logic.

[0013] More specifically, when the two-dimensional spin logic gate device is in the OR-NOT gate logic, the magnetic moment directions of the first input region and the second input region are both downward, and the two-dimensional spin logic gate device is in a conducting state; otherwise, the two-dimensional spin logic gate device is in a cutoff state.

[0014] To solve the above technical problems, the second solution provided by the present application is a preparation method of a multifunctional two-dimensional spin logic gate device, which is used to prepare the multifunctional two-dimensional spin logic gate device in the first solution, and specifically includes the following steps: S1, disposing a two-dimensional graphene material on a silicon dioxide surface of a substrate layer as a spin electron conducting layer; S2, using a mask or a photoetching plate to grow ferromagnetic semimetals on the surface of the spin electron conducting layer at intervals to form a magnetic control region and a second input region respectively; and S3, using a mask to grow a spin gapless semiconductor material in the center of a channel between the magnetic control region and the second input region to form a first input region.

[0015] The present application has the advantages that, different from the prior art, the present application provides a multifunctional two-dimensional spin logic gate device and a preparation method thereof, the device is provided with a magnetic control region, a first input region and a second input region on the surface of a two-dimensional graphene material, and the material characteristics of ferromagnetic semimetals and spin gapless semiconductors are used, so that the device has two logic operation modes of an AND gate logic and an OR-NOT gate logic, and other devices do not need to be introduced, thereby reducing power consumption and delay when performing multiple logic operations. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1is a cross-sectional structure schematic diagram of an embodiment of a multifunctional two-dimensional spin logic gate device in the application;

[0017] Figure 2 is a schematic diagram of the energy state density spatial distribution and current conduction of a multifunctional two-dimensional spin logic gate device in the application when the magnetization directions of the spin gapless semiconductor and the semimetal are the same (the magnetic moment directions are both upward): (a) V=0, no bias voltage, (b) V>0, positive bias voltage, (c) V<0, reverse bias voltage;

[0018] Figure 3 is a schematic diagram of the energy state density spatial distribution and current conduction of a multifunctional two-dimensional spin logic gate device in the application when the magnetization directions of the spin gapless semiconductor and the semimetal are opposite (the magnetic moment direction of the left is upward, and the magnetic moment direction of the right is downward): (a) V=0, no bias voltage, (b) V>0, positive bias voltage, (c) V<0, reverse bias voltage;

[0019] Figure 4 is a process flow chart of an embodiment of a preparation method of a multifunctional two-dimensional spin logic gate device in the application

[0020] In the figure: 1-substrate layer, 2-spin electron conduction layer, 3-logic electrode layer, 31-magnetic control area (HM1), 32-first input area (SGS), and 33-second input area (HM2). DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the application will be clearly and completely described below with reference to the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by a person of ordinary skill in the art without creative labor fall within the protection scope of the application.

[0022] For the first solution provided by the application, please refer to Figure 1 The multifunctional two-dimensional spin logic gate device includes a substrate layer, a spin electron conduction layer, and a logic electrode layer which are sequentially stacked, the logic electrode layer includes a magnetic control area (labeled as HM1 in Figure 1 ), a first input area (labeled as SGS in Figure 1 ), and a second input area (labeled as HM2 in Figure 1The first input area is arranged in the center of the magnetic control area and the second input area, wherein the magnetic control area is grounded, the second input area is connected with an external voltage source, that is, the magnetic control area HM1 and the second input area HM2 form two electrode ends, the magnetic control area and the second input area are made of ferromagnetic semi-metal materials, the first input area is made of spin gapless semiconductor materials, and the multi-functional two-dimensional spin logic gate device is switched between the AND gate logic and the NOR gate logic by adjusting the magnetization direction of the magnetic control area.

[0023] In the embodiment, the substrate layer is composed of silicon and silicon dioxide which are stacked in sequence, and the silicon dioxide is arranged close to the spin electron conduction layer; the spin electron conduction layer is made of two-dimensional graphene material; the magnetic control area and the second input area are made of any one of Co2MnGa, CeAlSi and TaAs; and the first input area is made of any one of Mn2Si, Co3Sn2S2, Fe3Sn2 and CoSn.

[0024] For the second solution provided by the application, refer to Figure 4 The preparation method of the multi-functional two-dimensional spin logic gate device is used for preparing the multi-functional two-dimensional spin logic gate device in the first solution, and specifically includes the following steps:

[0025] S1, arranging two-dimensional graphene material on the surface of the silicon dioxide of the substrate layer as a spin electron conduction layer. In this step, any one of mechanical peeling, chemical vapor deposition, wet transfer and dry transfer method can be used to prepare the two-dimensional graphene material, which is arranged on the surface of the silicon dioxide of the substrate layer as the spin electron conduction layer, and is not limited herein.

[0026] S2, using a mask or a photoetching plate to grow ferromagnetic semi-metal on the surface of the spin electron conduction layer at intervals to form the magnetic control area and the second input area.

[0027] S3, using a mask to grow spin gapless semiconductor material in the channel between the magnetic control area and the second input area to form the first input area. In this step, any one of magnetron sputtering, electron beam evaporation or chemical vapor deposition method can be used to grow the ferromagnetic semi-metal in S2 step or the spin gapless semiconductor material in S3 step according to actual needs, and is not limited herein. In the embodiment, the ferromagnetic semi-metal in S2 step or the spin gapless semiconductor material in S3 step is prepared by magnetron sputtering, and the specific magnetron sputtering parameters are as follows: the sputtering system is exposed to the atmosphere for a short time, and is filled with dry nitrogen, the nitrogen flow is 20 sccm, and after 30 minutes of pumping, the sputtering chamber pressure can reach 9.0*10 - 4Pa, sputtering power is 90W, sputtering pressure is 0.4Pa, target and substrate distance is 8cm, substrate heating temperature is 800°, sputtering non-uniformity: ≤±5%.

[0028] Specifically, the logic operation mechanism of the multifunctional two-dimensional spin logic gate device in the application is described in detail:

[0029] For Figure 1 the state shown, set the magnetization direction upward to represent logic '1', and the direction downward to represent logic '0', the magnetic control area HM1 as the left electrode is grounded, the second input area HM2 as the right electrode is connected with the external voltage source, and the right electrode is externally connected with an alternating compensation voltage source V OFFS , a direct current source V DC , and a current measuring meter A, wherein the alternating compensation voltage source V OFFS is used to provide an external voltage to generate an alternating current to offset the current noise irrelevant to the spin current, the direct current source V DC and the current measuring meter A are spin current measuring devices.

[0030] As Figure 2 shown, an external magnetic field is applied to make the spin gapless semiconductor (i.e. the first input area SGS) and the ferromagnetic semimetal (including the magnetic control area HM1 and the second input area HM2) magnetize in the same direction, when a forward bias is applied, the Fermi level position of the spin gapless semiconductor is adjusted to be lower than that of the ferromagnetic semimetal, so that the spin-up electrons from the spin gapless semiconductor penetrate the spin electron conduction layer and complete the transition to the ferromagnetic semimetal, which is manifested as a conduction state; however, when a reverse bias is applied, the Fermi level position of the spin gapless semiconductor is higher than that of the ferromagnetic semimetal, thereby hindering the transition channel of any spin electron, which is manifested as a cutoff state. Therefore, when the magnetization directions of the spin gapless semiconductor and the ferromagnetic semimetal are the same, the forward conduction and reverse cutoff current control function from the spin gapless semiconductor to the ferromagnetic semimetal can be realized.

[0031] As Figure 3As shown, the external magnetic field is applied to reverse the magnetization of the spin gapless semiconductor (i.e. the first input region SGS) and the ferromagnetic semimetal (including the magnetic control region HM1 and the second input region HM2), and to adjust the Fermi level position of the spin gapless semiconductor to be lower than that of the ferromagnetic semimetal when a forward bias is applied. In this case, the transition channel of the electrons with either spin up or spin down is blocked, and no current can be formed, which is represented as a cutoff state. When a reverse bias is applied, the Fermi level position of the spin gapless semiconductor is higher than that of the ferromagnetic semimetal. In this case, the electrons with spin up can penetrate the spin electron conduction layer from the ferromagnetic semimetal and then transition into the spin gapless semiconductor, thereby forming a reverse current, which is represented as a conduction state. Therefore, when the magnetization directions of the spin gapless semiconductor and the semimetal are opposite, the reverse conduction from the spin gapless semiconductor to the ferromagnetic semimetal and the forward cutoff current control function can be realized.

[0032] Further, based on the above mechanism, the specific logic operation modes of the AND gate logic and the NAND gate logic of the multifunctional two-dimensional spin logic gate device in the present application are described and tested and verified.

[0033] In the present embodiment, it is assumed that Figure 1 The magnetic control region HM1 is the left electrode, and the second input region HM2 is the right electrode. A forward bias is applied from left to right, i.e. the forward bias direction is set from the magnetic control region HM1 to the second input region HM2, and vice versa.

[0034] 1) AND gate logic of the device. As shown in FIG. 2, the device is applied with a forward bias from left to right. When the magnetic moment direction of the magnetic control region HM1 (referred to as the control layer) is downward, the magnetic moment direction of the first input region SGS (referred to as the A layer) is upward, and the magnetic moment direction of the second input region HM2 (referred to as the B layer) is upward, the transition of the electrons with spin up from the magnetic control region HM1 to the first input region SGS is blocked, and the transition of the electrons with spin down from the first input region SGS to the second input region HM2 is also blocked. Therefore, no current can be formed, which is represented as a cutoff state. Figure 1 2) NAND gate logic of the device. As shown in FIG. 3, the device is applied with a forward bias from left to right. When the magnetic moment direction of the magnetic control region HM1 (referred to as the control layer) is upward, the magnetic moment direction of the first input region SGS (referred to as the A layer) is upward, and the magnetic moment direction of the second input region HM2 (referred to as the B layer) is downward, the transition of the electrons with spin up from the magnetic control region HM1 to the first input region SGS is blocked, and the transition of the electrons with spin down from the first input region SGS to the second input region HM2 is also blocked. Therefore, no current can be formed, which is represented as a cutoff state. Figure 3 It is known that, only when the magnetic moment direction of the first input region SGS (referred to as the A layer) is upward, the transition of the electrons with spin up from the magnetic control region HM1 to the first input region SGS can be realized due to the opposite magnetic moment directions of the magnetic control region HM1 and the first input region SGS. At the same time, when the magnetic moment directions of the central first input region SGS and the second input region HM2 (referred to as the B layer) are the same and both upward, the current can also be conducted. Therefore, under this magnetic moment direction combination, the current from the magnetic control region HM1 (control layer) to the second input region HM2 (B layer) can be conducted; otherwise, any other magnetic moment direction combination will result in the cutoff of the device current. Figure 2 It is known that, only when the magnetic moment direction of the first input region SGS (referred to as the A layer) is upward, the transition of the electrons with spin up from the magnetic control region HM1 to the first input region SGS can be realized due to the opposite magnetic moment directions of the magnetic control region HM1 and the first input region SGS. At the same time, when the magnetic moment directions of the central first input region SGS and the second input region HM2 (referred to as the B layer) are the same and both upward, the current can also be conducted. Therefore, under this magnetic moment direction combination, the current from the magnetic control region HM1 (control layer) to the second input region HM2 (B layer) can be conducted; otherwise, any other magnetic moment direction combination will result in the cutoff of the device current.

[0035] Table 1

[0036]

[0037] 2) NOR logic of the device. As shown in Fig. 1, the device is composed of a magnetic control layer HM1 (control layer), a first input layer SGS (A layer) and a second input layer HM2 (B layer). The magnetic control layer HM1 is located between the first input layer SGS and the second input layer HM2. The magnetic control layer HM1 is magnetized in the direction of the arrow, and the first input layer SGS and the second input layer HM2 are magnetized in the direction of the arrow. Figure 1 The positive bias is applied from left to right. When the magnetic moment of the magnetic control layer HM1 (control layer) is in the upward direction, and only when the magnetic moment of the first input layer SGS (A layer) is in the downward direction, the magnetic moment of the magnetic control layer HM1 and the first input layer SGS are opposite, and the current from the magnetic control layer HM1 to the first input layer SGS is turned on through the magnetic tunnel junction (MTJ) structure. Figure 3 It is known that the current from the magnetic control layer HM1 to the first input layer SGS can be turned on. At the same time, the magnetic moment of the central first input layer SGS is the same as that of the second input layer HM2 (B layer), and the current from the first input layer SGS to the second input layer HM2 is turned on through the magnetic tunnel junction (MTJ) structure. Figure 2 Therefore, under this combination of magnetic moment directions, the current from the magnetic control layer HM1 (control layer) to the second input layer HM2 (B layer) can be turned on. Otherwise, any other combination of magnetic moment directions will result in the cutoff of the device current. As described above, when an external magnetic field is applied in the upward direction, the magnetic moment of the magnetic control layer is in the upward direction, and the NOR logic function can be realized. The corresponding truth table is shown in Table 2, where the magnetic moment in the upward direction is represented as "1", the magnetic moment in the downward direction is represented as "0", the current conduction is represented as "1", and the current cutoff is represented as "0"; the NOR logic relationship is W=NOR(A+B), W represents the current output signal value, A represents the A layer logic value, and B represents the B layer logic value.

[0038] Table 2

[0039]

[0040] In the specific test verification process, taking the AND logic of the device as an example, the control layer is magnetized in the downward direction by the magnetic field generator, and the steps of observing the magnetic logic operation are as follows:

[0041] (1) Without changing the magnetization direction of the control layer, the A layer and the B layer are sequentially magnetized in the four directions represented in the truth table, i.e. "A layer↓, B layer↓", "A layer↓, B layer↑", "A layer↑, B layer↓", "A layer↑, B layer↑". For each magnetization combination, after magnetizing the A layer and the B layer in a specific direction, the compensation voltage source V OFFS is turned on, and the current measurement table is read. OFFS

[0042] (2) Keep the compensation voltage source turned on, and at the same time turn on the direct current source to provide V DCi ​= 0.1V, 0.2V, 0.3V, 0.4V, 0.5V, 0.6V, 0.7V, 0.8V, 0.9V, 1.0V, read the current value I of the current meter in turn i (i = 1, 2, 3,..., 10), the effective current related to the spin in each measurement is I REi = I i - I OFF .

[0043] (3) record the on or high resistance state of the effective current I REi , that is, the on and off state of the current output signal, and check whether it meets the corresponding relationship of the AND gate logic truth table, and observe its relationship with the size of the applied DC voltage source.

[0044] For the NAND gate logic test and verification steps of the device, similar to the AND gate logic test and verification steps of the device described above, they will not be described here. Through specific experimental verification, the truth relationship described in Tables 1 and 2 above can be obtained, thereby proving that the multifunctional two-dimensional spin logic gate device in the present application can switch between AND gate logic and NAND gate logic by adjusting the magnetization direction of the magnetic control region, and can realize two kinds of logic operations without introducing other devices.

[0045] Unlike the prior art, the present application provides a multifunctional two-dimensional spin logic gate device and a preparation method thereof, by providing a magnetic control region, a first input region and a second input region on the surface of a two-dimensional graphene material, and utilizing the material properties of ferromagnetic semimetals and spin gapless semiconductors, the device has both AND gate logic and NAND gate logic logic operation modes, and does not require the introduction of other devices, reducing the power consumption and delay when performing multiple logic operations.

[0046] The above-described embodiments only express the embodiments of the present application, which are described in detail and specifically, but should not be understood as limiting the scope of the patent. It should be noted that for ordinary skilled persons in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of protection of the present application. Therefore, the scope of protection of the present application patent should be subject to the appended claims.

Claims

1. A multi-functional two-dimensional spin logic gate device, characterized by, The substrate layer, the spin electron conducting layer and the logic electrode layer are sequentially stacked, the logic electrode layer comprises a magnetic control area, a first input area and a second input area which are arranged in a horizontal direction and spaced from each other, and the first input area is arranged in the center of the magnetic control area and the second input area; The magnetic control area and the second input area adopt a ferromagnetic semimetal material, the first input area adopts a spin gapless semiconductor material, and the multifunctional two-dimensional spin logic gate device is switched between the AND gate logic and the NOR gate logic by adjusting the magnetization direction of the magnetic control area; The substrate layer is sequentially stacked by silicon and silicon dioxide, and the silicon dioxide is arranged close to the spin electron conducting layer; The spin electron conducting layer adopts a two-dimensional graphene material; When the magnetic moment direction of the magnetic control area is downward under the positive bias direction from the magnetic control area to the second input area and an external magnetic field is applied, the multifunctional two-dimensional spin logic gate device is configured as the AND gate logic; When the multifunctional two-dimensional spin logic gate device is in the AND gate logic, the magnetic moment directions of the first input area and the second input area are both upward, and the multifunctional two-dimensional spin logic gate device is in a conductive state; otherwise, the multifunctional two-dimensional spin logic gate device is in a cut-off state; When the magnetic moment direction of the magnetic control area is upward under the positive bias direction from the magnetic control area to the second input area and an external magnetic field is applied, the multifunctional two-dimensional spin logic gate device is configured as the NOR gate logic; When the multifunctional two-dimensional spin logic gate device is in the NOR gate logic, the magnetic moment directions of the first input area and the second input area are both downward, and the multifunctional two-dimensional spin logic gate device is in a conductive state; otherwise, the multifunctional two-dimensional spin logic gate device is in a cut-off state.

2. The multi-functional two-dimensional spin logic device as claimed in claim 1, wherein, The magnetic control area is grounded, and the second input area is connected with an external voltage source.

3. The multi-functional two-dimensional spin logic device as claimed in claim 1, wherein, The magnetic control area and the second input area both adopt any one of Co2MnGa, CeAlSi and TaAs; The first input area adopts any one of Mn2Si, Co3Sn2S2, Fe3Sn2 and CoSn.

4. A method of manufacturing a multi-functional two-dimensional spin logic gate device as claimed in claims 1 to 3, characterized in that, Specifically comprising the following steps: S1, arranging a two-dimensional graphene material on the surface of the silicon dioxide of the substrate layer as the spin electron conducting layer; S2, using a mask or a photoetching plate to grow ferromagnetic semimetals on the surface of the spin electron conducting layer to form the magnetic control area and the second input area; S3, using a mask to grow a spin gapless semiconductor material in the channel between the magnetic control area and the second input area to form the first input area.

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