Double-edge quantizer and high-resolution time measurement quantization circuit

Abstract

The invention discloses a double-edge quantizer and a high-resolution time measurement quantization circuit. The double-edge quantizer comprises a band-enabled NAND gate RS latch LATCH1 and a band-enabled NOR gate RS latch LATCH2, the LATCH1 and the LATCH2 are connected in parallel, rising edge phase discrimination and falling edge phase discrimination can be carried out on input periodic signals respectively, and phase discrimination results are output. Compared with a conventional NAND gate RS latch, the LATCH1 is additionally provided with a tube P3 and a tube P4, a grid electrode of the tube P3 is connected with a power supply, and a grid electrode of the tube P4 is connected with an enable signal EN; compared with a conventional NOR gate RS latch, the LATCH2 is additionally provided with an N7 tube and an N8 tube, a grid electrode of a P8 is grounded, a grid electrode of the N7 tube is connected with an inverse signal ENB of an enable signal, and the P3 tube and the N8 tube play roles in balancing and symmetry of a circuit structure; and when the EN and the ENB are enabled, Q1B and Q2B signals are respectively preset as a high level and a low level.

Description

Technical Field

[0001] This invention belongs to the field of electronic components technology and relates to a double-edge quantizer and a high-resolution time measurement quantization circuit. Background Technology

[0002] Time-to-digital converters (TDCs) are electronic components that convert time information into digital information. As devices that convert from the time domain to the digital domain, they enable precise time measurement. This capability makes TDCs crucial in various fields requiring time information, such as time measurement of detectors in high-energy physics experiments (HEP), positron emission tomography (PET), and lidar ranging (LiDAR). Time resolution is a critical parameter for TDCs; achieving higher time resolution requires not only a suitable architecture but also more sensitive quantization circuits. TDC architectures can be broadly categorized into three types: analog-based TDCs, fully digital TDCs, and subgate-level delay-resolution TDCs. Within limited process dimensions, subgate-level delay-resolution TDCs can achieve higher time resolution. These designs are typically implemented using vernier schemes, such as... Figure 1 As shown. A vernier-type TDC typically contains two delay lines with different delay times. Each delay line consists of an integer (N) delay units (if forming a ring delay chain, N must be an odd number ≥ 3). The delay difference between the delay units of the two delay lines is defined as Δτ. They delay the start and stop signals respectively. The delay outputs of each stage are quantized by a phase discriminator to obtain digitized time information. Δτ is the time resolution of the TDC.

[0003] Existing vernier-type TDCs can implement phase detection using D flip-flops or RS latches. For D flip-flops, when the data arrives before the clock, the D flip-flop outputs a high level "1", and vice versa, it outputs a low level "0", thus realizing the function of a phase detector. However, since D flip-flops require a certain setup time and hold time (on the order of tens to hundreds of picoseconds, depending on the process dimensions), high-precision detection and identification cannot be performed for picosecond-level time measurement circuits.

[0004] A traditional RS latch can be constructed from two NAND gates or two NOR gates, and their circuits and truth tables are as follows: Figure 2 As shown. In this example, the outputs Q and QB of the two NAND gates (or NOR gates) are connected to the input of the other gate, and their remaining inputs are defined as SB and RB (or R and S), respectively. In a traditional RS latch, the input state "00" of the NAND gate and the input state "11" of the NOR gate are both disabled and cannot be used.

[0005] Current research typically uses traditional RS latches for phase discrimination, which can only achieve single-edge discrimination. TDCs using only single-edge phase discrimination generally employ two types of delay chains: one is a ring-shaped delay chain composed of differential circuits; the other is a delay chain constructed using buffers, which are implemented by two NOT gates or NAND gates (or other inverting logic gates). The former has a more complex circuit structure and higher power consumption; while the latter, due to the need for buffers as unit delays, achieves a unit delay difference of 2Δτ between the two delay chains under the same conditions compared to a single NOT gate, thus doubling the time resolution.

[0006] Traditional D flip-flops, when used as phase discriminators, have long setup and hold times, making them unsuitable for higher-resolution time-delay phase detection (TDC), such as TDCs below 10 picoseconds or even 5 picoseconds. Conventional RS phase detectors can only detect single edges, suitable for non-ring-type vernier delay chains, but their phase discrimination accuracy is insufficient, and the obtained time resolution is 2Δτ. However, for ring-type vernier delay chains, half of the oscillation cycle consists of a falling edge signal, which cannot be detected by a single RS phase detector. Although differential delay units can be used to select rising edges for phase detection, the power consumption will increase by at least double. Summary of the Invention

[0007] To address the high-precision quantization problem in existing high-time-resolution time-to-digital converters, the present invention aims to provide a double-edge quantizer and a high-resolution time measurement quantization circuit, suitable for time quantization circuits of high-resolution vernier-type TDCs, in order to solve the problems of insufficient accuracy of phase discriminators, insufficient time resolution, excessive power consumption, or unsuitability for ring-type vernier TDCs in existing solutions.

[0008] This invention proposes a dual-edge quantizer with enable for phase discrimination in a vernier TDC. It can be turned off when not in operation to save power, and its outputs are in a deterministic state when not in operation—Q1B and Q2B are preset to high and low levels respectively, ensuring the normal operation of subsequent phase detectors and reducing false positives. Furthermore, it can simultaneously perform rising-edge and falling-edge phase detection of periodic signals, broadening its application range. Q1B is the output of a NAND gate-structured RS phase detector, and Q2B is the output of a NOR gate-structured RS phase detector; both represent the phase detection results. LATCH1 consists of two NAND gates, and LATCH2 consists of two NOR gates. Both LATCH1 and LATCH2 are symmetrical structures. For LATCH1, signal X (signal Y) directly outputs signal Q1 (Q1B) through the NAND gates; for LATCH2, signal X (signal Y) directly outputs signal Q2 (Q2B) through the NOR gates.

[0009] This quantizer improves the input signal connection method of the original RS latch, resulting in faster switching response and a smaller phase discrimination capability.

[0010] The time resolution of the delay chain or ring-shaped delay chain type vernier TDC implemented based on this quantizer can be achieved at the same or even lower cost (such as area and power consumption).

[0011] Based on the enabled double-edge quantizer circuit proposed in this invention, a delay chain or ring-oscillating delay chain type vernier TDC is constructed for the decision circuit and the enable signal generation circuit for determining when the Y chain catches up with the X chain.

[0012] The technical solution of this invention is as follows:

[0013] A double-edge quantizer, characterized in that it includes an enabled NAND gate RS latch LATCH1 and an enabled NOR gate RS latch LATCH2, wherein LATCH1 and LATCH2 are connected in parallel.

[0014] LATCH1 includes a first NAND gate, a second NAND gate, PMOS transistors P3 and P4. One input of the first NAND gate is connected to signal X, and the other input is connected to the output signal of the second NAND gate. One input of the second NAND gate is connected to signal Y, and the other input is connected to the output signal of the first NAND gate. The gate and source of P3 are connected to the power supply, and the drain of P3 is connected to the signal output terminal of the first NAND gate. The gate of P4 is connected to the enable signal EN, the source is connected to the power supply, and the drain of P4 is connected to the signal output terminal of the second NAND gate. Signal X outputs signal Q1 through the first NAND gate, and signal Y outputs signal Q1B through the second NAND gate.

[0015] LATCH2 includes a first NOR gate, a second NOR gate, NMOS transistors N7 and NMOS transistors N8. One input of the first NOR gate is connected to signal Y, and the other input is connected to the output signal of the second NOR gate. One input of the second NOR gate is connected to signal X, and the other input is connected to the output signal of the first NOR gate. The gate of N7 is connected to the inverted enable signal ENB and the source is grounded. The drain of N7 is connected to the signal output terminal of the first NOR gate. The gate and source of N8 are grounded. The drain of N8 is connected to the signal output terminal of the second NOR gate. Signal X outputs signal Q2 through the second NOR gate, and signal Y outputs signal Q2B through the first NOR gate.

[0016] A phase detection method for a dual-edge quantizer, characterized in that the first NAND gate is composed of PMOS transistors P1, PMOS transistor P2, NMOS transistor N1, and NMOS transistor N2 connected together, and the second NAND gate is composed of PMOS transistors P5, PMOS transistor P6, NMOS transistor N3, and NMOS transistor N4.

[0017] The Q1B signal is preset to high level via EN, and the Q2B signal is preset to low level via ENB;

[0018] When EN is low, P4 is turned on and Q1B is pulled high. At this time, LATCH1 is in "sleep" state and does not work.

[0019] When EN is high, P4 is off, and the phase detection of inputs X and Y begins. During phase detection, if X and Y are initially low, P1, P6, N2, and N4 are on, while P2, P5, N1, and N3 are off, and Q1 = Q1B = high. Subsequently, if the X signal rises before the Y signal, P1 is off, N1 is on, Q1B remains unchanged, and Q1 changes from high to low without changing with subsequent changes in the Y signal. If the Y signal rises before the X signal, P6 is off, N3 is on, Q1 remains unchanged, and Q1B changes from high to low without changing with subsequent changes in the X signal, thus identifying the order of the rising edges of X and Y signals and realizing the rising edge phase detection function.

[0020] When EN is low, ENB is high, N3 is turned on, Q2B is pulled low, and LATCH2 is in "sleep" state and does not work.

[0021] When ENB is low, N3 is off, enabling normal phase detection. During phase detection, X and Y are initially high, N5, N10, P7, and P9 are on, and N6, N9, P8, and P10 are off. Initially, Q2 = Q2B = low. Subsequently, if X falls before Y, N5 is off, P8 is on, Q2B remains unchanged, and Q2 changes from low to high without changing with subsequent changes in the Y signal. If X falls before Y, N10 is off, P10 is on, Q2 remains unchanged, and Q2B changes from low to high without changing with subsequent changes in the Y signal. This distinguishes the order of the falling edges of X and Y signals, achieving the falling edge phase detection function.

[0022] A high-resolution time measurement quantization circuit is characterized by comprising two ring-resonant delay chains, denoted as slow chain X and fast chain Y; wherein both slow chain X and fast chain Y include N delay units, the delay time of the delay unit in slow chain X is τx, and the delay time of the delay unit in fast chain Y is τy, Δτ=τx-τy; a dual-edge quantizer is connected between the output of each stage of slow chain X and fast chain Y, and the output signal X of the i-th delay unit in slow chain X is... <i-1>The X signal is the output signal Y of the i-th delay unit in the fast chain Y, which is also the signal of the double-edge quantizer. <i-1>As the Y signal of the double-edge quantizer, i = 1, 2, ..., N, the signals Q1B and Q2B output by the double-edge quantizer connected to the i-th stage of the slow chain X and the fast chain Y are denoted as TC. <i-1>and TC<i-1+N> ;TC<i-1+N> The signal output terminal of ~TC<2N> is connected to the decision unit to convert TC.<i-1+N> The N-bit output of TC<2N> is sent to the decision unit for decision-making.

[0023] Preferably, N is an odd number ≥ 3.

[0024] A quantization method for a high-resolution time measurement quantization circuit, characterized in that the decision unit determines the quantization operation based on the input TC.<i-1+N> ~TC<2N> makes a decision. When all N bits of the signal are 0, it means that the phase difference between any position in the fast chain Y and the corresponding position in the slow chain X is less than 180°. If one bit of the output is set from 0 to 1, it means that the delay unit corresponding to that bit of the fast chain Y catches up with the slow chain X. At this time, it indicates that the circuit quantization is complete, and the temperature code at that moment is output. The enable signal EN is pulled low to stop the circuit from working.

[0025] The advantages of this invention are as follows:

[0026] This invention proposes an improved quantizer based on a conventional RS latch. It includes an enable signal that can preset the output node level, preventing misjudgments during non-operation, and can be turned off after measurement, reducing power consumption. It also improves the transistors connected to the signal input of the conventional RS latch, increasing the switching speed and improving phase detection accuracy. Furthermore, it incorporates both NAND and NOR gates for simultaneous rising and falling edge phase detection, broadening its applicability and further reducing time resolution. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of a classic vernier delay chain type TDC.

[0028] Figure 2 This is a schematic representation of a traditional RS flip-flop and its truth value.

[0029] Figure 3 This is a schematic diagram of the double-edge quantizer proposed in this invention and its working principle.

[0030] Figure 4 This is the core circuit diagram of a vernier delay chain based on a dual-edge quantizer. Detailed Implementation

[0031] The present invention will now be described in further detail with reference to the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0032] This invention proposes a quantizer for high-resolution, vernier-type TDC. Figure 3 Its circuit implementation consists of an enabled NAND gate RS latch (LATCH1) and an enabled NOR gate RS latch (LATCH2), which can perform rising edge and falling edge phase detection on the input periodic signal and output the phase detection result. LATCH1, compared to a conventional NAND gate RS latch... Figure 2 On the left side, the input signal transistors N2 and N4 are replaced with N1 and N3, improving the response speed of signal X or signal Y and enhancing the discrimination accuracy of the phase detector (in specific TDC applications, signal X represents the output signal of the delay unit in the slow chain, and signal Y represents the output signal of the delay unit in the fast chain; if used only as a phase detector, signals X and Y are the signals to be identified); P3 and P4 transistors are added, with P3's gate connected to the power supply and P4's gate connected to the enable signal EN; similarly, compared to the conventional NOR gate RS latch, LATCH2 replaces the input signal transistors P7 and P9 with P8 and P10, and adds N7 and N8 transistors, with P8's gate grounded and N7's gate connected to the inverted enable signal ENB, i.e., EN is passed through an NOT gate to obtain ENB. P3 and N8 transistors play a role in balancing and symmetry of the circuit structure. While enabling, EN and ENB preset the Q1B and Q2B signals to high and low levels, respectively. At the end of the measurement, the enable signal is invalidated, and the circuit stops working to save power.

[0033] The specific phase detection principle is as follows: (1) When EN is low, P4 is turned on and Q1B is pulled high. At this time, LATCH1 is in a "sleep" state and does not work. When EN is high, P4 is turned off and the phase of input X and Y is detected. (2) During phase detection, if X and Y are initially low, P1, P6, N2 and N4 are turned on, and P2, P5, N1 and N3 are turned off. Initially, Q1 = Q1B = high level. Subsequently, if the X signal rises before the Y signal, that is, it changes from low level to high level, P1 will turn off and N1 will turn on. As a result, Q1B remains unchanged, and Q1 changes from high level to low level, and does not change with the subsequent changes of the Y signal. If Y rises before X, P6 is turned off and N3 is turned on. As a result, Q1 remains unchanged, and Q1B changes from high level to low level, and does not change with the subsequent changes of the X signal. Based on this, the order of the rising edges of X and Y signals can be detected, and the rising edge phase detection function is realized. (3) When the enable signal EN is low, ENB is high, N3 is turned on, and Q2B is pulled low. At this time, LATCH2 is in a "sleep" state and does not work. When ENB is low, N3 is turned off, realizing normal phase detection. (4) During phase detection, X and Y are initially high, N5, N10, P7 and P9 are turned on, and N6, N9, P8 and P10 are turned off. Initially, Q2 = Q2B = low. Subsequently, if X appears with a falling edge before Y, that is, it changes from high to low, N5 is turned off, P8 is turned on, and Q2B remains unchanged. Q2 changes from low to high and does not change with subsequent changes in the Y signal. If X appears with a falling edge before Y, N10 is turned off, P10 is turned on, and Q2 remains unchanged. Q2B changes from low to high and does not change with subsequent changes in the Y signal. Based on this, the order of the falling edges of X and Y signals can be identified, realizing the falling edge phase detection function. P3 in LATCH1 and N8 in LATCH2 serve to balance and symmetry the circuit structure.

[0034] Using this dual-edge RS quantizer as a phase detector, a vernier delay chain is constructed. The core circuit is as follows: Figure 4 As shown, there are two ring-shaped delay chains—a slow chain X and a fast chain Y, each composed of N delay units (NAND gates) (N is an odd number ≥ 3). The delay units of chains X and Y have delays of τx and τy, respectively, with a difference of Δτ = τx - τy. Each stage output of the two chains is connected to a [connector / gate]. Figure 3 The dual-edge quantizer shown has an output signal X of the i-th delay unit in the slow chain X. <i-1>The output signal Y of the i-th delay unit in the fast chain Y <i-1>The X and Y signals, i = 1, 2…N, are respectively used as the dual-edge quantizers. The Q1B and Q2B of the dual-edge quantizers output TC respectively. <i-1>and TC<i-1+N> And TC<i-1+N> The N output bits (~TC<2N>) are fed into a decision gate for judgment. When all N output bits are 0, it means that the phase difference between any position in the fast chain Y and the corresponding position in the slow chain X is less than 180°. If any output bit is set from 0 to 1, it means that the delay unit corresponding to that bit in the fast chain Y has caught up with the slow chain X. In other words, the decision gate is equivalent to a 15-bit OR gate; when all 15 bits are 0, the output is 0; when the fast chain signal Y... <k-1>Catching up with the slow chain signal X <k-1>At this point, the k-th bit is set from 0 to 1, and the output of the decision unit is also set from 0 to 1. The temperature code TC stored at this time is...<i-1+N> ~TC<2N> is {0 (first bit) 0…1 (kth bit)…00 (Nth bit). The temperature code indicates that the fast chain signal catches up with the slow chain signal at the kth bit. This indicates that the circuit quantization is complete. After outputting the temperature code at this moment, pull down the enable signal EN to stop the circuit from working.

[0035] Although specific embodiments of the invention have been disclosed for illustrative purposes to aid in understanding and implementing the invention, those skilled in the art will understand that various substitutions, variations, and modifications are possible without departing from the spirit and scope of the invention and the appended claims. Therefore, the invention should not be limited to the content disclosed in the preferred embodiments, and the scope of protection claimed by the invention is defined by the claims.

Claims

1. A double-edge quantizer, characterized in that, It includes an enabled NAND gate RS latch LATCH1 and an enabled NOR gate RS latch LATCH2, with LATCH1 and LATCH2 connected in parallel. LATCH1 includes a first NAND gate, a second NAND gate, PMOS transistors P3 and P4. One input of the first NAND gate is connected to signal X, and the other input is connected to the output signal of the second NAND gate. One input of the second NAND gate is connected to signal Y, and the other input is connected to the output signal of the first NAND gate. The gate and source of P3 are connected to the power supply, and the drain of P3 is connected to the signal output terminal of the first NAND gate. The gate of P4 is connected to the enable signal EN, the source is connected to the power supply, and the drain of P4 is connected to the signal output terminal of the second NAND gate. Signal X outputs signal Q1 through the first NAND gate, and signal Y outputs signal Q1B through the second NAND gate. LATCH2 includes a first NOR gate, a second NOR gate, NMOS transistors N7 and NMOS transistors N8. One input of the first NOR gate is connected to signal Y, and the other input is connected to the output signal of the second NOR gate. One input of the second NOR gate is connected to signal X, and the other input is connected to the output signal of the first NOR gate. The gate of N7 is connected to the inverted enable signal ENB and the source is grounded. The drain of N7 is connected to the signal output terminal of the first NOR gate. The gate and source of N8 are grounded. The drain of N8 is connected to the signal output terminal of the second NOR gate. Signal X outputs signal Q2 through the second NOR gate, and signal Y outputs signal Q2B through the first NOR gate.

2. A phase detection method for a double-edge quantizer as described in claim 1, characterized in that, The first NAND gate is composed of PMOS transistors P1, PMOS transistor P2, NMOS transistor N1, and NMOS transistor N2 connected together, and the second NAND gate is composed of PMOS transistors P5, PMOS transistor P6, NMOS transistor N3, and NMOS transistor N4. The Q1B signal is preset to high level via EN, and the Q2B signal is preset to low level via ENB; When EN is low, P4 is turned on and Q1B is pulled high. At this time, LATCH1 is in "sleep" state and does not work. When EN is high, P4 is off, and the phase detection of inputs X and Y begins. During phase detection, if X and Y are initially low, P1, P6, N2, and N4 are on, while P2, P5, N1, and N3 are off, and Q1 = Q1B = high. Subsequently, if the X signal rises before the Y signal, P1 is off, N1 is on, Q1B remains unchanged, and Q1 changes from high to low without changing with subsequent changes in the Y signal. If the Y signal rises before the X signal, P6 is off, N3 is on, Q1 remains unchanged, and Q1B changes from high to low without changing with subsequent changes in the X signal, thus identifying the order of the rising edges of X and Y signals and realizing the rising edge phase detection function. When EN is low, ENB is high, N3 is turned on, Q2B is pulled low, and LATCH2 is in "sleep" state and does not work. When ENB is low, N3 is off, enabling normal phase detection. During phase detection, X and Y are initially high, N5, N10, P7, and P9 are on, and N6, N9, P8, and P10 are off. Initially, Q2 = Q2B = low. Subsequently, if X falls before Y, N5 is off, P8 is on, Q2B remains unchanged, and Q2 changes from low to high without changing with subsequent changes in the Y signal. If X falls before Y, N10 is off, P10 is on, Q2 remains unchanged, and Q2B changes from low to high without changing with subsequent changes in the Y signal. This distinguishes the order of the falling edges of X and Y signals, achieving the falling edge phase detection function.

3. A high-resolution time measurement quantization circuit, characterized in that, It includes two ring resonant delay chains, denoted as slow chain X and fast chain Y; wherein, slow chain X and fast chain Y each include N delay elements, the delay time of the delay element in slow chain X is τx, and the delay time of the delay element in fast chain Y is τy, Δτ=τx-τy; A double-edge quantizer as described in claim 1 is connected between the outputs of each stage of the slow chain X and the fast chain Y, wherein the output signal X of the i-th delay unit in the slow chain X is... <i-1>The X signal is the output signal Y of the i-th delay unit in the fast chain Y, which is also the signal of the double-edge quantizer. <i-1>As the Y signal of the double-edge quantizer, i = 1, 2, ..., N, the signals Q1B and Q2B output by the double-edge quantizer connected to the i-th stage of the slow chain X and the fast chain Y are denoted as TC. <i-1> and TC<i-1+N> ;TC<i-1+N> The signal output terminal of ~TC<2N> is connected to the decision unit to convert TC.<i-1+N> The N-bit output of TC<2N> is sent to the decision unit for decision-making.< / i-1> 4. The high-resolution time measurement quantization circuit according to claim 3, characterized in that, N is an odd number that is ≥3.

5. A quantization operation method for the high-resolution time measurement quantization circuit of claim 3, characterized in that, The decision-making device is based on the input TC.<i-1+N> ~TC<2N> makes a decision. When all N bits of the signal are 0, it means that the phase difference between any position in the fast chain Y and the corresponding position in the slow chain X is less than 180°. If one bit of the output is set from 0 to 1, it means that the delay unit corresponding to that bit of the fast chain Y catches up with the slow chain X. At this time, it indicates that the circuit quantization is complete, and the temperature code at that moment is output. The enable signal EN is pulled low to stop the circuit from working.

Images