Metastability error field correction circuit for successive approximation analog-to-digital converter

Abstract

A metastable error field correction circuit of a successive approximation analog-to-digital converter comprises an OR gate and an AND gate constituting an error correction module and an OR gate, a flip-flop and a delay unit constituting an error detection module, wherein: the logical input ends of the OR gate and the AND gate of the error correction module are connected with the output end of the comparator of the analog-to-digital converter to be tested, the logical output ends of the OR gate and the AND gate are respectively output to the OR gate of the error detection module to obtain a decision signal whether a metastable phenomenon occurs, the flip-flop generates an error pre-correction signal according to the decision signal and the clock signal of the comparator of the analog-to-digital converter to be tested, and the delay unit generates a pair of error correction signals which are mutually inverted according to the decision signal and the error pre-correction signal of the flip-flop and outputs them to the OR gate and the AND gate of the error correction module to generate a corrected signal and then outputs the corrected signal to a latch. The present application corrects the error caused by the metastable state of the comparator in the field, can determine that the error is less than the acceptable range, and the forced setting will not cause error, thereby significantly improving the reliability of the ADC and ensuring that the ADC can still maintain high precision and stability under variable input conditions.

Description

Technical Field

[0001] This invention relates to a technology in the field of analog-to-digital conversion, specifically a metastable error field correction circuit for a successive approximation analog-to-digital converter. Background Technology

[0002] Metastability refers to the phenomenon where, during a turntable transition, the output of a circuit may fluctuate between two logic levels and fail to determine its final output state for a certain period of time. When the comparator's input approaches its decision threshold, the output may become unstable between high and low states, introducing uncertainty. Errors caused by metastability are difficult to calibrate like other errors in the ADC transfer function, potentially leading to output errors and performance degradation. Existing methods can only detect metastability or correct for errors caused by metastability in synchronous ADCs through additional back-end encoding logic. Summary of the Invention

[0003] This invention addresses the problems of existing analog-to-digital converters (ADCs) being unable to directly correct for metastable errors at the bit where they occur, unable to determine which bit in a SAR cycle the metastable error occurs in, and unable to determine whether the remaining error at the end of the SAR is less than an acceptable range, which easily leads to potential conversion errors. It proposes a field-based metastable error correction circuit for a successive approximation ADC. This circuit corrects errors caused by comparator metastability in the field, ensuring that the error is less than an acceptable range. Forced setting will not result in an error, thus significantly improving the reliability of the ADC and ensuring that it maintains high accuracy and stability under varying input conditions.

[0004] This invention is achieved through the following technical solution:

[0005] This invention relates to a metastable error field correction circuit for a successive approximation analog-to-digital converter (ADC), comprising: a NOR gate and a NAND gate constituting an error correction module, a NOR gate constituting an error detection module, a flip-flop, and a delay unit, wherein: the logic input terminals of the NOR gate and the NAND gate of the error correction module are connected to the output terminals of the comparator of the ADC under test; the logic output terminals of the NOR gate and the NAND gate are respectively output to the NOR gate of the error detection module to obtain a decision signal indicating whether metastability has occurred; the flip-flop generates an error pre-calibration signal based on the decision signal and the clock signal of the comparator of the ADC under test; the delay unit generates a pair of inverted error correction signals based on the decision signal and the error pre-calibration signal of the flip-flop and outputs them to the NOR gate and the NAND gate of the error correction module to generate a corrected signal, which is then output to a latch.

[0006] Technical effect

[0007] This invention generates a fixed detection time window through a comparator clock and a delay unit. The error correction signal generated by the delay unit forces the outputs of the NOR and NAND gates of the error correction module to produce an output result, skipping the comparison process of this data bit, allowing the asynchronous successive approximation logic to continue. Compared to existing technologies, this invention effectively eliminates errors caused by metastability. If metastability does not occur, the correction process will not affect normal SAR operation, thus ensuring the reliability and stability of the system in high-speed and high-precision applications. Attached Figure Description

[0008] Figure 1 This is a circuit diagram of the present invention;

[0009] Figure 2 for Figure 1 Sequence diagram. Detailed Implementation

[0010] like Figure 1 As shown, this embodiment relates to a metastable error field correction circuit for a successive approximation analog-to-digital converter (ADC). The circuit includes: a NOR gate and a NAND gate constituting an error correction module; a NOR gate and a D flip-flop constituting an error detection module; and a delay unit. The logic inputs of the NOR and NAND gates in the error correction module are connected to the output of the comparator of the ADC under test. The logic outputs of the NOR and NAND gates are respectively output to the NOR gate of the error detection module to obtain a decision signal `cmp_finish` indicating whether metastability has occurred. The clock signal `clk_cmp` of the comparator of the ADC under test serves as the clock signal of the D flip-flop. The decision signal `cmp_finish` serves as the reset signal of the D flip-flop. A positive power supply serves as the D input signal of the D flip-flop. The output Q of the D flip-flop outputs an error pre-calibration signal `meta_pre`. The delay unit generates two opposite error correction signals `meta_pos` and `meta_neg` based on the error pre-calibration signal `meta_pre` and the decision signal `cmp_finish`. The error correction signal `meta_pos` and the comparator output D... OUTORI After being corrected by an OR gate, the signal D is generated. OUT+ The latch output to the CDAC, the error correction signal meta_neg, and the comparator output D OUTORI After being generated and corrected by a NAND gate, signal D OUT- The latch outputs to the CDAC.

[0011] When the decision signal cmp_finish is low, the error precalibration signal meta_pre is reset to 0. When the decision signal cmp_finish is high, the error precalibration signal meta_pre will become 1 when the first rising edge of clk_cmp arrives.

[0012] When the decision signal cmp_finish is low, the error correction signal meta_pos is reset to 0 and meta_neg is reset to 1; when the decision signal cmp_finish is high, the error correction signal meta_pos is the signal after the error pre-calibration signal meta_pre is delayed.

[0013] The initial state of the clock signal clk_cmp is 0, and the comparator outputs D. OUTORI The initial state is 1 / 1, the initial state of the decision signal cmp_finish is 1, and the initial states of the error correction signals meta_pos and meta_neg are 0 and 1, respectively.

[0014] The ratio of NMOS to PMOS transistors in the comparator output stage needs to be set so that the PMOS drive capability is stronger than the NMOS, ensuring the comparator output D. OUTORI It is preferred to pull it high to avoid comparator output D. OUTORI The comparator may enter a 0 / 0 state during operation.

[0015] like Figure 2 The diagram shows the timing sequence for error correction due to metastability. When the comparator clock clk_cmp rises, the comparator begins comparison, and simultaneously, the D flip-flop in the error detection module is triggered, flipping its output from 0 to 1. This signal is then transmitted through a delay unit. The time range for metastability detection is t. meta When the comparator exhibits metastability, i.e. at t meta No clear output was produced, the decision signal cmp_finish remained high, the delay unit was not reset, the positive error correction signal meta_pos was pulled high, forcing the NOR gate output D to be... OUT+ Pulled to 0; the inverting error correction signal meta_neg is pulled low, forcing the NAND gate output D to be... OUT- The value is pulled to 1. Therefore, cmp_finish becomes 0, resetting the D flip-flop and delay unit, meta_pos becomes 0 again, and meta_neg becomes 1 again, awaiting the comparison in the next cycle. These operations effectively eliminate the metastability problem.

[0016] When the comparator does not exhibit metastability, i.e. during the metastability detection time t meta The system produces a clear output result. The decision signal cmp_finish will become 0, the D trigger and delay unit will be reset, meta_pos will remain 1, and meta_neg will remain 0. This will not affect normal SAR operation.

[0017] Through specific practical experiments, the output results of the ADC were continuously tested multiple times.27 The spectral performance of the ADC does not show significant degradation when analyzing individual data points, indicating the absence of metastability issues and demonstrating the high overall reliability of the ADC. In summary, this invention enables real-time correction during normal ADC operation and handles metastability problems in real time, improving the overall reliability of the system and ensuring the output stability of the ADC under different operating conditions. This invention effectively eliminates the uncertainty caused by metastability through simple logical assignment operations without requiring complex back-end encoding logic; this simplification makes the design more efficient.

[0018] The above-described specific implementations can be partially adjusted by those skilled in the art in different ways without departing from the principles and purpose of the present invention. The scope of protection of the present invention is defined by the claims and is not limited to the above-described specific implementations. All implementation schemes within the scope of the claims are bound by the present invention.

Claims

1. A metastable error field correction circuit for a successive approximation analog-to-digital converter, characterized in that, include: The error correction module consists of a NOR gate and a NAND gate, and the error detection module consists of a NOR gate, a flip-flop, and a delay unit. The logic inputs of the NOR gate and NAND gate of the error correction module are connected to the output of the comparator of the analog-to-digital converter under test. The logic outputs of the NOR gate and NAND gate are respectively output to the NOR gate of the error detection module to obtain a decision signal for whether metastability has occurred. The flip-flop generates an error pre-calibration signal based on the decision signal and the clock signal of the comparator of the analog-to-digital converter under test. The delay unit generates a pair of mutually inverted error correction signals based on the decision signal and the error pre-calibration signal of the flip-flop and outputs them to the NOR gate and NAND gate of the error correction module to generate the corrected signal and then outputs it to the latch. The ratio of NMOS and PMOS transistors in the comparator output stage needs to be set so that the PMOS size is stronger, to ensure that the comparator output does not enter a 0 / 0 state during comparator operation.

2. The metastable error field correction circuit for a successive approximation analog-to-digital converter according to claim 1, characterized in that, The initial state of the clock signal clk_cmp is 0, and the comparator outputs D. OUTORI The initial state is 1 / 1, the initial state of the decision signal cmp_finish is 1, and the initial states of the error correction signals meta_pos and meta_neg are 0 and 1, respectively.

3. The metastable error field correction circuit for a successive approximation analog-to-digital converter according to claim 1, characterized in that, The trigger mentioned is a D trigger.

4. A correction method for the circuit according to any one of claims 1-3, characterized in that, When the rising edge of the comparator clock arrives, the comparator starts comparing and triggers the flip-flop in the error detection module, causing the output to toggle from 0 to 1. When the comparator does not produce a clear output within the metastability detection time range, i.e., metastability occurs, the decision signal remains high, meaning the delay unit is not reset. The positive error correction signal is pulled high, forcing the NOR gate output to 0; the negative error correction signal is pulled low, forcing the NAND gate output to 1. The decision signal becomes 0, resetting the flip-flop and delay unit. The positive error correction signal becomes 0 again, and the negative error correction signal becomes 1 again, waiting for the comparison in the next cycle to eliminate metastability.

5. The correction method according to claim 4, characterized in that, When the comparator does not exhibit metastability, i.e., when a definite output result is produced within the metastability detection time, the decision signal will become 0, resetting the flip-flop and delay unit. The positive error correction signal will remain at 1, and the negative error correction signal will remain at 0.

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