Time residual processing circuit, correlation multi-sampling method, SS-ADC circuit and chip

Abstract

The invention relates to the field of integrated circuits, in particular to a time residual processing circuit, a correlation multi-sampling method, an SS-ADC circuit and a chip. And the time residual processing circuit is used for extracting a residual signal of a quantization result according to the output of the comparator in the SS-ADC and completing the quantization of a time residual. The time residual processing circuit is composed of a D trigger, a NOR gate, two resistors with the same resistance value, four NMOS tubes, two capacitors with different capacitance values and a comparator. The pulse width of a residual signal is subjected to rate stretching through a charging and discharging channel formed by the two capacitors. According to the related multi-sampling method and the circuit thereof, the ramp signal type and the repeated sampling frequency are adjusted according to the light intensity state of an input signal in the pixel signal quantization stage, and the time residual error of the process is quantized to correct the output of a comparator. According to the invention, the problems of insufficient precision and large power consumption of an SS-ADC adopted by an existing CIS circuit are solved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a time residual processing circuit, an optical intensity adaptive correlation multisampling method, an SS-ADC circuit, and a CIS chip. Background Technology

[0002] With the continuous advancement of CMOS image sensor (CIS) technology, the performance requirements for CIS are also gradually increasing. High-precision acquisition and conversion of pixel voltage is a key factor determining the performance of an image sensor system; the speed and accuracy of the CIS directly constrain the quality of the final image. Single-slope ADCs are widely used in high-performance CISs due to their inherent low power consumption and high linearity. However, in current research on high-performance ADCs, the presence of noise and the inherent asynchronicity of the SS-ADC quantization process—that is, the comparator flip point not always aligning with the clock edge—severely affect the improvement of the readout circuit's quantization accuracy. The error caused by this asynchrony is called the time residual. Therefore, processing the noise of the time residual is of paramount importance to ensure that the quantization result of the readout circuit is closer to the actual pixel voltage value.

[0003] In existing technologies, time residual quantization is generally implemented using a time-to-digital converter (TDC). For example, Deyan Levski et al. used a hybrid column-parallel TDC interpolated SS-ADC with digital delay unit feedback to quantize time residuals, achieving finer quantization. However, this circuit design introduces complex redundant correction circuitry, leading to increased power consumption. Overall, current research on low-noise, high-precision pixel quantization still faces two main problems: first, existing methods often do not employ optimal ramp generation methods when performing Correlated Multiple Sampling (CMS) operations, resulting in increased power consumption and reduced frame rate; second, existing CMS methods do not consider time residuals, leading to significant deviations between the quantized results and the actual voltage values. Summary of the Invention

[0004] To address the issues of insufficient accuracy and high power consumption in existing SS-ADCs used in CIS circuits, this invention provides a time residual processing circuit, an intensity-adaptive correlation multisampling method, an SS-ADC circuit, and a CIS chip.

[0005] The technical solution provided by this invention is as follows: A time residual processing circuit is used to extract the residual signal TR of the quantization result based on the quantization result Comp_out and the clock CLK output by the comparator in the SS-ADC, and generate its stretching signal T_stretch.

[0006] The time residual processing circuit includes one D flip-flop D1, one NOR gate NOR1, two resistors R1 and R2 of the same value, four NMOS transistors N1~N4, two capacitors C1 and C2 of different values, and one comparator OPA1. The clock input of D1 is connected to CLK, its input D is connected to one of the inputs of NOR1 and then to Comp_out, and its inverting output is... Connect to the other input terminal of NOR1. The output terminal of NOR1 is connected to the gate of N1 and used to output the residual signal TR. One end of R1 and R2 is connected to VDD, and the other end of R1 is connected to the drain of N1; the other end of R2 is connected to the drain of N2. The source of N1 is connected to the drain of N3, one end of C1, and the non-inverting input terminal of OPA1, and the connection point is denoted as Vn; the source of N2 is connected to the drain of N4, one end of C2, and the inverting input terminal of OPA1, and the connection point is denoted as Vp. The other ends of C1 and C2 are connected to the sources of N3 and N4 and then to VSS; the gate of N2 is connected to the residual enable signal TR1; the gate of N3 is connected to the input layer reset signal S1; the gate of N4 is connected to the reference side reset signal S2; the non-inverting output terminal of OPA1 outputs T_stretch.

[0007] Wherein, when the capacitance of C2 is N times that of C1, the pulse width of the output stretch signal T_stretch is N times that of the residual signal TR.

[0008] As a further improvement of the present invention, in the time residual processing circuit, the TR signal flips from low to high when Comp_out flips from high to low, and flips back from high to low when the next clock arrives. TR1 flips from low to high each time residual quantization begins, and flips back from high to low after residual quantization ends. S1 is high before the SS-ADC starts quantizing the reset signal and pixel signal, and low at other times. S2 is high before the SS-ADC starts quantizing the reset signal and pixel signal, and high before the SS-ADC performs the second repetition quantization of the reset signal, and low at other times.

[0009] The present invention also includes a light intensity adaptive correlation multisampling method, which includes a reset signal quantization stage and a pixel signal quantization stage, and includes the following steps: S1: During the reset signal quantization stage, the reset signal is repeatedly quantized n times using a standard ramp signal; and the average of the quantization results of the n repeated quantizations is taken as the quantization result Tbase of the reset signal.

[0010] Meanwhile, after the first reset signal quantization and after the nth reset signal quantization, the time residual processing circuit described above is used to quantize the single reset residual T1 and the full reset residual T2, respectively.

[0011] S2: In the pixel signal quantization stage, the pixel signal is first quantized using a full-range ramp, and the pixel signal is divided into strong light state, weak light state and low light state according to the initial quantization result T-comp.

[0012] (1) Under strong light conditions, the initial quantization result is used as the quantization result Tpixel of the pixel signal.

[0013] (2) In low light conditions, continue to generate m half-range small ramp signals to repeatedly quantize the pixel signal, and take the average of the quantization results of the first quantization and the m repeated quantizations as the quantization result Tpixel of the pixel signal.

[0014] (3) In low light conditions, continue to generate m quarter-range small ramp signals to repeatedly quantize the pixel signal, and take the average of the quantization results of the first quantization and the m repeated quantizations as the quantization result Tpixel of the pixel signal.

[0015] Meanwhile, after the pixel signal quantization is completed, the time residual processing circuit described above is used to quantize the entire pixel residual T3.

[0016] S3: Combining the light intensity state of the pixel signal, Tbase is corrected using T1 or T2, and Tpixel is corrected using T3, including: (i) Under strong light conditions, the final quantization result of the reset signal is Tbase+T1, and the final quantization result of the pixel signal is Tpixel+T3.

[0017] (ii) Under weak light and low light conditions, the final quantization result of the reset signal is: The final quantization result of the pixel signal is .

[0018] As a further improvement of the present invention, in step S2, the method for identifying the light intensity state of the pixel signal based on the initial quantization result T-comp is as follows: (1) When the T-comp flip occurs when the amplitude of the full-range ramp signal drops to 3 / 4A max Previously, this indicated that the pixel signal was in a dim state.

[0019] (2) When the T-comp flip occurs when the amplitude of the full-range ramp signal drops to 3 / 4A max and 1 / 2A maxWhen the value is between 0 and 1, it indicates that the pixel signal is in a weak light state.

[0020] (3) When the T-comp reversal occurs when the amplitude of the full-range ramp signal drops to 1 / 2A max Then, it indicates that the pixel signal is in a strong light state.

[0021] Among them, A max This represents the initial amplitude of the ramp signal across the full range.

[0022] This invention also includes an SS-ADC circuit, which uses the aforementioned light intensity adaptive correlation multiple sampling method to quantize the light sensing signal output by the pixel unit; the light sensing signal includes a reset signal and a pixel signal. The SS-ADC circuit provided by this invention includes: a ramp generator, a comparator, a light intensity recognition module, a residual generation module, and a correction module.

[0023] The ramp generator is used to continuously generate n standard range ramp signals during the reset signal quantization stage, and to first generate a full range ramp signal during the pixel signal quantization stage. Then, based on the light intensity status signal, it can choose to end the output after the full range ramp or continuously generate m half-range or quarter-range small ramp signals.

[0024] The comparator's two input ports are connected to the pixel unit and the output signal of the ramp generator, respectively. After comparing the two, it outputs the quantization result Comp_out. The quantization result of the initial quantization of the pixel signal is denoted as T-comp.

[0025] The light intensity recognition module is used to identify the light intensity state of the pixel signal based on T-comp and output a corresponding 2-bit light intensity code sel1sel0; sel1sel0 being 11, 10 and 00 respectively correspond to strong light state, weak light state and low light state.

[0026] The residual generation module uses the time residual processing circuit described above, and is used to generate three types of residuals T1, T2, and T3 based on Comp_out and CLK during the reset signal quantization stage and the pixel signal quantization stage.

[0027] The correction module is used to obtain the output of the comparator, and then, in combination with the identified light intensity code, to adaptively correct the quantization results of the reset signal quantization stage and the pixel signal quantization stage using T1, T2, and T3, thereby obtaining the final quantization result after eliminating the residuals.

[0028] As a further improvement of the present invention, the ramp generator adopts an output adjustable ramp generation circuit, and combines optical intensity encoding to sequentially generate corresponding standard range ramp signals, full range ramp signals and small ramp signals in different clock cycles.

[0029] Alternatively, the ramp generator includes four ramp generation circuits for generating standard-range ramp signals, full-range ramp signals, half-range ramp signals, and quarter-range ramp signals, respectively, as well as a selector. The selector is used to sequentially select each ramp generation circuit in different clock cycles in conjunction with optical intensity encoding, thereby outputting the required standard-range ramp signal, full-range ramp signal, and small ramp signal.

[0030] As a further improvement of the present invention, the light intensity recognition module includes two latches LAT1 and LAT2; two inverters INV1 and INV2; and two voltage converters LS1 and LS2. The circuit connection is as follows: LAT1's G terminal is connected to the pre-encoded first index signal U1, its D terminal is connected to T-comp, and its Q terminal is connected to the output of INV1 and the input signal terminal of LS1. The reference signal terminal of LS1 is connected to the output of INV1; the output of LS1 is used to output sel1. LAT2's G terminal is connected to the pre-encoded second index signal U0, its G terminal is connected to T-comp, and its D terminal is connected to the input of INV2 and the input signal terminal of LS2. The reference signal terminal of LS2 is connected to the output of INV2; the output of LS2 is used to output sel0.

[0031] Among them, the amplitude of U1 in the full-range ramp signal ranges from A max Reduced to 1 / 2A max The signal is high during the specified time period and low during the rest of the time period; the amplitude of U0 in the full-range ramp signal ranges from A... max Reduced to 3 / 4A max The voltage level is high during certain periods and low during other periods.

[0032] As a further improvement of the present invention, in the light intensity recognition module, when T-comp is high, sel1 and sel0 are dynamically adjusted according to U1 and U0 respectively; when T-comp changes from high to low, the circuit latches the level state of U1 and U0 at this time, and keeps sel1 and sel0 in the latched state until T-comp flips back to high.

[0033] As a further improvement of the present invention, the capacitance value of C2 is 16 times that of C1, N=16; the reset signal is quantized 4 times, n=4; in low light and low light conditions, the pixel signal is quantized 4 times, m=3.

[0034] The present invention also includes a CIS chip that employs the SS-ADC circuit described above.

[0035] The present invention has the following beneficial effects: This invention first provides a time residual processing circuit, which extracts the time residual generated during the quantization of the reset signal and pixel signal based on the comparator output during SS-ADC operation, and performs pulse width stretching on the output to achieve accurate quantization. Furthermore, during the quantization stage of the reset signal and pixel signal, this invention proposes for the first time a novel CMS strategy that identifies three light intensity states of the input signal based on the initial quantization result of the pixel signal, and employs differentiated ramp signals and repeated sampling times. Simultaneously, this invention also adaptively corrects the voltages of the reset signal and pixel signal based on the quantized time residual according to the light intensity state. Based on the aforementioned novel CMS operation logic, this invention also designs a corresponding SS-ADC circuit. The novel structure and principle of the SS-ADC provided by this invention can significantly improve the output accuracy of the circuit while reducing power consumption and balancing noise and speed. Attached Figure Description

[0036] Figure 1 This is a quantization timing diagram for the TCMS operation in a traditional SS-ADC.

[0037] Figure 2 This is a state diagram of the time residual generated during TCMS operation in a traditional SS-ADC.

[0038] Figure 3 This is a circuit diagram of the time residual processing circuit provided in Embodiment 1 of the present invention.

[0039] Figure 4 This is a flowchart of the light intensity adaptive correlation multisampling method provided in Embodiment 2 of the present invention.

[0040] Figure 5 This is a schematic diagram illustrating the principle of dividing illumination states in Embodiment 2 of the present invention.

[0041] Figure 6 This is an architecture diagram of the SS-ADC using an intensity-adaptive correlation multisampling method provided in Embodiment 3 of the present invention.

[0042] Figure 7 This is a circuit diagram of the light intensity recognition module in the SS-ADC of Embodiment 3 of the present invention.

[0043] Figure 8 This is a schematic diagram of the light intensity encoding signal in the light intensity recognition module of Embodiment 3 of the present invention.

[0044] Figure 9 This is a timing diagram of the signal used in the performance testing experiment to quantize the reset signal for weak light using the SS-ADC of this invention.

[0045] Figure 10 This is a simulation diagram of the column power consumption of the SS-ADC of this invention during performance testing experiments.

[0046] Figure 11 The simulation diagram shows the equivalent input noise of the SS-ADC of this invention at three process angles: tt, ss, and ff, during the performance test experiment. Detailed Implementation

[0047] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0049] Example 1 When quantizing the light-sensing signals output by each pixel unit in the CMOS circuit, the SS-ADC in the CIS chip typically uses the Traditional Correlation Multiple Sampling (TCMS) technique. The TCMS technique reduces random noise by averaging multiple samples, thereby improving the imaging quality of the image sensor. Figure 1 This is the quantization timing diagram for TCMS. It samples the reset signal and pixel signal output by the pixel unit multiple times using a standard ramp signal and a full-range ramp signal, respectively. The quantization results after multiple repeated samplings are then averaged, effectively reducing random noise such as thermal noise, 1 / f noise, and RTS. As the number of samplings increases, thermal noise is reduced to some extent, and the analog voltage of the quantized signal becomes closer to the actual voltage value. However, with the increase in the number of samplings, the power consumption of the column-level circuit also increases exponentially, leading to a significant decrease in the circuit's frame rate.

[0050] Reducing noise in the readout circuit helps make the quantization result closer to the actual pixel voltage value. However, in the SS-ADC quantization process, a counter is usually controlled by CLK to record the duration of the comparator's high level, thus reflecting the analog voltage. However, the D flip-flops in the counter are mostly edge-triggered, and the comparator's toggle does not always coincide with the clock edge. In this case, the asynchronous toggle of the comparator introduces a time residual and causes a non-negligible error between the final determined analog voltage and the actual voltage.

[0051] Specifically, Figure 2This is the signal flow graph of the SS-ADC when performing CMS operation. As can be seen from the graph, since the comparator toggle time does not always overlap with the clock edge, a time residual is introduced each time the reset signal and pixel signal are repeatedly sampled. These time residuals introduced when the SS-ADC quantizes the reset signal and pixel signal voltages will reduce the accuracy of the output quantization result.

[0052] To address the aforementioned time residual problem in SS-ADC operation, this embodiment provides a time residual processing circuit. This circuit extracts the residual signal TR from the quantization result (Comp_out) and clock (CLK) output by the comparator in the SS-ADC, and generates a stretched signal T_stretch for TR. It is particularly important to emphasize that because the time residuals generated during each repeated sampling and quantization process of the reset signal and pixel signal are very short, potentially even lower than the resolution of some conventional TDCs, traditional TDCs typically cannot achieve high-precision quantization of the time residuals.

[0053] Based on this, such as Figure 3 As shown, the time residual processing circuit provided in this embodiment includes one D flip-flop D1, one NOR gate NOR1, two resistors R1 and R2 of the same value, four NMOS transistors N1~N4, two capacitors C1 and C2 of different values, and one comparator OPA1. The clock input of D1 is connected to CLK, the input of D1 (D terminal) is connected to one of the inputs of NOR1 and then to Comp_out, and the inverting output of D1 (… The other input terminal of NOR1 is connected to the gate of NOR1. The output terminal of NOR1 is connected to the gate of N1 and used to output the residual signal TR. One end of R1 and R2 is connected to VDD, and the other end of R1 is connected to the drain of N1; the other end of R2 is connected to the drain of N2. The source of N1 is connected to the drain of N3, one end of C1, and the non-inverting input terminal of OPA1, and the connection point is denoted as Vn; the source of N2 is connected to the drain of N4, one end of C2, and the inverting input terminal of OPA1, and the connection point is denoted as Vp. The other ends of C1 and C2 are connected to the sources of N3 and N4 and then to VSS; the gate of N2 is connected to the residual enable signal TR1; the gate of N3 is connected to the input reset signal S1; the gate of N4 is connected to the reference side reset signal S2; the non-inverting output terminal of OPA1 outputs T_stretch.

[0054] exist Figure 3 In the time residual processing circuit shown, the D flip-flop D1 and the NOR gate NOR1 constitute a time residual extraction circuit, which is used to process the two signals based on the phase relationship between the clock signal CLK and the quantization result Comp_out output by the comparator, and then synthesize the time residual representation. Figure 2The residual signal TR in the time residual is specifically defined as follows: the TR signal flips from low to high when Comp_out transitions from high to low, and then flips back to low when the next clock arrives. Each high-level signal segment in the TR signal corresponds to a time residual, and the pulse width of that high-level segment is the duration of the time residual. The remaining components together form a signal stretching circuit. In the signal stretching circuit, R1, R2, N1~N4, C1, and C2 form two mirror-symmetrical charging and discharging channels. One charging and discharging channel charges C1 according to TR and pulls up the level of Vn. The other charging and discharging channel charges C2 according to the residual enable signal TR1 and pulls up the level of Vn. In particular, in this embodiment, the capacitance values ​​of C1 and C2 in the two charging and discharging channels are different; specifically, the capacitance value of C2 is N times that of C1. Therefore, under the condition that the initial voltages Vn and Vp are the same, when N1 and N2 are turned on and N3 and N4 are turned off to charge C1 and C2, assuming that the charging time on the C1 side is the time residual Δt in TR, the charging time on the C2 side needs to be N times that on the C1 side, i.e., NΔt, in order to make the voltage of Vp equal to that of Vn. In this state, this embodiment connects the two input terminals of OPA1 to Vp and Vn respectively, and quantizes the charging time on the C2 side, that is, to stretch and output Δt. That is, when the capacitance value of C2 is N times that of C1, the pulse width of the output stretch signal T_stretch is N times that of the residual signal TR.

[0055] Specifically, in practical applications, the operation logic of the time residual processing circuit to stretch TR and output the stretching signal T_stretch is as follows: First, set S1 and S2 to high level simultaneously to control N3 and N4 to conduct, so that the upper plates of C1 and C2 are grounded and discharged, thereby resetting Vn and Vp to low level.

[0056] Next, S1 and S2 are set to low level to close the discharge channel. Then, when the TR signal flips from low to high level (i.e., the time residual arrives), N1 turns on. At this time, the power supply charges C1, and the Vn voltage rises. Simultaneously, TR1 also flips from low to high level, and N2 turns on. The power supply charges C2, and the Vp voltage rises. Since the capacitance values ​​of C1 and C2 are different (C1 < C2), the Vn voltage rise rate is greater than Vp. Therefore, while TR and TR1 are both high, the Vp voltage is always less than Vn, and the stretching signal T_stretch output by OPA1 is high.

[0057] When the TR signal flips from high to low (i.e., the time residual ends), charging on the C1 side ends, with a total charging time of Δt. At this time, the voltage of Vn is still higher than Vp and no longer increases. Meanwhile, TR1 remains high, continuing to charge the C2 side. The voltage of Vp continues to rise, but still does not exceed the node voltage of Vn. During this process, T_stretch remains high.

[0058] Based on the capacitance relationship between C1 and C2, the charging rate on the Vn side is N times that on the Vp side. When the high-level state of TR1 lasts for NΔt, the voltage of Vp will be equal to that of Vn. At this time, the output of T_stretch flips, changing from high to low. Therefore, throughout the process, the pulse width of the time residual in the TR signal is Δt, while the pulse width of the stretching signal T_stretch is NΔt. The stretching circuit, by controlling the ratio of capacitors C2 and C1 to N, stretches the pulse width of the time residual in TR by a factor of N and outputs it as the stretching signal T_stretch.

[0059] Finally, when T_stretch transitions from high to low, the time residual quantization task ends, and TR1 is set back to low. Then, when the next round of time residual quantization begins, S1 and S2 are set high again to reset the levels of Vn and Vp.

[0060] Based on the above circuit principles, in the time residual processing circuit provided in this embodiment, TR1 flips from low to high level each time residual quantization begins, and flips back from high to low level after residual quantization is completed. S1 is high before the SS-ADC starts quantizing the reset signal and pixel signal, and low at other times. S2 is high before the SS-ADC starts quantizing the reset signal and pixel signal, and high before the SS-ADC performs the second repetition quantization of the reset signal, and low at other times.

[0061] The purpose of setting the signal difference between S2 and S1 is to extract and quantize the signal residuals of single quantization and multiple quantizations separately when the SS-ADC performs CMS operation on the reset signal. This part will be introduced in detail later.

[0062] Example 2 exist Figure 1 and Figure 2Building upon the traditional correlation multiple sampling (CMS) technique, this embodiment proposes a novel intensity-adaptive CMS method to further improve the power consumption and accuracy of the SS-ADC. Similar to TCMS, the intensity-adaptive CMS method in this embodiment also includes a reset signal quantization stage and a pixel signal quantization stage.

[0063] Specifically, such as Figure 4 As shown, the light intensity adaptive correlation multiple sampling method provided in this embodiment includes the following steps: S1: During the reset signal quantization stage, the reset signal is repeatedly quantized n times using a standard ramp signal; and the average of the quantization results of the n repeated quantizations is taken as the quantization result Tbase of the reset signal. At the same time, after the first reset signal quantization and after the nth reset signal quantization, the time residual processing circuit described above is used to quantize the single reset residual T1 and the full reset residual T2, respectively.

[0064] The single-reset residual refers to the time residual introduced after a single quantization of the reset signal using a standard ramp signal, while the full-process reset residual is the time residual introduced after multiple sampling and quantization of the reset signal using n consecutive standard ramp signals. Specifically, T2 = nT1.

[0065] S2: In the pixel signal quantization stage, the pixel signal is first quantized using a full-range ramp, and the pixel signal is divided into strong light state, weak light state and low light state according to the initial quantization result T-comp.

[0066] In this embodiment, a full-range ramp signal is used during the initial quantization of the pixel signal. Although this takes the longest time, it allows for a more comprehensive analysis of the pixel signal's intensity range, which helps in determining the current light intensity state. Specifically, during this quantization stage, the greater the intensity of the pixel signal, the later the comparator output flips. The method used in this embodiment to identify the light intensity state of the pixel signal based on the initial quantization result (T-comp) is as follows: Figure 5 As shown, the strategy is as follows: When the T-comp flip occurs, the amplitude of the full-range ramp signal drops to 3 / 4A. max Previously, this indicated that the pixel signal was in a dim state. When the T-comp flip occurs, the amplitude of the full-scale ramp signal drops to 3 / 4A. max and 1 / 2A max When the T-comp flip occurs, it indicates that the pixel signal is in a weak light state. When the full-scale ramp signal amplitude drops to 1 / 2A... max Then, it indicates that the pixel signal is in a strong light state. Among them, A max This represents the initial amplitude of the ramp signal across the full range.

[0067] Meanwhile, based on different light intensity states, this embodiment further adjusts the CMS operation strategy, including: (1) In strong light conditions, the initial quantization result is used as the quantization result Tpixel of the pixel signal. In strong light conditions, considering that the signal intensity value is high and the noise and error have little impact on the final quantization result, this embodiment cancels the subsequent resampling operation in this state.

[0068] (2) In low light conditions, continue to generate m half-range small ramp signals to repeatedly quantize the pixel signal, and take the average of the quantization results of the first quantization and the m repeated quantizations as the quantization result Tpixel of the pixel signal.

[0069] (3) In low light conditions, continue to generate m quarter-range small ramp signals to repeatedly quantize the pixel signal, and take the average of the quantization results of the first quantization and the m repeated quantizations as the quantization result Tpixel of the pixel signal.

[0070] In low-light and dim-light conditions, considering the weak intensity of pixel signals and the significant impact of noise and error on the accuracy of quantization results, CMS operation is still performed to reduce noise through repeated sampling and quantization. Specifically, unlike traditional schemes that use a full-range ramp in CMS operation, this embodiment uses an adaptive short-range small-ramp signal for repeated sampling and quantization of the pixel signal based on known light intensity conditions. Specifically, to ensure that the range of the small-ramp signal matches the current intensity range of the pixel signal, the small-ramp signal in low light is a half-range ramp signal, which gradually decreases from the peak Amax to 1 / 2Amax at a fixed slope. The small-ramp signal in dim light is a quarter-range ramp signal, which gradually decreases from the peak Amax to 3 / 4Amax at a fixed slope. Simultaneously, after pixel signal quantization, the time residual processing circuit described above is used to quantize the full-range pixel residual T3. It should be noted that in this embodiment, the total pixel residual T3 refers to the sum of the time residuals introduced throughout the entire pixel signal quantization process. Specifically, when the pixel signal is under strong light, T3 is the time residual introduced after one full-range ramp signal quantization; when the pixel signal is under weak light, T3 is the time residual introduced after m+1 half-range ramp signal quantizations; and when the pixel signal is under low light, T3 is the time residual introduced after m+1 quarter-range ramp signal quantizations.

[0071] S3: Combining the light intensity state of the pixel signal, Tbase is corrected using T1 or T2, and Tpixel is corrected using T3, including: (i) Under strong light conditions, the final quantization result of the reset signal is Tbase+T1, and the final quantization result of the pixel signal is Tpixel+T3.

[0072] (ii) Under weak light and low light conditions, the final quantization result of the reset signal is: The final quantization result of the pixel signal is .

[0073] Comparing this embodiment with traditional CMS technology reveals two main differences: First, during the pixel signal quantization stage, this embodiment identifies the signal strength and adaptively adjusts the range of the ramp signal and the number of repeated samples in the related multisampling technique based on the identification results. This shortens the quantization time and reduces circuit power consumption while maintaining accuracy. Second, while quantizing the reset signal and pixel signal, this embodiment also quantizes the time residual in the signal and uses the quantized time residual to correct the quantization results of the reset signal and pixel signal, thereby significantly improving the quantization accuracy of the SS-ADC. This eliminates the impact of the unavoidable time residual on the accuracy of the output quantization result during SS-ADC operation.

[0074] Example 3 To implement the intensity-adaptive correlation multiple sampling method of Embodiment 2 in the quantization output circuit of the CIS, this embodiment further provides an SS-ADC circuit. This circuit uses the intensity-adaptive correlation multiple sampling method of Embodiment 2 to quantize the light-sensing signal output by the pixel unit. Specifically, the light-sensing signal output by the pixel unit includes a reset signal and a pixel signal. The SS-ADC circuit needs to quantize and output the reset signal and the pixel signal sequentially.

[0075] Specifically, such as Figure 6 As shown, the SS-ADC circuit provided in this embodiment includes: a ramp generator, a comparator, a light intensity recognition module, a residual generation module, and a correction module.

[0076] The ramp generator is used to continuously generate n standard-range ramp signals during the reset signal quantization stage, and first generate a full-range ramp signal during the pixel signal quantization stage. Then, based on the light intensity status signal, it selects to end the output after the full-range ramp or continuously generate m half-range or quarter-range small ramp signals. Specifically, in summary, under strong light conditions, the ramp generator outputs n standard ramp signals and one full-range ramp signal. Under weak light conditions, the ramp generator outputs n standard ramp signals, one full-range ramp signal, and m half-range ramp signals. Under very low light conditions, the ramp generator outputs n standard ramp signals, one full-range ramp signal, and m quarter-range ramp signals. Based on the above functional requirements, in practical applications, the ramp generator of this embodiment can be implemented using two circuits with different principles and structures: In Scheme 1, the ramp generator uses an adjustable output ramp generation circuit, and combines optical intensity encoding to sequentially generate corresponding standard range ramp signals, full range ramp signals, and small ramp signals in different clock cycles. In Scheme 2, the ramp generator includes four ramp generation circuits for generating standard range ramp signals, full range ramp signals, half range ramp signals, and quarter range ramp signals, respectively, and a selector. The selector is used to sequentially select each ramp generation circuit in different clock cycles in conjunction with optical intensity encoding, thereby outputting the required standard range ramp signals, full range ramp signals, and small ramp signals. Considering that the latter contains four ramp generation circuits with fixed outputs, the power consumption and area of ​​the circuit will inevitably be relatively high. In practical applications, to reduce the circuit area and power consumption, the first scheme is preferred.

[0077] The comparator's two input ports are connected to the pixel unit and the output signal of the ramp generator, respectively. After comparing the two, it outputs the quantization result Comp_out. The quantization result of the initial quantization of the pixel signal is denoted as T-comp.

[0078] The light intensity recognition module identifies the light intensity state of the pixel signal based on the T-comp and outputs a corresponding 2-bit light intensity code sel1sel0; sel1sel0 of 11, 10, and 00 correspond to strong light, weak light, and low light states, respectively. In this embodiment, the generated light intensity code has two functions: one is to send it to the ramp generator, thereby changing the type of ramp signal it outputs to adjust the quantization method of the pixel signal; the other is to output it to the correction module, enabling the correction module to combine the light intensity state and the different quantization methods of the pixel signal to perform residual correction on the quantization results of the reset signal and the pixel signal using a differentiated strategy.

[0079] In practical applications, the light intensity recognition module can adopt, for example... Figure 7The circuit scheme is shown. Specifically, the light intensity recognition module includes two latches LAT1 and LAT2; two inverters INV1 and INV2; and two voltage converters LS1 and LS2. The circuit connection is as follows: the G terminal of LAT1 is connected to the pre-encoded first index signal U1, the D terminal is connected to T-comp, and the Q terminal is connected to the output terminal of INV1 and the input signal terminal of LS1. The reference signal terminal of LS1 is connected to the output terminal of INV1; the output terminal of LS1 is used to output sel1. The G terminal of LAT2 is connected to the pre-encoded second index signal U0, the D terminal is connected to T-comp, and the Q terminal is connected to the input terminal of INV2 and the input signal terminal of LS2. The reference signal terminal of LS2 is connected to the output terminal of INV2; the output terminal of LS2 is used to output sel0.

[0080] Among them, such as Figure 8 As shown, the amplitude of U1 in the full-range ramp signal ranges from A max Reduced to 1 / 2A max The signal is high during the specified time period and low during the rest of the time period; the amplitude of U0 in the full-range ramp signal ranges from A... max Reduced to 3 / 4A max The signal is high during certain periods and low during other periods. In the light intensity recognition module, when T-comp is high, sel1 and sel0 are dynamically adjusted according to U1 and U0, respectively; when T-comp changes from high to low, the circuit latches the level states of U1 and U0 at this time, and keeps sel1 and sel0 in the latched state until T-comp flips back to high.

[0081] Combination Figure 8 and Figure 9 As can be seen, the circuit principle of the light intensity recognition module in this embodiment is as follows: T-comp is the comparator output, D1 and D0 are the introduced index signals, and LAT1 and LAT2 function as follows: when T-comp is high, the values ​​of D1 and D0 are transmitted normally; when the T-comp output goes low, the code values ​​of D1 and D0 are latched at that moment. Furthermore, since the high level of D1 and D0 is 1.2V, while the high level of sel1 and sel0, used to output to the ramp generator and correction module, is 3V, voltage conversion is required for the latch input. LS1 and LS2 are voltage converters used to convert the latched 1.2V digital voltage to a 3V analog voltage. Thus, when T-comp corresponds to strong light, weak light, and low light conditions, the output 2-bit light intensity codes sel1 and sel0 are 11, 10, and 00, respectively.

[0082] The residual generation module employs the time residual processing circuit as described in Example 1, and is used to generate three types of residuals T1, T2, and T3 based on Comp_out and CLK during the reset signal quantization stage and the pixel signal quantization stage. The correction module acquires the comparator output, and then, in conjunction with the identified light intensity code, uses T1, T2, and T3 to adaptively correct the quantization results of the reset signal quantization stage and the pixel signal quantization stage, thereby obtaining the final quantization result after eliminating the residuals.

[0083] Specifically, as described in Example 1, the signal difference between S2 and S1 in the time residual processing circuit is to extract and quantize the signal residual from a single quantization and the signal residual from multiple quantizations separately when the SS-ADC performs CMS operation on the reset signal. Based on this, the SS-ADC circuit in this example, after adopting this time residual processing circuit, can simultaneously obtain T1 and T2 in each round of reset signal quantization. Then, in the correction phase, it can selectively use one of them to perform subsequent residual correction based on the light intensity state, thereby realizing the strategy of using differentiated time residual correction methods under different light intensity states as described in Example 2. This ensures that the correction strategies for pixel signals and reset signals in the light-sensing signal remain consistent, thereby reducing the complexity of circuit processing for different data and simplifying circuit design.

[0084] Furthermore, in this embodiment, considering factors such as circuit quantization accuracy and efficiency, as well as the complexity of signal management and circuit control, in practical applications, the capacitance value of C2 in the time residual processing circuit is set to 16 times that of C1, i.e., N=16. The reset signal is quantized 4 times, i.e., n=4. In low-light and low-light conditions, the pixel signal is quantized 4 times, i.e., m=3.

[0085] Based on the SS-ADC circuit provided in this embodiment, this embodiment further provides a CIS chip that employs the aforementioned SS-ADC circuit. Therefore, while reducing circuit power consumption, the influence of time residuals on the SS-ADC can be eliminated, significantly improving the quantization accuracy of the pixel unit output signal in the CIS chip.

[0086] To verify the performance of the time residual processing circuit and its SS-ADC circuit provided by this invention, technicians conducted simulation tests on the relevant circuit scheme. In the simulation experiment, the SS-ADC was manufactured using a 130nm CMOS process. A sampling rate of 133.33kHz was achieved at a main clock frequency of 200MHz. The analog section used a voltage of 3V, and the digital section used a voltage of 1.2V. The performance test content and results are as follows: 1. Time residual quantification This experiment first tested the time residual quantization effect of the SS-ADC circuit using the reset signal under low light conditions as an example. The corresponding overall timing signal flow diagram is shown below. Figure 9 As shown: When the offset cancellation enable signal is high, the comparator performs offset cancellation. When the comparator enable signal is high, the comparator starts comparison, Comp_out=1. When the light sensor signal intersects with the ramp signal, the comparator output flips. First, the reset signal is quantized, with fixed sampling and quantization four times. The coarse quantization counter records the duration of these four comparator high-level times under the control of CLK. Then, the pixel voltage is quantized for the first time. The pixel voltage magnitude is determined based on the first flip of the comparator during pixel voltage quantization. After logical determination, it is identified as a weak light signal. After the first full-range ramp, three 1 / 2-range ramp signals are adaptively generated to continue the CMS quantization operation, completing the four quantizations of the pixel signal. The pixel signal quantization ends when the comparator flips for the fourth time. Eight time residuals appear during the four quantizations of the reset voltage and the four quantizations of the pixel voltage, as shown in the figure. These are small pulses smaller than the clock width. The input is fed into the time stretching circuit for a 16-fold stretching operation, as shown in the residual stretching process diagram in the figure. The four time residuals of the four quantized reset voltages are first integrated uniformly in the design. When the reset signal is quantized (i.e., TR1=1), a 16-fold stretching operation is performed uniformly. The time residuals of the four quantized pixel voltages are processed in the same way. Dividing the quantized code value by four yields the final code value output. The lower right corner of the figure shows the generation of the adaptive ramp when the light intensity judgment module identifies low light. The timing sequence of the readout circuit is similar to that in low light, and will not be described further.

[0087] 2. Circuit power consumption This experiment further tested the column power consumption of the circuit when performing the task, and the results are as follows: Figure 10 As shown in the figure, analysis of the data reveals that the column power consumption of the circuit of this invention is 58.9 μW under strong light, 71.28 μW under low light, and 65.98 μW under weak light. It can be seen that under the light intensity adaptive strategy, the column power consumption under strong light is reduced by 17.36% compared to low light, and the power consumption under weak light is reduced by 7.4% compared to low light.

[0088] 3. Process robustness To verify the process robustness of the SS-ADC proposed in this invention, this experiment further simulated the equivalent input noise based on three process angles: tt, ss, and ff. The results show that... Figure 11 As shown.

[0089] Analysis of the data in the figure shows that the equivalent input noise of this circuit is 104.255 μVrms in the best case, 193.417 μVrms in the worst case, and 126.193 μVrms at a typical tt angle. The data indicates that this circuit exhibits stable and excellent noise suppression performance at different process angles, demonstrating good process adaptability.

[0090] 4. Linearity To verify the linearity of the circuit proposed in this invention, the static performance parameters of the SS-ADC were simulated using the code density method. At the tt process corner, one LSB value simulated five code values, totaling 10240 code values. The simulation results showed no errors or missing codes. The differential nonlinearity (DNL) was +0.8 / -1.0 LSB, and the integral nonlinearity (INL) was +1.4 / -1.4 LSB. The test results show that the novel SS-ADC proposed in this invention has good linearity and meets the design requirements.

[0091] The above-described embodiments are merely one implementation of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A temporal residual processing circuit, characterized by: It is used for extracting the residual signal TR of the quantization result according to the quantization result Comp_out of the comparator output in the SS-ADC and the clock CLK, and generating its stretch signal T_stretch; The time residual processing circuit comprises: 1 D flip-flop D1, 1 NOR gate NOR1, 2 resistors R1 and R2 with the same resistance, 4 NMOS tubes N1-N4, 2 capacitors C1 and C2 with different capacitances, and 1 comparator OPA1; the clock end of D1 is connected with CLK, the input end of D1 is connected with one of the input ends of NOR1 and connected with Comp_out, and the inverting output end of D1 is connected with the other input end of NOR1; the output end of NOR1 is connected with the gate of N1 and is used for outputting the residual signal TR; one end of R1 and R2 is connected with VDD, and the other end of R1 is connected with the drain of N1; the other end of R2 is connected with the drain of N2; the source of N1 is connected with the drain of N3, one end of C1 and the non-inverting input end of OPA1, and the connection point is recorded as Vn; the source of N2 is connected with the drain of N4, one end of C2 and the inverting input end of OPA1, and the connection point is recorded as Vp; the other ends of C1 and C2 are connected with the sources of N3 and N4 and VSS; the gate of N2 is connected with the residual enable signal TR1; the gate of N3 is connected with the input layer reset signal S1; the gate of N4 is connected with the reference side reset signal S2; and the non-inverting output end of OPA1 outputs T_stretch. Wherein, when the capacitance value of C2 is N times of that of C1, the pulse width of the output T_stretch is N times of that of TR.

2. The time residual processing circuit according to claim 1, characterized in that: The TR signal flips from low to high when Comp_out flips from high to low, and flips from high to low when the next clock arrives; TR1 flips from low to high when starting residual quantization, and flips from high to low after the end of residual quantization; S1 is high before SS-ADC starts quantization for reset signal and pixel signal, and is low at other times; S2 is high before SS-ADC starts quantization for reset signal and pixel signal, and is high before SS-ADC starts second repeated quantization for reset signal, and is low at other times.

3. A light intensity adaptive correlation multisampling method, characterized in that: It comprises a reset signal quantization stage and a pixel signal quantization stage; S1: in the reset signal quantization stage, a standard slope signal is used to repeatedly quantize the reset signal n times; The average of the quantization results of the n times of repeated quantization is taken as the quantization result Tbase of the reset signal; After the end of the first reset signal quantization and the end of the n times of reset signal quantization, the time residual processing circuit as claimed in claim 1 or 2 is used to quantize single reset residual T1 and full-range reset residual T2 respectively; S2: in the pixel signal quantization stage, a full-range slope is used to quantize the pixel signal firstly, and the pixel signal is divided into strong light state, weak light state and micro light state according to the first quantization result T-comp; In the strong light state, the first quantization result is taken as the quantization result Tpixel of the pixel signal; In the weak light state, continue to generate m times of half-range small slope signals to repeatedly quantize the pixel signal, and take the average of the quantization results of the initial quantization and the m times of repeated quantization as the quantization result Tpixel of the pixel signal; In the weak light state, continue to generate m times of half-range small slope signals to repeatedly quantize the pixel signal, and take the average of the quantization results of the initial quantization and the m times of repeated quantization as the quantization result Tpixel of the pixel signal; After the quantization of the pixel signal is completed, the time residual processing circuit as claimed in claim 1 or 2 is used to quantize the full-range pixel residual T3; S3: in combination with the light intensity state of the pixel signal, Tbase is corrected by using T1 or T2, and Tpixel is corrected by using T3, including: In the strong light state, the final quantization result of the reset signal is Tbase+T1, and the final quantization result of the pixel signal is Tpixel+T3; In the weak light and micro light state, the final quantization result of the reset signal is , and the final quantization result of the pixel signal is .

4. The method of claim 3, wherein, In step S2, the method for identifying the light intensity state of the pixel signal according to the initial quantization result T-comp is: (1) When the flip of T-comp occurs before the amplitude of the full-range ramp signal drops to 3 / 4 A max , it indicates that the pixel signal is in the faint light state; (2) When the flipping of T-comp occurs between the amplitude of full-range ramp signal dropping to 3 / 4 A max and 1 / 2 A max , it indicates that the pixel signal is in a weak light state; (3) When the inversion of T-comp occurs at the time when the amplitude of the full-range ramp signal drops to 1 / 2 A max after that, the pixel signal indicates a strong light state; where A max represents the initial amplitude of the full-scale ramp signal.

5. A SS-ADC circuit, characterized by The method for quantizing the light sensing signal output by the pixel unit is implemented by using the light intensity adaptive related multi-sampling method as claimed in claim 3 or 4; The SS-ADC circuit comprises: a slope generator for continuously generating n standard-range slope signals in the reset signal quantization stage, and for generating a full-range slope signal in the pixel signal quantization stage, and then for selecting to end the output after the full-range slope or to continuously generate m half-range or quarter-range small slope signals according to the light intensity state signal; a comparator with two input ports respectively connected to the output signals of the pixel unit and the slope generator, and outputting a quantization result Comp_out after comparing the two signals; wherein the quantization result of the initial quantization of the pixel signal is recorded as T-comp; a light intensity identification module for identifying the light intensity state of the pixel signal according to T-comp, and outputting a corresponding 2-bit light intensity code sel1sel0; sel1sel0 is 11, 10 and 00 respectively corresponding to the strong light state, the weak light state and the micro light state; a residual generation module using the time residual processing circuit as claimed in claim 1 or 2, and for generating three types of residuals T1, T2 and T3 according to Comp_out and CLK in the reset signal quantization stage and the pixel signal quantization stage; a correction module for obtaining the output of the comparator, and then combining the identified light intensity code to adaptively correct the quantization results of the reset signal quantization stage and the pixel signal quantization stage by using T1, T2 and T3, and further obtaining the final quantization results of the two after eliminating the residuals.

6. The SS-ADC circuit of claim 5, wherein: The slope generator uses an output-adjustable slope generation circuit, and generates the corresponding standard-range slope signal, full-range slope signal and small slope signal in the different clock periods in combination with the light intensity code. Alternatively, the slope generator comprises four slope generation circuits for generating a full-scale slope signal, a half-scale slope signal, a quarter-scale slope signal and a standard-scale slope signal respectively, and a gate; the gate is used to sequentially gate each slope generation circuit in different clock cycles in combination with the light intensity coding, and then output the required standard-scale slope signal, full-scale slope signal and small slope signal.

7. The SS-ADC circuit of claim 5, wherein: The light intensity recognition module comprises two latches LAT1 and LAT2, two inverters INV1 and INV2 and two voltage converters LS1 and LS2, and is connected as follows: The G terminal of the LAT1 is connected with a pre-encoded first index signal U1, the D terminal is connected with a T-comp, the Q terminal is connected with the output terminal of the INV1 and the input signal terminal of the LS1, the reference signal terminal of the LS1 is connected with the output terminal of the INV1, and the output terminal of the LS1 is used for outputting sel1; the G terminal of the LAT2 is connected with a pre-encoded second index signal U0, the D terminal is connected with the T-comp, the Q terminal is connected with the input terminal of the INV2 and the input signal terminal of the LS2, the reference signal terminal of the LS2 is connected with the output terminal of the INV2, and the output terminal of the LS2 is used for outputting sel0. Wherein, U1 is high in the period when the amplitude of full-range ramp signal decreases from A max to 1 / 2A max , and low in the rest period; U0 is high in the period when the amplitude of full-range ramp signal decreases from A max to 3 / 4A max , and low in the rest period.

8. The SS-ADC circuit of claim 5, wherein: In the light intensity recognition module, when the T-comp is at a high level, the sel1 and the sel0 are dynamically adjusted according to the U1 and the U0 respectively; when the T-comp changes from the high level to the low level, the circuit latches the level state of the U1 and the U0 at this time, and makes the sel1 and the sel0 keep the latched state until the T-comp reverts to the high level.

9. The SS-ADC circuit of claim 5, wherein: The capacitance value of the C2 is 16 times of the C1, N=16; the repeated quantization times of the reset signal is 4, n=4; in the weak light and micro light state, the repeated quantization times of the pixel signal is 4, m=3.

10. A CIS chip, characterized by, It adopts the SS-ADC circuit according to any one of claims 5-9.

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