Timing circuit for increasing reading speed

Abstract

The application provides a timing circuit for improving reading speed, a first delay module, a second delay module and a third delay module, a first DQ flip-flop, a second DQ flip-flop, a third DQ flip-flop, a second NOR gate, a NAND gate and a delay unit; a first output end of the first delay module is used for outputting a first delay clock signal, a second output end of the first delay module and a read end are respectively connected with input ends of the NAND gate, and an output end of the NAND gate is used for outputting a clear signal; output ends of the delay unit are respectively connected with CLK ends of the first DQ flip-flop and the third DQ flip-flop, so that a second delay clock signal lags behind a signal of the RSTB end. The application generates a logical relationship between the CLR signal and a delay signal of the first delay module, that is, when the CLR signal is high, no matter what state of the first delay clock signal is at this time, the second delay clock signal is low, and the truncation function is normal.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, in particular to a timing circuit for improving read speed. BACKGROUND

[0002] The timing generation module in prior art, as shown in the figure, in order to support fast read, the truncation function of read is made in the circuit, that is, to ensure that the rising edge of the next read period can reset the control signal (SAEN or sean) of the sensitive amplifier (SA). The signal used for truncation here is the clear signal (clr) in the figure. Figure 1

[0003] Please refer to Figure 1 , the clr signal is generated by the read and the rdb (read signal delayed for a short time) through the NAND gate. Therefore, the rising edge of the read will trigger a high level pulse of the clr. The delcl is the delay signal of the read, and the delay time of the signal is greater than that of the rdb signal.

[0004] Because the parasitic RC (capacitance resistance) of the clr signal in the actual layout is large, the falling edge of the clr signal and the rising edge of the third clock delay signal, that is, the DELCL signal, may collide, resulting in competition between the RSTB signal of the flip-flop triggering the saen signal and the CLK (clock) signal, that is, when the rising edge of the DELCL signal comes, the rstsaenb signal of the third DQ flip-flop is low and is still resetting, and the SAEN signal cannot be normally set high.

[0005] In order to solve the above problems, a new timing circuit for improving read speed needs to be proposed. SUMMARY

[0006] In view of the above-mentioned defects of the prior art, the purpose of the present application is to provide a timing circuit for improving read speed, which is used to solve the problem that in the actual layout of the prior art, the parasitic RC (capacitance resistance) of the clr signal is large, the falling edge of the clr signal and the rising edge of the third clock delay signal, that is, the DELCL signal, may collide, resulting in competition between the RSTB signal of the flip-flop triggering the saen signal and the CLK (clock) signal, that is, when the rising edge of the DELCL signal comes, the rstsaenb signal of the third DQ flip-flop is low and is still resetting, and the SAEN signal cannot be normally set high.

[0007] In order to achieve the above-mentioned purposes and other related purposes, the present application provides a timing circuit for improving read speed, comprising:

[0008] ​a first delay module for generating an address setup time, a second delay module for generating a pre-charge time, and a third delay module for generating a sense amplifier time, a first DQ flip-flop, a second DQ flip-flop, a third DQ flip-flop, a second NOR gate, a NAND gate, and a delay unit;

[0009] The first to third delay modules are connected to the first and second bias voltages;

[0010] The first output terminal of the first delay module is used for outputting a first delay clock signal, the second output terminal of the first delay module and the read terminal are respectively connected to the input terminals of the NAND gate, and the output terminal of the NAND gate is used for outputting a clear signal;

[0011] The D terminals of the first DQ flip-flop, the second DQ flip-flop, and the third DQ flip-flop are connected to an internal power supply;

[0012] The first output terminal of the first delay module and the output terminal of the NAND gate are respectively connected to the input terminals of the delay unit, and the output terminal of the delay unit is used for outputting a second delay clock signal;

[0013] The Q terminal of the first DQ flip-flop is connected to the input terminal of the second delay module, and the Q terminal of the third DQ flip-flop is connected to a sense amplifier control signal;

[0014] The Q terminal of the first DQ flip-flop is connected to the input terminal of the second delay module, the output terminal of the second delay module is connected to the CLK terminal of the second DQ flip-flop, the Q terminal of the second DQ flip-flop is connected to the input terminal of the third delay module, and the output terminal of the third delay module is used for outputting a sense amplifier delay control signal;

[0015] The RSTB terminal of the first DQ flip-flop is connected to the output terminal of the second delay module, for forming a third delay clock signal and transmitting the third delay clock signal to the CLK terminal of the second DQ flip-flop;

[0016] The output terminal of the third delay module and the output terminal of the NAND gate are respectively connected to the two input terminals of the second NOR gate, and the output terminal of the second NOR gate is respectively connected to the RSTB terminal of the second DQ flip-flop and the RSTB terminal of the third DQ flip-flop;

[0017] The output terminal of the delay unit is respectively connected to the CLK terminal of the first DQ flip-flop and the CLK terminal of the third DQ flip-flop, so that the second delay clock signal lags behind the signal of the RSTB terminal.

[0018] Preferably, the delay unit comprises a first NOR gate and an inverter group connected in series with the first NOR gate, two input ends of the first NOR gate are connected with a CLK end of the first DQ flip-flop and a CLK end of the third DQ flip-flop respectively, an output end of the first NOR gate is connected with an input end of the inverter group, and an output end of the inverter group outputs the second delay clock signal.

[0019] Preferably, the inverter group comprises two first inverters and a second inverter connected in series.

[0020] Preferably, the timing circuit further comprises first to third current reference units, which provide first and second bias voltages for the first to third delay modules respectively.

[0021] As described above, the timing circuit for improving reading speed of the present application has the following beneficial effects:

[0022] The present application generates a logical relationship between the clear signal CLR and the first delay clock signal delclb, that is, when the CLR signal is high, the delclb signal is low. And after adding two-stage inverters to the NOR gate, it ensures that after the clr signal is low, the rstsaenb signal of the third DQ flip-flop is faster than the second delay clock signal delcl_new to be high, so that the sensitive amplifier control signal SAEN can be correctly output, and the normal truncation function is realized. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 The timing circuit structure schematic diagram of the prior art is shown;

[0024] Figure 2 The timing circuit structure schematic diagram of the present application is shown;

[0025] Figure 3 The reference current unit structure schematic diagram of the present application is shown;

[0026] Figure 4 The truncation simulation waveform diagram of the circuit in the prior art is shown, and the function fails.

[0027] Figure 5 The truncation waveform simulation diagram of the circuit of the present application is shown, and the function is successful.

[0028] BRIEF DESCRIPTION OF DRAWINGS

[0029] First delay module 01

[0030] Second delay module 02

[0031] Third delay module 03

[0032] First DQ flip-flop 11

[0033] Second DQ flip-flop 12

[0034] Third DQ flip-flop 13

[0035] NAND gate 41

[0036] First NOR gate 21

[0037] Second NOR gate 31

[0038] First inverter 22

[0039] Second inverter 23

[0040] First delayed clock signal delclb

[0041] Second delayed clock signal delcl_new

[0042] Third delayed clock signal delcl

[0043] Charging signal PRECHG

[0044] Sensing amplifier control signal SAEN

[0045] Sensing amplifier delay control signal Delsaen

[0046] Clear signal clr

[0047] Address setup time Tcl

[0048] Precharge time Tpc

[0049] Sensing amplifier time Tsa

[0050] First bias voltage pbias

[0051] Second bias voltage nbias

[0052] Signal rstsaenb at the RSTB terminal of the third DQ flip-flop DETAILED DESCRIPTION

[0053] The present application is herein described, by way of example only, with reference to certain embodiments thereof. It is contemplated that deviations in form can be made thereto without departing from the spirit of the application and that the scope of the application should be governed by the following claims and not by the description herein.

[0054] Referring to Figure 2 The present application provides a timing circuit for improving read speed, comprising:

[0055] The first delay module 01 generates an address setup time Tcl, the second delay module 02 generates a pre-charge time Tpc, and the third delay module generates a sense amplifier time Tsa, the first DQ flip-flop 11, the second DQ flip-flop 12, the third DQ flip-flop 13, the second NOR gate 31, the NAND gate 41, and a delay unit;

[0056] The first to third delay modules (01, 02, 03) are connected to the first and second bias voltages (pbias, nbias);

[0057] The first output end of the first delay module 01 is used to output a first delay clock signal delclb, the second output end of the first delay module 01 and the read end are respectively connected to the input ends of the NAND gate 41, and the output end of the NAND gate 41 is used to output a clear signal clr;

[0058] The D ends of the first DQ flip-flop 11, the second DQ flip-flop 12, and the third DQ flip-flop 13 are connected to an internal power supply;

[0059] The first output end of the first delay module 01 and the output end of the NAND gate 41 are respectively connected to the input ends of the delay unit, and the output end of the delay unit is used to output a second delay clock signal delcl_new;

[0060] The Q end of the first DQ flip-flop 11 is connected to the input end of the second delay module 02 through a charging signal PRECHG, and the Q end of the third DQ flip-flop 13 is connected to a sense amplifier control signal SAEN;

[0061] The Q end of the first DQ flip-flop 11 is connected to the input end of the second delay module 02, the output end of the second delay module 02 is connected to the CLK end of the second DQ flip-flop 12, the Q end of the second DQ flip-flop 12 is connected to the input end of the third delay module 03, and the output end of the third delay module 03 is used to output a sense amplifier delay control signal Delsaen;

[0062] The RSTB end of the first DQ flip-flop 11 is connected to the output end of the second delay module 02, used to form a third delay clock signal delcl and transmitted to the CLK end of the second DQ flip-flop 12;

[0063] The output end of the third delay module 03 and the output end of the NAND gate 41 are respectively connected to the two input ends of the second NOR gate 31, and the output end of the second NOR gate 31 is respectively connected to the RSTB end of the second DQ flip-flop 12 and the RSTB end of the third DQ flip-flop 13;

[0064] The output ends of the delay units are connected with the CLK ends of the first DQ flip-flop 11 and the third DQ flip-flop 13 respectively, so that the second delay clock signal delcl_new lags behind the signal rstsaenb at the RSTB end.

[0065] In the embodiment of the application, the delay unit comprises a first NOR gate 21 and an inverter group connected in series with the first NOR gate 21, the two input ends of the first NOR gate 21 are connected with the CLK ends of the first DQ flip-flop 11 and the third DQ flip-flop 13 respectively, the output end of the first NOR gate 21 is connected with the input end of the inverter group, and the output end of the inverter group outputs the second delay clock signal delcl_new.

[0066] In the embodiment of the application, the inverter group is composed of two first inverters 22 and a second inverter 23 connected in series.

[0067] In the embodiment of the application, please refer to Figure 3 , the timing circuit further comprises first to third current reference units, the first to third current reference units provide first and second bias voltages (pbias, nbias) for the first to third delay modules (01, 02, 03) respectively, a current reference unit (IREF) is mirrored to the above-mentioned delay modules, and the length of time is controlled by the charging and discharging of the capacitor by the mirror current.

[0068] The principle of the timing circuit for improving the reading speed of the application is as follows:

[0069] The application generates a logical relationship between the clear signal CLR and the first delay clock signal delclb, that is, when the CLR signal is high, the delclb signal is low. And two-stage buffer inverters are added after the NOR gate, which ensures that after the clr signal is low, the rstsaenb signal of the third DQ flip-flop is faster than the second delay clock signal delcl_new is high, so that the sensitive amplifier control signal SAEN can be correctly output, and the normal truncation function is realized. Compared with the simulation waveform graph (as shown in Figure 4 ) of the prior art circuit, the truncation function fails, and the truncation waveform simulation graph of the circuit of the application is as shown in Figure 5 , and the truncation function is successful.

[0070] It should be noted that the diagrams provided in the embodiments only illustrate the basic concept of the application in a schematic manner, and only the components related to the application are shown in the diagrams, not the number, shape and size of the components when actually implemented. The actual implementation of each component may be arbitrarily changed in shape, number and proportion, and the layout pattern of the components may be more complex.

[0071] In summary, the application generates a logical relationship between the clear signal CLR and the first delay clock signal delclb, that is, when the CLR signal is high, the delclb signal is low. A two-stage inverter is added after the NOR gate, which ensures that after the clr signal is low, the rstsaenb signal of the third DQ flip-flop is higher than the second delay clock signal delcl_new, so that the sensitive amplifier control signal SAEN can be correctly output, and the normal truncation function is realized. Therefore, the application effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0072] The above embodiments only exemplarily illustrate the principles and effects of the application, and are not used to limit the application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the application should be covered by the claims of the application.

Claims

1. A timing circuit for increasing read speed, characterized by, The application relates to a delay module for a memory device, which comprises: a first delay module (01) for generating an address setup time (Tcl), a second delay module (02) for generating a precharge time (Tpc) and a third delay module for generating a sense amplifier time (Tsa), a first DQ flip-flop (11), a second DQ flip-flop (12), a third DQ flip-flop (13), a second NOR gate (31), a NAND gate (41) and a delay unit; the first to third delay modules (01, 02, 03) are connected to first and second bias voltages (pbias, nbias); a first output terminal of the first delay module (01) is used for outputting a first delay clock signal (delclb), a second output terminal of the first delay module (01) and a read terminal are respectively connected to input terminals of the NAND gate (41), and an output terminal of the NAND gate (41) is used for outputting a clear signal (clr); D terminals of the first DQ flip-flop (11), the second DQ flip-flop (12) and the third DQ flip-flop (13) are connected to internal power supplies; the first output terminal of the first delay module (01) and the output terminal of the NAND gate (41) are respectively connected to input terminals of the delay unit, and an output terminal of the delay unit is used for outputting a second delay clock signal (delcl_new); a Q terminal of the first DQ flip-flop (11) is connected to an input terminal of the second delay module (02) through a charging signal (PRECHG), and a Q terminal of the third DQ flip-flop (13) is connected to a sense amplifier control signal (SAEN); the Q terminal of the first DQ flip-flop (11) is connected to the input terminal of the second delay module (02), an output terminal of the second delay module (02) is connected to a CLK terminal of the second DQ flip-flop (12), a Q terminal of the second DQ flip-flop (12) is connected to an input terminal of the third delay module (03), and an output terminal of the third delay module (03) is used for outputting a sense amplifier delay control signal (Delsaen); an RSTB terminal of the first DQ flip-flop (11) is connected to the output terminal of the second delay module (02), used for forming a third delay clock signal (delcl) and transmitting the third delay clock signal (delcl) to the CLK terminal of the second DQ flip-flop (12); the output terminal of the third delay module (03) and the output terminal of the NAND gate (41) are respectively connected to two input terminals of the second NOR gate (31), and an output terminal of the second NOR gate (31) is respectively connected to an RSTB terminal of the second DQ flip-flop (12) and an RSTB terminal of the third DQ flip-flop (13); the output terminal of the delay unit is respectively connected to the CLK terminal of the first DQ flip-flop (11) and the CLK terminal of the third DQ flip-flop (13), so that the second delay clock signal (delcl_new) lags behind a signal (rstsaenb) of the RSTB terminal of the third DQ flip-flop.

2. The timing circuit for increasing read speed according to claim 1, wherein: The delay unit comprises a first NOR gate (21) and an inverter group connected in series with the first NOR gate (21), two input ends of the first NOR gate (21) are connected with a CLK end of the first DQ flip-flop (11) and a CLK end of the third DQ flip-flop (13) respectively, an output end of the first NOR gate (21) is connected with an input end of the inverter group, and output ends of the inverter group output a second delay clock signal (delcl_new).

3. The timing circuit for increasing read speed of claim 2, wherein: The inverter group is composed of two first inverters (22) and a second inverter (23) connected in series.

4. The read speed improvement timing circuit of claim 1, wherein: The timing circuit further comprises first to third current reference units, and the first to third current reference units provide first and second bias voltages (pbias, nbias) for the first to third delay modules (01, 02, 03) respectively.

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