The register mapping state of the flushed instruction is restored by taking a snapshot of another register mapping state and traversing the reorder buffer (ROB) entries in the processor.

Abstract

A register mapping circuit is provided for restoring the register mapping state associated with a flushed instruction by traversing ROB entries from a snapshot of another register mapping state. The register mapping circuit includes ROB control circuitry, a snapshot circuitry, and a register rename recovery circuitry (RRRC). The ROB control circuitry assigns ROB entries to instructions entering the processor pipeline, including target ROB entries assigned to a target instruction and other ROB entries assigned to other instructions. The snapshot circuitry captures a snapshot of the logical register-to-physical register mapping state in a rename mapping table associated with a subset of instructions that can be flushed. If the target instruction is flushed, the RRRC restores the rename mapping table register mapping state corresponding to the target instruction based on a snapshot in the ROB entries assigned to another instruction, and traverses the register mapping updates in the intermediate ROB entries.

Description

TECHNICAL FIELD

[0001] The technology of this disclosure relates to instruction processing in an instruction pipeline in a computer processor (multiple "processors"), and more specifically, to recovering the state of the structure of an instruction pipeline in a processor after a speculatively mispredicted conditional control (e.g., branch) instruction. BACKGROUND

[0002] Microprocessors, also referred to as "processors," perform computing tasks for a wide variety of applications. A conventional microprocessor includes a central processing unit (CPU) that includes one or more processor cores, also referred to as "CPU cores." The CPU executes computer program instructions ("instructions") that process input data and produce data results. The data results generated in a sequence of instructions can be intermediate data, stored to be used as input data for subsequent instructions. To avoid the latency caused by storing intermediate data in an external memory and then reading the intermediate data back into the processor from the external memory, the intermediate data can be temporarily stored in permanent registers within the processor.

[0003] An instruction set architecture (ISA) makes a number of registers available as operands in instructions. However, there can not be enough available registers in the ISA to avoid multiple instructions in the instruction pipeline using the same register. Therefore, it is often desirable to provide more physical registers than the number of logical registers defined in the ISA to store intermediate data. Thus, for different instructions, the processor can assign the logical registers available in the ISA to different physical registers. The processor maps the logical registers in the processed instructions to the physical registers via a rename map table to track the actual physical registers storing the data. The processor includes register renaming circuitry in the instruction pipeline to rename the logical registers to physical registers for accessing the data in the physical registers to execute the instructions. The logical register to physical register mapping in the rename map table will be released when the physical register is stale, complete, and no longer used. Stale means that a newer write to the same logical register has been committed. Complete means that the result corresponding to the physical register has been written to the physical register file. No longer used means that all instructions that need to consume the physical register have passed the point of reading the register file. The processor stores the renaming information associated with each instruction in program order in a reorder buffer (ROB) and retains the latest renaming state in the rename map table. Once an executed instruction is committed, the logical register to physical register renaming for that instruction is saved into a committed map table (CMT).

[0004] Control risk can occur in an instruction pipeline where a next instruction in the instruction pipeline cannot be executed without causing an incorrect result. For example, control risk can occur as a result of execution of a control flow instruction that causes an exact interrupt in a processor. One example of a control flow instruction that can cause control risk is a conditional branch instruction. A conditional branch instruction can redirect the flow path of instruction execution based on a condition evaluated at the time the condition of the control branch instruction is executed. Thus, a processor can have to suspend the fetch of additional instructions until the conditional branch instruction has been executed, resulting in reduced processor performance and increased power consumption. One approach to maximizing processor performance involves utilizing a prediction circuit to speculatively predict the outcome of the condition of a conditional branch instruction. Processing of new instructions based on the prediction can include changes to register mapping information in a rename map table. However, a mispredicted branch instruction requires execution of a misprediction recovery process whereby the instruction pipeline is flushed and the instruction pipeline fetch unit is redirected to fetch new instructions starting from the address of the conditional branch instruction. As part of this misprediction recovery process, the rename map table containing register mapping information for uncommitted instructions in the instruction pipeline must be returned to its previous register mapping state before instructions in the correct branch are processed. Because the ROB retains the most recent register rename state for uncommitted instructions in the rename map table, instruction entries in the ROB containing the most recent register rename state can be used to restore the previous state of register mapping performed prior to the speculatively mispredicted instruction. In misprediction recovery, it is desirable to restore the register state in the processor as soon as possible to minimize the performance loss due to the speculative misprediction. SUMMARY

[0005] Exemplary aspects disclosed herein include taking a snapshot of another register mapping state and walking through reorder buffer (ROB) entries in a processor to restore the register mapping state of a flushed instruction. Instructions in a processor pipeline will be committed in program order even though they will be processed out of order for efficiency. Because all instructions use the same set of logical registers, different instructions can use the same logical register operand for different purposes. To this end, a rename map table is used to map the logical register operands of an instruction to unique physical registers. As each new instruction enters the processor pipeline, the rename map table is updated to maintain the most recent logical register to physical register mapping. The updates from the various instructions are stored in corresponding reorder buffer (ROB) entries in program order. When the processor pipeline is flushed due to a target instruction failing to execute as expected, all instructions after the target instruction can be flushed from the processor pipeline and the state of the rename map table will be returned to the state of the logical register to physical register mapping that existed prior to the target instruction entering the processor pipeline.

[0006] In this regard, in one exemplary aspect, a register mapping circuit is disclosed for restoring the register mapping state associated with flushed instructions by traversing ROB entries starting from the ROB entry of a snapshot having another register mapping state. The register mapping circuit includes ROB control circuitry, snapshot circuitry, and register rename recovery circuitry (RRRC). The ROB control circuitry assigns ROB entries in the ROB to uncommitted instructions entering the processor's pipeline. Uncommitted instructions include target instructions and may include other instructions older and newer than the target instructions. ROB entries include target ROB entries assigned to target instructions and other ROB entries assigned to other instructions. The snapshot circuitry is configured to capture a snapshot of the rename map state corresponding only to a subset of uncommitted instructions that can be flushed. For example, the snapshot circuitry may be configured to capture only one snapshot of the rename map for each given number of instructions, or only one snapshot of the rename map for predefined ROB entries in the ROB. The snapshot circuitry stores each rename map snapshot in association with a snapshot ROB entry assigned to the corresponding instruction.

[0007] In the exemplary aspects disclosed herein, when the RRRC receives an instruction flushing instruction in the pipeline from the target instruction, the RRRC restores the logical register-to-physical register mapping state of the rename map table to the state corresponding to the target instruction, based on a snapshot of the rename map table stored in association with snapshot ROB entries. That is, the RRRC first restores the rename map table to the state of a snapshot from another instruction in the ROB, and then traverses the updates stored in the ROB entries of the instructions in between to restore the register mapping state of the target instruction. The RRRC first restores the rename map table to the state of a snapshot from another instruction in the ROB because the snapshot circuitry is not configured to capture a snapshot of the rename map table for each instruction or even for each instruction that can be flushed. In this way, the RRRC may be required to traverse the ROBs between the entries assigned to the target instruction and the entries of another instruction with a captured snapshot of the rename map table to restore the rename map table. Therefore, the snapshot circuitry does not need to capture a snapshot of the rename map table for every instruction that can be flushed, and the amount of snapshot resources required by the register map circuitry is reduced compared to snapshot-based recovery. Furthermore, compared to typical ROB traversal methods, using a snapshot of the rename map captured in association with uncommitted instructions can significantly reduce the number of ROB entries that need to be traversed up to or from the target ROB entry in a typical flush.

[0008] In this regard, in one exemplary aspect, a register mapping circuit in a processor is disclosed. The register mapping circuit includes ROB control circuitry configured to assign multiple ROB entries in a ROB to multiple uncommitted instructions in a processor pipeline, wherein the multiple uncommitted instructions include target instructions and other instructions, the multiple ROB entries include target ROB entries assigned to target instructions and other ROB entries assigned to other instructions, and the other instructions include older instructions in the processor pipeline preceding the target instructions and newer instructions in the processor pipeline following the target instructions. The register mapping circuitry further includes snapshot circuitry configured to capture a rename map snapshot, the rename map snapshot including the logical register-to-physical register mapping state of the rename map, the rename map snapshot corresponding to a first other instruction among the other instructions, and storing the rename map snapshot in association with the snapshot ROB entries assigned to the first other instruction among the other instructions. The register mapping circuitry further includes a register rename recovery circuitry configured to receive an instruction flushing instruction from the processor pipeline from the target instruction, and in response to the flushing instruction, restore the logical register-to-physical register mapping state of the rename mapping table to the state corresponding to the target instruction based on a snapshot of the rename mapping table stored in association with snapshot ROB entries.

[0009] In another exemplary aspect of this document, a register mapping circuit is disclosed, comprising ROB control circuitry configured to assign ROB entries of a plurality of ROB entries in a ROB to each of a plurality of uncommitted instructions in a processor pipeline. In the register mapping circuitry, the plurality of uncommitted instructions include target instructions and other instructions, and the plurality of ROB entries include target ROB entries assigned to the target instructions and other ROB entries assigned to the other instructions, the other instructions including older instructions in the processor pipeline preceding the target instructions and newer instructions in the processor pipeline following the target instructions. The register mapping circuitry includes a snapshot circuitry configured to capture at least one rename map snapshot, each rename map snapshot including the logical register-to-physical register mapping state of the rename map, each rename map snapshot corresponding to a corresponding instruction in the other instructions, and storing the at least one rename map snapshot in association with one of the other ROB entries assigned to the corresponding other instruction in the other instructions. The register mapping circuitry includes a register renaming recovery circuitry configured to receive an instruction flushing instruction from the target instruction in the processor pipeline, and in response to the flushing instruction, determine that a first number of other ROB entries between the target ROB entry and other ROB entries that are closest to the renaming mapping table snapshot is greater than a second number of other ROB entries from the target ROB entry to the end ROB entry, the end ROB entry including one of the following: a head ROB entry assigned to the oldest instruction in the older instructions, and a tail ROB entry assigned to the newest instruction in the newer instructions. The register renaming recovery circuit is further configured to: in response to the end of a ROB entry, including the head ROB entry, restore the logical register to physical register mapping state of the rename mapping table based on the committed mapping table (CMT) and register mapping information in other ROB table entries from the head ROB table entry to the target ROB table entry; and in response to the end of a ROB entry, including the tail ROB entry, restore the logical register to physical register mapping state of the rename mapping table based on the rename mapping table and register mapping information in other ROB entries from the tail ROB entry to the target ROB entry.

[0010] In another exemplary aspect, a method for register mapping circuitry in a processor is disclosed. The method includes: assigning multiple ROB entries from a register mapping block (ROB) to multiple uncommitted instructions in a processor pipeline, including assigning a target ROB entry from the multiple ROB entries to a target instruction among the multiple uncommitted instructions, and configuring other ROB entries from the multiple ROB entries to other instructions among the multiple uncommitted instructions, wherein the other instructions include older instructions in the processor pipeline preceding the target instruction and newer instructions in the processor pipeline following the target instruction. The method further includes capturing a snapshot of a rename mapping table, the snapshot including a logical register-to-physical register mapping state of the rename mapping table, the snapshot corresponding to a first other instruction among the other instructions, and storing the rename mapping table snapshot associated with snapshot ROB entries assigned to the first other instruction among the other instructions. The method further includes: receiving an indication of flushing instructions in the processor pipeline from the target instruction, and in response to the flushing indication, restoring the logical register-to-physical register mapping state of the rename mapping table to the state corresponding to the target instruction based on the rename mapping table snapshot stored in association with the snapshot ROB entries.

[0011] In another exemplary aspect, a method for execution in a register-mapped circuit is disclosed. The method includes: assigning a plurality of ROB entries in a register map to a plurality of uncommitted instructions in a processor pipeline; the assignment includes configuring a target ROB entry in the plurality of ROB entries to a target instruction in the plurality of uncommitted instructions; and assigning other ROB entries in the plurality of ROB entries to other instructions in the plurality of uncommitted instructions, wherein the other instructions include older instructions in the processor pipeline preceding the target instruction and newer instructions in the processor pipeline following the target instruction. The method further includes: capturing at least one rename map snapshot, each rename map snapshot including the logical register-to-physical register mapping state of the rename map, each rename map snapshot corresponding to a corresponding instruction in other instructions; and storing the at least one rename map snapshot in association with one of the other ROB entries of the corresponding instruction assigned to the other instructions. The method further includes: receiving an instruction flushing instruction in the processor pipeline from a target instruction, and in response to the flushing instruction, determining that a first number of other ROB entries between the target ROB entry and the closest other ROB entry associated with the rename map snapshot is greater than a second number of other ROB entries from the target ROB entry to the end ROB entry, wherein the end ROB entry includes one of the following: a head ROB entry assigned to the oldest instruction among older instructions, and a tail ROB entry assigned to the latest instruction among newer instructions. The method further includes, in response to the end ROB entry including the head ROB entry, restoring the logical register-to-physical register mapping state of the rename map based on CMT and register mapping information in the other ROB entries from the head ROB entry to the target ROB entry; and in response to the end ROB entry including the tail ROB entry, restoring the logical register-to-physical register mapping state of the rename map based on the rename map and register mapping information in the other ROB entries from the head ROB entry to the target ROB entry. Attached Figure Description

[0012] The accompanying drawings, which are included in and form part of this specification, illustrate several aspects of this disclosure and, together with this description, serve to explain the principles of this disclosure.

[0013] Figure 1 It is a schematic diagram of instruction processing circuitry including an instruction pipeline for processing computer instructions to be executed, wherein register mapping circuitry, combined with speculative instruction flow control, maintains the program order of submitted instructions.

[0014] Figure 2It is a schematic diagram of an instruction processing circuit including an exemplary register mapping circuit, which is configured to restore the register mapping state of the rename mapping table in response to an instruction based on a snapshot of the rename mapping table corresponding to another instruction.

[0015] Figure 3 It is a diagram. Figure 2 A flowchart of an exemplary process of a register mapping circuit, which is used to restore the register mapping state of the rename mapping table based on a snapshot of the register mapping state of the rename mapping table for another instruction, in response to an instruction from a target instruction.

[0016] Figure 4 It includes Figure 1 A schematic diagram of a component of an instruction processing circuit, which is provided to describe a snapshot-based method for restoring a previous state of a rename mapping table, the previous state corresponding to when the target instruction to be flushed is entered into the processor.

[0017] Figure 5 It includes Figure 1 A schematic diagram of the components of the instruction processing circuit is provided to describe a method that traverses reorder buffer (ROB) entries to restore the previous state of the rename mapping table corresponding to the target instruction to be flushed when it enters the processor.

[0018] Figure 6 It includes Figure 2 A schematic diagram of components of an exemplary register mapping circuit is provided to explain the register mapping state of restoring the rename mapping table in response to an instruction from a target command, for use in... Figure 5 and Figure 6 The previously known methods in the table are compared with a snapshot of the rename mapping table corresponding to another instruction;

[0019] Figure 7 It includes Figure 2 A schematic diagram of the components of an exemplary register mapping circuit is provided to illustrate an additional example of restoring the register mapping state of a rename mapping table based on a snapshot of the rename mapping table corresponding to another instruction in response to an instruction from the target.

[0020] Figure 8 This is a block diagram of an exemplary processor-based system including a processor. Figure 2 The register mapping circuit in the middle is configured to restore the register mapping state of the rename mapping table based on a snapshot of the rename mapping table corresponding to another instruction, in response to an instruction from the target instruction. Detailed Implementation

[0021] The exemplary aspects disclosed herein include restoring the register mapping state of a flushed instruction by taking a snapshot of another register mapping state and traversing the reorder buffer (ROB) entries in the processor. Instructions in the processor pipeline are submitted in program order, even if they are processed out of order for efficiency. Since all instructions use the same set of logical registers, different instructions may use the same logical register operands for different purposes. To address this, a rename map is used to map the logical register operands of an instruction to unique physical registers. As each new instruction enters the processor pipeline, the rename map is updated to maintain the latest logical register-to-physical register mapping. Updates from each instruction are stored in the corresponding reorder buffer (ROB) entries in program order. When the processor pipeline is flushed because a target instruction failed to execute as expected, all instructions following the target instruction may be flushed from the processor pipeline, and the state of the rename map will be returned to the state of the logical register-to-physical register mapping that existed before the target instruction entered the processor pipeline.

[0022] In this regard, in one exemplary aspect, a register mapping circuit is disclosed for restoring the register mapping state associated with flushed instructions by traversing ROB entries starting from the ROB entry of a snapshot having another register mapping state. The register mapping circuit includes ROB control circuitry, snapshot circuitry, and register rename recovery circuitry (RRRC). The ROB control circuitry assigns ROB entries in the ROB to uncommitted instructions entering the processor pipeline. Uncommitted instructions include target instructions and may include other instructions older and newer than the target instructions. ROB entries include target ROB entries assigned to target instructions and other ROB entries assigned to other instructions. The snapshot circuitry is configured to capture a snapshot of the rename map state corresponding only to a subset of uncommitted instructions that can be flushed. For example, the snapshot circuitry may be configured to capture only one snapshot of the rename map for each given number of instructions, or only one snapshot of the rename map for predefined ROB entries in the ROB. The snapshot circuitry stores each rename map snapshot in association with a snapshot ROB entry assigned to the corresponding instruction.

[0023] In the exemplary aspects disclosed herein, when the RRRC receives an instruction flush instruction in the pipeline from the target instruction, the RRRC restores the logical register-to-physical register mapping state of the rename map table to the state corresponding to the target instruction, based on a snapshot of the rename map table stored in association with snapshot ROB entries. That is, the RRRC first restores the rename map table to the state of a snapshot from another instruction in the ROB, and then traverses the updates stored in the ROB entries of the instructions in between to restore the register mapping state of the target instruction. The RRRC first restores the rename map table to the state of a snapshot from another instruction in the ROB because the snapshot circuitry is not configured to capture a snapshot of the rename map table for each instruction or even for each instruction that can be flushed. In this way, the RRRC may be required to traverse the ROBs between the entries assigned to the target instruction and the entries of another instruction with a captured snapshot of the rename map table to restore the rename map table. Therefore, the snapshot circuitry does not need to capture a snapshot of the rename map table for every instruction that can be flushed, and the amount of snapshot resources required by the register map circuitry is reduced compared to snapshot-based recovery. Furthermore, compared to typical ROB traversal methods, using a snapshot of the rename map captured in association with uncommitted instructions can significantly reduce the number of ROB entries that need to be traversed up to or from the target ROB entry in a typical flush.

[0024] Figure 1 The diagram illustrates an instruction processing circuit 100, which is provided in the CPU core 102 of the processor 104. The instruction processing circuit 100 includes one or more instruction pipelines I0-I... N The instruction fetch circuit 108 fetches computer instructions 106F from a series of instructions 106 for execution, the series of instructions 106 being stored, for example, in an instruction cache memory 110 or an instruction memory 112. The instruction fetch circuit 108 is configured to provide the fetched instructions 106F to one or more instruction pipelines I0-I0. N As the instruction stream 114 in the instruction processing circuit 100, the instruction 106F fetched in the instruction processing circuit 100 needs to be preprocessed before reaching the execution circuit 116 to be executed. Instruction pipeline I0-I N Different processing circuits or stages across the instruction processing circuit 100 are provided to preprocess and process the fetched instruction 106F through a series of steps before it is executed by the execution circuit 116. These steps can be executed simultaneously to increase throughput.

[0025] Continue to refer to Figure 1The instruction processing circuit 100 includes an instruction decoding circuit 118, which is configured to decode the fetched instruction 106F pointed to by the instruction fetch circuit 108 into a decoded instruction 106D to determine the instruction type and the required action. The decoded instruction 106D is placed in the instruction pipeline I0-I. N One or more of these register names are then provided to the renaming circuit 120 in the instruction processing circuit 100 to determine whether any register names in the decoded instruction 106D need to be renamed to avoid any register dependencies that would prevent parallel or out-of-order processing. The renaming circuit 120 is configured to invoke the rename mapping table (RMT) 122 to rename the logical source register operands and / or logical destination register operands of the decoded instruction 106D to available physical registers 124(1)-124(X)(P0,P1,…,P) in the physical register file (PRF) 126. X The RMT 122 contains multiple mapping entries, each corresponding to a specific logic register R0-R0. P The mapping entries are configured to store information as address pointers pointing to physical registers 124(1)-124(X) in PRF 126. Each physical register 124(1)-124(X) in PRF 126 is configured to store data for the source register operand and / or destination register operand of the decoding instruction 106D.

[0026] Instruction processing circuitry 100 also includes register access (RACC) circuitry 128, which is configured to access one of the physical registers 124(1)-124(X) in PRF 126, which are composed of logic registers R0-R P One of the mapping entries is named and indicated as the source register operand of the decoded instruction 106D. The RACC circuit 128 retrieves the value generated in the PRF 126 by the previously executed instruction 106E in the execution circuit 116. Furthermore, in the instruction processing circuit 100, the scheduler circuit 130 is provided in the instruction pipeline I0-I. N The instruction is configured to store the decode instruction 106D in a reserved entry until all source register operands for the decode instruction 106D are available. A write circuit 132 is provided in the instruction processing circuit 100 to write back (i.e., commit) the value produced by the executed instruction 106E to memory such as PRF 126, a data cache memory system (not shown), or main memory (not shown).

[0027] Continue to refer to Figure 1The instruction processing circuit 100 also includes a flow control prediction circuit 134. The flow control prediction circuit 134 is configured to speculatively predict the result of conditions of a fetched conditional flow control instruction 106F (such as a conditional branch instruction), which controls which path in the instruction control flow path of instruction flow 114 is fetched to the instruction pipeline I0-I for execution. N In this method, by using an accurate speculative prediction approach, the condition of the conditional flow control instruction 106F being fetched does not need to be resolved during the execution of the execution circuit 116 before the instruction processing circuit 100 can continue processing the speculatively fetched instruction 106F. The prediction made by the flow control prediction circuit 134 can be provided as prediction information 136 to the instruction fetch circuit 108, so that the instruction fetch circuit 106 can use it to determine the next instruction 106 to be fetched.

[0028] However, when the conditional flow control instruction 106F is executed in the execution circuit 116, if it is determined that the condition of the conditional flow control instruction 106F has been mispredicted, the instruction 106F is interrupted. Before or after the conditional flow control instruction 106F, the instruction pipeline I0-I in the instruction processing circuit 100... N Speculative fetch instructions 106F that were previously processed are flushed because the direction of program flow differs from the prediction, and processing of these instructions will not be included. For these instructions 106F, the calculated address of the memory location may be invalid or inaccessible for some other reason; loading or storing these instructions 106F can also cause subsequent instructions 106F to be flushed. Under these conditions, the program flow of instruction processing circuit 100 is interrupted, and instruction processing circuit 100 returns to its previous state. The previous state to which the instruction processing circuit returns depends on the type of interrupted instruction and can be a state that existed before the interrupted instruction 106F or as a result of the interrupted instruction 106F, which is the target instruction to be flushed. CPU core 102 includes register mapping circuitry 138, which includes RMT 122 and PRF 126 to maintain logical register-to-physical register mappings. Register mapping circuit 138 includes mapping control circuit 140, which can restore the logical register to physical register mapping state in the event of flushing caused by the target instruction. This state may have been entered into the instruction pipeline I0-I of processing circuit 100 after the target instruction 106. N Instruction 106 in the code is changed.

[0029] Continue to refer to Figure 1The register mapping circuit 138 also includes a reorder buffer (ROB) 142, which includes entries (“ROB entries”) 144(1)-144(N) assigned to instructions 106 that are being processed by the instruction processing circuit 100 but have not yet been committed (“uncommitted instructions”). The ROB index identifies the position of each ROB entry 144(1)-144(N) in the ROB 142. The ROB entries 144(1)-144(N) are assigned to instructions 106 sequentially in program order. The ROB entry 144(1)-144(N) assigned to the oldest uncommitted instruction 106 in the ROB 142 is called the head entry 146. When the oldest uncommitted instruction 106 is committed, the head entry 146 becomes the next ROB entry 144(1)-144(N). The entries assigned to the instruction pipeline I0-I... N The new ROB entries 144(1)-144(N) of the latest uncommitted instruction 106 are referred to as tail entries 148. Tail entries 148 are changed each time a new ROB entry 144(1)-144(N) is assigned to a new instruction 106. When ROB entries 144(1)-144(N) are initially assigned to instruction 106, the ROB index for each instruction 106 is reported back to the instruction processing circuit 100. In this way, the instruction processing circuit 100 can identify the ROB index assigned to the target instruction 106. As a result of instruction 106 (“register mapping information”), the logical registers R0-R in RMT 122 are... P Information related to changes in the mapping is stored in association with ROB entries 144(1)-144(N) assigned to instruction 106. The register mapping information stored for uncommitted instruction 106 is used to implement RMT 122 recovery in response to flushing.

[0030] Continue to refer to Figure 1 The register mapping circuit 100 also includes a committed mapping table (CMT) 150 for mapping entries, wherein each logical register R0-R of the processor 104 p The logical register-to-physical register mapping is stored as a result of committed instruction 106. CMT 150 is updated only when instruction 106 is committed. CMT 150 does not change in response to flushing. Mapping control circuitry 140 controls register mapping circuitry 138, which includes managing flush recovery of RMT 122.

[0031] Figure 2 This is a diagram of an exemplary register mapping circuit 200 in the instruction processing circuit 202 according to this disclosure. The register mapping circuit 200 performs operations related to... Figure 1The register mapping described in register mapping circuit 138 is different from that described below. However, register mapping circuit 200 is optimized to restore the logical register to physical register mapping state from the pipeline flush of the target instruction by taking a snapshot of RMT 204 corresponding to the instruction other than the target instruction. Figure 2 The register mapping circuit 200 includes RMT 204, CMT 206, and ROB 208. RMT 204 and CMT 206 include entries containing logical register names (LRNs) and associated physical register names (PRNs) to indicate the mapping or relationship between logical registers and physical registers for an instruction. The physical register name is identified in... Figure 2 The physical registers in the physical register file are not shown. The register mapping circuit 200 is controlled by the mapping control circuit 210, which is interfaced with the instruction processing circuit 202.

[0032] although Figure 2 Not shown, but instruction processing circuitry 202 includes [specifications for...]. Figure 1 The instruction pipeline I0-I of the instruction processing circuit 100 N The circuitry for each stage includes an instruction decoding circuit 118, a renaming circuit 120, a RACC circuit 128, and a scheduler circuit 130. Although not shown, the processing circuitry 202 also includes... Figure 1 Located in instruction pipeline I0-I N The instruction processing circuitry 100 at each end includes an instruction fetch circuitry 108, a flow control prediction circuitry 134, an execution circuitry 116, and a write circuitry 132, and may include an optional instruction cache 110. These circuits are located in the instruction processing circuitry 202 as described above. Figure 1 It operates as described in the instruction processing circuit 100.

[0033] When instruction 212 enters instruction pipeline I0-I in instruction processing circuit 202 N At that time, the logical register-to-physical register mapping state (“register mapping state”) in the RMT 204 is updated. The register mapping state in the RMT 204 includes the state from the entry into instruction pipeline I0-I N The last instruction 212 onwards refers to the state of the logical register-to-physical register mapping of all architecture registers in instruction processing circuit 202. The register mapping state of RMT 204 is used to enter the instruction pipeline I0-I... NThe register mapping information 214 for each new instruction (i.e., information indicating the physical registers to which the logical registers are mapped for the corresponding instruction) is updated. When a misprediction or other interruption occurs, the instruction flow is interrupted, and the instruction pipeline I0-I following the target instruction 216 (i.e., all "newer instructions 212") is decommissioned. N All instructions will be flushed. Target instruction 216 is the instruction that causes a change in flow control and is referred to herein as the target of the flush. Instructions preceding target instruction 216 (“older instruction 212”) are not affected by the flush. Depending on the type of target instruction 216, the register mapping information 214 in target instruction 216 may or may not be reversed (i.e., undoed) upon recovery from the flush.

[0034] Under normal operation, the ROB control circuit 218 assigns the target ROB entry 220 in ROB 208 to the target instruction 216. When other ROB entries 222 enter the instruction pipeline I0-I... N At the same time, ROB control circuit 218 also assigns other ROB entries 222 to other instructions 212. These other instructions 212 are all uncommitted instructions 212, including older and newer instructions 212. As further described below, snapshot circuit 224 in register mapping circuit 200 captures a snapshot of RMT 204 (“RMT snapshot 226”), which is the snapshot since entering instruction pipeline I0-I N Starting with the latest instruction 212, a copy of all register mapping information 214 included in the register mapping state of RMT 204 is captured. Snapshot circuitry 224 captures RMT snapshot 226 corresponding to instruction 212, and RMT snapshot 226 is associated with snapshot ROB entry 227 in ROB 208. RMT snapshot 226 may be captured before or after any register mapping information 214 of RMT 204 is modified by the corresponding instruction 212.

[0035] Storing RMT snapshot 226 in association with snapshot ROB entry 227 may involve storing RMT snapshot 226 within snapshot ROB entry 227 of ROB 208, or storing RMT snapshot 226 in another register, table, or memory, for example, which may be referenced by an index of snapshot ROB entry 227. Other methods for storing RMT snapshot 226 in association with ROB entry 222 are within the scope of this disclosure. For example, to identify which ROB entries 222 are snapshot ROB entries 227, the location of snapshot ROB entries 227 associated with RMT snapshot 226 may be tracked or recorded in a list or table. Alternatively, each ROB entry 222 may include an indicator, and the indicator in snapshot ROB entry 227 may be updated to indicate that snapshot ROB entry 227 is associated with RMT snapshot 226. As disclosed herein, the snapshot circuit 224 of register mapping circuit 200 does not capture RMT snapshot 226 corresponding to each instruction 212 that may be a target of flushing.

[0036] When register mapping circuit 200 receives instruction pipeline I0-I N When the instruction 216 is identified, the register renaming and recovery circuit (RRRC) 228 receives the flush instruction. The flush instruction can be a voltage or current level of an electrical signal received in the register mapping circuit 200. In response to the flush instruction, RRRC 228 restores the register mapping state of RMT 204 to the state corresponding to the target instruction 216. Sometimes, snapshot circuit 224 will capture an RMT snapshot 226 corresponding to the target instruction 226, as shown in the following reference. Figure 4 The discussed case involves a simple replication of RMT snapshot 226 to RMT 204 to restore the register mapping state of RMT 204. However, as described above, the snapshot circuit 224 of register mapping circuit 200 does not capture an RMT snapshot 226 corresponding to each instruction 212 that could be flushed, as such a method would require significant snapshot resources. In the absence of an RMT snapshot 226 associated with the target instruction 216, the register mapping state of RMT 204 corresponding to the target instruction 216 can be restored based on the RMT snapshot 226 stored in association with a snapshot ROB entry 227 assigned to one of the other instructions 212.

[0037] To better understand the operation of register mapping circuit 200, and to restore the register mapping state of RMT 204 under various conditions, refer to... Figure 2Several scenarios are described in detail. In the first example, RRRC 228 can take an RMT snapshot 226 that is older than the target instruction 216. In the first case of this example, the RMT snapshot 226 corresponding to the next older uncommitted instruction 212 (i.e., the instruction after the target instruction 216) is captured by the snapshot circuit 224. The RMT snapshot 226 at the next older instruction 212 is associated with the snapshot ROB entry 227 adjacent to the target ROB entry 220. Therefore, there are no other ROB entries 222 between the target ROB entry 220 and the snapshot ROB entry 227. As mentioned above, the RMT snapshot 226 can be captured before or after any register mapping information 214 of the next older instruction 212 is applied to the RMT 204. If RMT snapshot 226 is captured after the register mapping information of the next older instruction 212 is applied, the RMT snapshot will correspond to the register mapping state of RMT 204 immediately preceding the target instruction 216. If the register mapping information of the target instruction 217 is to be overwritten, the register mapping state of RMT 204 is restored by simply copying RMT snapshot 226 into RMT 204. Copying RMT snapshot 226 corresponding to the older instruction 212 into the register mapping state of RMT 204 restores the register mapping state of RMT 204 to the point when the older instruction 212 entered instruction pipeline I0-I. N The latest instruction 212 states the state, effectively reversing all changes to RMT 204 since that state existed.

[0038] In the second case, a variation of the first case described above, if the RMT snapshot 226 corresponding to the next older uncommitted instruction 212 is captured by the snapshot circuit 224 before the register mapping information 214 of the next older instruction 212 is applied to the RMT 204, then the effect of the register mapping information 214 of the next older instruction 212 needs to be reversed. Therefore, after the RMT snapshot 226 is copied into the RMT 204, the RRRC 228 will obtain the register mapping information of the next older instruction 212 from the other ROB entries 222 assigned to that next older instruction 212 and restore the register mapping state of the RMT 204 to the state corresponding to the target instruction 216.

[0039] In the third case, a variant of the first or second case described above, the register mapping information of the target instruction 216 will not be overwritten due to the instruction type of the target instruction 216. Therefore, after RMT snapshot 226 is copied into RMT 204, RRRC 228 will obtain the register mapping information 214 of the target instruction 216 from the target ROB entry 220 and modify the register mapping information 214 in the register mapping state of RMT 204 accordingly. After copying the contents of RMT snapshot 226 corresponding to the older instruction 212 into RMT 204, modifying the register mapping state of RMT 204 based on the register mapping information 214 from the target ROB entry 220 or from one of the other ROB entries 222 is to re-execute or reapply the changes made by such register mapping information 214.

[0040] In the fourth case of the first example, the RMT snapshot 226 corresponding to the next older uncommitted instruction 212 is not captured by the snapshot circuit 224. In this case, the closest RMT snapshot 226 corresponding to another instruction 212 corresponds to the older instruction 212 assigned to a snapshot ROB entry 227 that is not the next to the target ROB entry 220. Depending on the size of ROB 208, snapshot ROB entry 227 can be separated from the target ROB entry 220 by any number of other ROB entries 222. In this case, RRRC 228 first copies the contents of the RMT snapshot 226 corresponding to the older ROB instruction 212 into the RMT 204. Next, if the second case above applies (i.e., the RMT snapshot 226 was captured before the register mapping information 214 of the older instruction 212 was applied to the RMT 204), RRRC 228 obtains the register mapping information 224 from the snapshot ROB entry 227 and modifies the RMT 204. Then, for each of the other ROB entries between snapshot ROB entry 227 and target ROB entry 220, RRRC 228 obtains register mapping information 214 from the other ROB entries 222 and modifies RMT 204 based on the register mapping information 214 from the other ROB entries 222, in the order from snapshot ROB entry 227 to target ROB entry 220. This order of application of register mapping information 214 from the other ROB entries 222 is referred to herein as “traversing” the other ROB entries 222. Similar to the third case above, if target instruction 216 is not flushed, register mapping information 214 in the target ROB entry 220 assigned to target instruction 216 can also be obtained and applied to RMT 204 to restore the register mapping state of RMT 204.

[0041] In the example above, even though snapshot ROB entry 227 may be separated from the target ROB entry 220 by a certain number of other ROB entries 222, snapshot ROB entry 227 is still closer to the target ROB entry 220 than the current header entry 230 of ROB 208, which is assigned to the oldest uncommitted instruction 212. Therefore, compared to restoring the register mapping state of RMT 204 from CMT 206, traversing the other ROB entries 222 starting from the RMT snapshot 226 associated with snapshot ROB entry 227 will require traversing fewer other ROB entries 222, as will be explained further below.

[0042] In the second example, RRRC 228 can employ an RMT snapshot 226 that is newer than the target instruction 216. In the fifth case, under the second example, the newer RMT snapshot 226 corresponding to the next newer uncommitted instruction 212 can be captured by the snapshot circuit 224 before or after any register mapping information 214 of the next newer instruction 212 is applied to RMT 204. The newer RMT snapshot 226 is associated with a snapshot ROB entry 227 adjacent to the target ROB entry 220. Therefore, there are no other ROB entries 222 between the target ROB entry 220 and the snapshot ROB entry 227. If the newer RMT snapshot 226 is captured before the register mapping information 214 of the next newer instruction 212 is applied, then the RMT snapshot 226 will correspond to the register mapping state of the RMT 204 immediately following the target instruction 216. If the register mapping information 214 of the target instruction 216 will not be overwritten, the register mapping state of RMT 204 can be restored by copying the newer RMT snapshot 226 into RMT 204. By copying the newer RMT snapshot 226 corresponding to the newer instruction 212 into the register mapping state of RMT 204, the register mapping state of RMT 204 can be restored to the state when the newer instruction 212 is the latest instruction, effectively undoing all changes to RMT 204 from any other instruction 212 that is even newer than the newer instruction 212 (i.e., from the newer instruction 212 to the latest instruction 212 assigned to tail entry 232 of ROB 208).

[0043] In the sixth case, a variation of the fifth case described above under the second example, after the register mapping information 214 of the next newer instruction 212 is applied to the RMT 204, if the newer RMT snapshot 226 corresponding to the next newer uncommitted instruction 212 is captured by the snapshot circuit 224, the effect of the register mapping information 214 of the next newer instruction 212 on the RMT 204 needs to be reversed. Therefore, after copying the newer RMT snapshot 226 into the RMT 204, the RRRC 228 obtains the register mapping information 214 in the next newer instruction 212 from the other ROB entries 222 allocated to the next newer instruction 212, and reverses (undoes) the effect of the register mapping information 214 applied to the register mapping state of the RMT 204 by the next newer instruction 212. In this way, the register mapping state of the RMT 204 corresponding to the target instruction 216 is restored.

[0044] In the seventh case, a variant of the fifth or sixth case described above under the second example, the register mapping information 214 of the target instruction 216 will be flushed. Therefore, after copying the newer RMT snapshot 226 into RMT 204, RRRC 228 will obtain the register mapping information 214 of the target instruction 216 from the target ROB entry 220 and modify the register mapping information 214 in the register mapping state of RMT 204 accordingly. After copying the contents of the newer RMT snapshot 226 corresponding to the newer instruction 212 into RMT 204, modifying the register mapping information 214 in the register mapping state of RMT 204 based on the register mapping information 214 from the target ROB entry 220 or from one of the other ROB entries 222 is to undo or reverse the register mapping change caused by the newer instruction 212.

[0045] In the eighth case of the second example, the newer RMT snapshot 226 corresponding to the next newer uncommitted instruction 212 is not captured by the snapshot circuit 224. In this case, the closest newer RMT snapshot 226 corresponds to another instruction 212 assigned to a snapshot ROB entry 227 that is not the next to the target ROB entry 220. In this case, the snapshot ROB entry 227 can be separated from the target ROB entry 220 by a certain number of other ROB entries 222. Here, RRRC 228 first copies the contents of the RMT snapshot 226 corresponding to the newer instruction 212 into the RMT 204. Next, if the second case described above applies (i.e., the newer RMT snapshot 226 is captured after the register mapping information 214 of the older instruction 212 is applied to the RMT 204), then RRRC 228 obtains the register mapping information 214 from the snapshot ROB entry 227 and modifies the RMT 204 (reversing the effect of the register mapping information 214 on the RMT 204). Then, for each of the other ROB entries between snapshot ROB entry 227 and target ROB entry 220, RRRC 228 obtains register mapping information 214 from the other ROB entries 222 and modifies RMT 204 based on the register mapping information 214 from the other ROB entries 222, in the order from snapshot ROB entry 227 to target ROB entry 220. As in the seventh case in the second example above, if target instruction 216 is to be flushed, the register mapping information 214 of target instruction 216 can also be obtained from target ROB entry 220 and reversed in RMT 204 to restore the register mapping state of RMT 204 to the state corresponding to target instruction 216.

[0046] In the second example, where RRRC 228 uses a newer RMT snapshot 226, snapshot ROB entry 227 is closer to the target ROB entry 220 than the current tail entry 232 assigned to ROB 208, which is the latest uncommitted instruction 212. Therefore, traversing other ROB entries 222 from the RMT snapshot 226 associated with snapshot ROB entry 227 would require traversing fewer other ROB entries 222 than traversing back from tail entry 232 without the newer RMT snapshot 226.

[0047] In the third example, unlike statically using either the older RMT snapshot 226 or the newer RMT snapshot 226, RRRC 228 determines a first number of other ROB entries between the target ROB entry 220 and the older snapshot ROB entry 227 (the snapshot ROB entry 227 between the header entry 230 and the target ROB entry 220), and determines a second number of other ROB entries 222 between the target ROB entry 220 and the newer snapshot ROB entry 227 (the snapshot ROB entry 227 between the tail entry 232 and the target ROB entry 220). Next, RRRC 228 determines that the first number is less than the second number, meaning that restoring the register mapping state of RMT 204 by traversing the older ROB entries 222 will require traversing fewer other ROB entries 222 compared to restoring the register mapping state of RMT 204 by traversing the newer other ROB entries 222. To reduce the recovery time of the register mapping state of RMT204, RRRC 228 can dynamically select a shorter path that traverses fewer other ROB entries 222, as described above.

[0048] The illustrations of ROB 208, mapping control circuit 210, RMT 204, and CMT 206 are merely examples for explaining the circuits and processes disclosed herein and are not intended to limit this disclosure. For example, the number of ROB entries 222 in ROB 208 may be greater or less than the number shown, and may include more or other information than shown and disclosed herein. RMT 204 and CMT 206 may also include... Figure 2 The different numbers of entries and different data shown are not limited to this disclosure.

[0049] Figure 3 yes Figure 2 A flowchart of an exemplary process 300 of the register mapping circuit 200 is provided, which uses an RMT snapshot 226 corresponding to another instruction 212 to restore the register mapping state of RMT 204 to the state corresponding to the target ROB entry 220. Process 300 includes: allocating a plurality of ROB entries 220, 222 in ROB 208 to processor pipelines I0-I. N The multiple uncommitted instructions 212 (box 302) include assigning target ROB entries 220 in multiple ROB entries 220 and 222 to target instructions 216 in multiple uncommitted instructions 212 (box 304), and assigning other ROB entries 222 in multiple ROB entries 222 to other instructions 212 in multiple uncommitted instructions 212, wherein the other instructions include processor pipeline I0-I N The older instruction 212 preceding the target instruction 216 and the processor pipeline I0-IN (Box 306) The newer instruction 212 following the target instruction 216. Process 300 further includes capturing an RMT snapshot 226, which includes the logical register-to-physical register mapping state of the RMT 204, corresponding to a first additional instruction 212 among the other instructions 212 (Box 308). Process 300 includes storing the RMT snapshot 226 in association with a snapshot ROB entry 227 assigned to the first additional instruction 212 among the other instructions 212 (Box 310). Process 300 also includes receiving processor pipeline I0-I from the target instruction 216. N The instruction in the flush instruction is indicated (box 312). The process 300 further includes: in response to the flush instruction, restoring the logical register to physical register mapping state of RMT 204 to the state corresponding to the target instruction 216 based on the RMT snapshot 226 stored in association with snapshot ROB entry 227 (box 314).

[0050] Based on the RMT snapshot 226 corresponding to other instructions 212 and traversing other ROB entries 222 (if any) between the snapshot ROB entry 227 associated with the RMT snapshot 226 and the target ROB entry 220, the register mapping circuit 200 restores the register mapping state of the RMT 204 to the state corresponding to the target instruction 216. The determination of the other instructions 212 captured by the corresponding RMT snapshot 226 can be customized based on various factors, such as test results, statistical analysis, program type, historical results, and the required worst-case snapshot resources. For example, the RMT snapshot 226 can enter the instruction pipeline I0-I every N instructions (where N is an integer). N When captured, this will result in RMT snapshot 226 being stored in association with every N ROB entries 222. Alternatively, RMT snapshot 226 can be captured at every N branch instructions. In another example, RMT snapshot 226 can be captured only for instructions 212 that have a high probability of being mispredicted (e.g., a probability threshold determined based on a heuristic). For example, a history of which conditional instructions are more likely to be mispredicted can be stored and used to generate the probability threshold. Other methods for determining when to capture RMT snapshot 226 are also possible.

[0051] The method described above for determining under what circumstances RMT snapshot 226 was captured differs from previously known snapshot-based methods, which refer to... Figure 4 Describe it. Figure 4 yes Figure 1Another illustration shows the register mapping circuit 138, which includes only RMT 122, ROB 142, and CMT 150. ROB 142 includes a header entry 146 and a tail entry 148. Figure 4 Illustrations also include RMT snapshots 402 and 404, which are copies of RMT 122. RMT snapshots 402 and 404 are associated with ROB entries 406 and 408, respectively. That is, RMT snapshot 402 is a copy of the register mapping state of RMT 122 associated with snapshot ROB entry 406, and RMT snapshot 404 is a copy of the register mapping state of RMT 122 associated with snapshot ROB entry 408. Snapshot ROB entry 406 is assigned to the first conditional branch instruction 410, and snapshot ROB entry 408 is assigned to the second conditional branch instruction 412. According to... Figure 4 The method shown in the illustration captures RMT snapshots only in relation to instructions that could cause flushing (e.g., due to misprediction), and captures them in relation to each instruction that could cause flushing. RMT snapshots 406 and 408 are the only snapshots associated with any entries 144(1)-144(N) in ROB 142, indicating that the first and second conditional branch instructions 410 and 412 are instruction pipelines I0-I N The only instructions that could cause a flush are those that can cause a flush. Therefore, in this method, there are RMT snapshots 406 and 408 corresponding to each instruction that could cause a flush, and the corresponding RMT snapshots 406 and 408 can be copied into RMT 122 to immediately restore the register mapping state of RMT 122 to the state corresponding to instruction 410 or 412. No register mapping information from ROB entries 144(1)-144(N) is needed because ROB entries are not “traversed” in this method. However, Figure 4 In the worst case, snapshot-based methods can require a significant amount of snapshot resources to store snapshots. For example, the actual number of ROB entries 144(1)–144(N) can be much larger than [the number of ROB entries]. Figure 4 The number of ROB entries 144(1)-144(N) is shown. If each ROB entry 144(1)-144(N) is assigned to a conditional branch instruction that may cause a flush, then the RMT snapshot must be stored for each of the many ROB entries 144(1)-144(N), which will require a large amount of additional snapshot resources in the instruction processing circuit 100. If snapshot resources are insufficient, the instruction pipeline may be suspended until snapshot resources become available, causing delays in the instruction processing circuit 100.

[0052] refer to Figure 5 Another previously known method that does not require snapshot resources is described.Figure 5 yes Figure 1 Another illustration of the register mapping circuit 138 in the diagram includes only RMT 122, ROB 142, and CMT 150. Unlike capturing an RMT snapshot that can be copied into RMT 122, the method of traversing ROB entries 144(1)-144(N) completely avoids the use of snapshot resources. For example, target ROB entry 502 in ROB 142 is assigned to target instruction 504 that can cause a flush (e.g., a conditional branch instruction). In this case, since no RMT snapshot is available, the only known state of RMT 122 is its current state and the state of CMT 150 since the last committed instruction.

[0053] The register mapping circuit 138 can determine the "traversal" of ROB entries 144(1)-144(N) between the target ROB entry 502 and the head entry 146 by obtaining the register mapping information of each instruction with ROB entries 144(1)-144(N) and sequentially redoing or undoing (depending on the traversal direction) the effects of this register mapping information. For example, CMT 150 can be copied into RMT 122, and instructions can be traversed from head entry 146 back to target ROB entry 502, as described above. Alternatively, by traversing ROB entries 144(1)-144(N) sequentially from target ROB entry 502 back to head entry 146 and performing restoration using the register mapping information from CMT 150, all register mapping information that has been changed in RMT 122 since target instruction 504 can be identified and restored.

[0054] Figure 5 The register mapping circuit 138 can also determine the ROB entries traversed between the target ROB entry 502 and the tail entry 148. Specifically, ROB entry 142 can be traversed from the target ROB entry 502 to the tail entry 148, or from the tail entry 148 back to the target ROB entry 502. Alternatively, the register mapping circuit 138 can select the traversal direction (i.e., to / from the head entry 146 or to / from the tail entry 148) depending on the location of the target ROB entry 502 during flushing and the direction that allows for faster recovery of the register mapping state of RMT 122.

[0055] Figure 6 yes Figure 2 The diagrams for RMT 204, CMT 206, and ROB 208 are provided for further discussion. Figure 2 The exemplary register mapping circuit 200 in the example is used for reference. As will be explained, Figure 2 The register mapping circuit 200 in the middle can, in some cases, be based on the above regardingFigure 4 and Figure 5 The previously known methods discussed are used to perform the operation.

[0056] exist Figure 6 If the snapshot circuit 224 happens to capture an RMT snapshot 226 associated with the target ROB entry 220 (assigned to the target instruction 216), it can be easily compared with a reference. Figure 4 The described snapshot-based method replicates the data to RMT 204 in a similar manner to restore the register mapping state of RMT 204 to the state corresponding to the target instruction 216. However, this... Figure 6 This is not a typical case because there is no RMT snapshot 226 in register mapping circuit 200 corresponding to each instruction that could cause a flush. Therefore, if the RMT snapshot 226 corresponding to the target instruction 216 is not captured, the register mapping state of RMT 204 will need to be restored based on the known state of RMT 204, such as the RMT snapshot 226 or CMT 206 associated with the newer other ROB entries 222. There are two (2) newer other ROB entries 222 between the target ROB entry 220 assigned to the target instruction 216 and the header entry 230 of the oldest uncommitted instruction 212 assigned to ROB 208. There are five (5) other ROB entries 222 of the newer ROB 208 between the target ROB entry 220 and the snapshot ROB entry 227 of the other ROB entries 222 associated with RMT snapshot 226. Therefore, restoring the register mapping state of RMT 204 based on CMT 206 only requires copying CMT 206 into RMT 204 and traversing the header entry 230 and the other two older ROB entries 222. However, restoring the register mapping state of RMT 204 based on RMT snapshot 226 requires traversing five (5) newer other ROB entries 222. If restoring RMT 204 based on CMT 206 and traversing two older other ROB entries 222 allows RMT 204 to be restored faster than restoring based on RMT snapshot 226 and traversing five newer other ROB entries 222, the register mapping circuit 200 can be selected to work with... Figure 5 The method described above is similar to that used to restore RMT 204 based on CMT 206.

[0057] Figure 7 yes Figure 2Another illustration of the register mapping circuit 200 includes RMT 204, CMT 206, and ROB 208. Here, RRRC 228 of the mapping control circuit 210, ROB control circuit 218, and snapshot circuit 224 are not shown. Snapshot circuit 224 captures one of RMT snapshots 226(1)-226(3) every N instructions 212, where N = 5. RMT snapshot 226(1) corresponds to instruction 212(1), RMT snapshot 226(2) corresponds to instruction 212(6), and RMT snapshot 226(3) corresponds to instruction 212(11). Thus, one in every five entries of the other ROB entries 222 is assigned to one of the other instructions 212. Target ROB entry 220 is assigned to target instruction 216, which is a conditional branch instruction whose condition is mispredicted and flushing is indicated. Reference Figure 7 Additional examples of the operation of the register mapping circuit 200 based on the above scenario are described.

[0058] In the first example where the register mapping state of RMT 204 is restored to the state corresponding to the target ROB entry 220, RMT snapshot 226 corresponding to another instruction 212 is used, and RRRC 228 uses the older RMT snapshot 226 in snapshot ROB entry 227. In this example, the register mapping state of RMT 204 is restored based on RMT snapshot 226(1) corresponding to the other instruction 212(1).

[0059] In the second example, RRRC 228 uses a newer RMT snapshot 226. Here, there are currently newer RMT snapshots 226(2) and 226(3). RRRC 228 can determine a first number 222 of other ROB entries between the snapshot ROB entries 227 associated with RMT snapshot 226(2) and a second number 222 of other ROB entries between the snapshot ROB entries 227 associated with RMT snapshot 226(3). In this case, based on RMT snapshot 226(2), the register mapping state of RMT 204 can be recovered in a shorter time because there are fewer other ROB entries 222 to traverse.

[0060] In the third example, RRRC 228 can determine the closest snapshot ROB entry 227 associated with RMT snapshot 226 in any direction (i.e., for which a small number of other ROB entries 222 will be traversed), and select the option with the shorter number. Figure 7 In this context, RMT snapshot 226(2) is associated with the nearest snapshot ROB entry 227 and will be selected to complete the recovery in the shortest time.

[0061] Figure 8 This is a block diagram of an exemplary processor-based system 800, which includes a processor 802 (e.g., a microprocessor) and instruction processing circuitry 804. The processor-based system 800 can be... Figure 1 The instruction processing circuit 100 is used as an example. The instruction processing circuit 804 can be... Figure 2 The instruction processing circuit 202 is used as an example. The processor-based system 800 can be one or more circuits included in an electronic board, such as a printed circuit board (PCB), server, personal computer, desktop computer, notebook computer, personal digital assistant (PDA), computing board, mobile device, or any other device, and can represent, for example, a server or user's computer. In this example, the processor-based system 800 includes a processor 802. Processor 802 represents one or more general-purpose processing circuits, such as a microprocessor, central processing unit, etc. More specifically, processor 802 can be an EDGE instruction set microprocessor, or other processor implementing an instruction set that supports explicit consumer naming for delivering values ​​produced by the execution of producer instructions. Processor 802 is configured to execute processing logic in instructions for performing the operations and steps discussed herein. In this example, processor 802 includes an instruction cache 808, a temporary, fast-access memory storage for instructions accessible to the instruction processing circuit 804. Instructions fetched or prefetched from memory, such as instructions fetched from main memory 810 via system bus 812, are stored in instruction cache 808. The instruction processing circuit 804 is configured to process instructions fetched into the instruction cache 808 and process these instructions for execution.

[0062] Processor 802 may include RRRC 814 for restoring the state of the RMT in instruction processing circuitry 804 in response to a flush instruction indicating a flush of certain instructions in the instruction pipeline due to a failed instruction. Processor 802 may be Figure 1 The processor 104 in the system can be configured to minimize the traversal of the reorder buffer during RMT recovery. The processor-based system 800 may also include a cache memory 816 to temporarily store data from the main memory 810 for fast access by the processor 802.

[0063] Processor 802 and main memory 810 are coupled to system bus 812 and can be coupled to peripheral devices included in processor-based system 800. As is well known, processor 802 communicates with these other devices by exchanging address, control, and data information on system bus 812. For example, as a slave device, processor 802 can transmit bus transaction requests to memory controller 819 in main memory 810. Although Figure 8 While not illustrated, multiple system buses 812 may be provided, each forming a different architecture. In this example, the memory controller 819 is configured to provide memory access requests to the memory array 820 in the main memory 810. The memory array 820 consists of an array of storage bit cells for storing data. As a non-limiting example, the main memory 810 may be read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM), and static memory (e.g., flash memory, static random access memory, etc.).

[0064] Other devices can be connected to system bus 812. For example... Figure 8 As shown, these devices may include main memory 810, one or more input devices 822, one or more output devices 824, modem 826, and one or more display controllers 828. The input devices 822 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output devices 824 may include any kind of output device, including but not limited to audio, video, other visual indicators, etc. Modem 826 may be configured to allow data exchange with any device from network 830. Network 830 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), and Bluetooth. TM Networks and the Internet. Modem 826 can be configured to support any type of communication protocol required. Processor 802 can also be configured to access display controller(s) 828 via system bus 812 to control information sent to one or more displays 832. The displays(s) 832 can include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, etc.

[0065] Figure 8The processor-based system 800 may include a set of instructions 834, which are executed by processor 802 for any application desired according to these instructions. The instructions 834 may be stored in main memory 810, processor 802, and / or instruction cache 808, which are examples of non-transitory computer-readable media 836. The instructions 834 may also reside wholly or at least partially in main memory 810 and / or in processor 802 during execution. The instructions 834 may also be transmitted or received over network 830 via modem 826, thus network 830 includes computer-readable media 836.

[0066] Although computer-readable medium 836 is shown as a single medium in the exemplary embodiments, the term "computer-readable medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) storing one or more sets of instructions. The term "computer-readable medium" should also be understood to include any medium capable of storing, encoding, or carrying a set of instructions executable by a processing device, and any medium capable of enabling a processing device to perform any one or more methods of the embodiments disclosed herein. Therefore, the term "computer-readable medium" should be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0067] The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be constituted by hardware components or embodied in machine-executable instructions that can be used by a general-purpose or special-purpose processor programmed with these instructions to execute the steps. Alternatively, these steps may be performed by a combination of hardware and software.

[0068] The embodiments disclosed herein may be provided as a computer program product or software, which may include a machine-readable medium (or computer-readable medium) stored on instructions that can be used to program a computer system (or other electronic device) to perform processes according to the embodiments disclosed herein. A machine-readable medium includes any mechanism that stores or transmits information in a machine-readable (e.g., computer-readable) form. For example, machine-readable media include: machine-readable storage media (e.g., ROM, random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.); and the like.

[0069] Unless otherwise explicitly stated, and as can be clearly seen from the preceding discussion, throughout the description, discussions using terms such as “processing,” “computing,” “determining,” “displaying,” etc., refer to the actions and processes of a computer system or similar electronic computing device that manipulate and convert data and memory represented as physical (electronic) quantities in computer system registers and into other data represented as physical quantities in computer system memory or registers or other such information storage, transmission, or display devices.

[0070] The algorithms and displays presented herein are not inherently linked to any particular computer or other device. Various systems can be used with programs based on the teachings of this document, or it can be demonstrated that it is convenient to construct more specialized devices to perform the required method steps. The required structures of various such systems are apparent from the description above. Furthermore, the embodiments described herein are not described with reference to any particular programming language. It will be understood that the teachings of the embodiments described herein can be implemented using a variety of programming languages.

[0071] Those skilled in the art will further understand that the various exemplary logic blocks, modules, circuits, and algorithms described in conjunction with the embodiments disclosed herein can be implemented as electronic hardware, stored in memory, or on another computer-readable medium and executed by a processor or other processing device, or a combination of both. The components of the distributed antenna system described herein can be applied as examples to any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information as required. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been generally described above in accordance with their functionality. How these functions are implemented depends on the specific application, design choices, and / or design constraints imposed on the entire system. Skilled artisans can implement the described functions in different ways for each specific application, but such implementation decisions should not be construed as causing a departure from the scope of this embodiment.

[0072] The various exemplary logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein can be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination designed to perform the functions described herein. Furthermore, the controller can be a processor. The processor can be a microprocessor, but can also be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0073] The embodiments disclosed herein can be embodied in hardware and instructions stored in the hardware, and can reside in, for example, RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium can be part of the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a remote station. Alternatively, the processor and storage medium can reside as discrete components in a remote station, base station, or server.

[0074] It should also be noted that the operational steps described in any exemplary embodiments herein are for illustrative and discussion purposes only. The described operations can be performed in many different sequences other than those shown. Furthermore, the operations described in a single operational step can actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary embodiments can be combined. Those skilled in the art will also understand that information and signals can be represented using any of a variety of techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced in the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0075] Unless otherwise expressly stated, no method described herein shall be construed as requiring its steps to be performed in a particular order. Therefore, if a method claim does not actually enumerate the order in which its steps are performed, or if the claim or description does not specifically state that these steps are limited to a particular order, then no particular order shall ever be inferred.

[0076] It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the invention. Since those skilled in the art can make modifications, combinations, sub-combinations, and variations of the disclosed embodiments that incorporate the spirit and essence of the invention, the invention should be construed as encompassing everything within the scope of the appended claims and their equivalents.

Claims

1. A register mapping circuit in a processor, comprising: a reorder buffer (ROB) control circuit configured to allocate a plurality of ROB entries in a ROB to a plurality of non-committed instructions in a processor pipeline, wherein: the plurality of non-committed instructions includes a target instruction and other instructions; the plurality of ROB entries includes a target ROB entry allocated to the target instruction and other ROB entries allocated to the other instructions; and the other instructions include older instructions in the processor pipeline before the target instruction and newer instructions in the processor pipeline after the target instruction; a snapshot circuit configured to: capture a rename map table snapshot including a logical register to physical register mapping state of a rename map table, the rename map table snapshot corresponding to a first of the other instructions; and store the rename map table snapshot in association with a snapshot ROB entry allocated to the first of the other instructions; and a register rename recovery circuit configured to: receive an indication of a flush of instructions in the processor pipeline from the target instruction; and in response to the indication of the flush, restore the logical register to physical register mapping state of the rename map table to a state corresponding to the target instruction based on the rename map table snapshot stored in association with the snapshot ROB entry, wherein if the first of the other instructions includes an older instruction: no rename map table snapshot is stored in association with any of the other ROB entries allocated to a newer instruction; and a first number of the other ROB entries between the target ROB entry and the snapshot ROB entry is less than a second number of the other ROB entries from the target ROB entry to a tail ROB entry of the other ROB entries, the tail ROB entry allocated to a newest of the newer instructions; or wherein if the first of the other instructions includes a newer instruction: no rename map table snapshot is stored in association with any of the other ROB entries allocated to an older instruction; and a first number of the other ROB entries between the target ROB entry and the snapshot ROB entry is less than a second number of the other ROB entries from the target ROB entry to a head ROB entry of the other ROB entries, the head ROB entry allocated to an oldest of the older instructions.

2. The register mapping circuit of claim 1, wherein the register rename recovery circuit is further configured to restore the logical register to physical register mapping state of the rename map table based on register mapping information in at least one of: the snapshot ROB entry; one or more of the other ROB entries between the snapshot ROB entry and the target ROB entry; and the target ROB entry.

3. The register mapping circuit of claim 1, wherein: the rename map table snapshot is a first rename map table snapshot; the snapshot circuit is further configured to: capture a second rename map table snapshot corresponding to a second other instruction of the other instructions; and store the second rename map table snapshot in association with a second ROB entry of the other ROB entries that is assigned to the second other instruction; and a first number of the other ROB entries between the target ROB entry and the snapshot ROB entry is less than a second number of the other ROB entries between the target ROB entry and the second ROB entry.

4. The register mapping circuit of claim 3, wherein the first other instruction and the second other instruction each comprise an older instruction.

5. The register mapping circuit of claim 3, wherein the first other instruction and the second other instruction each comprise a newer instruction.

6. The register mapping circuit of claim 3, wherein: a first one of the first other instruction and the second other instruction comprises an older instruction; and a second one of the first other instruction and the second other instruction comprises a newer instruction.

7. The register mapping circuit of claim 1, wherein: the first other instruction comprises an older instruction; and to restore the logical register to physical register mapping state of the rename map table to the state corresponding to the target instruction, the register rename recovery circuit is further configured to: copy the logical register to physical register mapping state in the rename map table snapshot to the rename map table; modify register mapping information of the logical register to physical register mapping state of the rename map table based on register mapping information in the target ROB entry; and in order, modify the register mapping information of the logical register to physical register mapping state of the rename map table based on register mapping information in the other ROB entries from the snapshot ROB entry to the target ROB entry.

8. The register mapping circuit of claim 1, wherein: the first other instruction comprises an older instruction; and to restore the logical register to physical register mapping state of the rename map table to the state corresponding to the target instruction, the register rename recovery circuit is further configured to: identify register mapping information of the logical register to physical register mapping state of the rename map table that is updated by the target instruction or the newer instruction, the identified register mapping information comprising first register mapping information and second register mapping information; in order, modify the first register mapping information of the identified register mapping information based on register mapping information in the other ROB entries from the snapshot ROB entry to the target ROB entry. based on the register mapping information in the target ROB entry, modifying the first of the identified register mapping information; and based on the rename map table snapshot, modifying the second of the identified register mapping information.

9. The register mapping circuit of claim 1, wherein: the first other instruction comprises a more recent instruction; and to restore the logical register to physical register mapping state in the rename map table to the state corresponding to the target instruction, the register rename recovery circuit is further configured to: copy the logical register to physical register mapping state from the rename map table snapshot to the rename map table; and sequentially modify the logical register to physical register mapping state in a register map table based on register mapping information in the other ROB entries from the snapshot ROB entry to the target ROB.

10. The register mapping circuit of claim 1, wherein: the first other instruction comprises a more recent instruction; and to restore the logical register to physical register mapping state of the rename map table to the state corresponding to the target instruction, the register mapping state recovery circuit is further configured to: identify register mapping information of the logical register to physical register mapping state in the rename map table that was updated by the target instruction or the more recent instruction, the identified register mapping information comprising first register mapping information and second register mapping information; sequentially modify the first of the identified register mapping information based on register mapping information in the other ROB entries from the snapshot ROB entry to the target ROB entry; and based on the rename map table snapshot, modify the second of the identified register mapping information.

11. The register mapping circuit of claim 1, wherein none of the other ROB entries are between the target ROB entry and the snapshot ROB entry.

12. The register mapping circuit of claim 1, wherein the snapshot circuit configured to capture the rename map table snapshot is further configured to capture a rename map table snapshot corresponding to a conditional instruction having a misprediction probability above a threshold.

13. The register mapping circuit of claim 1, wherein the snapshot circuit configured to capture the rename map table snapshot is further configured to capture a rename map table snapshot corresponding to every Nth conditional instruction identified as having a misprediction probability above a threshold.

14. The register mapping circuit of claim 1, wherein the snapshot circuit configured to capture the rename map table snapshot is further configured to capture a rename map table snapshot corresponding to an instruction assigned to every Nth ROB entry in the ROB. ​ 15. The register mapping circuit of claim 1, configured to track locations of other ROB entries associated with the rename map table snapshot.

16. The register mapping circuit of claim 1, configured to update an indicator indicating that the rename map table snapshot is associated with the snapshot ROB entry allocated to the first other instruction.

17. The register mapping circuit of claim 1, further configured to update an indicator indicating that a second rename map table snapshot is associated with a second ROB entry allocated to a second other instruction.

18. A register mapping circuit, comprising: reorder buffer (ROB) control circuitry configured to allocate a ROB entry of a plurality of ROB entries in a ROB to each of a plurality of non-committed instructions in a processor pipeline, wherein: the plurality of non-committed instructions includes a target instruction and other instructions; the plurality of ROB entries includes a target ROB entry allocated to the target instruction and other ROB entries allocated to the other instructions; and the other instructions include older instructions in the processor pipeline before the target instruction and newer instructions in the processor pipeline after the target instruction; snapshot circuitry configured to: capture at least one rename map table snapshot, each rename map table snapshot including a logical register to physical register mapping state of a rename map table, each rename map table snapshot corresponding to a respective other instruction of the other instructions; and store the at least one rename map table snapshot in association with one of the other ROB entries allocated to the respective other instruction of the other instructions; and register rename recovery circuitry configured to: receive an indication of a flush of instructions in the processor pipeline from the target instruction; and in response to the indication of the flush, determine that a first number of the other ROB entries between the target ROB entry and a closest other ROB entry of the other ROB entries associated with a rename map table snapshot is greater than a second number of the other ROB entries from the target ROB entry to an end ROB entry, the end ROB entry including one of: a head ROB entry allocated to an oldest instruction of the older instructions, and a tail ROB entry allocated to a newest instruction of the newer instructions; in response to the end ROB entry including the head ROB entry, restore the logical register to physical register mapping state of the rename map table based on a committed mapping table (CMT) and register mapping information in the other ROB entries from the head ROB entry to the target ROB entry; and in response to the end ROB entry including the tail ROB entry, restore the logical register to physical register mapping state of the rename map table based on the rename map table and register mapping information in the other ROB entries from the tail ROB entry to the target ROB entry.

19. A method of register mapping circuitry in a processor, the method comprising: allocating a plurality of reorder buffer (ROB) entries in a ROB to a plurality of non-committed instructions in a processor pipeline, including: allocating a target ROB entry of the plurality of ROB entries to a target instruction of the plurality of non-committed instructions; and allocating other ROB entries of the plurality of ROB entries to other instructions of the plurality of non-committed instructions, wherein the other instructions include older instructions in the processor pipeline before the target instruction and younger instructions in the processor pipeline after the target instruction; capturing a rename map table snapshot, the rename map table snapshot including a logical register to physical register mapping state of a rename map table, the rename map table snapshot corresponding to a first other instruction of the other instructions; storing a rename map table snapshot in association with a snapshot ROB entry allocated to the first other instruction of the other instructions; receiving an indication of a flush of an instruction in the processor pipeline from the target instruction; and restoring, in response to the indication of the flush, the logical register to physical register mapping state of the rename map table to a state corresponding to the target instruction based on the rename map table snapshot stored in association with the snapshot ROB entry, wherein if the first other instruction includes an older instruction: no rename map table snapshot is stored in association with any of the other ROB entries allocated to younger instructions; and a first number of the other ROB entries between the target ROB entry and the snapshot ROB entry is less than a second number of the other ROB entries from the target ROB entry to a tail ROB entry of the other ROB entries, the tail ROB entry allocated to a youngest instruction of the younger instructions; or wherein if the first other instruction includes a younger instruction: no rename map table snapshot is stored in association with any of the other ROB entries allocated to older instructions; and a first number of the other ROB entries between the target ROB entry and the snapshot ROB entry is less than a second number of the other ROB entries from the target ROB entry to a head ROB entry of the other ROB entries, the head ROB entry allocated to an oldest instruction of the older instructions.

20. The method of claim 19, further comprising restoring the logical register to physical register mapping state of the rename map table based on register mapping information in at least one of: the snapshot ROB entry; one or more of the other ROB entries between the snapshot ROB entry and the target ROB entry; and the target ROB entry.

21. The method of claim 19, further comprising: capturing a second rename map table snapshot corresponding to a second other instruction of the other instructions; and and storing the second rename map table snapshot in association with a second ROB entry of the other ROB entries that is assigned to a second other instruction; wherein a first number of the other ROB entries between the target ROB entry and the snapshot ROB entry is less than a second number of the other ROB entries between the target ROB entry and the second ROB entry.

22. The method of claim 21, wherein the first other instruction and the second other instruction each comprise an older instruction.

23. The method of claim 21, wherein the first other instruction and the second other instruction each comprise a newer instruction.

24. The method of claim 21, wherein: a first one of the first other instruction and the second other instruction comprises an older instruction; and a second one of the first other instruction and the second other instruction comprises a newer instruction.

25. The method of claim 19, wherein: the first other instruction comprises an older instruction; and restoring the logical register to physical register mapping state of the rename map table to the state corresponding to the target instruction further comprises: copying the logical register to physical register mapping state in the rename map table snapshot to the rename map table; based on register mapping information in the target ROB entry, modifying register mapping information of the logical register to physical register mapping state of the rename map table; and in order, based on register mapping information in the other ROB entries from the snapshot ROB entry to the target ROB entry, modifying the register mapping information of the logical register to physical register mapping state of the rename map table.

26. The method of claim 19, wherein: the first other instruction comprises an older instruction; and restoring the logical register to physical register mapping state of the rename map table to the state corresponding to the target instruction further comprises: identifying register mapping information of the logical register to physical register mapping state of the rename map table that was updated by the target instruction or the newer instruction, the identified register mapping information comprising first register mapping information and second register mapping information; in order, based on register mapping information in the other ROB entries from the snapshot ROB entry to the target ROB entry, modifying the first register mapping information of the identified register mapping information; based on register mapping information in the target ROB entry, modifying the first register mapping information of the identified register mapping information; and based on the rename map table snapshot, modifying the second register mapping information of the identified register mapping information.

27. The method of claim 19, wherein: the first other instruction comprises a newer instruction; and restoring the logical register to physical register mapping state in the rename map table to the state corresponding to the target instruction further comprises: copying the logical register to physical register mapping state from the rename map table snapshot to the rename map table; and sequentially modifying the logical register to physical register mapping state in a register map table based on register mapping information from the snapshot ROB entry to the other ROB entries of the target ROB.

28. The method of claim 19, wherein: the first other instruction comprises a younger instruction; and restoring the logical register to physical register mapping state of the rename map table to the state corresponding to the target instruction further comprises: identifying register mapping information of the logical register to physical register mapping state in the rename map table that was updated by the target instruction or the younger instruction, the identified register mapping information comprising first register mapping information and second register mapping information; sequentially modifying the first register mapping information of the identified register mapping information based on register mapping information from the snapshot ROB entry to the other ROB entries of the target ROB entry; and modifying the second register mapping information of the identified register mapping information based on the rename map table snapshot.

29. The method of claim 19, wherein none of the other ROB entries are between the target ROB entry and the snapshot ROB entry.

30. The method of claim 19, wherein capturing the rename map table snapshot further comprises capturing the rename map table snapshot corresponding to a conditional instruction having a misprediction probability above a threshold.

31. The method of claim 19, wherein capturing the rename map table snapshot further comprises capturing the rename map table snapshot corresponding to every Nth conditional instruction identified as having a misprediction probability above a threshold.

32. The method of claim 19, wherein capturing the rename map table snapshot further comprises capturing a rename map table snapshot corresponding to an instruction assigned to every Nth ROB entry in the ROB.

33. The method of claim 19, further comprising tracking a location of the other ROB entries associated with the rename map table snapshot.

34. The method of claim 19, further comprising updating an indicator indicating that the rename map table snapshot is associated with the snapshot ROB entry assigned to the first other instruction.

35. The method of claim 19, further comprising updating an indicator indicating that a second rename map table snapshot is associated with a second ROB entry assigned to a second other instruction.

36. A method performed in a register mapping circuit, comprising: allocating a plurality of reorder buffer (ROB) entries in a ROB to a plurality of uncommitted instructions in a processor pipeline, comprising: assigning a target ROB entry of the plurality of ROB entries to a target instruction of the plurality of uncommitted instructions; and assigning other ROB entries of the plurality of ROB entries to other instructions of the plurality of uncommitted instructions, wherein the other instructions include older instructions in the processor pipeline that precede the target instruction and newer instructions in the processor pipeline that follow the target instruction; capturing at least one rename map table snapshot, each rename map table snapshot including a logical register to physical register mapping state of a rename map table, each rename map table snapshot corresponding to a respective other instruction of the other instructions; storing the at least one rename map table snapshot in association with one of the other ROB entries assigned to the respective other instruction of the other instructions; receiving an indication of a flush of instructions in the processor pipeline from the target instruction; in response to the indication of the flush, determining that a first number of the other ROB entries between the target ROB entry and a closest other ROB entry associated with a rename map table snapshot is greater than a second number of the other ROB entries from the target ROB entry to an end ROB entry, the end ROB entry including one of a head ROB entry assigned to an oldest instruction of the older instructions and a tail ROB entry assigned to a newest instruction of the newer instructions; in response to the end ROB entry including the head ROB entry, restoring the logical register to physical register mapping state of the rename map table based on a committed map table (CMT) and register mapping information in the other ROB entries from the head ROB entry to the target ROB entry; and in response to the end ROB entry including the tail ROB entry, restoring the logical register to physical register mapping state of the rename map table based on the rename map table and register mapping information in the other ROB entries from the tail ROB entry to the target ROB entry.

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