Pixel circuit, driving method thereof, display panel, and display device

Abstract

A pixel circuit, a driving method thereof, a display panel, and a display device. The driving circuit (04) included in the pixel circuit can control the on / off states of a second node (N2) and a third node (N3) under the control of the potential of a first node (N1). The light-emitting control circuit (03) included in the pixel circuit can control the on / off states between the cathode of a light-emitting element and the second node (N2), and can also control the on / off states between the third node (N3) and a pull-down power supply terminal (LVSS) under the control of a light-emitting control signal. The potential of the first node (N1) is not affected by the potential of the anode of the light-emitting element. Furthermore, when the cathode of the light-emitting element is conducted with the second node (N2), the second node (N2) is conducted with the third node (N3), and the third node (N3) is conducted with the pull-down power supply terminal (LVSS), the light-emitting element can emit light reliably.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a pixel circuit, a driving method thereof, a display panel, and a display device. Background Art

[0002] Pixels in a display device generally include a pixel circuit and a light-emitting element. The pixel circuit can output a driving signal to the light-emitting element to drive the light-emitting element to emit light.

[0003] In related technologies, a pixel circuit generally includes a light-emitting control circuit and a driving circuit. Both the light-emitting control circuit and the driving circuit are connected to the anode of the light-emitting element, and the cathode of the light-emitting element is connected to a pull-down power supply terminal. The light-emitting control circuit is configured to control the driving circuit to transmit a driving signal to the anode of the light-emitting element, so that the light-emitting element emits light under the pressure difference between the driving signal and the pull-down power supply signal provided by the pull-down power supply terminal.

[0004] However, in related technologies, the potential of the driving signal transmitted by the driving circuit to the light-emitting element will shift under the influence of the anode potential of the light-emitting element. As a result, the display effect of the display device is poor. Summary of the Invention

[0005] Embodiments of the present disclosure provide a pixel circuit, a driving method thereof, a display panel, and a display device. The technical solutions are as follows:

[0006] On the one hand, a pixel circuit is provided. The pixel circuit includes a reset circuit, a data writing circuit, a light-emitting control circuit, and a driving circuit.

[0007] The reset circuit is respectively connected to a reset control terminal, a reset power supply terminal, and a first node. The reset circuit is configured to transmit the reset power supply signal provided by the reset power supply terminal to the first node in response to the reset control signal provided by the reset control terminal.

[0008] The data writing circuit is respectively connected to a gate signal terminal, a data signal terminal, and the first node. The data writing circuit is configured to transmit the data signal provided by the data signal terminal to the first node in response to the gate driving signal provided by the gate signal terminal.

[0009] The light-emitting control circuit is respectively connected to a light-emitting control terminal, a pull-down power supply terminal, a second node, a third node, and the cathode of the light-emitting element. The anode of the light-emitting element is connected to a driving power supply terminal. The light-emitting control circuit is configured to control the on / off of the cathode of the light-emitting element and the second node, and control the on / off of the third node and the pull-down power supply terminal in response to the light-emitting control signal provided by the light-emitting control terminal.

[0010] The driving circuit is respectively connected to the first node, the second node, and the third node, and the driving circuit is configured to control the connection and disconnection between the second node and the third node in response to the potential of the first node.

[0011] Optionally, the light-emitting control circuit includes: a first light-emitting control sub-circuit and a second light-emitting control sub-circuit;

[0012] The first light-emitting control sub-circuit is respectively connected to the light-emitting control terminal, the cathode of the light-emitting element, and the second node, and the first light-emitting control sub-circuit is configured to control the connection and disconnection between the cathode of the light-emitting element and the second node in response to the light-emitting control signal;

[0013] The second light-emitting control sub-circuit is respectively connected to the light-emitting control terminal, the third node, and the pull-down power supply terminal, and the second light-emitting control sub-circuit is configured to control the connection and disconnection between the third node and the pull-down power supply terminal in response to the light-emitting control signal.

[0014] Optionally, the first light-emitting control sub-circuit includes: a first light-emitting control transistor; the second light-emitting control sub-circuit includes: a second light-emitting control transistor;

[0015] The gate of the first light-emitting control transistor is connected to the light-emitting control terminal, the first pole of the first light-emitting control transistor is connected to the cathode of the light-emitting element, and the second pole of the first light-emitting control transistor is connected to the second node;

[0016] The gate of the second light-emitting control transistor is connected to the light-emitting control terminal, the first pole of the second light-emitting control transistor is connected to the third node, and the second pole of the second light-emitting control transistor is connected to the pull-down power supply terminal.

[0017] Optionally, the reset circuit is further connected to the cathode of the light-emitting element, and the reset circuit is further configured to transmit the reset power signal to the cathode of the light-emitting element in response to the reset control signal.

[0018] Optionally, the reset circuit includes: a first reset sub-circuit and a second reset sub-circuit;

[0019] The first reset sub-circuit is respectively connected to the reset control terminal, the reset power supply terminal, and the first node, and the first reset sub-circuit is configured to transmit the reset power signal to the first node in response to the reset control signal;

[0020] The second reset sub - circuit is respectively connected to the reset control terminal, the reset power supply terminal and the cathode of the light - emitting element. The second reset sub - circuit is configured to transmit the reset power supply signal to the cathode of the light - emitting element in response to the reset control signal.

[0021] Optionally, the first reset sub - circuit includes: a first reset transistor; the second reset sub - circuit includes: a second reset transistor;

[0022] The gate of the first reset transistor is connected to the reset control terminal, the first pole of the first reset transistor is connected to the reset power supply terminal, and the second pole of the first reset transistor is connected to the first node;

[0023] The gate of the second reset transistor is connected to the reset control terminal, the first pole of the second reset transistor is connected to the reset power supply terminal, and the second pole of the second reset transistor is connected to the cathode of the light - emitting element.

[0024] Optionally, the data writing circuit is also respectively connected to the second node and the third node;

[0025] The data writing circuit is configured to transmit the data signal to the third node in response to the gate driving signal and control the on - off of the second node and the first node.

[0026] Optionally, the data writing circuit includes: a first data writing sub - circuit and a second data writing sub - circuit;

[0027] The first data writing sub - circuit is respectively connected to the gate signal terminal, the data signal terminal and the third node. The first data writing sub - circuit is configured to transmit the data signal to the third node in response to the gate driving signal;

[0028] The second data writing sub - circuit is respectively connected to the gate signal terminal, the second node and the first node. The second data writing sub - circuit is configured to control the on - off of the second node and the first node in response to the gate driving signal.

[0029] Optionally, the first data writing sub - circuit includes: a first data writing transistor; the second data writing sub - circuit includes: a second data writing transistor;

[0030] The gate of the first data writing transistor is connected to the gate signal terminal, the first pole of the first data writing transistor is connected to the data signal terminal, and the second pole of the first data writing transistor is connected to the third node;

[0031] The gate of the second data writing transistor is connected to the gate signal terminal, a first pole of the second data writing transistor is connected to the second node, and a second pole of the second data writing transistor is connected to the first node.

[0032] Optionally, the pixel circuit further includes: a potential regulating circuit;

[0033] The potential regulating circuit is respectively connected to the pull-down power supply terminal and the first node, and the potential regulating circuit is configured to regulate the potential of the first node based on a pull-down power supply signal provided by the pull-down power supply terminal.

[0034] Optionally, the potential regulating circuit includes: a storage capacitor;

[0035] A first end of the storage capacitor is connected to the first node, and a second end of the storage capacitor is connected to the pull-down power supply terminal.

[0036] Optionally, the driving circuit includes: a driving transistor;

[0037] The gate of the driving transistor is connected to the first node, a first pole of the driving transistor is connected to the second node, and a second pole of the driving transistor is connected to the third node.

[0038] On the other hand, a driving method for a pixel circuit is provided, which is applied to the pixel circuit as described in the above aspect. The method includes:

[0039] In a reset stage, the potential of a reset power supply signal provided by a reset power supply terminal is a first potential. A reset circuit responds to the reset power supply signal and transmits the reset power supply signal provided by the reset power supply terminal to a first node, and the potential of the reset power supply signal is the first potential;

[0040] In a data writing stage, the potentials of gate driving signals provided by a gate signal terminal are all the first potential. A data writing circuit responds to the gate driving signals and transmits data signals provided by a data signal terminal to the first node;

[0041] In a light emitting stage, the potential of the first node and the potential of a light emitting control signal provided by a light emitting control terminal are both the first potential. A driving circuit responds to the potential of the first node and controls the second node and the third node to conduct. A light emitting control circuit responds to the light emitting control signal, controls the cathode of a light emitting element to conduct with the second node, and controls the third node to conduct with the pull-down power supply terminal.

[0042] In yet another aspect, a display panel is provided. The display panel includes: a substrate, and a plurality of pixels located on the substrate;

[0043] The pixel includes: a light-emitting element, and a pixel circuit as described in the above aspect, the pixel circuit being connected to the light-emitting element, and the pixel circuit being configured to drive the light-emitting element to emit light.

[0044] In another aspect, a display device is provided, which includes: a power supply component, and a display panel as described in the above aspect;

[0045] The power supply component is connected to the display panel, and the power supply component is configured to supply power to the display panel. Description of the Drawings

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will briefly introduce the drawings required for description in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0047] Figure 1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0048] Figure 2 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure;

[0049] Figure 3 is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present disclosure;

[0050] Figure 4 is a schematic structural diagram of still another pixel circuit provided by an embodiment of the present disclosure;

[0051] Figure 5 is a schematic structural diagram of still another pixel circuit provided by an embodiment of the present disclosure;

[0052] Figure 6 is a schematic structural diagram of still another pixel circuit provided by an embodiment of the present disclosure;

[0053] Figure 7 is a schematic structural diagram of still another pixel circuit provided by an embodiment of the present disclosure;

[0054] Figure 8 is a schematic structural diagram of still another pixel circuit provided by an embodiment of the present disclosure;

[0055] Figure 9 is a schematic structural diagram of still another pixel circuit provided by an embodiment of the present disclosure;

[0056] Figure 10 is a flowchart of a driving method for a pixel circuit provided by an embodiment of the present disclosure;

[0057] Figure 11 is a timing diagram of each signal terminal in a pixel circuit provided by an embodiment of the present disclosure;

[0058] Figure 12 is an equivalent circuit diagram of a pixel circuit in a reset stage provided by an embodiment of the present disclosure;

[0059] Figure 13 is an equivalent circuit diagram of a pixel circuit in a data writing stage provided by an embodiment of the present disclosure;

[0060] Figure 14 is an equivalent circuit diagram of a pixel circuit in a light emitting stage provided by an embodiment of the present disclosure;

[0061] Figure 15 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure;

[0062] Figure 16 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure. Detailed implementation manners

[0063] In order to make the objectives, technical solutions, and advantages of the present disclosure clearer, the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0064] In all embodiments of the present disclosure, the transistors used can be thin film transistors, field effect transistors, or other devices with the same characteristics. According to their functions in the circuit, the transistors used in the embodiments of the present disclosure are mainly switching transistors. Since the source and drain of the switching transistors used here are symmetric, their source and drain can be interchanged. In the embodiments of the present disclosure, the source is referred to as the first pole and the drain is referred to as the second pole. According to the form in the accompanying drawings, the middle terminal of the transistor is defined as the gate, the signal input terminal is defined as the source, and the signal output terminal is defined as the drain. In addition, the switching transistors used in the embodiments of the present disclosure can include either P-type switching transistors or N-type switching transistors. Among them, the P-type switching transistor conducts when the gate is at a low level and cuts off when the gate is at a high level, and the N-type switching transistor conducts when the gate is at a high level and cuts off when the gate is at a low level. In addition, for multiple signals in each embodiment of the present disclosure, there are corresponding first potential and second potential. The first potential and the second potential only represent that the potential of the signal has two state quantities, and do not represent that the first potential or the second potential has a specific value throughout the text.

[0065] Figure 1 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure. As Figure 1 shown, the pixel circuit includes: a reset circuit 01, a data writing circuit 02, a light emitting control circuit 03, and a driving circuit 04.

[0066] The reset circuit 01 can be respectively connected to the reset control terminal RST, the reset power supply terminal IVDD, and the first node N1. The reset circuit 01 can be used to transmit the reset power supply signal provided by the reset power supply terminal IVDD to the first node N1 in response to the reset control signal provided by the reset control terminal RST.

[0067] For example, the reset circuit 01 can transmit the reset power supply signal provided by the reset power supply terminal IVDD to the first node N1 when the potential of the reset control signal provided by the reset control terminal RST is the first potential. The potential of the reset power supply signal can be the first potential. Optionally, the first potential can be an effective potential.

[0068] The data writing circuit 02 can be respectively connected to the gate signal terminal GATE, the data signal terminal DATA, and the first node N1. The data writing circuit 02 can be used to transmit the data signal provided by the data signal terminal DATA to the first node N1 in response to the gate driving signal provided by the gate signal terminal GATE.

[0069] For example, the data writing circuit 02 can transmit the data signal provided by the data signal terminal DATA to the first node N1 when the potential of the gate driving signal provided by the gate signal terminal GATE is the first potential.

[0070] The light emitting control circuit 03 can be respectively connected to the light emitting control terminal EM, the pull-down power supply terminal LVSS, the second node N2, the third node N3, and the cathode of the light emitting element L1. The anode of the light emitting element L1 can be connected to the driving power supply terminal LVDD. The light emitting control circuit 03 can be used to control the connection and disconnection between the cathode of the light emitting element L1 and the second node N2, and control the connection and disconnection between the third node N3 and the pull-down power supply terminal LVSS in response to the light emitting control signal provided by the light emitting control terminal EM.

[0071] For example, the light emitting control circuit 03 can control the cathode of the light emitting element L1 to conduct with the second node N2 and control the third node N3 to conduct with the pull-down power supply terminal LVSS when the potential of the light emitting control signal provided by the light emitting control terminal EM is the first potential. Also, the light emitting control circuit 03 can control the cathode of the light emitting element L1 to disconnect from the second node N2 and control the third node N3 to disconnect from the pull-down power supply terminal LVSS when the potential of the light emitting control signal is the second potential. Optionally, the second potential can be an invalid potential, and the second potential can be a low potential relative to the first potential.

[0072] The driving circuit 04 can be respectively connected to the first node N1, the second node N2, and the third node N3. The driving circuit 04 can be used to control the connection and disconnection between the second node N2 and the third node N3 in response to the potential of the first node N1. That is, the first node N1 is the control node for controlling the operation of the driving circuit 04.

[0073] For example, when the potential of the first node N1 is the first potential, the driving circuit 04 can control the second node N2 and the third node N3 to conduct. Also, when the potential of the first node N1 is the second potential, the driving circuit 04 can control the second node N2 and the third node N3 to be disconnected.

[0074] In the embodiment of the present disclosure, when the driving circuit 04 controls the second node N2 and the third node N3 to conduct, and the light-emitting control circuit 03 controls the cathode of the light-emitting element L1 to conduct with the second node N2 and controls the third node N3 to conduct with the pull-down power supply terminal LVSS, a loop is formed among the driving power supply terminal LVDD, the light-emitting element L1, the second node N2, the third node N3, and the pull-down power supply terminal LVSS. The pull-down power supply terminal LVSS can transmit a pull-down power signal to the third node N3 through the light-emitting control circuit 03, and the potential of the pull-down power signal can be the second potential. The driving circuit 04 can transmit a driving signal (such as a driving current) to the first node N1 based on the potential of the first node N1 and the potential of the third node N3 (i.e., the potential of the pull-down power signal). Furthermore, the light-emitting element L1 can emit light under the drive of the driving signal.

[0075] Reference Figure 1 , since the first node N1 described in the embodiment of the present disclosure is not directly or indirectly connected to any pole (including the anode and the cathode) of the light-emitting element L1, the potential of the first node N1 is not affected by the potential of any pole of the light-emitting element L1, and the potential of the first node N1 can remain stable. Furthermore, based on the principle of driving the light-emitting element L1 to emit light introduced above, the driving circuit 04 can transmit a driving signal that can enable the light-emitting element L1 to accurately represent a gray scale to the light-emitting element L1 based on the potential of the first node N1 and the potential of the third node N3. In this way, the display device including this pixel circuit has a better display effect.

[0076] In summary, the embodiment of the present disclosure provides a pixel circuit. The driving circuit included in the pixel circuit can control the on / off of the second node and the third node under the control of the potential of the first node. The light-emitting control circuit included in the pixel circuit can control the on / off of the cathode of the light-emitting element and the second node under the control of a light-emitting control signal, and can control the on / off of the third node and the pull-down power supply terminal. Thus, it can be known that the potential of the first node is not affected by the potential of the anode of the light-emitting element. Furthermore, when the cathode of the light-emitting element is conducted with the second node, the second node is conducted with the third node, and the third node is conducted with the pull-down power supply terminal, the light-emitting element can emit light reliably. The display device including this pixel circuit has a better display effect.

[0077] Figure 2 is a schematic structural diagram of another pixel circuit provided by the embodiment of the present disclosure. AsFigure 2 As shown, the driving circuit 04 in the pixel circuit may include: a driving transistor T0.

[0078] The gate of the driving transistor T0 may be connected to the first node N1, the first pole of the driving transistor T0 may be connected to the third node N3, and the second pole of the driving transistor T0 may be connected to the second node N2.

[0079] Optionally, the first pole of the driving transistor T0 may be referred to as the source electrode, and the second pole may be referred to as the drain electrode. Alternatively, the first pole of the driving transistor T0 may be referred to as the drain electrode, and the second pole may be referred to as the source electrode.

[0080] Figure 3 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure. As Figure 3 shown, the pixel circuit may further include: a potential adjustment circuit 05.

[0081] The potential adjustment circuit 05 may be respectively connected to the pull-down power supply terminal LVSS and the first node N1. The potential adjustment circuit 05 may be configured to adjust the potential of the first node N1 based on the pull-down power signal provided by the pull-down power supply terminal LVSS.

[0082] By flexibly adjusting the potential of the first node N1 through the potential adjustment circuit 05, the stability of the potential of the first node N1 can be ensured. Furthermore, it can further ensure that the driving circuit 04 (i.e., Figure 3 the driving transistor T0 shown) transmits a driving signal that can enable the light-emitting element L1 to accurately display gray levels based on the potential of the first node N1 and the potential of the third node N3.

[0083] In addition, since the potential adjustment circuit 05 is connected to the pull-down power supply terminal LVSS and is not directly or indirectly connected to any pole of the light-emitting element L1, the potential of any pole of the light-emitting element L1 will not be affected by the potential adjustment circuit 05, and the potential adjustment circuit 05 will not adjust the potential of the first node N1 based on the potential of any pole of the light-emitting element L1. That is, it ensures that the potential of the first node N1 and the potential of any pole of the light-emitting element L1 do not affect each other, and further ensures that the potential stability of the first node N1 is relatively good.

[0084] Figure 4 is a schematic structural diagram of yet another pixel circuit provided by an embodiment of the present disclosure. As Figure 4 shown, in this pixel circuit, the reset circuit 01 may further be connected to the cathode of the light-emitting element L1. The reset circuit 01 may further be configured to transmit a reset power signal to the cathode of the light-emitting element L1 in response to a reset control signal.

[0085] For example, when the potential of the reset control signal is at the first potential, the reset circuit 01 can transmit a reset power signal to the cathode of the light-emitting element L1 to perform reset noise reduction on the cathode of the light-emitting element L1. In this way, after each time the light-emitting element L1 is driven to emit light, the reset circuit 01 can first reset the cathode of the light-emitting element L1 to ensure that the light-emitting element L1 can reliably receive the drive signal in the next light-emitting stage, and further ensure that the light emitted by the light-emitting element L1 can accurately represent the gray scale.

[0086] Figure 5 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure. As Figure 5 shown, the data writing circuit 02 can also be respectively connected to the second node N2 and the third node N3.

[0087] The data writing circuit 02 can be configured to transmit a data signal to the third node N3 in response to a gate driving signal, and control the on / off of the second node N2 and the first node N1.

[0088] For example, when the potential of the gate driving signal is at the first potential, the data writing circuit 02 can transmit a data signal to the third node N3 and control the second node N2 to conduct with the first node N1. At this time, if the driving circuit 04 controls the second node N2 to conduct with the third node N3 under the control of the first node N1, the driving transistor T0 included in the driving circuit 04 will become a diode connection mode, and the potential of the first node N1 and the potential of the third node N3 can be the same. In this way, the purpose of writing the data signal to the first node N1 is achieved.

[0089] By setting that the data writing circuit 02 is also connected to the second node N2 and the third node N3, and setting that the data writing circuit 02 has the functions introduced in the above Figure 5 embodiment, it can be made that when writing the data signal to the first node N1, the threshold voltage Vth of the driving transistor T0 is also written to the first node N1. Furthermore, the driving current finally transmitted by the driving circuit 04 to the light-emitting element L1 is independent of the threshold voltage Vth of the driving transistor T0 included therein. In this way, the problem that the transmitted driving current is inaccurate due to the drift of the threshold voltage Vth can be reliably avoided, and the display effect is further ensured to be good.

[0090] Figure 6 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure. As Figure 6 shown, the reset circuit 01 can include: a first reset sub-circuit 011 and a second reset sub-circuit 012.

[0091] Among them, the first reset sub-circuit 011 can be respectively connected to the reset control terminal RST, the reset power supply terminal IVDD, and the first node N1. The first reset sub-circuit 011 can be configured to transmit a reset power signal to the first node N1 in response to a reset control signal.

[0092] For example, the first reset sub-circuit 011 can transmit a reset power signal to the first node N1 when the potential of the reset control signal is a first potential.

[0093] The second reset sub-circuit 012 can be respectively connected to the reset control terminal RST, the reset power supply terminal IVDD, and the cathode of the light-emitting element L1. The second reset sub-circuit 012 can be configured to transmit a reset power signal to the cathode of the light-emitting element L1 in response to a reset control signal.

[0094] For example, the second reset sub-circuit 012 can transmit a reset power signal to the cathode of the light-emitting element L1 when the potential of the reset control signal is a first potential.

[0095] Figure 7 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure. As Figure 7 shown, the data writing circuit includes: a first data writing sub-circuit 021 and a second data writing sub-circuit 022.

[0096] Among them, the first data writing sub-circuit 021 can be respectively connected to the gate signal terminal GATE, the data signal terminal DATA, and the third node N3. The first data writing sub-circuit 021 can be configured to transmit a data signal to the third node N3 in response to a gate driving signal.

[0097] For example, the first data writing sub-circuit 021 can transmit a data signal to the third node N3 when the potential of the gate driving signal is a first potential.

[0098] The second data writing sub-circuit 022 can be respectively connected to the gate signal terminal GATE, the second node N2, and the first node N1. The second data writing sub-circuit 022 can be configured to control the connection and disconnection between the second node N2 and the first node N1 in response to a gate driving signal.

[0099] For example, the second data writing sub-circuit 022 can control the conduction between the second node N2 and the first node N1 when the potential of the gate driving signal is a first potential.

[0100] Figure 8 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure. As Figure 8 shown, the light-emitting control circuit 03 can include: a first light-emitting control sub-circuit 031 and a second light-emitting control sub-circuit 032.

[0101] Among them, the first light-emitting control sub-circuit 031 can be respectively connected to the light-emitting control terminal EM, the cathode of the light-emitting element L1, and the second node N2. The first light-emitting control sub-circuit 031 can be configured to control the connection and disconnection between the cathode of the light-emitting element L1 and the second node N2 in response to a light-emitting control signal.

[0102] For example, when the potential of the light-emitting control signal is a first potential, the first light-emitting control sub-circuit 031 can control the conduction between the cathode of the light-emitting element L1 and the second node N2, and when the potential of the light-emitting control signal is a second potential, the first light-emitting control sub-circuit 031 can control the disconnection between the cathode of the light-emitting element L1 and the second node N2.

[0103] The second light-emitting control sub-circuit 032 can be respectively connected to the light-emitting control terminal EM, the third node N3, and the pull-down power supply terminal LVSS. The second light-emitting control sub-circuit 032 can be configured to control the connection and disconnection between the third node N3 and the pull-down power supply terminal LVSS in response to a light-emitting control signal.

[0104] For example, when the potential of the light-emitting control signal is a first potential, the second light-emitting control sub-circuit 032 can control the conduction between the third node N3 and the pull-down power supply terminal LVSS, and when the potential of the light-emitting control signal is a second potential, the second light-emitting control sub-circuit 032 can control the disconnection between the third node N3 and the pull-down power supply terminal LVSS.

[0105] Figure 9 is a schematic structural diagram of another pixel circuit provided by an embodiment of the present disclosure. As Figure 9 shown, the potential adjustment circuit 05 described in the above embodiment may include: a storage capacitor C1.

[0106] The first end of the storage capacitor C1 can be connected to the first node N1, and the second end of the storage capacitor C1 can be connected to the pull-down power supply terminal LVSS.

[0107] Continuing to refer to Figure 9 , the first light-emitting control sub-circuit 031 may include: a first light-emitting control transistor T1. The second light-emitting control sub-circuit 032 may include: a second light-emitting control transistor T2.

[0108] Among them, the gate of the first light-emitting control transistor T1 can be connected to the light-emitting control terminal EM, the first pole of the first light-emitting control transistor T1 can be connected to the cathode of the light-emitting element L1, and the second pole of the first light-emitting control transistor T1 can be connected to the second node N2.

[0109] The gate of the second light-emitting control transistor T2 can be connected to the light-emitting control terminal EM, the first pole of the second light-emitting control transistor T2 can be connected to the third node N3, and the second pole of the second light-emitting control transistor T2 can be connected to the pull-down power supply terminal LVSS.

[0110] Continue to refer to Figure 9 , the first reset sub-circuit 011 may include: a first reset transistor T3. The second reset sub-circuit 031 includes: a second reset transistor T4.

[0111] Wherein, the gate of the first reset transistor T3 may be connected to the reset control terminal RST, the first pole of the first reset transistor T3 may be connected to the reset power supply terminal IVDD, and the second pole of the first reset transistor T3 may be connected to the first node N1.

[0112] The gate of the second reset transistor T4 may be connected to the reset control terminal RST, the first pole of the second reset transistor T4 may be connected to the reset power supply terminal IVDD, and the second pole of the second reset transistor T4 may be connected to the cathode of the light-emitting element L1.

[0113] Continue to refer to Figure 9 , the first data writing sub-circuit 021 may include: a first data writing transistor T5. The second data writing sub-circuit 022 may include: a second data writing transistor T6.

[0114] Wherein, the gate of the first data writing transistor T5 may be connected to the gate signal terminal GATE, the first pole of the first data writing transistor T5 may be connected to the data signal terminal DATA, and the second pole of the first data writing transistor T5 may be connected to the third node N3.

[0115] The gate of the second data writing transistor T6 may be connected to the gate signal terminal GATE, the first pole of the second data writing transistor T6 may be connected to the second node N2, and the second pole of the second data writing transistor T6 may be connected to the first node N1.

[0116] Based on the above introduction, it can be seen that in the embodiments of the present disclosure, the cathode of the light-emitting element L1 is connected to the drain of the driving transistor T0. The first reset transistor T3 and the second reset transistor T4 are connected to the reset power supply terminal IVDD. The storage capacitor C1 is connected to another power supply terminal (i.e., the pull-down power supply terminal LVSS) independent of the reset power supply terminal IVDD. Thus, combined Figure 9 it can be known that the anode and cathode potentials of the light-emitting element L1 will not change due to the potential stored in the storage capacitor C1, and the storage capacitor C1 will not adjust the potential of the first node N1 (i.e., the gate of the driving transistor T0) based on the potential of any pole of the light-emitting element L1 through its coupling effect. Furthermore, the stability of the potential of the first node N1 is ensured.

[0117] It should be noted that Figure 9The pixel circuit shown is a 7T1C (i.e., 7 transistors and 1 capacitor) structure. Of course, the pixel circuit described in the embodiments of the present disclosure can also be adapted to other structures, such as 6T1C.

[0118] It should also be noted that in the above embodiments, it is described by taking each transistor as an N-type transistor and the first potential being a high potential relative to the second potential as an example. Of course, each transistor can also be a P-type transistor. When each transistor is a P-type transistor, the first potential is a low potential relative to the second potential. In addition, if each transistor is a P-type transistor, then in combination with Figure 5 , the data writing circuit 02 can be connected only to the first node N1 and the third node N3, without the need to be connected to the second node N2. That is, in combination with Figure 9 , the first pole of the second data writing transistor T6 can be connected to the third node N3, and the second pole of the second data writing transistor T6 can be connected to the first node N1.

[0119] In summary, the embodiments of the present disclosure provide a pixel circuit. The driving circuit included in the pixel circuit can control the on / off of the second node and the third node under the control of the potential of the first node. The light emission control circuit included in the pixel circuit can control the on / off of the cathode of the light emitting element and the second node under the control of the light emission control signal, and control the on / off of the third node and the pull-down power supply terminal. Thus, it can be seen that the potential of the first node is not affected by the potential of the anode of the light emitting element. Furthermore, when the cathode of the light emitting element is conducted with the second node, the second node is conducted with the third node, and the third node is conducted with the pull-down power supply terminal, the light emitting element can emit light reliably. The display device including this pixel circuit has a good display effect.

[0120] Figure 10 is a flowchart of a driving method for a pixel circuit provided by the embodiments of the present disclosure. This method can be used to drive a pixel circuit as shown in Figures 1 to 9 any one. As shown in Figure 10 , this method can include:

[0121] Step 1001, reset stage: The potential of the reset power signal provided by the reset power supply terminal is the first potential. The reset circuit responds to the reset power signal and transmits the reset power signal provided by the reset power supply terminal to the first node.

[0122] Optionally, the potential of the reset power signal can be the first potential.

[0123] Step 1002, data writing stage: The potentials of the gate drive signals provided by the gate signal terminal are all the first potential. The data writing circuit responds to the gate drive signal and transmits the data signal provided by the data signal terminal to the first node.

[0124] Step 1003, the light-emitting stage, the potential of the first node and the potential of the light-emitting control signal provided by the light-emitting control terminal are both the first potential. The driving circuit responds to the potential of the first node to control the conduction between the second node and the third node. The light-emitting control circuit responds to the light-emitting control signal to control the conduction between the cathode of the light-emitting element and the second node, and controls the conduction between the third node and the pull-down power supply terminal.

[0125] Exemplarily, taking Figure 9 each transistor in the pixel circuit shown as an N-type transistor and the first potential being a high potential relative to the second potential as an example, the driving principle of the pixel circuit described in the embodiments of the present disclosure will be introduced in detail.

[0126] Figure 11 is a timing diagram of each signal terminal in a pixel circuit provided by an embodiment of the present disclosure. As Figure 11 shown, in the reset stage t1, the potential of the reset control signal provided by the reset control terminal RST is the first potential, and both the first reset transistor T3 and the second reset transistor T4 are turned on. The reset power signal provided by the reset power supply terminal IVDD is transmitted to the first node N1 through the turned-on first reset transistor T3, and is transmitted to the cathode of the light-emitting element L1 through the turned-on second reset transistor T4. Thus, if V_ivdd is used to identify the potential of the reset power signal provided by the reset power supply terminal IVDD, then in this reset stage t1, the potential of the first node N1 and the potential of the cathode of the light-emitting element L1 are both set to V_ivdd, and this V_ivdd can be the first potential.

[0127] In addition, referring to Figure 11 , in the reset stage t1, the potential of the gate driving signal provided by the gate signal terminal GATE and the potential of the light-emitting control signal provided by the light-emitting control terminal EM are both the second potential. Thus, the first light-emitting control transistor T1, the second light-emitting control transistor T2, the first data writing transistor T5, and the second data writing transistor T6 can all be turned off. The equivalent circuit diagram of the pixel circuit in the reset stage t1 can be referred to Figure 12 .

[0128] In the data writing stage t2, the potential of the reset control signal can jump to the second potential, and both the first reset transistor T3 and the second reset transistor T4 are turned off. The potential of the gate driving signal provided by the gate signal terminal GATE jumps to the first potential. The potential of the first node N1 is maintained at V_ivdd under the coupling action of the storage capacitor C1, that is, maintained at the first potential. The first data writing transistor T5, the second data writing transistor T6, and the driving transistor T0 are all turned on, and the driving transistor T0 becomes a diode connection mode under the control of the turned-on second data writing transistor T6, that is, it operates in the saturation region. The data signal provided by the data signal terminal DATA is transmitted to the third node N3 through the turned-on first data writing transistor T5.

[0129] During the reset phase t1, the potential V_ivdd of the reset power signal provided by the reset power supply terminal IVDD written to the first node N1 is greater than the potential of the data signal written to the first node N1 during the data writing phase t2, and the threshold voltage Vth of the N-type driving transistor T0 is a positive number. Therefore, the first node N1 directly connected to the storage capacitor C1 discharges continuously along the path of the second node N2 to the third node N3, that is, the potential of the first node N1 continuously decreases until the potential of the first node N1 decreases to Vdata + Vth, and the driving transistor T0 is turned off, and the data writing phase t2 ends. Here, Vdata refers to the potential of the data signal.

[0130] In addition, referring to Figure 11 , during the data writing phase t2, the potential of the light emission control signal is maintained at the second potential. In this way, both the first light emission control transistor T1 and the second light emission control transistor T2 can be turned off. The equivalent circuit diagram of the pixel circuit during the data writing phase t2 can be referred to Figure 13 .

[0131] During the light emission phase t3, the potential of the gate driving signal jumps to the second potential, and both the first data writing transistor T5 and the second data writing transistor T6 are turned off. The potential of the light emission control signal jumps to the first potential, and both the first light emission control transistor T1 and the second light emission control transistor T2 are turned on. The potential of the first node N1 is still the first potential Vdata + Vth, and the driving transistor T0 is turned on. In this way, the driving power supply terminal LVDD, the light emitting element L1, the first light emission control transistor T1, the driving transistor T0, the second light emission control transistor T2, and the pull-down power supply terminal LVSS can form a loop. The pull-down power signal provided by the pull-down power supply terminal LVSS can be transmitted to the third node N3 through the second light emission control transistor T2. The driving transistor T0 can transmit a driving signal to the second node N2 based on the potential of the first node N1 and the potential of the third node N3. This driving signal can be transmitted to the light emitting element L1 through the turned-on first light emission control transistor T1, thereby driving the light emitting element L1 to emit light.

[0132] In addition, referring to Figure 11 , during the light emission phase t3, the potential of the reset control signal is maintained at the second potential. In this way, both the first reset transistor T3 and the second reset transistor T4 are turned off. The equivalent circuit diagram of the pixel circuit during the light emission phase t3 can be referred to Figure 14 .

[0133] Optionally, assuming that the potential of the pull-down power signal is V_lvss, then at the light-emitting stage t3, the potential Vs of the third node N3 (i.e., the source s of the driving transistor T0) is V_lvss. The driving signal transmitted by the driving transistor T0 to the light-emitting element L1 based on the potential Vdata+Vth of the first node N1 (i.e., the gate g of the driving transistor T0) and the potential V_lvss of the third node N3 can be a driving current.

[0134] The driving current Id can be:

[0135] Id = k(Vgs - Vth) 2 = k(Vg - Vs - Vth) 2

[0136] = k(Vdata + Vth - V_lvss - Vth) 2 = k(Vdata - V_lvss) 2 .

[0137] Among them, k is a process design-related constant of the driving transistor T0, and k can satisfy:

[0138]

[0139] Among them, μ is the carrier mobility of the driving transistor T0, C OX is the capacitance of the gate insulating layer of the driving transistor T0, and W / L is the aspect ratio of the driving transistor T0. Thus, it can be determined that when the light-emitting element L1 is operating normally, the magnitude of the driving current for driving the light-emitting element L1 is independent of the threshold voltage Vth of the driving transistor T0. Therefore, the influence of the threshold voltage Vth of the driving transistor T0 on the driving current is eliminated, that is, effective compensation for the threshold voltage Vth of the driving transistor T0 is achieved, making the picture display more stable, improving the display uniformity, and improving the display effect.

[0140] In summary, the embodiments of the present disclosure provide a driving method for a pixel circuit. At the light-emitting stage, under the control of the light-emitting control signal, the light-emitting control circuit controls the conduction between the cathode of the light-emitting element and the second node, and controls the conduction between the third node and the pull-down power supply terminal. The driving circuit can control the conduction between the second node and the third node under the control of the potential of the first node. Thus, it can be seen that the potential of the first node is not affected by the potential of the anode of the light-emitting element. Furthermore, the light-emitting element can emit light reliably at the light-emitting stage, and the display device including this pixel circuit has a good display effect.

[0141] Figure 15 is a schematic structural diagram of a display panel provided by the embodiments of the present disclosure. As Figure 15As shown, the display panel may include: a substrate substrate 001, and a plurality of pixels 000 located on the substrate substrate 001.

[0142] Among them, the pixel 000 may include: a light-emitting element L1, and a pixel circuit 00 as shown in Figures 1 to 9 any one. The pixel circuit 00 may be connected to the light-emitting element L1, and the pixel circuit 00 may be used to drive the light-emitting element L1 to emit light.

[0143] Figure 16 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure. As shown in Figure 16 the display device may include: a power supply component J1, and a display panel M1 as shown in Figure 15 any one.

[0144] Among them, the power supply component J1 may be connected to the display panel M1, and the power supply component J1 may be used to supply power to the display panel M1.

[0145] Optionally, the light-emitting element L1 described in the embodiments of the present disclosure may be an extreme super light-emitting diode (ULED), also known as a multi-zone light-distributing independently controlled light-emitting diode. Furthermore, the pixel circuit for driving the light-emitting element L1 may also be referred to as a ULED pixel circuit. A display device including the ULED pixel circuit may also be referred to as a ULED display device.

[0146] Optionally, the display device may be: any product or component with a display function such as a ULED display device, a Micro LED display device, a liquid crystal display device, an electronic paper, an organic light emitting diode (OLED) display device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, etc.

[0147] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the above-described pixel circuit, display substrate, and display device may refer to the corresponding processes in the foregoing method embodiments, and will not be described herein again.

[0148] The above are only optional embodiments of the present disclosure, and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A pixel circuit, characterized in that, The pixel circuit includes: a reset circuit, a data writing circuit, a light emission control circuit, and a driving circuit; The reset circuit is respectively connected to a reset control terminal, a reset power supply terminal, a first node, and the cathode of the light emitting element. When the potential of the reset control signal provided by the reset control terminal is a first potential, the reset circuit transmits the reset power supply signal provided by the reset power supply terminal to the first node, and transmits the reset power supply signal to the cathode of the light emitting element; the first potential is an effective potential; the light emitting element is an extreme super light emitting diode; The data writing circuit is respectively connected to a gate signal terminal, a data signal terminal, and the first node. The data writing circuit is configured to transmit the data signal provided by the data signal terminal to the first node when the potential of the gate driving signal provided by the gate signal terminal is a first potential; the data writing circuit is further respectively connected to a second node and a third node; the data writing circuit is configured to transmit the data signal to the third node when the potential of the gate driving signal is a first potential, and control the second node and the first node to conduct; The light emission control circuit is respectively connected to a light emission control terminal, a pull-down power supply terminal, the second node, the third node, and the cathode of the light emitting element. The anode of the light emitting element is connected to a driving power supply terminal; the light emission control circuit is configured to control the cathode of the light emitting element to conduct with the second node and control the third node to conduct with the pull-down power supply terminal when the light emission control signal provided by the light emission control terminal is a first potential, and control the cathode of the light emitting element to be disconnected from the second node and control the third node to be disconnected from the pull-down power supply terminal when the light emission control signal provided by the light emission control terminal is a second potential; the second potential is an invalid potential; The driving circuit includes: a driving transistor; the gate of the driving transistor is connected to the first node, the first pole of the driving transistor is connected to the second node, the second pole of the driving transistor is connected to the third node. The driving circuit is configured to control the second node and the third node to conduct when the potential of the first node is a first potential, and control the second node and the third node to be disconnected when the potential of the first node is a second potential; if the driving circuit controls the second node and the third node to conduct, the data signal is written into the first node, and the potential of the first node is the same as the potential of the third node; when writing the data signal into the first node, the threshold voltage of the driving transistor is also written into the first node; Wherein, the light emission control circuit includes: a first light emission control sub-circuit and a second light emission control sub-circuit; the reset circuit includes: a first reset sub-circuit and a second reset sub-circuit; The first light-emitting control sub-circuit is respectively connected to the light-emitting control terminal, the cathode of the light-emitting element, and the second node. The first light-emitting control sub-circuit is configured to control the conduction between the cathode of the light-emitting element and the second node when the potential of the light-emitting control signal is a first potential, and to control the disconnection between the cathode of the light-emitting element and the second node when the potential of the light-emitting control signal is a second potential; The second light-emitting control sub-circuit is respectively connected to the light-emitting control terminal, the third node, and the pull-down power supply terminal. The second light-emitting control sub-circuit is configured to control the conduction between the third node and the pull-down power supply terminal when the potential of the light-emitting control signal is a first potential, and to control the disconnection between the third node and the pull-down power supply terminal when the potential of the light-emitting control signal is a second potential; The first reset sub-circuit is respectively connected to the reset control terminal, the reset power supply terminal, and the first node. The first reset sub-circuit is configured to transmit the reset power supply signal to the first node when the potential of the reset control signal is a first potential; The second reset sub-circuit is respectively connected to the reset control terminal, the reset power supply terminal, and the cathode of the light-emitting element. The second reset sub-circuit is configured to transmit the reset power supply signal to the cathode of the light-emitting element when the potential of the reset control signal is a first potential; Moreover, the first light-emitting control sub-circuit and the second light-emitting control sub-circuit share the light-emitting control terminal, the first reset sub-circuit and the second reset sub-circuit share the reset control terminal, and the period during which the potential of the reset control signal is an effective potential does not overlap with the period during which the potential of the light-emitting control signal is an effective potential.

2. The pixel circuit according to claim 1, wherein The first light-emitting control sub-circuit includes: a first light-emitting control transistor; the second light-emitting control sub-circuit includes: a second light-emitting control transistor; The gate of the first light-emitting control transistor is connected to the light-emitting control terminal, the first pole of the first light-emitting control transistor is connected to the cathode of the light-emitting element, and the second pole of the first light-emitting control transistor is connected to the second node; The gate of the second light-emitting control transistor is connected to the light-emitting control terminal, the first pole of the second light-emitting control transistor is connected to the third node, and the second pole of the second light-emitting control transistor is connected to the pull-down power supply terminal.

3. The pixel circuit according to claim 1, wherein The first reset sub-circuit includes: a first reset transistor; the second reset sub-circuit includes: a second reset transistor; The gate of the first reset transistor is connected to the reset control terminal, the first pole of the first reset transistor is connected to the reset power supply terminal, and the second pole of the first reset transistor is connected to the first node; The gate of the second reset transistor is connected to the reset control terminal, the first pole of the second reset transistor is connected to the reset power supply terminal, and the second pole of the second reset transistor is connected to the cathode of the light-emitting element.

4. The pixel circuit according to any one of claims 1 to 3, characterized in that, The data writing circuit includes: a first data writing sub-circuit and a second data writing sub-circuit; The first data writing sub - circuit is respectively connected to the gate signal terminal, the data signal terminal, and the third node. The first data writing sub - circuit is configured to transmit the data signal to the third node in response to the gate driving signal. The second data writing sub - circuit is respectively connected to the gate signal terminal, the second node, and the first node. The second data writing sub - circuit is configured to control the connection and disconnection between the second node and the first node in response to the gate driving signal.

5. The pixel circuit according to claim 4, wherein The first data writing sub - circuit includes: a first data writing transistor; the second data writing sub - circuit includes: a second data writing transistor. The gate of the first data writing transistor is connected to the gate signal terminal, the first pole of the first data writing transistor is connected to the data signal terminal, and the second pole of the first data writing transistor is connected to the third node. The gate of the second data writing transistor is connected to the gate signal terminal, the first pole of the second data writing transistor is connected to the second node, and the second pole of the second data writing transistor is connected to the first node.

6. The pixel circuit according to any one of claims 1 to 3, characterized in that, The pixel circuit further includes: a potential adjustment circuit. The potential adjustment circuit is respectively connected to the pull - down power supply terminal and the first node. The potential adjustment circuit is configured to adjust the potential of the first node based on the pull - down power supply signal provided by the pull - down power supply terminal.

7. The pixel circuit according to claim 6, characterized in that, The potential adjustment circuit includes: a storage capacitor. The first end of the storage capacitor is connected to the first node, and the second end of the storage capacitor is connected to the pull - down power supply terminal.

8. A driving method for a pixel circuit, characterized in that, Applied to the pixel circuit according to any one of claims 1 to 7, the method includes: In the reset stage, the potential of the reset power supply signal provided by the reset power supply terminal is a first potential. The reset circuit transmits the reset power supply signal provided by the reset power supply terminal to the first node in response to the reset power supply signal, and the potential of the reset power supply signal is the first potential. In the data writing stage, the potential of the gate driving signal provided by the gate signal terminal is the first potential. The data writing circuit transmits the data signal provided by the data signal terminal to the first node in response to the gate driving signal. In the light - emitting stage, the potential of the first node and the potential of the light - emitting control signal provided by the light - emitting control terminal are both the first potential. The driving circuit controls the conduction between the second node and the third node in response to the potential of the first node. The light - emitting control circuit controls the conduction between the cathode of the light - emitting element and the second node in response to the light - emitting control signal, and controls the conduction between the third node and the pull - down power supply terminal.

9. A display panel, characterized in that, The display panel includes: a substrate, and a plurality of pixels located on the substrate. The pixel includes: a light - emitting element, and the pixel circuit according to any one of claims 1 to 7. The pixel circuit is connected to the light - emitting element, and the pixel circuit is configured to drive the light - emitting element to emit light.

10. A display device, characterized in that, The display device includes: a power supply component, and the display panel according to claim 9. The power supply component is connected to the display panel, and the power supply component is configured to supply power to the display panel.

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