Display substrate and display device

Abstract

A display substrate and a display device, the display substrate comprising a display area (10) and a non-display area (20) surrounding the display area (10); the display substrate further comprises a plurality of scan lines (101), a plurality of data lines (102) and a plurality of data fan-out lines (21), at least part of the scan lines (101) is located in the display area; at least part of the data lines (102) is located in the display area; at least part of the data fan-out lines (21) is located in the non-display area (10), the data fan-out lines (21) are coupled with corresponding data lines (102); the plurality of data fan-out lines (21) comprises a plurality of first data fan-out lines (210) and a plurality of second data fan-out lines (211), the first data fan-out lines (210) are arranged in the same layer and of the same material as the scan lines (101), and the second data fan-out lines (211) are arranged in the same layer and of the same material as the data lines (102).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display substrate and a display device. BACKGROUND

[0002] In recent years, with the progress of display technology, active matrix organic light emitting diode (AMOLED) display panel has become one of the hotspots in the field of flat panel display research. AMOLED display panel has faster response speed, higher contrast ratio and wider viewing angle than traditional thin film transistor liquid crystal display (TFT-LCD). With the development of display technology, more and more electronic devices have higher requirements for the size of the frame of AMOLED display panel, so that AMOLED display panel gradually develops towards narrow frame. SUMMARY

[0003] The purpose of the present disclosure is to provide a display substrate and a display device.

[0004] To achieve the above purpose, the present disclosure provides the following technical solutions.

[0005] The first aspect of the present disclosure provides a display substrate, comprising a display area and a non-display area surrounding the display area; the display substrate further comprises:

[0006] a plurality of scan lines, at least part of the scan lines being located in the display area;

[0007] a plurality of data lines, at least part of the data lines being located in the display area;

[0008] a plurality of data fan-out lines, at least part of the data fan-out lines being located in the non-display area, the data fan-out lines being coupled with corresponding data lines; the plurality of data fan-out lines comprises a plurality of first data fan-out lines and a plurality of second data fan-out lines, the first data fan-out lines being arranged in the same layer and with the same material as the scan lines, and the second data fan-out lines being arranged in the same layer and with the same material as the data lines.

[0009] Optionally, the orthographic projection of at least part of the first data fan-out lines on the base of the display substrate at least partially overlaps with the orthographic projection of the second data fan-out lines on the base.

[0010] Optionally, at least part of the first data fan-out line comprises a first line segment, and at least part of the second data fan-out line comprises a second line segment, a projection of the first line segment on the base is coincident with a projection of the second line segment on the base.

[0011] Optionally, the display substrate further comprises:

[0012] A power line, the power line comprising a first power layer, at least part of the first power layer is located between the first data fan-out line and the second data fan-out line in a direction perpendicular to a base of the display substrate.

[0013] Optionally, the power line further comprises a second power layer, the second power layer is coupled with the first power layer;

[0014] At least part of the first power layer and at least part of the second power layer are both located in the non-display region, the first power layer and the second power layer are stacked, and at least part of the first power layer is located between the second power layer and the base of the display substrate.

[0015] Optionally, at least part of the second data fan-out line is located between the first power layer and the second power layer in a direction perpendicular to the base of the display substrate.

[0016] Optionally, the display substrate further comprises a conductive connection part, at least part of the conductive connection part is located between the first power layer and the second power layer, and the conductive connection part is coupled with the first power layer and the second power layer respectively.

[0017] Optionally, the display substrate comprises a first gate metal layer, a second gate metal layer, a first source-drain metal layer and a second source-drain metal layer which are sequentially stacked away from a base of the display substrate;

[0018] The scan line is provided in the same layer and with the same material as the first gate metal layer, and the data line is provided in the same layer and with the same material as the first source-drain metal layer;

[0019] The first power layer is provided in the same layer and with the same material as the second gate metal layer, the second power layer is provided in the same layer and with the same material as the second source-drain metal layer, and the conductive connection part is provided in the same layer and with the same material as the first source-drain metal layer.

[0020] Optionally, the power line comprises a positive power line, the first power layer comprises a first positive power layer, and the second power layer comprises a second positive power layer;

[0021] At least part of the first positive power supply layer extends along a first direction, the first positive power supply layer comprises a first middle portion and two first end portions, the first middle portion is located between the two first end portions along the first direction, the two first end portions are symmetrical about a middle axis extending along a second direction in the display substrate, and the second direction intersects the first direction;

[0022] A maximum width of the first end portion in the second direction is less than a maximum width of the first middle portion in the second direction.

[0023] Optionally, the first end portion comprises a first target portion, the first target portion has a first width in the second direction, and the first width gradually increases in a direction away from the first middle portion.

[0024] Optionally, the first end portion further comprises a second target portion, the first target portion is located between the second target portion and the first middle portion along the first direction, the second target portion has a second width along the second direction, and the second width gradually decreases in a direction away from the first middle portion.

[0025] Optionally, the non-display area comprises a bending area, a projection of the first middle portion on a base of the display substrate does not overlap a projection of the bending area on the base.

[0026] Optionally, the second positive power supply layer comprises a second middle portion and two second end portions, at least part of the second middle portion is located between the two second end portions along the first direction, and the two second end portions are symmetrical about the middle axis extending along the second direction in the display substrate.

[0027] A projection of the second end portion on a base of the display substrate at least partially overlaps a projection of the first end portion on the base, and a projection of the second middle portion on the base at least partially overlaps a projection of the first middle portion on the base.

[0028] Optionally, the second end portion comprises a third target portion, the third target portion has a third width in the second direction, and the third width gradually increases in a direction away from the second middle portion.

[0029] Optionally, the second end portion further comprises a fourth target portion, the third target portion is located between the fourth target portion and the second middle portion along the first direction, and a width of the fourth target portion in the second direction is equal to a maximum value of the third width.

[0030] Optionally, the second end portion further comprises a fifth target portion, the fourth target portion is located between the fifth target portion and the second intermediate portion along the first direction, the fifth target portion has a fifth width in the second direction, the fifth width gradually decreases in a direction away from the second intermediate portion.

[0031] Optionally, the second intermediate portion comprises:

[0032] a first transmission portion, two ends of the first transmission portion are coupled with the two second end portions one by one;

[0033] a second transmission portion, at least part of the second transmission portion extends along the first direction, the first transmission portion is located between the display area and the second transmission portion;

[0034] at least one connection portion, the at least one connection portion is located between the first transmission portion and the second transmission portion, the connection portion is coupled with the first transmission portion and the second transmission portion respectively; the connection portion has an orthographic projection on the base of the display substrate, and the orthographic projection at least partially overlaps with the orthographic projection of the bending area of the display substrate on the base;

[0035] two first wire-in portions, at least part of the first wire-in portions extends along the second direction, the two first wire-in portions are coupled with two ends of the second transmission portion one by one.

[0036] Optionally, the conductive connection portion comprises two first conductive connection portions, the two first conductive connection portions are symmetrical about the central axis; the first conductive connection portions are coupled with the first end portion and the second end portion respectively.

[0037] Optionally, the first conductive connection portion extends from the lower frame of the display substrate to the side frame of the display substrate.

[0038] Optionally, the orthographic projection of the first conductive connection portion on the base has a first overlapping area with the orthographic projection of the first end portion on the base of the display substrate, the first conductive connection portion is coupled with the first end portion through a first via, and the orthographic projection of the first via on the base at least partially overlaps with the first overlapping area;

[0039] the orthographic projection of the first conductive connection portion on the base has a second overlapping area with the orthographic projection of the second end portion on the base, the first conductive connection portion is coupled with the second end portion through a second via, and the orthographic projection of the second via on the base at least partially overlaps with the second overlapping area.

[0040] Optionally, the first via and the second via are arranged along the first direction.

[0041] Optionally, the display substrate further comprises:

[0042] a plurality of gate driving circuits and a plurality of first signal lines for providing corresponding signals to the plurality of gate driving circuits;

[0043] a projection of the first via on the base substrate is located between a projection of the plurality of first signal lines on the base substrate and a projection of the plurality of data fan-out lines on the base substrate;

[0044] a projection of the second via on the base substrate at least partially overlaps with a projection of at least part of the first signal lines on the base substrate.

[0045] Optionally, the power supply lines comprise negative power supply lines, the first power supply layer comprises a first negative power supply layer, and the second power supply layer comprises a second negative power supply layer.

[0046] The first negative power supply layer comprises two first negative power supply patterns, the two first negative power supply patterns are symmetrical about the central axis, and at least part of the first end portion is located between the display area and the first negative power supply patterns.

[0047] Optionally, the first negative power supply patterns comprise a sixth target portion and a seventh target portion, the sixth target portion is located between the seventh target portion and the central axis, and a width of the sixth target portion in the second direction is greater than a maximum width of the first end portion in the second direction.

[0048] Optionally, the seventh target portion has a seventh width in the second direction, and the seventh width gradually decreases in a direction away from the central axis.

[0049] Optionally, the second negative power supply layer comprises:

[0050] a ring-shaped portion surrounding the display area, the ring-shaped portion having an opening at a lower frame of the display substrate, and at least part of the second end portion is located between the ring-shaped portion and the display area;

[0051] two second wire-in portions, at least part of the second wire-in portions extending in the second direction, and the two second wire-in portions being coupled to two ends of the opening of the ring-shaped portion one by one.

[0052] Optionally, the second wire-in portion is provided with an opening hole, and a projection of the opening hole on a base substrate of the display substrate at least partially overlaps with a projection of a bending area in the display substrate on the base substrate.

[0053] Optionally, the conductive connection part includes a second conductive connection part, the second conductive connection part surrounds the display area, and the second conductive connection part has an opening at the lower frame of the display substrate; and the second conductive connection part is coupled with the first negative power supply layer and the second negative power supply layer respectively.

[0054] Optionally, the second conductive connection part includes a surrounding part, two first parts and two second parts.

[0055] At least part of the display area is surrounded by the surrounding part, two ends of the surrounding part are coupled with the first ends of the two second parts one by one, and the second ends of the two second parts are coupled with the two first parts one by one, and the two first parts form an opening of the second conductive connection part.

[0056] The extension direction of the first part intersects with the first direction and the second direction, the orthographic projection of the first part on the base of the display substrate has a third overlapping area with the orthographic projection of the first negative power supply layer on the base, the first part is coupled with the first negative power supply layer through a third via hole, and the orthographic projection of the third via hole on the base at least partially overlaps with the third overlapping area.

[0057] At least part of the second part extends along the first direction, the orthographic projection of the second part on the base and / or the orthographic projection of the surrounding part on the base has a fourth overlapping area with the orthographic projection of the second negative power supply layer on the base, and the second part and / or the surrounding part is coupled with the second negative power supply layer through a fourth via hole, and the orthographic projection of the fourth via hole on the base at least partially overlaps with the fourth overlapping area.

[0058] Optionally, the extension direction of the orthographic projection of the third via hole on the base intersects with the first direction and the second direction.

[0059] Based on the technical solutions of the above display substrate, the second aspect of the present disclosure provides a display device including the above display substrate. BRIEF DESCRIPTION OF DRAWINGS

[0060] The accompanying drawings, which are included to provide a further understanding of the present disclosure, constitute a part of the present disclosure, and the illustrative embodiments of the present disclosure and their descriptions serve to explain the present disclosure and do not constitute improper limitations on the present disclosure. In the drawings:

[0061] Figure 1 A schematic diagram of the overall structure of a power line in a display substrate provided by an embodiment of the present disclosure is shown.

[0062] Figure 2 A schematic diagram of a first layout of a data fan-out line provided by an embodiment of the present disclosure is shown.

[0063] Figure 3 A cross-sectional view of a data fan-out line provided by an embodiment of the present disclosure;

[0064] Figure 4 A second layout view of a data fan-out line provided by an embodiment of the present disclosure;

[0065] Figure 5 A schematic view of a data fan-out line coupled with a fan-out extension line provided by an embodiment of the present disclosure;

[0066] Figure 6 A third layout view of a data fan-out line provided by an embodiment of the present disclosure;

[0067] Figure 7 A fourth layout view of a data fan-out line provided by an embodiment of the present disclosure;

[0068] Figure 8 A structure view of a portion of a positive power supply line and a negative power supply line at a lower left corner of a display substrate provided by an embodiment of the present disclosure;

[0069] Figure 9 A first layout view of a lower left corner of a display substrate provided by an embodiment of the present disclosure;

[0070] Figure 10 A second layout view of a lower left corner of a display substrate provided by an embodiment of the present disclosure;

[0071] Figure 11 A layout view of an active layer of a lower left corner of a display substrate provided by an embodiment of the present disclosure;

[0072] Figure 12 A layout view of a first gate metal layer of a lower left corner of a display substrate provided by an embodiment of the present disclosure;

[0073] Figure 13 A layout view of a second gate metal layer of a lower left corner of a display substrate provided by an embodiment of the present disclosure;

[0074] Figure 14 A layout view of an interlayer insulating layer of a lower left corner of a display substrate provided by an embodiment of the present disclosure;

[0075] Figure 15 A layout view of a first source-drain metal layer of a lower left corner of a display substrate provided by an embodiment of the present disclosure;

[0076] Figure 16 A layout view of a second source-drain metal layer of a lower left corner of a display substrate provided by an embodiment of the present disclosure;

[0077] Figure 17A layout schematic diagram of a second gate metal layer and a first source-drain metal layer in a lower left corner of a display substrate provided by an embodiment of the present disclosure is shown in FIG. 1A.

[0078] Figure 18 A layout schematic diagram of a first source-drain metal layer and a second source-drain metal layer in a lower left corner of a display substrate provided by an embodiment of the present disclosure is shown in FIG. 1B.

[0079] Figure 19 A layout schematic diagram of a passivation layer in a lower left corner of a display substrate provided by an embodiment of the present disclosure is shown in FIG. 1C.

[0080] Figure 20 A layout schematic diagram of a first planarization layer in a lower left corner of a display substrate provided by an embodiment of the present disclosure is shown in FIG. 1D.

[0081] Figure 21 A cross-sectional schematic diagram of a display region in a display substrate provided by an embodiment of the present disclosure is shown in FIG. 1E. DETAILED DESCRIPTION

[0082] To further illustrate the display substrate and display device provided by the embodiments of the present disclosure, the following will describe in detail with reference to the accompanying drawings.

[0083] With the development of display technology, more and more electronic devices have higher requirements for the size of the display panel frame, so that the display panel gradually develops towards a narrow frame direction. Therefore, it is necessary to reduce the size of the structure provided in the frame of the display panel under the condition of meeting the electrical and process requirements, so as to reduce the frame width of the display panel.

[0084] Please refer to Figures 1 to 7 , Figure 12 and Figure 15 , the present disclosure provides a display substrate, comprising: a display region 10 and a non-display region 20 surrounding the display region 10; the display substrate further comprises:

[0085] a plurality of scan lines 101, at least part of the scan lines 101 being located in the display region 10;

[0086] a plurality of data lines 102, at least part of the data lines 102 being located in the display region 10;

[0087] a plurality of data fan-out lines 21, at least part of the data fan-out lines 21 being located in the non-display region 20, the data fan-out lines 21 being coupled with corresponding data lines 102; the plurality of data fan-out lines 21 comprises a plurality of first data fan-out lines 210 and a plurality of second data fan-out lines 211, the first data fan-out lines 210 being provided in the same layer and with the same material as the scan lines 101, and the second data fan-out lines 211 being provided in the same layer and with the same material as the data lines 102.

[0088] Exemplarily, the display substrate includes a display area and a non-display area 20 surrounding the display area 10, the display area 10 includes a plurality of sub-pixels for realizing the display function of the display substrate; the display substrate includes side frames oppositely arranged along a first direction, such as a left frame and a right frame, and the display substrate further includes an upper frame and a lower frame oppositely arranged along a second direction. Exemplarily, the first direction includes a horizontal direction, and the second direction includes a vertical direction.

[0089] As shown in Figure 7 , exemplarily, the plurality of scan lines 101 are arranged along the second direction, and the scan lines 101 include portions extending along the first direction, and at least part of the scan lines 101 are located in the display area. The scan lines 101 are used to provide scan signals for the sub-pixel driving circuit 60 included in the sub-pixels in the display area.

[0090] As shown in Figure 6 and Figure 7 , exemplarily, the plurality of data lines 102 are arranged along the first direction, and the data lines 102 include portions extending along the second direction, and at least part of the data lines 102 are located in the display area. The data lines 102 are used to provide data signals for the sub-pixel driving circuit 60 included in the sub-pixels in the display area.

[0091] As shown in Figure 6 and Figure 7 , exemplarily, the plurality of data fan-out lines 21 correspond to the plurality of data lines 102 one-to-one, and the data fan-out lines 21 are coupled to the corresponding data lines 102 for providing data signals for the corresponding data lines 102. Exemplarily, the plurality of data fan-out lines are located in the lower frame of the display substrate. Exemplarily, the data fan-out lines and the corresponding data lines 102 are coupled through a conductive part A, and the conductive part A is made of a first gate metal layer.

[0092] As shown in Figure 4 and Figure 5 , exemplarily, the display substrate further includes a plurality of fan-out extension lines 212, at least part of the fan-out extension lines 212 correspond to the plurality of data fan-out lines 21 one-to-one, and the fan-out extension lines 212 are respectively coupled to the corresponding data fan-out lines 21 and the corresponding pins in the driving chip, and the fan-out extension lines 212 are used to transmit data signals provided by the driving chip to the corresponding data fan-out lines 21.

[0093] Exemplarily, the display substrate comprises a substrate, and an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer GI2, a second gate metal layer, an interlayer insulating layer ILD, a first source-drain metal layer, a first planarization layer PLN1, a second source-drain metal layer, a second planarization layer, an anode layer, a light-emitting functional layer, and a cathode layer are sequentially stacked on the substrate in a direction away from the substrate. Exemplarily, the display substrate can further comprise a passivation layer PVX between the first source-drain metal layer and the first planarization layer PLN1. It should be noted that Figure 11 A layout diagram of the active layer in the lower left corner of the display substrate is shown.

[0094] As Figure 10 Exemplarily, at least part of the fan-out extension lines 212 extend in the second direction, the plurality of fan-out extension lines 212 are arranged in the first direction with intervals, the fan-out extension lines 212 are arranged in the same layer and made of the same material as the second source-drain metal layer, and the orthogonal projection of the fan-out extension lines 212 on the substrate at least partially overlaps with the orthogonal projection of the bending area 30 of the display substrate on the substrate. Since the side of the second source-drain metal layer facing the substrate is next to the first planarization layer, and the side of the second source-drain metal layer away from the substrate is next to the second planarization layer, and both the first planarization layer and the second planarization layer are made of organic materials, arranging the fan-out extension lines 212 in the same layer and made of the same material as the second source-drain metal layer is beneficial to the reliability of the fan-out extension lines 212 at the bending area 30.

[0095] Exemplarily, the plurality of data fan-out lines comprise a plurality of first data fan-out lines 210 and a plurality of second data fan-out lines 211, and the plurality of first data lines 102 are uniformly distributed, and the plurality of second data lines 102 are uniformly distributed. Arranging the first data fan-out lines 210 in the same layer and made of the same material as the scan lines 101 enables the first data fan-out lines 210 and the scan lines 101 to be formed in the same patterning process. Similarly, arranging the second data fan-out lines 211 in the same layer and made of the same material as the data lines 102 enables the second data fan-out lines 211 and the data lines 102 to be formed in the same patterning process, which can better simplify the manufacturing process of the display substrate and reduce the manufacturing cost of the display substrate.

[0096] As Figure 4 and Figure 5As shown, exemplarily, the fan-out extension line 212 and its corresponding coupled data line 102 are disposed on different layers. The fan-out extension line 212 is directly coupled to the corresponding data line 102 through at least one via; or, the fan-out extension line 212 is coupled to the corresponding data line 102 through at least one via and a conductive portion. It should be noted that the fan-out extension line 212 is directly coupled to the second data fan-out line 211 through at least one via, and the fan-out extension line 212 is coupled to the first data fan-out line 210 through a via and a conductive portion, wherein the conductive portion is made of a first source / drain metal layer.

[0097] As can be seen from the specific structure of the display substrate described above, in the display substrate provided in this embodiment, by setting the multiple data fan-out lines including multiple first data fan-out lines 210 and multiple second data fan-out lines 211, the first data fan-out lines 210 are disposed in the same layer and with the same material as the scan lines 101, and the second data fan-out lines 211 are disposed in the same layer and with the same material as the data lines 102; thus, the first data fan-out lines 210 and the second data fan-out lines 211 are disposed in different layers. In this way, by shortening the distance between the orthographic projection of the first data fan-out line 210 on the substrate and the orthographic projection of the second data fan-out line 211 on the substrate, the overall space occupied by the multiple data fan-out lines is reduced, and the overall width of the multiple data fan-out lines in the second direction is reduced, thereby effectively narrowing the bottom bezel width of the display substrate and improving the competitiveness of the display products formed by the display substrate.

[0098] like Figure 3 As shown, in some embodiments, at least a portion of the orthographic projection of the first data fan-out line 210 on the substrate 80 of the display substrate is provided to at least partially overlap with the orthographic projection of the second data fan-out line 211 on the substrate 80.

[0099] The above configuration shortens the distance between the orthographic projection of the first data fan-out line 210 on the substrate and the orthographic projection of the second data fan-out line 211 on the substrate, reducing the overall space occupied by the multiple data fan-out lines, thereby effectively narrowing the bottom bezel width of the display substrate and enhancing the competitiveness of the display products formed by the display substrate.

[0100] like Figures 2 to 7 As shown, in some embodiments, at least a portion of the first data fan-out line 210 includes a first line segment, and at least a portion of the second data fan-out line 211 includes a second line segment, wherein the orthographic projection of the first line segment on the substrate coincides with the orthographic projection of the second line segment on the substrate.

[0101] For example, the extension direction of the first line segment intersects both the first direction and the second direction.

[0102] In the display substrate provided by the above embodiment, by setting the orthographic projection of the first line segment on the base to coincide with the orthographic projection of the second line segment on the base, the problem of uneven line width of the first data fan-out line 210 and the second data fan-out line 211 is improved, the distance between the orthographic projection of the first data fan-out line 210 on the base and the orthographic projection of the second data fan-out line 211 on the base is further shortened, the space occupied by the plurality of data fan-out lines as a whole is reduced, thereby effectively narrowing the lower frame width of the display substrate, and improving the competitiveness of the display product formed by the display substrate.

[0103] As Figure 3 , Figure 8 , Figure 9 , Figure 13 , Figure 16 , Figure 17 and Figure 18 indicate that, in some embodiments, the display substrate further comprises:

[0104] a power line, the power line comprising a first power layer (such as a first positive power layer 220 and a first negative power layer 240), at least part of the first power layer being located between the first data fan-out line 210 and the second data fan-out line 211 in a direction perpendicular to the base of the display substrate.

[0105] For example, the orthographic projection of the first power layer on the base at least partially overlaps the orthographic projection of the first data fan-out line 210 on the base. For example, the orthographic projection of the first power layer on the base at least partially overlaps the orthographic projection of the second data fan-out line 211 on the base.

[0106] In the display substrate provided by the above embodiment, by setting at least part of the first power layer to be located between the first data fan-out line 210 and the second data fan-out line 211, the first power layer can separate the first data fan-out line 210 and the second data fan-out line 211 in a direction perpendicular to the base, and since a static direct current signal is transmitted on the first power layer, the crosstalk between the first data fan-out line 210 and the second data fan-out line 211 is effectively reduced.

[0107] As Figure 3 , Figure 8 , Figure 9 , Figure 13 , Figure 16 , Figure 17 and Figure 18As shown, in some embodiments, the power line further includes a second power layer (such as a second positive power layer 221, a second negative power layer 241), which is coupled to the first power layer.

[0108] At least a portion of the first power layer and at least a portion of the second power layer are both located in the non-display area 20. The first power layer and the second power layer are stacked, and at least a portion of the first power layer is located between the second power layer and the substrate of the display substrate.

[0109] For example, the power cord includes a positive power cord 22 and a negative power cord 24.

[0110] For example, the first power layer and the second power layer are stacked, and in a direction perpendicular to the substrate, at least a portion of the first power layer is located between the second power layer and the substrate of the display substrate.

[0111] For example, the orthographic projection of the first power layer on the substrate at least partially overlaps with the orthographic projection of the second power layer on the substrate.

[0112] In the display substrate provided in the above embodiments, by setting the power line to include the first power layer and the second power layer, the area of ​​the power line is effectively increased, and the voltage drop (loading) of the power signal transmitted on the power line is reduced.

[0113] like Figure 3 As shown, in some embodiments, at least a portion of the second data fan-out line 211 is located between the first power layer (such as the first positive power layer 220, the first negative power layer 240) and the second power layer (such as the second positive power layer 221, the second negative power layer 241) in a direction perpendicular to the base of the display substrate.

[0114] For example, the orthographic projection of the second data fanout line 211 on the substrate at least partially overlaps with the orthographic projection of the first power layer on the substrate.

[0115] The above-mentioned arrangement, in which at least a portion of the second data fan-out line 211 is located between the first power layer and the second power layer, not only effectively reduces crosstalk between the first data fan-out line 210 and the second data fan-out line 211, but also ensures the stability of the data signal transmitted on the second data fan-out line 211.

[0116] like Figure 8 , Figure 9 , Figure 15 ,Figure 17 and Figure 18 As shown, in some embodiments, the display substrate further includes conductive connection portions (such as a first conductive connection portion 23 and a second conductive connection portion 25), at least a portion of which is located between the first power layer (such as a first positive power layer 220 and a first negative power layer 240) and the second power layer (such as a second positive power layer 221 and a second negative power layer 241), and the conductive connection portions are coupled to the first power layer and the second power layer respectively.

[0117] For example, the orthographic projection of the conductive connection on the substrate at least partially overlaps with the orthographic projection of the first power layer on the substrate; the orthographic projection of the conductive connection on the substrate at least partially overlaps with the orthographic projection of the second power layer on the substrate.

[0118] For example, the conductive connection portion is disposed on a different layer from both the first power layer and the second power layer. In the direction perpendicular to the substrate, at least a portion of the conductive connection portion is located between the first power layer and the second power layer. The conductive connection portion is coupled to the first power layer and the second power layer respectively through corresponding vias.

[0119] The display substrate described above also includes conductive connection portions, which are coupled to the first power layer and the second power layer respectively, thus ensuring the connection performance between the first power layer and the second power layer.

[0120] like Figure 6 , Figure 7 and Figure 20 As shown, in some embodiments, the display substrate includes a first gate metal layer 96, a second gate metal layer 97, a first source / drain metal layer SD1, and a second source / drain metal layer SD2, which are sequentially stacked along a direction away from the substrate of the display substrate.

[0121] The scan line 101 is disposed in the same layer and with the same material as the first gate metal layer 96, and the data line 102 is disposed in the same layer and with the same material as the first source and drain metal layer SD1.

[0122] The first power layer and the second gate metal layer 97 are disposed in the same layer and with the same material, the second power layer and the second source / drain metal layer SD2 are disposed in the same layer and with the same material, and the conductive connection portion is disposed in the same layer and with the first source / drain metal layer SD1.

[0123] like Figure 6As shown, the first gate metal layer 96 includes the gate of the thin film transistor and the plate of the capacitor in the sub-pixel driving circuit 60; the second gate metal layer 97 includes the plate of the capacitor in the sub-pixel driving circuit 60, and some signal lines in the display substrate; the first source-drain metal layer SD1 includes some signal lines in the display substrate, and some conductive connection patterns; and the second source-drain metal layer SD2 includes some signal lines in the display substrate, and some conductive connection patterns.

[0124] It should be noted that, Figure 21 The base 90, the active layer 98, the first planarization layer PLN1, the second planarization layer PLN2, the pixel definition layer PDL, the anode layer 91, the light-emitting functional layer EL, the cathode layer 92, the first inorganic encapsulation layer 93, and the organic encapsulation layer 94 are also shown in FIG. 1.

[0125] The above-described arrangement of the scan line 101 in the same layer and of the same material as the first gate metal layer 96 enables the scan line 101 and the first gate metal layer 96 to be formed in the same patterning process; the above-described arrangement of the data line 102 in the same layer and of the same material as the first source-drain metal layer SD1 enables the data line 102 and the first source-drain metal layer SD1 to be formed in the same patterning process; the above-described arrangement of the first power supply layer in the same layer and of the same material as the second gate metal layer 97 enables the first power supply layer and the second gate metal layer 97 to be formed in the same patterning process; the above-described arrangement of the second power supply layer in the same layer and of the same material as the second source-drain metal layer SD2 enables the second power supply layer and the second source-drain metal layer SD2 to be formed in the same patterning process; and the above-described arrangement of the first conductive connection part 23 in the same layer and of the same material as the first source-drain metal layer SD1 enables the first conductive connection part 23 and the first source-drain metal layer SD1 to be formed in the same patterning process. Therefore, the display substrate provided by the above-described embodiment can effectively simplify the manufacturing process of the display substrate and reduce the manufacturing cost of the display substrate when the display substrate is arranged in the above-described manner.

[0126] It should be noted that the "same layer" in the embodiments of the present disclosure can refer to a film layer on the same structure layer. Alternatively, for example, the film layers in the same layer can be layers formed by using the same film forming process to form a film layer for forming a specific pattern, and then patternizing the film layer by using the same mask plate through a one-time patterning process. According to different specific patterns, the one-time patterning process can include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure can be continuous or discontinuous. These specific patterns can also be at different heights or have different thicknesses.

[0127] As Figure 8 , Figure 9 , Figure 13 ,Figure 15 、 Figure 16 In some embodiments, the power lines include a positive power line 22, the first power layer includes a first positive power layer 220, and the second power layer includes a second positive power layer 221.

[0128] At least part of the first positive power layer 220 extends along a first direction, the first positive power layer 220 includes a first middle portion 2202 and two first end portions 2201, the first middle portion 2202 is located between the two first end portions 2201 along the first direction, and the two first end portions 2201 are symmetrical about a middle axis 40 extending along a second direction in the display substrate, the second direction intersecting the first direction.

[0129] As shown in FIG. 1, a maximum width of the first end portion 2201 in the second direction is less than a maximum width of the first middle portion 2202 in the second direction. Figure 8 In an example, the power lines include a positive power line 22 for transmitting a positive power signal VDD. The first power layer includes a first positive power layer 220, and the second power layer includes a second positive power layer 221, the first positive power layer 220 being coupled with the second positive power layer 221.

[0130] In an example, the first positive power layer 220 includes a first middle portion 2202 and two first end portions 2201, the first middle portion 2202 and the two first end portions 2201 being formed as an integral structure.

[0131] In an example, a width of the first middle portion 2202 in the second direction is uniform or non-uniform.

[0132] In an example, the first middle portion 2202 is symmetrical about the middle axis 40 extending along the second direction in the display substrate, and the two first end portions 2201 are symmetrical about the middle axis 40 extending along the second direction in the display substrate.

[0133] The display substrate provided by the above embodiments effectively reduces the layout difficulty of the first positive power layer 220 by setting the first positive power layer 220 to include the first middle portion 2202 and the two first end portions 2201, and ensures the uniformity and stability of the signal transmitted by the positive power line 22.

[0134] In an example, the display substrate further includes a second positive power line 222, the second positive power line 222 being arranged on the second positive power layer 221.

[0135] Figure 13 ​As shown, in some embodiments, the first end portion 2201 includes a first target portion 2201a, which has a first width D1 in the second direction, and the first width D1 gradually increases in the direction away from the first intermediate portion 2202.

[0136] For example, the first width D1 can range from 71 micrometers to 157 micrometers and may include endpoint values.

[0137] In the display substrate provided in the above embodiments, by setting the first end 2201 to include the first target portion 2201a, not only is a good connection performance between the first positive power layer 220 and the second positive power layer 221 guaranteed, but the layout difficulty of the first positive power layer 220 is also effectively reduced, ensuring the uniformity and stability of the signal transmitted by the positive power line 22.

[0138] like Figure 8 and Figure 13 As shown, in some embodiments, the first end portion 2201 further includes a second target portion 2201b, which is located between the second target portion 2201b and the first intermediate portion 2202 along the first direction. The second target portion 2201b has a second width D2 along the second direction, and the second width D2 gradually decreases along the direction away from the first intermediate portion 2202.

[0139] For example, the second target portion 2201b and the first target portion 2201a are formed as an integral structure.

[0140] For example, the second width D2 is less than or equal to 157 micrometers.

[0141] In the display substrate provided in the above embodiments, by setting the first end 2201 to also include a second target portion 2201b, not only is good connection performance between the first positive power layer 220 and the second positive power layer 221 guaranteed, but the layout difficulty of the first positive power layer 220 is also effectively reduced, ensuring the uniformity and stability of the signal transmitted by the positive power line 22.

[0142] like Figure 8 As shown, in some embodiments, the non-display area 20 includes a bending area 30, and the orthographic projection of the first intermediate portion 2202 on the substrate of the display substrate does not overlap with the orthographic projection of the bending area 30 on the substrate.

[0143] For example, the non-display area 20 includes a bending area 30, which is located on the lower edge of the display substrate and extends along the first direction.

[0144] The above setting the first intermediate portion 2202 on the base of the display substrate, the projection, and the projection of the bending area 30 on the base do not overlap, avoid the first intermediate portion 2202 bending, thereby guaranteeing the reliability of the first intermediate portion 2202.

[0145] As shown in Figure 8 , Figure 9 , Figure 16 and Figure 18 indicated, in some embodiments, the second positive power layer 221 includes: a second intermediate portion 2210 and two second end portions 2211, at least part of the second intermediate portion 2210 is located between the two second end portions 2211 along the first direction, and the two second end portions 2211 are symmetric about the central axis 40 extending in the second direction in the display substrate.

[0146] The projection of the second end portion 2211 on the base of the display substrate at least partially overlaps the projection of the first end portion 2201 on the base; the projection of the second intermediate portion 2210 on the base at least partially overlaps the projection of the first intermediate portion 2202 on the base.

[0147] Exemplarily, the second positive power layer 221 includes a second intermediate portion 2210 and two second end portions 2211, and the second intermediate portion 2210 and the two second end portions 2211 are formed as an integral structure.

[0148] Exemplarily, the second intermediate portion 2210 is symmetric about the central axis 40 extending in the second direction in the display substrate, and the two second end portions 2211 are symmetric about the central axis 40 extending in the second direction in the display substrate.

[0149] In the display substrate provided by the above embodiment, by setting the second positive power layer 221 to include a second intermediate portion 2210 and two second end portions 2211, the layout difficulty of the second positive power layer 221 is effectively reduced, and the uniformity and stability of the signal transmitted by the positive power line 22 are guaranteed.

[0150] As shown in Figure 16 indicated, in some embodiments, the second end portion 2211 includes a third target portion 2211a, the third target portion 2211a has a third width D3 in the second direction, and the third width D3 gradually increases in a direction away from the second intermediate portion 2210.

[0151] Exemplarily, the third width D3 is in a range of 73 microns to 175 microns, and can include an end point value.

[0152] In the display substrate provided by the above embodiment, by arranging that the second end portion 2211 further comprises the third target portion 2211a, not only is the connection performance between the first positive power supply layer 220 and the second positive power supply layer 221 ensured, but also the layout difficulty of the second positive power supply layer 221 is effectively reduced, and the uniformity and stability of the signal transmitted by the positive power supply line 22 are ensured.

[0153] As shown in Figure 16 In some embodiments, the second end portion 2211 further comprises a fourth target portion 2211b, and the third target portion 2211a is located between the fourth target portion 2211b and the second intermediate portion 2210 along the first direction, and the fourth target portion 2211b has a width D4 in the second direction, and the width D4 is equal to the maximum value of the third width D3.

[0154] For example, the width D4 in the second direction is uniform.

[0155] For example, the value of the width D4 includes 175 microns. For example, the value of the width D4 ranges between 170 microns and 180 microns, and can include the end point value.

[0156] In the display substrate provided by the above embodiment, by arranging that the second end portion 2211 further comprises the fourth target portion 2211b, and the width of the fourth target portion 2211b in the second direction is equal to the maximum value of the third width, not only is the connection performance between the first positive power supply layer 220 and the second positive power supply layer 221 ensured, but also the layout difficulty of the second positive power supply layer 221 is effectively reduced, and the uniformity and stability of the signal transmitted by the positive power supply line 22 are ensured.

[0157] As shown in Figure 16 In some embodiments, the second end portion 2211 further comprises a fifth target portion 2211c, and the fourth target portion 2211b is located between the fifth target portion 2211c and the second intermediate portion 2210 along the first direction, and the fifth target portion 2211c has a fifth width D5 in the second direction, and the fifth width D5 gradually decreases in the direction away from the second intermediate portion 2210.

[0158] For example, the value of the fifth width D5 ranges between 84 microns and 175 microns, and can include the end point value.

[0159] For example, the fifth target portion 2211c, the fourth target portion 2211b and the third target portion 2211a are formed as an integral structure.

[0160] In the display substrate provided by the above embodiment, the second end portion 2211 further comprises the fifth target portion 2211c, the fifth target portion 2211c has a fifth width in the second direction, and the fifth width gradually decreases in a direction away from the second intermediate portion 2210. Not only is the connection performance between the first positive power supply layer 220 and the second positive power supply layer 221 ensured, but also the layout difficulty of the second positive power supply layer 221 is effectively reduced, and the uniformity and stability of the signal transmitted by the positive power supply line 22 are ensured.

[0161] As shown in Figure 8 In some embodiments, the second intermediate portion 2210 comprises:

[0162] a first transmission portion 2210a, both ends of the first transmission portion 2210a are coupled with the two second end portions 2211 one by one;

[0163] a second transmission portion 2210b, at least part of the second transmission portion 2210b extends in the first direction, and the first transmission portion 2210a is located between the display area and the second transmission portion 2210b;

[0164] at least one connecting portion 2210c, the at least one connecting portion 2210c is located between the first transmission portion 2210a and the second transmission portion 2210b, and the connecting portion 2210c is coupled with the first transmission portion 2210a and the second transmission portion 2210b respectively; the orthographic projection of the connecting portion 2210c on the base of the display substrate at least partially overlaps with the orthographic projection of the bending area 30 of the display substrate on the base;

[0165] two first wire-in portions 2210d, at least part of the first wire-in portion 2210d extends in the second direction, and the two first wire-in portions 2210d are coupled with both ends of the second transmission portion 2210b one by one.

[0166] For example, the first transmission portion 2210a, the second transmission portion 2210b, the at least one connecting portion 2210c and the two first wire-in portions 2210d are formed as an integral structure.

[0167] As shown in Figure 1 For example, the display area of the display substrate is provided with a grid-shaped power supply layer 103, and the first transmission portion 2210a is coupled with the grid-shaped power supply layer 103.

[0168] For example, the length of the first transmission portion 2210a in the first direction is less than the length of the second transmission portion 2210b in the first direction.

[0169] Exemplarily, the second intermediate portion 2210 comprises a plurality of connection portions 2210c located between the first transmission portion 2210a and the second transmission portion 2210b, the plurality of connection portions 2210c are arranged in the first direction, and each of the connection portions 2210c is coupled with the first transmission portion 2210a and the second transmission portion 2210b respectively.

[0170] Exemplarily, the connection portion 2210c is at least partially overlapped with the projection of the bending area 30 of the display substrate on the substrate, and at least part of the connection portion 2210c is bent.

[0171] Exemplarily, the two first wire-in portions 2210d extend away from the display area in the second direction. The two first wire-in portions 2210d are coupled with a driving chip to receive a positive power signal provided by the driving chip.

[0172] The second intermediate portion 2210 is arranged as described above, which not only ensures the reliability of the second positive power layer 221 when bending, guarantees the good transmission performance of the second positive power layer 221, but also effectively reduces the layout difficulty of the second positive power layer 221, and guarantees the uniformity and stability of the transmission signal of the positive power line 22.

[0173] As shown in Figure 8 , Figure 9 , Figure 15 , Figure 17 and Figure 18 In some embodiments, the conductive connection portion comprises two first conductive connection portions 23, the two first conductive connection portions 23 are symmetrical about the central axis 40; and the first conductive connection portion 23 is coupled with the first end portion 2201 and the second end portion 2211 respectively.

[0174] Exemplarily, the two first conductive connection portions 23 correspond to the two first end portions 2201 one by one, the two first conductive connection portions 23 correspond to the two second end portions 2211 one by one, and the first conductive connection portion 23 is coupled with the corresponding first end portion 2201 and the corresponding second end portion 2211 respectively.

[0175] The display substrate provided by the above embodiments comprises the two first conductive connection portions 23, which not only guarantees the good connection performance of the first positive power layer 220 and the second positive power layer 221, but also effectively reduces the layout difficulty of the conductive connection portion, and guarantees the uniformity and stability of the transmission signal of the positive power line 22.

[0176] As Figure 8 , Figure 9 , Figure 15 , Figure 17 and Figure 18 indicated, in some embodiments, the first conductive connection part 23 is arranged to extend from the lower frame of the display substrate to the side frame of the display substrate.

[0177] For example, among the two first conductive connection parts 23, one first conductive connection part 23 extends from the lower frame of the display substrate to the left side frame of the display substrate, and the other first conductive connection part 23 extends from the lower frame of the display substrate to the right side frame of the display substrate.

[0178] For example, the first conductive connection part 23 extends along the corner of the display area in an arc shape.

[0179] The above arrangement can better reduce the voltage drop of the positive power line 22 when transmitting a power signal.

[0180] As Figure 9 , Figure 10 , Figure 14 , Figures 17 to 20 indicated, in some embodiments, the first conductive connection part 23 has a first overlapping area with the orthographic projection of the first end part 2201 on the substrate, the first conductive connection part 23 is coupled to the first end part 2201 through a first via Via1, and the orthographic projection of the first via Via1 on the substrate at least partially overlaps with the first overlapping area.

[0181] The orthographic projection of the first conductive connection part 23 on the substrate has a second overlapping area with the orthographic projection of the second end part 2211 on the substrate, the first conductive connection part 23 is coupled to the second end part 2211 through a second via Via2, and the orthographic projection of the second via Via2 on the substrate at least partially overlaps with the second overlapping area.

[0182] For example, the first via Via1 penetrates the interlayer insulating layer, and the second via Via2 penetrates the passivation layer and the first planar layer. For example, when the display substrate does not include a passivation layer, the second via Via2 only penetrates the first planar layer.

[0183] In some embodiments, the first via Via1 and the second via Via2 are arranged along the first direction.

[0184] The above arrangement is conducive to narrowing the width of the lower frame of the display substrate.

[0185] like Figure 9 , Figure 10 , Figure 14 , Figures 17 to 20 As shown, in some embodiments, the display substrate further includes:

[0186] Multiple gate drive circuits GOA and multiple first signal lines 50 for providing corresponding signals to the multiple gate drive circuits GOA;

[0187] The orthographic projection of the first via Via1 on the substrate is located between the orthographic projections of the plurality of first signal lines 50 on the substrate and the orthographic projections of the plurality of data fan-out lines on the substrate;

[0188] The orthographic projection of the second via Via2 on the substrate overlaps with at least a portion of the orthographic projection of the first signal line 50 on the substrate.

[0189] For example, the gate drive circuit GOA is disposed on the left and right bezels of the display substrate, and the plurality of first signal lines 50 are disposed on the left and right sides of the lower bezel of the display substrate. The first signal lines 50 are coupled to the driver chip via connecting lines. It should be noted that the connecting lines are located at... Figure 16 The location marked 70 can also be equipped with touch connection lines for transmitting touch signals. Additionally, as... Figure 6 As shown, the gate drive circuit GOA can provide a scan signal to the scan line through the signal transmission line B.

[0190] The above configuration can effectively narrow the width of the bottom bezel of the display substrate while avoiding a short circuit between the positive power line 22 and the first signal line 50.

[0191] like Figure 1 , Figure 8 , Figure 9 , Figure 13 , Figure 16 , Figure 17 and Figure 18 As shown, in some embodiments, the power line includes a negative power line 24, the first power layer includes a first negative power layer 240, and the second power layer includes a second negative power layer 241.

[0192] The first negative power layer 240 includes two first negative power patterns 2401, which are symmetrical about the central axis 40, and at least a portion of the first end 2201 is located between the display area and the first negative power pattern 2401.

[0193] For example, the power line includes a negative power line 24 for transmitting a negative power signal VSS. The first power layer includes a first negative power layer 240, and the second power layer includes a second negative power layer 241, with the first negative power layer 240 and the second negative power layer 241 coupled together.

[0194] For example, at least a portion of the orthographic projection of the first negative power supply pattern 2401 onto the substrate is located between the orthographic projection of the first signal line 50 onto the substrate and the orthographic projection of the first end 2201 onto the substrate.

[0195] The above-mentioned configuration of the first negative power supply layer 240 includes two first negative power supply patterns 2401, which are symmetrical about the central axis 40. This effectively reduces the layout difficulty of the first negative power supply layer 240 and ensures the uniformity and stability of the signal transmitted by the negative power supply line 24.

[0196] like Figure 13 As shown, in some embodiments, the first negative power source pattern 2401 includes a sixth target portion 2401a and a seventh target portion 2401b, the sixth target portion 2401a being located between the seventh target portion 2401b and the central axis 40, and the width D6 of the sixth target portion 2401a in the second direction being greater than the maximum width (e.g., D2) of the first end portion 2201 in the second direction.

[0197] For example, the sixth target portion 2401a and the seventh target portion 2401b are formed as an integral structure.

[0198] For example, the width of the sixth target portion 2401a in the second direction may be uniform or non-uniform.

[0199] For example, the width D6 can be 392 micrometers. For example, the width D6 can range from 387 micrometers to 397 micrometers, and may include endpoint values.

[0200] The width of the sixth target portion 2401a in the second direction is greater than the maximum width of the first end portion 2201 in the second direction, which effectively ensures the transmission performance of the negative power line 24 and reduces the voltage drop generated when the negative power line 24 transmits signals.

[0201] like Figure 13 As shown, in some embodiments, the seventh target portion 2401b is provided with a seventh width D7 in the second direction, and the seventh width D7 gradually decreases along the direction away from the central axis 40.

[0202] For example, the seventh width D7 can range from 73 micrometers to 392 micrometers and may include endpoint values.

[0203] The above configuration not only ensures good connection performance between the first negative power layer 240 and the second negative power layer 241, but also effectively reduces the layout difficulty of the first negative power pattern 2401, and ensures the uniformity and stability of the signal transmitted by the negative power line 24.

[0204] like Figure 8 and Figure 16 As shown, in some embodiments, the second negative power supply layer 241 includes:

[0205] An annular portion 2411 surrounds the display area and has an opening on the lower edge of the display substrate. At least a portion of the second end portion 2211 is located between the annular portion 2411 and the display area.

[0206] Two second cable inlets 2412, at least a portion of which extends along the second direction, are coupled one-to-one with the two ends of the annular portion 2411 at the opening.

[0207] For example, the annular portion 2411 and the two second infeed portions 2412 are formed as an integral structure.

[0208] For example, at least a portion of the second inlet 2412 extends along the second direction in a direction away from the display area.

[0209] For example, the annular portion 2411 and the two second infeed portions 2412 are both symmetrical about the central axis 40.

[0210] For example, at least a portion of the second transmission section 2210b, the first input section 2210d, and the connection section 2210c are located between the two second input sections 2412.

[0211] For example, one end of the second input line 2412 away from the display area is coupled to the driver chip and receives the negative power signal provided by the driver chip.

[0212] By configuring the second negative power layer 241 with the above structure, not only is the layout difficulty of the negative power line 24 reduced, but the stability and uniformity of the signal transmission of the negative power line 24 are also guaranteed.

[0213] like Figure 8As shown, in some embodiments, the second inlet portion 2412 is provided with an opening 2412a, the orthographic projection of the opening 2412a on the substrate of the display substrate at least partially overlaps with the orthographic projection of the bending area 30 in the display substrate on the substrate.

[0214] The above configuration can better ensure the reliability of the second infeed section 2412 when it bends in the bending area 30.

[0215] like Figure 8 , Figure 9 , Figure 15 , Figure 17 and Figure 18 As shown, in some embodiments, the conductive connection portion includes a second conductive connection portion 25, which surrounds the display area and has an opening on the lower edge of the display substrate; the second conductive connection portion 25 is coupled to the first negative power supply layer 240 and the second negative power supply layer 241 respectively.

[0216] For example, the second conductive connection portion 25 is symmetrical about the central axis 40.

[0217] The above configuration effectively ensures the connection performance between the first negative power layer 240 and the second negative power layer 241, and guarantees the uniformity and stability of the signal transmitted by the negative power line 24.

[0218] like Figure 9 , Figures 13 to 20 As shown, in some embodiments, the second conductive connection portion 25 includes: a surrounding portion 251, two first portions 252 and two second portions 253;

[0219] At least a portion of the display area is surrounded by the surrounding portion 251, the two ends of the surrounding portion 251 are coupled one-to-one with the first ends of the two second portions 253, the second ends of the two second portions 253 are coupled one-to-one with the two first portions 252, and an opening of the second conductive connection portion 25 is formed between the two first portions 252.

[0220] like Figure 9 , Figure 13 , Figure 15 and Figure 17As shown, the extension direction of the first portion 252 intersects both the first direction and the second direction. The orthographic projection of the first portion 252 on the substrate of the display substrate has a third overlapping area with the orthographic projection of the first negative power layer 240 on the substrate. The first portion 252 is coupled to the first negative power layer 240 through a third via Via3. The orthographic projection of the third via Via3 on the substrate at least partially overlaps with the third overlapping area.

[0221] like Figure 9 , Figure 15 , Figure 16 , Figures 18 to 20 As shown, at least a portion of the second part 253 extends along the first direction, and the orthographic projection of the second part 253 on the substrate and / or the orthographic projection of the surrounding portion on the substrate has a fourth overlapping area with the orthographic projection of the second negative power layer 241 on the substrate. The second part 253 and / or the surrounding portion are coupled to the second negative power layer 241 through a fourth via Via4, and the orthographic projection of the fourth via Via4 on the substrate at least partially overlaps with the fourth overlapping area.

[0222] For example, the surrounding portion 251, the two first portions 252 and the two second portions 253 are formed as an integral structure.

[0223] For example, the surrounding portion 251 is symmetrical about the central axis 40, the two first portions 252 are symmetrical about the central axis 40, and the two second portions 253 are symmetrical about the central axis 40.

[0224] For example, the surrounding portion 251 is not closed on the lower edge of the display substrate and has two ends. For example, the two first portions 252 are not directly connected, and an opening for the second conductive connection portion 25 is formed between the two first portions 252.

[0225] For example, the third via Via3 penetrates the interlayer insulating layer, and the fourth via Via4 penetrates the passivation layer and the first planarization layer. For example, when the display substrate does not include a passivation layer, the fourth via Via4 only penetrates the first planarization layer.

[0226] For example, at least a portion of the orthographic projection of the fourth via Via4 onto the substrate extends along the first direction. For example, at least a portion of the orthographic projection of the fourth via Via4 onto the substrate extends along a corner region of the display substrate.

[0227] By configuring the second conductive connection portion 25 with the above structure, the connection performance between the first negative power supply layer 240 and the second negative power supply layer 241 is well guaranteed, and the uniformity and stability of the signal transmitted by the negative power supply line 24 are guaranteed.

[0228] like Figure 14 As shown, in some embodiments, the extension direction of the orthographic projection of the third via Via3 on the substrate intersects both the first direction and the second direction.

[0229] The above arrangement not only helps to reduce the layout difficulty of the negative power line 24 and the second conductive connection part 25, but also ensures the connection performance between the first negative power layer 240 and the second negative power layer 241.

[0230] This disclosure also provides a display device, including the display substrate provided in the above embodiments.

[0231] In the display substrate provided in the above embodiments, by setting the multiple data fan-out lines including multiple first data fan-out lines 210 and multiple second data fan-out lines 211, the first data fan-out lines 210 are disposed in the same layer and with the same material as the scan lines 101, and the second data fan-out lines 211 are disposed in the same layer and with the same material as the data lines 102; thus, the first data fan-out lines 210 and the second data fan-out lines 211 are disposed in different layers. In this way, by shortening the distance between the orthographic projection of the first data fan-out line 210 on the substrate and the orthographic projection of the second data fan-out line 211 on the substrate, the overall space occupied by the multiple data fan-out lines is reduced, and the overall width of the multiple data fan-out lines in the second direction is reduced, thereby effectively narrowing the bottom bezel width of the display substrate and improving the competitiveness of the display products formed by the display substrate.

[0232] Therefore, the display device provided in this embodiment of the present disclosure, when including the above-described display substrate, also has the above-described beneficial effects, which will not be repeated here.

[0233] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer.

[0234] This disclosure also provides a method for manufacturing a display substrate. The method is used to manufacture the display substrate provided in the above embodiments. The display substrate includes: a display area and a non-display area 20 surrounding the display area; the manufacturing method includes: manufacturing multiple scan lines 101, multiple data lines 102, and multiple data fan-out lines.

[0235] At least a portion of the scan line 101 is located in the display area;

[0236] At least a portion of the data line 102 is located in the display area;

[0237] At least a portion of the data fan-out line is located in the non-display area 20, and the data fan-out line is coupled to the corresponding data line 102; the multiple data fan-out lines include multiple first data fan-out lines 210 and multiple second data fan-out lines 211, the first data fan-out lines 210 are disposed in the same layer and with the same material as the scan line 101, and the second data fan-out lines 211 are disposed in the same layer and with the same material as the data line 102.

[0238] For example, the multiple data fan-out lines include multiple first data fan-out lines 210 and multiple second data fan-out lines 211. The multiple first data lines 102 are evenly distributed, and the multiple second data lines 102 are evenly distributed. The first data fan-out lines 210 and the scan lines 101 are disposed in the same layer and made of the same material, so that the first data fan-out lines 210 and the scan lines 101 can be formed in the same patterning process. Similarly, the second data fan-out lines 211 and the data lines 102 are disposed in the same layer and made of the same material, so that the second data fan-out lines 211 and the data lines 102 can be formed in the same patterning process. This simplifies the manufacturing process of the display substrate and reduces the manufacturing cost of the display substrate.

[0239] In the display substrate manufactured using the manufacturing method provided in this embodiment, the multiple data fan-out lines include multiple first data fan-out lines 210 and multiple second data fan-out lines 211. The first data fan-out lines 210 are disposed in the same layer and with the same material as the scan lines 101, and the second data fan-out lines 211 are disposed in the same layer and with the same material as the data lines 102. This allows the first data fan-out lines 210 and the second data fan-out lines 211 to be disposed in different layers. In this way, by shortening the distance between the orthographic projection of the first data fan-out line 210 on the substrate and the orthographic projection of the second data fan-out line 211 on the substrate, the overall space occupied by the multiple data fan-out lines is reduced, and the overall width of the multiple data fan-out lines in the second direction is reduced. This effectively narrows the bottom bezel width of the display substrate and enhances the competitiveness of the display products formed by the display substrate.

[0240] In the various method embodiments of this disclosure, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps are within the scope of protection of this disclosure without any creative effort.

[0241] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0242] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0243] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0244] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0245] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display substrate, comprising: The display area and the non-display area surrounding the display area; The display substrate further includes: Multiple scan lines, at least a portion of which are located in the display area; Multiple data lines, at least a portion of which are located in the display area; Multiple data fan-out lines, at least a portion of which are located in the non-display area, are coupled to corresponding data lines; the multiple data fan-out lines include multiple first data fan-out lines and multiple second data fan-out lines, wherein the first data fan-out lines are disposed in the same layer and material as the scan lines, and the second data fan-out lines are disposed in the same layer and material as the data lines; The display substrate further includes: A power line, the power line including a first power layer, wherein at least a portion of the first power layer is located between the first data fan-out line and the second data fan-out line in a direction perpendicular to the base of the display substrate.

2. The display substrate according to claim 1, wherein, At least a portion of the orthographic projection of the first data fan-out line onto the substrate of the display substrate overlaps at least partially with the orthographic projection of the second data fan-out line onto the substrate.

3. The display substrate according to claim 2, wherein, At least a portion of the first data fan-out line includes a first line segment, and at least a portion of the second data fan-out line includes a second line segment, wherein the orthographic projection of the first line segment on the substrate coincides with the orthographic projection of the second line segment on the substrate.

4. The display substrate according to claim 1, wherein, The power line also includes a second power layer, which is coupled to the first power layer; At least a portion of the first power layer and at least a portion of the second power layer are both located in the non-display area. The first power layer and the second power layer are stacked together, and at least a portion of the first power layer is located between the second power layer and the substrate of the display substrate.

5. The display substrate according to claim 4, wherein, In a direction perpendicular to the substrate of the display substrate, at least a portion of the second data fan-out line is located between the first power layer and the second power layer.

6. The display substrate according to claim 4 or 5, wherein, The display substrate further includes a conductive connection portion, at least a portion of which is located between the first power layer and the second power layer, and the conductive connection portion is coupled to the first power layer and the second power layer respectively.

7. The display substrate according to claim 6, wherein, The display substrate includes a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer, which are sequentially stacked along a direction away from the substrate of the display substrate. The scan lines are disposed in the same layer and with the same material as the first gate metal layer, and the data lines are disposed in the same layer and with the same material as the first source and drain metal layers. The first power layer and the second gate metal layer are disposed in the same layer and with the same material, the second power layer and the second source / drain metal layer are disposed in the same layer and with the same material, and the conductive connection portion is disposed in the same layer and with the first source / drain metal layer.

8. The display substrate according to claim 6, wherein, The power line includes a positive power line, the first power layer includes a first positive power layer, and the second power layer includes a second positive power layer. At least a portion of the first positive power layer extends along a first direction. The first positive power layer includes a first intermediate portion and two first ends. The first intermediate portion is located between the two first ends along the first direction. The two first ends are symmetrical about a central axis extending along a second direction in the display substrate. The second direction intersects the first direction. The maximum width of the first end portion in the second direction is less than the maximum width of the first middle portion in the second direction.

9. The display substrate according to claim 8, wherein, The first end portion includes a first target portion having a first width in the second direction, the first width gradually increasing in a direction away from the first middle portion.

10. The display substrate according to claim 9, wherein, The first end portion further includes a second target portion, which is located between the second target portion and the first intermediate portion along the first direction. The second target portion has a second width along the second direction, and the second width gradually decreases along the direction away from the first intermediate portion.

11. The display substrate according to claim 8, wherein, The non-display area includes a bending area, and the orthographic projection of the first middle portion onto the substrate of the display substrate does not overlap with the orthographic projection of the bending area onto the substrate.

12. The display substrate according to claim 8, wherein, The second positive power layer includes: a second intermediate portion and two second ends, at least a portion of the second intermediate portion being located between the two second ends along the first direction, and the two second ends being symmetrical about a central axis extending along the second direction in the display substrate; The orthographic projection of the second end portion onto the substrate of the display substrate at least partially overlaps with the orthographic projection of the first end portion onto the substrate; the orthographic projection of the second middle portion onto the substrate at least partially overlaps with the orthographic projection of the first middle portion onto the substrate.

13. The display substrate according to claim 12, wherein, The second end portion includes a third target portion having a third width in the second direction, the third width gradually increasing in a direction away from the second middle portion.

14. The display substrate according to claim 13, wherein, The second end also includes a fourth target portion, and the third target portion is located between the fourth target portion and the second intermediate portion along the first direction, wherein the width of the fourth target portion in the second direction is equal to the maximum value of the third width.

15. The display substrate according to claim 14, wherein, The second end also includes a fifth target portion, and the fourth target portion is located between the fifth target portion and the second intermediate portion along the first direction. The fifth target portion has a fifth width in the second direction, and the fifth width gradually decreases along the direction away from the second intermediate portion.

16. The display substrate according to claim 12, wherein, The second intermediate part includes: A first transmission section, wherein the two ends of the first transmission section are coupled one-to-one with the two second ends; A second transmission unit, at least a portion of which extends along the first direction, and the first transmission unit is located between the display area and the second transmission unit; At least one connecting portion is located between the first transmission portion and the second transmission portion, and the connecting portion is coupled to the first transmission portion and the second transmission portion respectively; the orthographic projection of the connecting portion on the substrate of the display substrate at least partially overlaps with the orthographic projection of the bending area of ​​the display substrate on the substrate. Two first input lines, at least a portion of which extend along the second direction, are coupled one-to-one with the two ends of the second transmission section.

17. The display substrate according to claim 12, wherein, The conductive connection portion includes two first conductive connection portions, which are symmetrical about the central axis; the first conductive connection portions are respectively coupled to the first end and the second end.

18. The display substrate according to claim 17, wherein, The first conductive connection extends from the lower edge of the display substrate to the side edge of the display substrate.

19. The display substrate according to claim 17, wherein, The orthographic projection of the first conductive connection portion on the substrate and the orthographic projection of the first end portion on the substrate of the display substrate have a first overlapping area. The first conductive connection portion is coupled to the first end portion through a first via. The orthographic projection of the first via portion on the substrate at least partially overlaps with the first overlapping area. The orthographic projection of the first conductive connection portion on the substrate and the orthographic projection of the second end portion on the substrate have a second overlapping area. The first conductive connection portion is coupled to the second end portion through a second via. The orthographic projection of the second via portion on the substrate at least partially overlaps with the second overlapping area.

20. The display substrate according to claim 19, wherein, The first via and the second via are arranged along the first direction.

21. The display substrate according to claim 19, wherein, The display substrate further includes: Multiple gate drive circuits and multiple first signal lines for providing corresponding signals to the multiple gate drive circuits; The orthographic projection of the first via on the substrate is located between the orthographic projections of the plurality of first signal lines on the substrate and the orthographic projections of the plurality of data fan-out lines on the substrate; The orthographic projection of the second via on the substrate overlaps with at least a portion of the orthographic projection of the first signal line on the substrate.

22. The display substrate according to claim 12, wherein, The power line includes a negative power line, the first power layer includes a first negative power layer, and the second power layer includes a second negative power layer. The first negative power layer includes two first negative power patterns, which are symmetrical about the central axis, and at least a portion of the first end is located between the display area and the first negative power pattern.

23. The display substrate according to claim 22, wherein, The first negative power source pattern includes a sixth target portion and a seventh target portion. The sixth target portion is located between the seventh target portion and the central axis. The width of the sixth target portion in the second direction is greater than the maximum width of the first end in the second direction.

24. The display substrate according to claim 23, wherein, The seventh target portion has a seventh width in the second direction, and the seventh width gradually decreases along the direction away from the central axis.

25. The display substrate according to claim 22, wherein, The second negative power supply layer includes: An annular portion surrounding the display area, the annular portion having an opening on the lower edge of the display substrate, and at least a portion of the second end located between the annular portion and the display area; Two second cable inlets, at least a portion of which extend along the second direction, are coupled one-to-one with the two ends of the annular portion at the opening.

26. The display substrate according to claim 25, wherein, The second inlet section is provided with an opening, and the orthographic projection of the opening on the substrate of the display substrate at least partially overlaps with the orthographic projection of the bending area in the display substrate on the substrate.

27. The display substrate according to claim 22, wherein, The conductive connection portion includes a second conductive connection portion surrounding the display area, and the second conductive connection portion having an opening on the lower edge of the display substrate; the second conductive connection portion is coupled to the first negative power layer and the second negative power layer respectively.

28. The display substrate according to claim 27, wherein, The second conductive connection portion includes: The surrounding section consists of two first parts and two second parts; At least a portion of the display area is surrounded by the surrounding portion, and the two ends of the surrounding portion are coupled one-to-one with the first ends of the two second portions. The second ends of the two second portions are coupled one-to-one with the two first portions. An opening of the second conductive connection portion is formed between the two first portions. The extension direction of the first part intersects both the first direction and the second direction. The orthographic projection of the first part on the substrate of the display substrate has a third overlapping area with the orthographic projection of the first negative power layer on the substrate. The first part is coupled to the first negative power layer through a third via. The orthographic projection of the third via on the substrate at least partially overlaps with the third overlapping area. At least a portion of the second part extends along the first direction, and the orthographic projection of the second part on the substrate and / or the orthographic projection of the surrounding portion on the substrate has a fourth overlapping area with the orthographic projection of the second negative power layer on the substrate. The second part and / or the surrounding portion is coupled to the second negative power layer through a fourth via, and the orthographic projection of the fourth via on the substrate at least partially overlaps with the fourth overlapping area.

29. The display substrate according to claim 28, wherein, The extension direction of the orthographic projection of the third via on the substrate intersects both the first direction and the second direction.

30. A display device comprising a display substrate as claimed in any one of claims 1 to 29.

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