Drive unit for an electric vehicle

Abstract

An exemplary drive unit for an electric vehicle includes a first electric motor, a first axle mechanically couplable to the first electric motor, a second electric motor, a second axle mechanically couplable to the second electric motor, and a dual power inverter module electrically couplable to a high voltage DC power source. The dual power inverter module includes a first inverter configured to convert the high voltage DC power to three-phase high voltage AC power and electrically couplable to provide the three-phase high voltage AC power to the first electric motor, a second inverter configured to convert the high voltage DC power to three-phase high voltage AC power and electrically couplable to provide the three-phase high voltage AC power to the second electric motor, and a common controller configured to control the first inverter and the second inverter.

Description

Technical Field

[0001] This disclosure relates to an inverter for a drive unit in an electric vehicle. Background Technology

[0002] Conventional electric vehicles with two electric motors per drive unit have two inverters (one inverter per motor), and each inverter is controlled by its own inverter controller. The use of a separate inverter controller for each inverter increases weight and energy consumption, resulting in a reduction in vehicle range. Summary of the Invention

[0003] The various embodiments disclosed in this invention include electric vehicles and exemplary drive units for electric vehicles.

[0004] In an exemplary embodiment, a drive unit for an electric vehicle includes: a first electric motor; a first axle mechanically coupled to the first electric motor; a second electric motor; a second axle mechanically coupled to the second electric motor; and a dual-power inverter module electrically coupled to a high-voltage direct current (DC) power source. The dual-power inverter module includes: a first inverter configured to convert high-voltage DC power into three-phase high-voltage alternating current (AC) power and electrically coupled to provide three-phase high-voltage AC power to the first electric motor; a second inverter configured to convert high-voltage DC power into three-phase high-voltage AC power and electrically coupled to provide three-phase high-voltage AC power to the second electric motor; and a common controller configured to control the first and second inverters.

[0005] In another exemplary embodiment, the drive unit for an electric vehicle includes: a first synchronous electric motor; a first axle mechanically coupled to the first synchronous electric motor; a second synchronous electric motor; a second axle mechanically coupled to the second synchronous electric motor; a first gear set mechanically coupled between the first synchronous electric motor and the first axle; a second gear set mechanically coupled between the second synchronous electric motor and the second axle; and a dual-power inverter module electrically coupled to a high-voltage direct current (DC) power source. The dual-power inverter module includes: a first inverter configured to convert high-voltage DC power into three-phase high-voltage alternating current (AC) power and electrically coupled to provide three-phase high-voltage AC power to the first synchronous electric motor; a second inverter configured to convert high-voltage DC power into three-phase high-voltage AC power and electrically coupled to provide three-phase high-voltage AC power to the second synchronous electric motor; and a common controller configured to control the first and second inverters.

[0006] In another exemplary embodiment, the electric vehicle includes: a body; a high-voltage direct current (DC) battery disposed within the body; and at least one drive unit. The at least one drive unit includes: a first electric motor; a first axle mechanically coupled to the first electric motor; a second electric motor; a second axle mechanically coupled to the second electric motor; and a dual-power inverter module electrically coupled to a high-voltage direct current (DC) power source. The dual-power inverter module includes: a first inverter configured to convert high-voltage DC power into three-phase high-voltage alternating current (AC) power and electrically coupled to provide three-phase high-voltage AC power to the first electric motor; a second inverter configured to convert high-voltage DC power into three-phase high-voltage AC power and electrically coupled to provide three-phase high-voltage AC power to the second electric motor; and a common controller configured to control the first and second inverters.

[0007] The above description of the invention is merely illustrative and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, other aspects, embodiments, and features will become apparent from the accompanying drawings and the following detailed description. Attached Figure Description

[0008] Exemplary embodiments are shown in the accompanying drawings. The embodiments and drawings disclosed herein are intended to be illustrative and not restrictive.

[0009] Figure 1A This is a schematic diagram of an exemplary electric vehicle having at least one drive unit.

[0010] Figure 1B It has an exemplary driver unit. Figure 1A A perspective view of the lower body structure of an electric vehicle.

[0011] Figure 2A yes Figure 1B A perspective view of an exemplary driving unit.

[0012] Figure 2B yes Figure 1B Another perspective view of the drive unit.

[0013] Figure 2C yes Figure 1B Side plan view of the drive unit.

[0014] Figure 2D yes Figure 1B An exploded perspective view of the drive unit.

[0015] Figure 2E This is a perspective view of another exemplary drive unit.

[0016] Figure 3A It is a block diagram in the form of a partial schematic of an exemplary dual inverter with common control.

[0017] Figure 3B This is a perspective view of an exemplary dual inverter with common control.

[0018] Figure 4A This is a simplified schematic diagram of an exemplary dual inverter with a common DC link capacitor.

[0019] Figure 4B and Figure 4C It is a graph of the waveform without the elimination of ripples.

[0020] Figure 4D This is a flowchart illustrating an exemplary method for synchronizing pulse width modulation clocks.

[0021] Figure 4E and Figure 4F It is a graph of an exemplary ripple waveform with elimination.

[0022] Figure 4G The lookup table is shown.

[0023] Figure 5A This is a block diagram of an exemplary component of a drive unit configured to place two inverters in a safe state in response to a detected fault associated with either inverter.

[0024] Figure 5B It is a curve of torque versus speed.

[0025] Figure 5C yes Figure 5A A block diagram detailing the components.

[0026] Figure 5D This is a simplified schematic diagram of an open-circuit upper and lower three-terminal power semiconductor device.

[0027] Figure 5E This is a simplified schematic diagram of the lower group of three-terminal power semiconductor devices with short circuit.

[0028] Figure 5F This is a simplified schematic diagram of the upper three-terminal power semiconductor device with short circuit.

[0029] Figure 5G This is a flowchart of an exemplary method for placing two inverters of a drive unit into a safe state in response to a detected fault associated with either inverter.

[0030] Figure 6A This is a schematic diagram of an exemplary circuit used to detect the loss of low-voltage DC power.

[0031] Figure 6BIt is a block diagram in the form of a partial schematic diagram showing the details of an exemplary backup circuit used to provide low-voltage DC power.

[0032] Figure 6C This is a flowchart of a method for placing the two inverters of a drive unit in a safe state in response to the loss of low-voltage DC power.

[0033] The same reference symbols in various diagrams generally indicate the same elements. Detailed Implementation

[0034] In the following detailed description, reference is made to the accompanying drawings, which form part of the detailed description. In the drawings, like reference numerals generally identify like parts unless the context otherwise indicates. The exemplary embodiments described in the detailed description, drawings, and claims are not intended to be limiting. Other embodiments may be utilized and other changes may be made without departing from the spirit or scope of the subject matter presented herein.

[0035] Various publicly available implementations include exemplary dual-power inverter modules, electric vehicles, and methods.

[0036] Now for reference Figure 1A and Figure 1B As outlined in various embodiments, the electric vehicle 10 includes a body 12. A high-voltage direct current (DC) battery 14 is disposed within the body 12. Left front wheels and right front wheels 16 (only left front wheel 16 is shown) and left rear wheels and right rear wheels 18 (only left rear wheel 18 is shown) are configured to rotate. At least one drive unit 20 is mechanically coupled to rotate either the front wheel 16 or the rear wheel 18 (and in some embodiments, one drive unit 20 is mechanically coupled to rotate the front wheel 16, and another drive unit 20 is mechanically coupled to rotate the rear wheel 18). Each drive unit 20 is electrically connected to receive high-voltage DC power from the battery 14. Each drive unit 20 includes axles 22A and 22B mechanically coupled to rotate the associated wheel 16 or 18; and electric motors 24A and 24B mechanically coupled to rotate their respective associated axles 22A and 22B. As will be explained below, each drive unit 20 also includes a dual-power inverter module 26 electrically connected to receive high-voltage DC power from battery 14. The dual-power inverter module 26 includes two inverters (not shown) configured to generate three-phase high-voltage alternating current (AC) power from the high-voltage DC power and to supply three-phase high-voltage AC power to an associated electric motor. A common controller (not shown) is configured to control both inverters in the dual-power inverter module 26.

[0037] For the sake of simplicity, illustrative details are set forth below in the context of motor vehicles by way of non-limiting example. However, it should be understood that vehicle 10 may be any type of vehicle as required, without limitation. As shown by way of non-limiting example, in various embodiments, vehicle 10 may be an electric vehicle (i.e., a fully electric vehicle) or a hybrid vehicle. For example, and as shown by way of non-limiting example, in various embodiments, vehicle 10 may include a motor vehicle driven by wheels and / or rails, such as, but not limited to, automobiles, trucks, SUVs, vans, all-terrain vehicles (ATVs), motorcycles, electric bicycles, tractors, lawnmowers, such as, but not limited to, ride-on lawnmowers, snowmobiles, etc. As shown by another non-limiting example, in various embodiments, vehicle 10 may include marine vessels, such as, but not limited to, small boats, ships, submarines, submersibles, autonomous underwater vehicles (AUVs), etc. As given by way of another non-limiting example, in various embodiments, vehicle 10 may include an aircraft, such as, but not limited to, a fixed-wing aircraft, a rotary-wing aircraft, and a light-above-air (LTA) aircraft.

[0038] For the sake of brevity, exemplary details regarding the drive unit 20 are set forth in the context of a motor vehicle. Since the vehicle 10 is not limited to the exemplary example of a motor vehicle, it should be understood that the drive unit 20 is not limited to applications in motor vehicles. Therefore, in various embodiments, one(s) of the drive unit 20 is configured to drive the vehicle 10. That is, in various embodiments, one(s) of the electric motors of the drive unit 20 can drive any drive component that drives any propulsion device, such as, but not limited to, one or more wheels, one or more tracks, one or more propellers, one or more thrusters, one or more rotors, etc., associated with the vehicle 10.

[0039] For example, in some embodiments of a motor vehicle, a drive unit 20 may include a motor configured to drive a drive member (such as an axle or chain link) that drives a wheel or track; in some other embodiments of a motor vehicle, a drive unit 20 may include a motor configured to drive an axle that rotates two wheels or two tracks; and in some other embodiments of a motor vehicle, a drive unit 20 may include: a motor configured to drive an axle that rotates a wheel or track; and another motor configured to drive another axle that rotates another wheel or track.

[0040] Similarly, in some embodiments of a marine vessel, a drive unit 20 may include a motor configured to drive a propeller or thruster; in some other embodiments of a marine vessel, a drive unit 20 may include a motor configured to drive a shaft that rotates two propellers or two thrusters; and in some other embodiments of a marine vessel, a drive unit 20 may include: a motor configured to drive a shaft that rotates a propeller or thruster; and another motor configured to drive another shaft that rotates another propeller or thruster.

[0041] Similarly, in some embodiments of the aircraft, a drive unit 20 may include a motor configured to drive a propeller or rotor; in some other embodiments of the aircraft, a drive unit 20 may include a motor configured to drive a shaft that rotates two propellers or two rotors; and in some other embodiments of the aircraft, a drive unit 20 may include: a motor configured to drive a shaft that rotates a propeller or rotor; and another motor configured to drive another shaft that rotates another propeller or rotor.

[0042] Now that the overview has been given, illustrative details will be explained with examples, which are given for illustrative purposes only and not as limitations.

[0043] As described above, at least one drive unit 20 is mechanically coupled to rotate the front wheel 16 or the rear wheel 18 (and in some embodiments, one drive unit 20 is mechanically coupled to rotate the front wheel 16, and another drive unit 20 is mechanically coupled to rotate the rear wheel 18). Also as mentioned above, each drive unit 20 includes axles 22A and 22B, which are mechanically coupled to rotate the associated wheel 16 or 18; and electric motors 24A and 24B, which are mechanically coupled to rotate their respective associated axles 22A and 22B.

[0044] For further reference Figures 2A to 2E In various embodiments, each electric motor 24A and 24B is mechanically coupled to its associated axle 22A and 22B via gear sets 28A and 28B, respectively. Each of the gear sets 28A and 28B is configured to provide speed and torque conversion from its associated electric motor 24A or 24B to its associated axle 22A or 22B, and ultimately to the associated wheel 16 or 18.

[0045] like Figure 2DAs shown, shaft 21A is configured to rotate via its associated rotor 27 of electric motor 24A, and shaft 21B is configured to rotate via its associated rotor 27 of electric motor 24B. Shafts 21A and 21B are supported and constrained within bearings (not shown) disposed on frame 19. Gear set 28A is disposed within frame 19 and configured to rotatably engage wheel shaft 22A, and gear set 28B is disposed within frame 19 and configured to rotatably engage wheel shaft 22B. Electric motor 24A is configured to rotatably engage gear set 28A, and electric motor 24B is configured to rotatably engage gear set 28B.

[0046] In various embodiments, each of gear sets 28A and 28B is configured to provide speed and torque conversion from its associated electric motor 24A or 24B to its associated axle 22A or 22B, and ultimately to the associated wheel 16 or 18. For example, and by way of illustration only, in various embodiments, gear 28C is configured to rotate via its associated shaft 21A or 21B. Gear 28D is mounted on a shaft (not shown for clarity) and configured to mesh with gear 28C. Gear 28E is also mounted on a shaft (not shown for clarity). Gear 28F is mounted on axle 22A or 22B and configured to mesh with gear 28E. It should be understood that in various embodiments, gear sets 28A and 28B may include any number of suitable gears (such as, but not limited to, planetary gears), wherein the gear ratios are selected according to the needs of a particular application to achieve the desired speed and torque conversion. It should be understood that gears for electric vehicles are well known in the art. Therefore, in order to understand the subject matter disclosed in this invention, it is not necessary to further describe their construction and operation.

[0047] In some embodiments, axles 22A and 22B may be fixedly coupled to their associated wheels 16 or 18. For example, but not limited to, in some such embodiments, the front wheel 16 may be fixedly coupled to its associated axles 22A and 22B. It should be understood that such fixed coupling may help reduce mechanical complexity and may help enable the front wheel 16 to remain steerable (such as when towing the vehicle 10 with the front wheel 16 and rear wheel 18 engaged on the road surface (i.e., flat towing)).

[0048] In some other embodiments, axles 22A and 22B may be removably coupled to their associated wheels 16 or 18. For example, but not limited to, in some such embodiments, rear wheel 18 may be removably coupled to its associated axles 22A and 22B. It should be understood that such removable coupling of rear wheel 18 may help avoid the generation of braking torque and / or uncontrolled power generation during towing.

[0049] It should be understood that each drive unit 20 drives either the left or right front wheels 16 or the left or right rear wheels 18. Therefore, the electric motors 24A and 24B of a given drive unit 20 can both experience the same or similar range of speed and torque requirements. To serve such a range of speed and torque requirements, in various embodiments, the electric motors 24A and 24B of a given drive unit 20 can both have the same voltage and current ratings. For example, in various embodiments (such as in high-voltage systems), the line-to-line voltage rating can be in the range of about 300 Vrms to about 600 Vrms, and the current rating can be in the range of about 300 Arms to about 900 Arms. Given only as an example without limitation, an exemplary voltage rating could be 312 Vrms, and an exemplary current rating could be 550 Arms (based on a 400VDC system). However, it should be understood that the electric motors 24A and 24B can have any voltage and current ratings required for a particular application.

[0050] In various embodiments, electric motors 24A and 24B can be any suitable type of electric motor as required. For example, in some embodiments, electric motors 24A and 24B may include synchronous electric motors. In some such embodiments, synchronous electric motors may include, but are not limited to, permanent magnet electric motors. In some other embodiments, electric motors 24A and 24B may include, but are not limited to, asynchronous motors (or induction motors), similar to multiphase AC induction motors.

[0051] As described above, in various embodiments, each drive unit 20 drives either the left or right front wheels 16 or the left or right rear wheels 18, and therefore, the electric motors 24A and 24B of a given drive unit 20 can both experience the same or similar speed and torque demand range. Thus, in various embodiments, the two inverters of a given drive unit 20 can have the same voltage output rating and the same current output rating. By way of illustration and not limitation, in various embodiments, the two inverters of a given drive unit 20 can have a voltage output rating of 312 Vrms and a current output rating of 550 Arms (based on a 400 VDC input). However, it should be understood that the inverters of a given drive unit 20 can have any voltage output rating and any current output rating required for a particular application.

[0052] It should be understood that, in various implementations, the dual-power inverter module 26 can be physically associated with the frame 19 in any suitable manner required for a particular application. For example, but not limited to, in some implementations, and as... Figures 2A to 2C As shown, the dual-power inverter module 26 can be a module within a sealed container and physically mounted on frame 19 outside the frame. As another example and as... Figure 2EAs shown, but not limited to, in some other embodiments, the dual-power inverter module 26 may be integrated with the frame 19. In some such embodiments, the housing 29 has an opening (not shown) defined therein. Inverter circuitry (described below) is disposed in the housing 29. In such embodiments, the opening of the housing 29 mates with an opening (not shown) in the frame 19. Such other embodiments are discussed in co-owned U.S. Patent Application Serial No. 17 / 244,288, filed April 29, 2021, entitled “Inverter Module for Integration with Vehicle Drive Unit,” which is assigned to and filed by the applicant, the entire contents of which are incorporated herein by reference.

[0053] For further reference Figure 3A and Figure 3B In various embodiments, a dual power inverter module (DPIM) 26 is provided. As described above, in various embodiments, the DPIM 26 includes two inverters 30A and 30B configured to generate three-phase high-voltage AC power from high-voltage DC power and supply three-phase high-voltage AC power to an associated electric motor 24A or 24B; and a common controller 32 configured to control both inverters 30A and 30B.

[0054] In various embodiments, the DC link capacitor 34 may be electrically connected to a high-voltage DC power source, such as battery 14. In some embodiments, the electrical connection to battery 14 may include electrical connector 36. A suitable cable 38 may be electrically connected to electrical connector 36 and may also be electrically connected to battery 14.

[0055] In various embodiments, power inverter 30A may be electrically connected to DC link capacitor 34 and is configured to convert high-voltage DC power into three-phase high-voltage AC power. Power inverter 30A is further configured to supply three-phase high-voltage AC power to electric motor 24A (such as a right motor or a left motor). Power inverter 30B may be electrically connected to DC link capacitor 34 and is configured to convert high-voltage DC power into three-phase high-voltage AC power. Power inverter 30B is further configured to supply three-phase high-voltage AC power to electric motor 24B (such as the left motor or the other of the right motor).

[0056] In various embodiments, a common controller 32 may be electrically connected to power inverters 30A and 30B. The common controller 32 is configured to control power inverters 30A and 30B. The common controller 32 may be any suitable computer processor-based controller as required. Given by way of example only and not limitation, in various embodiments, the common controller 32 may include a computer processing unit (CPU), a general-purpose processor, a digital signal processor, a field-programmable gate array, and / or any combination thereof. While controllers are well-known and further descriptions of their construction and operation are not necessary for understanding the disclosed subject matter, further details regarding the common controller 32 will be set forth below with respect to additional functionality.

[0057] In various implementations, the common controller 32 may be electrically connected to receive low-voltage DC power, such as 12VDC. The common controller 32 may also be electrically connected to receive vehicle status signals and vehicle fault indication signals. Exemplary responses to various vehicle faults and 12VDC losses will be further discussed below.

[0058] In various implementations, power inverter 30A and power inverter 30B each include a group 40 of three-terminal power semiconductor devices 42 and a group 44 of three-terminal power semiconductor devices 42.

[0059] In some embodiments, the three-terminal power semiconductor device 42 may include an insulated-gate bipolar transistor (IGBT). In some such embodiments, the IGBT may include a silicon (Si) IGBT. In some embodiments, the three-terminal power semiconductor device 42 may include a metal-oxide-semiconductor field-effect transistor (MOSFET). In some such embodiments, the MOSFET may include a silicon carbide (SiC) MOSFET. However, it should be understood that the three-terminal power semiconductor device 42 may also include a power semiconductor device 42 comprising at least three terminals and may include additional terminals, such as, but not limited to, a Kelvin source terminal, a Kelvin emitter terminal, a current sensing terminal, and / or a temperature sensing terminal.

[0060] It should be understood that SiC MOSFETs offer advantages over Si IGBTs at low phase currents and have a lower conduction drop compared to IGBTs below 700 Apk. However, it should be understood that this value can vary depending on the size of the inverter. Therefore, it should be understood that SiC MOSFETs can provide an efficiency gain of up to approximately 3% to 5% in a typical drive cycle compared to Si IGBTs.

[0061] In some all-wheel drive (AWD) electric vehicles 10, the front wheels 16 serve as the sole drive wheels until additional torque and / or power beyond a predetermined amount is required. In such electric vehicles 10, when additional torque and / or power beyond a predetermined amount is required, the rear wheels are driven solely by their associated drive units 20. In some such AWD electric vehicles 10, to utilize the efficiency of SiC MOSFETs relative to Si IGBTs, the drive unit 20 driving the front wheels 16 may include an inverter 40 with SiC MOSFETs, and the drive unit 20 driving the rear wheels 18 may include an inverter 40 with Si IGBTs. However, it should be understood that any drive unit 20 may include an inverter 40, which may include SiC MOSFETs or SiIGBTs as needed.

[0062] In various embodiments, power inverter 30A includes gate drive circuitry 46A configured to drive the gate terminals 48 of groups 40 and 44 of three-terminal power semiconductor devices 42 of power inverter 30A. Similarly, power inverter 30B includes gate drive circuitry 46B configured to drive the gate terminals 48 of groups 40 and 44 of three-terminal power semiconductor devices 42 of power inverter 30B. In various embodiments, among other functions, controller 32 is configured to generate low-power on and off signals 66A and 66B, and to provide on and off signals 66A and 66B to gate drive circuitry 46A and 46B, respectively. The low-power on and off signals 66A and 66B can be approximately a few milliamps of current and logic level voltage (such as 3.3V or 5V).

[0063] In various embodiments, gate drive circuits 46A and 46B include suitable power amplifiers that amplify low-power on / off signals 66A and 66B and generate high-power on / off signals 66A' and 66B'. To drive gate terminal 48, the high-power on / off signals 66A' and 66B' can be several hundred milliamps or approximately amperes, with voltages ranging from 15V to 20V, depending on the specific application. The high-power on / off signals 66A' and 66B' are then electrically coupled to drive the associated gate terminal 48. Gate drive circuitry is well-known, and further description of its construction and operation is unnecessary for understanding the disclosed subject matter.

[0064] In view of the illustrative details provided above by way of non-limiting examples, it should be understood that, in various embodiments, providing a controller 32 for two inverters 30A and 30B may serve the following purposes: (i) a single interface for vehicle status signals and vehicle fault indication signals; (ii) a single DC link capacitor 34; (iii) a single common controller 32; and (iv) a single interface for low-voltage DC power, such as 12VDC.

[0065] In view of the illustrative details provided above by way of non-limiting example, it should be understood that, in various embodiments, integrating the mounting of DPIM 26 with drive unit 20 can provide integration of the coolant interface. For example, in various embodiments, water cooling provided for inverters 30A and 30B can be provided to the stator windings of electric motors 24A and 24B.

[0066] As described above, in various embodiments, a single motor 24A or 24B drives a single wheel, such as a front wheel 16 or a rear wheel 18. It should be understood that each wheel can operate with unique speed and torque. As illustrated by a non-limiting example, going around a curve or losing traction can produce different wheel speeds, while traction control or torque vectoring can result in different wheel torques. Also as mentioned above, in various embodiments, the dual-power inverter module 26 combines two inverters 30A and 30B into a single module 26 and thus shares common components such as the DC link capacitor 34.

[0067] Therefore, various embodiments include only one DC link capacitor 34, which is electrically connected to provide high-voltage DC power to both inverters 30A and 30B of the DPIM 26. It should be understood that the size of the DC link capacitor 34 can be reduced and possibly minimized. As explained below, various embodiments can help reduce stress on the DC link capacitor 34 (which can have a reduced size) and ripple current on the DC high-voltage bus (which can include cable 38) due to high-frequency current harmonics generated from inverters 30A and 30B.

[0068] In various implementations, inverters 30A and 30B use pulse width modulation (PWM) to generate variable amplitude and frequency voltage sources to drive electric motors 24A and 24B. Different PWM methods (such as, for example, continuous PWM and discontinuous PWM) can be employed depending on the specific needs of the situation. Each PWM method generates its own unique ripple current harmonic spectrum, which can be reflected on the DC bus.

[0069] For example, in continuous PWM, each phase switches continuously (i.e., in various implementations, all three-terminal power semiconductor devices 42 in both inverters 30A and 30B switch continuously). Therefore, continuous PWM can result in insignificant switching losses in inverters 30A and 30B. In continuous PWM, the second harmonic of the switching frequency is the dominant harmonic frequency in the ripple current. Continuous PWM (such as space vector modulation) can be used when it is desirable to minimize harmonic content and ripple on the AC output and DC input currents, as well as to minimize acoustic noise. For example, some vehicles may use continuous PWM at high torque to minimize acoustic noise.

[0070] As another example, in discontinuous PWM, each phase switches discontinuously (i.e., in various implementations, all three-terminal power semiconductor devices 42 in both inverters 30A and 30B are not switched discontinuously). In such implementations, only two of the three phases switch at any given time, and the remaining third phase keeps either the upper or lower switch continuously on, thus contributing to increased inverter efficiency and reducing losses during discontinuous PWM. It should be understood that the use of discontinuous PWM can have other non-beneficial effects, such as increased acoustic noise or harmonic content in the AC output or DC input current. In discontinuous PWM, each phase has two 60-degree segments in which the switch remains low or high and does not switch a total of 120 degrees within the fundamental cycle. That is, in discontinuous PWM, each phase is not switched for one-third of the time. This results in significantly lower switching losses and higher efficiency. It should be understood that while discontinuous PWM requires lower switching losses than continuous PWM, it may also require higher acoustic noise, and harmonics can be placed across motors 24A and 24B and the DC link capacitor 34. In discontinuous PWM, the first harmonic of the switching frequency is the dominant harmonic frequency. Discontinuous PWM can be used where the highest efficiency and lowest losses are desired, and acoustic noise is not a problem. For example, some vehicles may have thermal problems under high torque, and therefore, discontinuous PWM is used to reduce losses under those conditions.

[0071] In various implementation schemes and further reference Figure 4A DC link capacitor 34 is used to convert inductor L cable The effects of the DC voltage source (i.e., battery 14) are decoupled from inverters 30A and 30B. See also... Figure 4B and Figure 4CThe DC link capacitor 34 provides a low-impedance path for the ripple current 50, which is generated by inverters 30A and 30B and may otherwise flow back to the DC high-voltage bus. The ripple current 50 is a factor in determining the size of the DC link capacitor 34, and therefore, reducing the ripple current 50 can help reduce the size of the DC link capacitor 34 (and the stress on it). The ripple current 50 is caused by the AC load current flowing into motors 24A and 24B and the pulse width modulation (PWM) of inverters 30A and 30B. Figure 4B and Figure 4C As shown and given for illustration only and not as a limitation, the motor current is 550 Arms, the modulation index is 0.48, the power factor is 1, the switching frequency is 10 kHz, and the fundamental frequency is 250 Hz. Without elimination, the ripple current 50 can have an amplitude of approximately 712 Arms.

[0072] For further reference Figure 4D In various embodiments, a method 52 for synchronizing pulse width modulation (PWM) clocks is provided. It should be understood that, in various embodiments, synchronizing PWM clocks can help eliminate ripple current 50. Method 52 begins at block 53. At block 54, the PWM method of the first power inverter and the PWM method of the second power inverter are identified. At block 56, the switching frequency of the first power inverter and the switching frequency of the second power inverter are identified and compared. At block 58, an optimized phase shift between the first and second power inverters is determined in response to the PWM methods of the first and second power inverters and the switching frequencies of the first and second power inverters. At block 60, the optimized phase shift is synchronized between the first and second power inverters.

[0073] Method 52 ends at box 61.

[0074] like Figure 4E and Figure 4F As shown and given for illustration only and not as a limitation, the motor current is 550 Arms, the modulation index is 0.48, the power factor is 1, the switching frequency is 10 kHz, and the fundamental frequency is 250 Hz. With the elimination described herein, the ripple current 50 can be reduced to an amplitude of approximately 147 Arms.

[0075] In view of the above overview, in various implementation schemes, and as Figure 3AAs shown, the common controller 32 includes processor 64A and processor 64B. In some embodiments, processors 64A and 64B may be separate processors. However, it should be understood that in some other embodiments (using two PWM generators), the functions of processors 64A and 64B can be combined into a single processor, depending on the needs of a specific application. Regardless of whether processors 64A and 64B are separate or combined into a single processor, it should be understood that processor 64A acts as the master processor and processor 64B acts as the slave processor.

[0076] Processor 64A is operatively coupled to computer-readable medium 65A, such as any suitable computer memory configured to store computer-executable instructions configured to cause processor 64A to perform the functions described below. Processor 64B is operatively coupled to computer-readable medium 65B, such as any suitable computer memory configured to store computer-executable instructions configured to cause processor 64B to perform the functions described below. Processor 64A is configured to generate a first clock signal (e.g., using a crystal) and a second clock signal for controlling the generation of on / off signals 66A for driving power inverter 30A. The second clock signal is provided to processor 64B to control the generation of on / off signals 66B for driving power inverter 30B.

[0077] Processor 64A selects the PWM method for power inverter 30A, and processor 64B selects the PWM method for power inverter 30B. Processor 64B (i.e., the slave processor) informs processor 64A (i.e., the master processor) of its PWM method (except in the case where PWM method switching is not used). The factors for selecting continuous PWM and discontinuous PWM have been discussed above.

[0078] Processor 64A selects the switching frequency for power inverter 30A, and processor 64B selects the switching frequency for power inverter 30B. The frequencies are even multiples of each other and are selected from predetermined values. As illustrated and not limited by example, in various embodiments, the switching frequencies can be 2.5 kHz and 10 kHz, resulting in even multiples of four. However, it should be understood that other frequencies (resulting in even multiples) can be selected as needed. In various embodiments, the processor 64A (i.e., the main processor) outputs a reference at the lowest selectable frequency, where the desired phase shift is a function of the PWM mode.

[0079] Processor 64A is configured to determine an optimized phase shift between power inverters 30A and 30B in response to the PWM methods of power inverter 30A and 30B, as well as the switching frequencies of power inverter 30A and 30B. For example, in some such embodiments and further reference... Figure 4G The processor 64A can access a lookup table 68, which is filled with cells containing optimized phase shift values ​​arranged according to rows 70 and columns 72 of the PWM method. It should be understood that in some embodiments, the PWM method of power inverter 30A and the PWM method of power inverter 30B can be the same pulse width modulation method. It should also be understood that in some other embodiments, the PWM method of power inverter 30A and the PWM method of power inverter 30B can be different PWM methods.

[0080] like Figure 4G As shown, when both power inverters 30A and 30B use continuous PWM, the phase shift is set to 90 degrees. When both power inverters 30A and 30B use discontinuous PWM, the phase shift is set to 180 degrees. The phase shift is set to 90 degrees for different PWM methods.

[0081] In some other such embodiments, processor 64A may execute an algorithm for determining an optimized phase shift between power inverters 30A and 30B in response to PWM methods for power inverters 30A and 30B. For example, the algorithm may include if-then statements, such as:

[0082] If both PWM methods are continuous PWM, then the optimized phase shift is 90 degrees;

[0083] If both PWM methods are discontinuous PWM, then the optimized phase shift is 180 degrees; and

[0084] If one PWM method is continuous PWM and the other is discontinuous PWM, then the optimized phase shift is 90 degrees.

[0085] Processor 64A is also configured to achieve optimized phase shift synchronization between power inverter 30A and power inverter 30B. As described above, processor 64B is configured to receive a second clock signal and drive power inverter 30B.

[0086] In various implementations, the processor 64A is further configured to shift the second clock signal from the first clock signal by a determined optimized phase shift.

[0087] In various embodiments, processor 64A is further configured to identify the dominant harmonic frequency between the harmonic frequencies of the PWM methods of power inverter 30A and power inverter 30B, and to determine an optimized phase shift between power inverter 30A and power inverter 30B in response to the dominant harmonic frequency between the harmonic frequencies of the PWM methods of power inverter 30A and power inverter 30B. It should be understood that determining the optimized phase shift between power inverter 30A and power inverter 30B in response to the dominant harmonic frequency between the harmonic frequencies of the PWM methods of power inverter 30A and power inverter 30B can help eliminate the dominant high-frequency components of the ripple current 50.

[0088] In some such implementations, the primary harmonic frequency may include a second harmonic frequency (a harmonic of the switching frequency). For example, in such implementations, the PWM method may include continuous PWM. In such implementations, the optimized phase shift is 90 degrees. It should be understood that a 90-degree phase shift will offset the primary harmonic (second harmonic frequency) by 180 degrees, thereby resulting in the elimination of the primary harmonic component of the ripple current 50.

[0089] In some other such embodiments, the primary harmonic frequency may include the first harmonic frequency. For example, in such embodiments, the PWM method may include discontinuous PWM. In such embodiments, the optimized phase shift is 180 degrees. It should be understood that a 180-degree phase shift will shift the primary harmonic (first harmonic frequency) by 180 degrees, thereby resulting in the elimination of the primary harmonic component of the ripple current 50.

[0090] It should be understood that actual DC bus harmonics can reside in the sideband group surrounding the switching frequency. The separation of these harmonics from the switching frequency harmonics is a function of the motor fundamental frequency.

[0091] In various implementations, processor 64A is configured to identify and compare the switching frequency of power inverter 30A and the switching frequency of power inverter 30B. As described above, only two frequencies that are even multiples of each other are used.

[0092] For example, in some embodiments, it may be desirable to change the switching frequency. For example, in some embodiments, the switching frequency may be 10 kHz. In such embodiments, at low motor speeds (e.g., below 500 RPM), it may be desirable to reduce the switching frequency to 2.5 kHz to protect the switches 42 in inverters 30A and 30B, thereby helping to reduce stress in inverters 30A and 30B. Maintaining an even relationship between switching frequencies allows for harmonic alignment and increases the chance of eliminating major harmonics.

[0093] In electric vehicles where each wheel is independently driven by its own associated electric motor via its own axle, there is no mechanical coupling between the wheels. In such vehicles, if one inverter shuts down due to a fault and the other inverter does not respond properly, a torque difference may exist between the two wheels. Such a torque difference can negatively impact the vehicle's controllability.

[0094] To help avoid such torque differences and to refer to other sources Figures 5A to 5G In various embodiments, a fault associated with power inverter 30A or power inverter 30B (or the circuitry associated with both inverters 30A and 30B as described below) results in the application of the same fault action (as described below) to both inverters 30A and 30B. In such embodiments, applying the same fault action to both inverters 30A and 30B places inverters 30A and 30B in a “safe state” and helps to apply balanced torque to both wheels associated with drive unit 20, which includes inverters 30A and 30B. By applying the same fault action to both inverters 30A and 30B and equalizing torque to both wheels associated with drive unit 20, which includes inverters 30A and 30B, various embodiments can help reduce the likelihood of torque differentials that could negatively impact vehicle controllability.

[0095] As described above, processor 64A is operatively coupled to computer-readable medium 65A, such as any suitable computer memory configured to store computer-executable instructions configured to cause processor 64A to perform the functions described below. Also as described above, processor 64B is operatively coupled to computer-readable medium 65B, such as any suitable computer memory configured to store computer-executable instructions configured to cause processor 64B to perform the functions described below. In various embodiments and as will be described below, the computer-executable instructions are configured to cause their associated processors 64A and 64B to apply the same fault action to power inverters 30A and 30B, respectively, to apply equalized torque to each wheel 16 or 18 operatively coupled to drive unit 20 in response to a fault associated with power inverter 30A or power inverter 30B.

[0096] In various implementation schemes and such Figure 5A As shown, various faults associated with inverters 30A and 30B are monitored by processors 64A and 64B for inverters 30A and 30B, respectively. For such faults, in various embodiments, processors 64A and 64B monitor the three-terminal power semiconductor devices 42 ( Figure 3AThe same fault response is applied. In various embodiments, such faults associated with inverters 30A and 30B and monitored by processors 64A and 64B respectively may include, but are not limited to, overcurrent, overvoltage, undervoltage, overtemperature, overspeed, etc. In various embodiments, signals indicating such faults may be provided to controller 32 via data link 74, which may include any suitable data communication connection or network as needed, such as, but not limited to, wide area network (WAN), local area network (LAN), controller area network (CAN), peer-to-peer network, data bus, etc., and provided to processors 64A and 64B. In various embodiments, signals indicating vehicle status (such as motor speed and battery 14 voltage) are also provided to controller 32 via data link 74.

[0097] In various implementation schemes and also as Figure 5A As shown, controller 32 includes a communication link 82 between processors 64A and 64B. It should be understood that communication link 82 enables processor 64A or processor 64B to communicate to the other processor 64B or 64A, respectively, that a fault detected by processor 64A or processor 64B has been identified, that a fault action will be taken, and what fault action will be taken. Communication link 82 may include any suitable data link or data bus as needed.

[0098] In various embodiments, fault actions taken by processors 64A and 64B for faults monitored by inverters 30A and 30B, respectively, may include, for example, opening all three-terminal semiconductor devices 42 of inverters 30A and 30B and / or short-circuiting the three-terminal semiconductor devices 42 of row 40 or row 44 of inverters 30A and 30B. As will be explained below, in various embodiments, the fault actions applied to both inverters 30A and 30B for faults monitored by processors 64A and 64B depend on the motor speed. As will also be explained below, the fault actions applied to both inverters 30A and 30B for faults not monitored by processors 64A and 64B do not depend on the motor speed.

[0099] In various embodiments, and as described above, fault actions by processors 64A and 64B for faults monitored by inverters 30A and 30B, respectively, may include, for example, opening all three-terminal semiconductor devices 42 of inverters 30A and 30B and / or short-circuiting three-terminal semiconductor devices 42 of rows 40 or 44 of inverters 30A and 30B, and may be speed-dependent. For such faults monitored by processors 64A and 64B, it should be understood that applying fault actions simultaneously to both inverters 30A and 30B can help reduce braking torque and reduce regenerative current to battery 14. Because processors 64A and 64B are operatively coupled to various data communication connections or networks to receive data regarding motor speed, processors 64A and 64B are suitably configured to determine the same fault action to be applied based on motor speed. In various embodiments, processor 64A selects an appropriate speed-dependent fault action for its associated electric motor 24A, and processor 64B selects an appropriate speed-dependent fault action for its associated electric motor 24B. Other faults not monitored by processors 64A and 64B have fault actions that do not depend on the motor speed and will be discussed further below.

[0100] like Figure 5B As shown, in various implementations, the same fault action applied to inverters 30A and 30B can be based on motor speed. In such implementations, the same fault action may include applying a threshold speed v to the motor. th The following opens all three-terminal semiconductor devices 42 in inverters 30A and 30B, and at the threshold speed v th The above causes the three-terminal semiconductor device 42 of group 40 or group 44 of inverters 30A and 30B to be short-circuited.

[0101] like Figure 5B As shown, graph 76 plots the motor speed versus torque under various conditions for the three-terminal semiconductor devices 42 of inverters 30A and 30B. Curve 78 shows the torque generated by opening all three-terminal semiconductor devices 42 of inverters 30A and 30B. At the threshold speed v... th Below this, the torque is essentially insignificant, and at the threshold speed v th As the motor speed increases, the braking torque becomes increasingly significant. It should also be understood that in such cases, the back electromotive force (back EMF) increases with the motor speed, and in some situations, this back EMF can cause the electric motors 24A and 24B to operate as uncontrolled generators capable of producing back EMF and applying unwanted regenerative current to the DC link capacitor 34 and battery 14.

[0102] Also Figure 5BAs shown, curve 80 illustrates the torque caused by a three-phase short circuit in the three-terminal semiconductor devices 42 of group 40 or group 44. As the motor speed increases from zero, the braking torque increases rapidly and reaches its maximum value. As the motor speed continues to increase, the braking torque decreases and approaches the threshold speed v at which the motor speed reaches its maximum value. th The previous asymptotic minimization value.

[0103] Therefore, in various embodiments where processors 64A and 64B monitor for faults in inverters 30A and 30B, fault actions suitably include speed-dependent fault actions that help minimize both the braking torque to the DC link capacitor 34 and the unwanted regenerative current to the battery 14. In such embodiments, fault actions suitably include actions where the motor speed is less than a threshold speed v. th This causes all three-terminal power semiconductor devices 42 in both inverters 30A and 30B to be open-circuited, and occurs when the motor speed is greater than the threshold speed v. th This causes a short circuit in one group of three-terminal power semiconductor devices 42 (i.e., group 40 or group 44) of inverters 30A and 30B.

[0104] In various implementations, fault actions based on curves 78 and 80 can be implemented using the reverse EMF and voltage of battery 14 (as opposed to directly taking fault actions in response to reported motor speed). For example, in various implementations, the motor reverse EMF is calculated and compared to the battery voltage. In such implementations, when the reverse EMF is less than the battery voltage (by means of a design safety margin selected as needed), the speed-dependent fault action involves turning on all three-terminal power semiconductor devices 42 of both inverters 30A and 30B. When the reverse EMF exceeds a predetermined percentage of the battery voltage, the speed-dependent fault action involves short-circuiting the three-terminal power semiconductor devices 42 of a group of three-terminal power semiconductor devices 42 (i.e., group 40 or group 44) of inverters 30A and 30B. If necessary, a certain amount of hysteresis can be used to prevent “jittering” between different fault actions.

[0105] like Figure 5AAs shown, processor 64A is associated with power inverter 30A, and processor 64B is associated with power inverter 30B. Memory 65A (i.e., a computer-readable medium) and memory 65B (again, a computer-readable medium) are each configured to store computer-executable instructions that cause their associated processors 64A and 64B to apply the same fault action to power inverters 30A and 30B, respectively, in response to a fault associated with either power inverter 30A or power inverter 30B, to apply equalized torque to each wheel 16 or 18 operatively coupled to drive unit 20.

[0106] For example Figure 5A As shown, in various embodiments, signals indicating parameters such as vehicle speed, faults such as those mentioned above, are supplied to controller 32 via data link 74 and provided to processors 64A and 64B. In such embodiments, computer-executable instructions are further configured to cause their associated processor 64A or 64B to monitor for faults.

[0107] Low-voltage DC power (such as 12V) is supplied to controller 32 to power components as needed. Controller 32 then supplies 12V DC power to gate drive circuits 46A and 46B.

[0108] like Figure 5A As shown, processor 64A is operatively coupled to provide control signal 86 to driver 46A1 of gate 48 of group 40 (sometimes referred to as the "upper group") and control signal 88 to driver 46A2 of gate 48 of group 44 (sometimes referred to as the "lower group"). Similarly, processor 64B is operatively coupled to provide control signal 90 to driver 46B1 of gate 48 of group 40 (sometimes referred to as the "upper group") and control signal 92 to driver 46B2 of gate 48 of group 44 (sometimes referred to as the "lower group"). In various embodiments, drivers 46A1, 46A2, 46B1, and 46B2 are suitable power amplifiers that amplify low-power control signals 86, 88, 90, and 92 and generate high-power fault-action signals 86', 88', 90', and 92', which are then provided to their associated gate terminals 48.

[0109] like Figure 5CAs shown, in various embodiments, additional circuitry is required to provide control signals 86, 88, 90, and 92 to their respective drivers 46A1, 46A2, 46B1, and 46B2. Each processor 64A and 64B is operatively coupled to receive the fault indication signal as described above, and processors 64A and 64B are operatively coupled to each other via communication link 82. Processor 64A is operatively coupled to provide control signals 86 and 88 to buffers 94 and 96, respectively, and processor 64B is operatively coupled to provide control signals 90 and 92 to buffers 98 and 100, respectively. Buffers 94, 96, 98, and 100 are any suitable buffers, such as, but not limited to, octal buffers.

[0110] Buffer 94 is operatively coupled to driver 46A1, buffer 96 is operatively coupled to driver 46A2, buffer 98 is operatively coupled to driver 46B1, and buffer 100 is operatively coupled to driver 46B2. When processor 64A or processor 64B receives a fault indication signal for monitoring associated inverters 30A or 30B, the processor receiving the monitored fault indication signal communicates the presence of the monitored fault via communication link 82. The fault action is as follows.

[0111] When processor 64A receives a fault indication signal, it communicates via communication link 82 to processor 64B that a fault detected by processor 64A has been identified, and that processor 64B will take the appropriate fault action, as described below. Conversely, when processor 64B receives a fault indication signal, it communicates via communication link 82 to processor 64A that a fault detected by processor 64B has been identified, and that processor 64A will take the appropriate fault action, as described below. It should also be understood that in various embodiments, the processor receiving the fault indication signal also performs the fault action (which requires other processors to do the same).

[0112] When the motor speed is less than the threshold speed v th(Or, if the reverse EMF is lower than the voltage of battery 14 by at least the design safety margin) and a fault has been detected, processors 64A and 64B generate control signals 86, 88, 90, and 92, which are configured to disconnect all gate terminals 48 of inverters 30A and 30B, and thus cause all three-terminal power semiconductor devices 42 of inverters 30A and 30B to open. Control signals 86, 88, 90, and 92 are provided to buffers 94, 96, 98, and 100, respectively, and subsequently to drivers 46A1, 46A2, 46B1, and 46B2, which provide fault action signals 86', 88', 90', and 92' to all gate terminals 48 of inverters 30A and 30B. Figure 5D As shown, all three-terminal power semiconductor devices in groups 40 and 44 of inverters 30A and 30B are opened.

[0113] When the motor speed is greater than the threshold speed v th When a fault is detected (or the reverse EMF exceeds a predetermined percentage of the battery voltage), processors 64A and 64B generate control signals 86, 88, 90, and 92. These control signals are configured to disconnect the gate terminal 48 of the three-terminal power semiconductor device 42 in one of groups 40 or 44 of inverters 30A and 30B, and to connect the gate terminal 48 of the three-terminal power semiconductor device 42 in the other of groups 44 or 40 of inverters 30A and 30B. Therefore, the three-terminal power semiconductor device 42 in one of groups 40 or 44 of inverters 30A and 30B is open-circuited, and the three-terminal power semiconductor device 42 in the other of groups 44 or 40 of inverters 30A and 30B is short-circuited.

[0114] It should be understood that the three-terminal power semiconductor device 42 of either group 40 or 44 of inverters 30A and 30B can be open-circuited or short-circuited as needed. It should also be understood that a three-terminal power semiconductor device 42 that has already failed will not be open-circuited or short-circuited (because it has already failed). In some embodiments and as in... Figure 5EAs shown, the three-terminal power semiconductor devices 42 of group 40 of both inverters 30A and 30B are open-circuited, and the three-terminal power semiconductor devices 42 of group 44 of both inverters 30A and 30B are short-circuited. In this embodiment, processors 64A and 64B generate control signals 86 and 90, which are configured to disconnect all gate terminals 48 of group 40 of inverters 30A and 30B, and thus open-circuit all three-terminal power semiconductor devices 42 in group 40 of inverters 30A and 30B. Processors 64A and 64B also generate control signals 88 and 92, which are configured to turn on all gate terminals 48 of group 44 of inverters 30A and 30B, and thus short-circuit all three-terminal power semiconductor devices 42 in group 44 of inverters 30A and 30B. Control signals 86, 88, 90 and 92 are provided to buffers 94, 96, 98 and 100 respectively, and then to drivers 46A1, 46A2, 46B1 and 46B2, which provide fault operation signals 86', 88', 90' and 92' to all gate terminals 48 of inverters 30A and 30B.

[0115] In some other implementations and such Figure 5F As shown, the three-terminal power semiconductor devices 42 of group 44 of both inverters 30A and 30B are open-circuited, and the three-terminal power semiconductor devices 42 of group 40 of both inverters 30A and 30B are short-circuited. In this embodiment, processors 64A and 64B generate control signals 86 and 90, which are configured to disconnect all gate terminals 48 of group 44 of inverters 30A and 30B, and thus open-circuit all three-terminal power semiconductor devices 42 of group 44 of inverters 30A and 30B. Processors 64A and 64B also generate control signals 88 and 92, which are configured to turn on all gate terminals 48 of group 40 of inverters 30A and 30B, and thus short-circuit all three-terminal power semiconductor devices 42 of group 40 of group 40 of inverters 30A and 30B. Control signals 86, 88, 90 and 92 are provided to buffers 94, 96, 98 and 100 respectively, and then to drivers 46A1, 46A2, 46B1 and 46B2, which provide fault operation signals 86', 88', 90' and 92' to all gate terminals 48 of inverters 30A and 30B.

[0116] In various implementation schemes, and also as Figure 5A and Figure 5CAs shown, various faults associated with inverters 30A and 30B are not monitored by processors 64A and 64B of inverters 30A and 30B respectively, because such faults are faults in one or both of processors 64A and / or 64B or in the circuitry associated with processors 64A and 64B (described below). For such faults, in various embodiments, by enabling the three-terminal power semiconductor device 42 of one of groups 40 or 44 of inverters 30A and 30B ( Figure 3A A short circuit affects the three-terminal power semiconductor devices 42 of both inverters 30A and 30B. Figure 3A The same fault response is applied. Because the functionality of processors 64A and 64B is unverifiable under such fault conditions, it is unverifiable that processors 64A and 64B can receive and process information about the motor speed (or the reverse EMF or voltage of battery 14). Therefore, a default fault action is required in such cases. In various embodiments, the default action is a three-phase short circuit of the three-terminal power semiconductor device 42 in one of groups 44 or 40 of inverters 30A and 30B.

[0117] In various implementation schemes and such Figure 5A and Figure 5C As shown, controller 32 includes health monitoring circuitry 102 configured to monitor the health of processors 64A and 64B via data links 104 and 106, respectively. In some such embodiments, health monitoring circuitry 102 includes a field-programmable gate array (“FPGA”). In such embodiments, health monitoring circuitry 102 may be programmed to perform safety checks, such as manual safety checks, and to monitor whether processors 64A and / or 64B are operating normally (or fully operating normally). In some such embodiments, health monitoring circuitry 102 may be programmed to implement a rolling counter to perform such monitoring of processors 64A and 64B. In some such embodiments, processors 64A and 64B also monitor whether health monitoring circuitry 102 is operational. Therefore, a fault in health monitoring circuitry 102 is considered a fault in the circuitry associated with processors 64A and 64B.

[0118] In various implementation schemes and also as Figure 5A and Figure 5C As shown, controller 32 includes a three-phase short-circuit circuit 108. In such embodiments, the three-phase short-circuit circuit 108 is configured to generate a fault action signal (described below) for faults not monitored by processors 64A and 64B, since faults may include faults in processors 64A and / or 64B and / or health monitoring circuits 102. The fault action signal generated by the three-phase short-circuit circuit 108 passes through a three-terminal power semiconductor device 42 of one of groups 40 or 44 of inverters 30A and 30B ( Figure 3A A short circuit affects the three-terminal power semiconductor devices 42 of both inverters 30A and 30B. Figure 3A Apply the same fault response.

[0119] In various implementations, the three-phase short-circuit circuit 108 is located external to processors 64A and 64B and is configured to apply the same fault action to power inverters 30A and 30B to apply equal torque to each wheel 16 or 18 operatively coupled to drive unit 20 in response to a fault not detected by processor 64A or processor 64B. Figure 5A and Figure 5C As shown, a three-phase short-circuit circuit 108 is coupled to receive a control signal 110 from a health monitoring circuit 102, a control signal 112 from a processor 64A, and a control signal 114 from a processor 64B. The health monitoring circuit 102 is configured to generate the control signal 110 in response to receiving a processor fault indication signal from the processor 64A via data link 104 indicating a fault within the processor 64A, or from the processor 64B via data link 106 indicating a fault within the processor 64B. Processors 64A and 64B are configured to generate control signals 112 and 114, respectively, in response to detecting a fault in the health monitoring circuit 102 (such as, but not limited to, a fault in a rolling counter) via data links 104 and 106.

[0120] In various implementation schemes and such Figure 5C As shown, the three-phase short-circuit circuit 108 includes a voltage regulator 116, a buffer 118, and a buffer 120. In some such embodiments, the voltage regulator 116 includes a voltage regulator configured to convert 12VDC to 5VDC. In such embodiments, control signals 110, 112, and 114 are suitably 12VDC signals. In response to the application of any of the 12VDC control signals 110, 112, or 114, the voltage regulator 116 outputs a 5VDC control signal 122. The control signal 122 is input to buffers 118 and 120. Buffer 118 is coupled to provide the control signal 122 to a driver 46A2 of group 44 of power inverter 30A. Driver 46A2 generates and provides a fault action signal 88' to the gate terminal 48 of group 44 of power inverter 30A, thereby short-circuiting the three-terminal power semiconductor devices 42 of group 44 of power inverter 30A. Buffer 120 is coupled to provide control signal 122 to driver 46B2 of group 44 of power inverter 30B. Driver 46B2 generates and provides fault action signal 92' to gate terminal 48 of group 44 of power inverter 30B, thereby short-circuiting three-terminal power semiconductor device 42 of group 44 of power inverter 30B.

[0121] It should be understood that short-circuiting the three-terminal power semiconductor devices 42 of group 44 of inverters 30A and 30B is given for illustration only and not as a limitation. In some embodiments, the three-terminal power semiconductor devices 42 of group 40 of inverters 30A and 30B are short-circuited (and the three-terminal power semiconductor devices 42 of group 44 of inverters 30A and 30B are kept open).

[0122] For further reference Figure 5G In various embodiments, an exemplary method 124 is provided for applying the same fault action to a first power inverter and a second power inverter to apply balanced torque to each wheel operatively coupled to the drive unit in response to a fault associated with either the first or second power inverter.

[0123] Method 124 begins at box 126. At box 128, a fault associated with either the first or second power inverter of the drive unit of the electric vehicle is detected. At box 130, in response to the detected fault, the same fault action is applied to both the first and second power inverters to apply balanced torque to each wheel operatively coupled to the drive unit. Method 124 ends at box 130.

[0124] In various implementation schemes, a first processor for a first power inverter and a second processor for a second power inverter can monitor for faults.

[0125] In various implementations, a processor for an inverter with an associated fault can transmit fault actions to a processor for an inverter without an associated fault.

[0126] In various implementations, the fault action may include opening all groups of three-terminal power semiconductor devices in the first power inverter and the second power inverter when the motor speed is less than a threshold speed, or short-circuiting one group of three-terminal power semiconductor devices in the first power inverter and the second power inverter when the motor speed is greater than a threshold speed.

[0127] In various implementations, a fault associated with the first or second power inverter of the drive unit of the electric vehicle may include a fault in the first processor of the first power inverter, or a fault in the second processor of the second power inverter, or a fault in the health monitoring circuitry of the first and second processors.

[0128] In various implementations, applying the same fault action to the first power inverter and the second power inverter to apply balanced torque to each wheel operatively coupled to the drive unit may include applying the same fault action to the first power inverter and the second power inverter by circuitry located outside the first processor and the second processor to apply balanced torque to each wheel operatively coupled to the drive unit.

[0129] In various implementations, a fault action may include short-circuiting a set of three-terminal power semiconductor devices in the first power inverter and the second power inverter.

[0130] Nevertheless, it should be understood that in some cases, the speed of one motor may differ from the speed of another motor. For example, during cornering, the outer wheel may rotate faster than the inner wheel. Similarly, wheels may rotate at different speeds under various wheel slip conditions. In some such cases, because processor 64A selects an appropriate speed-dependent fault action for its associated electric motor 24A, and processor 64B selects an appropriate speed-dependent fault action for its associated electric motor 24B, the speed-dependent fault action of one motor of drive unit 20 (e.g., based on the reverse EMF and voltage of battery 14) may differ from the speed-dependent fault actions of the other motors of drive unit 20.

[0131] In addition to the faults associated with inverters 30A and 30B described above, the loss of low-voltage DC power to controller 32 (such as 12VDC and referred to herein as 12V) causes the same fault action to be applied to both inverters 30A and 30B to help avoid torque imbalance between the two wheels 16 or 18 driven by the same drive unit 20.

[0132] It should be understood that, such as Figure 5A and Figure 5C As shown, processors 64A and 64B, drivers 46A1, 46A2, 46B1 and 46B2, health monitoring circuit 102, and three-phase short-circuit circuit 108 all include components powered by low-voltage DC power (12V) supplied to controller 32. It should be understood that the loss of the 12V supplied to controller 32 means that processors 64A and 64B, drivers 46A1, 46A2, 46B1 and 46B2, health monitoring circuit 102, and three-phase short-circuit circuit 108 cannot be used to apply the same fault operation to both inverters 30A and 30B, as described above.

[0133] Therefore, in various implementations and as described below, the capability is provided to apply the same fault action to both inverters 30A and 30B in the event of a 12V loss in the supply to controller 32.

[0134] like Figure 5A and Figure 5C As shown and further reference Figures 6A to 6B In various embodiments and by way of the outline, detection circuit 140 is configured to detect a loss of low-voltage DC power (12V) supplied to controller 32. Backup power circuit 84A is associated with power inverter 30A, and backup power circuit 84B is associated with power inverter 30B. Each backup power circuit 84A and 84B is configured to convert high-voltage DC power (such as 450VDC) to low-voltage DC power (such as, for example, a buck DC-DC converter) in response to the detection of a loss of low-voltage DC power supplied to controller 32. Three-phase short-circuit circuit 108 is configured to apply the same fault action to power inverters 30A and 30B to apply equalized torque to each wheel 16 or 18 operatively coupled to drive unit 20 in response to the detection of a loss of low-voltage DC power supplied to controller 32.

[0135] like Figure 5A , Figure 5C and Figure 6A As shown, in various embodiments, detection circuit 140 uses optocoupler 141 to detect the loss of low-voltage DC power (12V) supplied to controller 32. Low-voltage DC power (such as 12V) is supplied to resistor R1, which is connected in series with resistor R2. Resistors R1 and R2 act as a voltage divider. A control signal 143 at a suitable voltage (such as, but not limited to, 5V) is supplied from node 145 between resistors R1 and R2 to a light-emitting diode (LED) 145 of optocoupler 141. When powered, LED 145 converts the electrical input into light and emits light (visible light or infrared (IR) light). Phototransistor 147 detects the light emitted by LED 145 and turns on. In various embodiments, phototransistor 149 is a pull-down transistor. Phototransistor 149 is coupled to provide an enable signal 151 to backup power circuits 84A and 84B.

[0136] During normal operation, control signal 143 is supplied to LED 147, and LED 147 emits light. Phototransistor 149 detects the light and turns on. Because phototransistor 149 is a pull-down transistor, enable signal 151 is low when phototransistor 149 is on. When enable signal 151 is low, enable signal 151 pulls down backup power circuits 84A and 84B (such as buck DC-DC converters), causing backup power circuits 84A and 84B to be disconnected and preventing the application of a three-phase short circuit.

[0137] In the event of a loss of low-voltage DC power (12V), signal 143 disappears and LED 147 stops emitting light. Consequently, phototransistor 149 disconnects and enable signal 151 goes high. When enable signal 151 is high, backup power circuits 84A and 84B are activated and a three-phase short circuit is applied, as described below. For example, enable signal 151 can activate the buck DC-DC converter in each of backup power circuits 84A and 84B to convert high-voltage DC power to low-voltage DC power (12V).

[0138] In various embodiments, gate drive circuits 46A and 46B respectively include backup power supply circuits 84A and 84B. High-voltage DC power (such as 450V) is supplied to each of the backup power supply circuits 84A and 84B. Each backup power supply circuit 84A and 84B is configured to convert the 450VDC power into low-voltage DC power, such as 12VDC power. Therefore, if desired, backup power supply circuits 84A and 84B appropriately include a buck DC-DC converter (as described above), a voltage divider circuit (as described below), etc.

[0139] like Figure 6B As shown, in some embodiments, if desired, each backup power circuit 84A and 84B may optionally include a normally open relay 152 having a relay coil 154 operatively coupled to receive low-voltage DC power (12V) from the controller 32. In such embodiments, the normally open relay 152 also includes a normally open contact 156. As described above, during normal operation, low-voltage DC power 12V is supplied to the relay coil 154, and the relay coil 154 is energized, thereby opening the normally open contact 156. In the event of a loss of low-voltage DC power (12V), the relay coil 154 is de-energized, thereby closing the normally open contact 156. Therefore, in such embodiments, the detection circuit 140 appropriately includes the relay coil 154, and the low-voltage DC power (12V) from the controller 32 can be considered a control signal.

[0140] In such embodiments, each backup power circuit 84A and 84B suitably includes a voltage divider 158 operatively coupled to receive high-voltage DC power. The voltage divider 158 is configured to convert the high-voltage DC power to low-voltage DC power and is further configured to output the low-voltage DC power to a normally open contact 156. In such embodiments, during normal operation (when low-voltage DC power is supplied to the relay coil 154 and the normally open contact 156 is open), backup power circuits 84A and 84B do not provide 12V power. Conversely, in the event of a loss of low-voltage DC power (12V) (when the relay coil 154 is de-energized and the normally open contact 156 is closed), backup power circuits 84A and 84B provide 12V power. Therefore, in such embodiments, each backup power circuit 84A and 84B also suitably includes a normally open contact 156.

[0141] As described above, in various embodiments, power inverters 30A and 30B each include two groups 40 and 44 of three-terminal power semiconductor devices 42. As described below, the three-phase short-circuit circuit 108 is further configured to short-circuit either group 40 or 44 of the three-terminal power semiconductor devices 42 in power inverters 30A and 30B in response to the detection of a loss of low-voltage DC power supplied to controller 32.

[0142] like Figure 5A and Figure 5C As shown, regardless of the detected loss of low-voltage DC power (12V) and how the low-voltage DC power (12V) is generated by backup power circuits 84A and 84B, the low-voltage DC power (12V) is supplied from backup power circuits 84A and 84B to voltage regulator 116. In response to the application of low-voltage DC power (12V), voltage regulator 116 outputs a 5VDC control signal 122. Control signal 122 is input to buffers 118 and 120. Buffer 118 is coupled to provide control signal 122 to driver 46A2 of group 44 of power inverter 30A. Driver 46A2 generates and provides fault action signal 88' to gate terminal 48 of group 44 of power inverter 30A, thereby short-circuiting the three-terminal power semiconductor device 42 of group 44 of power inverter 30A. Buffer 120 is coupled to provide control signal 122 to driver 46B2 of group 44 of power inverter 30B. The driver 46B2 generates and provides a fault action signal 92' to the gate terminal 48 of the group 44 of the power inverter 30B, thereby short-circuiting the three-terminal power semiconductor device 42 of the group 44 of the power inverter 30B.

[0143] It should be understood that short-circuiting the three-terminal power semiconductor devices 42 of group 44 of inverters 30A and 30B is given for illustration only and not as a limitation. In some embodiments, the three-terminal power semiconductor devices 42 of group 40 of inverters 30A and 30B are short-circuited (and the three-terminal power semiconductor devices 42 of group 44 of inverters 30A and 30B are kept open).

[0144] In various implementation schemes and such Figure 6C As shown, a method 160 is provided for applying the same fault action to two inverters of a drive unit of an electric vehicle in the event of a 12V loss in the common controller supplying the two inverters.

[0145] Method 160 begins at block 162. At block 164, a loss of low-voltage direct current (DC) power supplied to the controllers of the first processor of the first power inverter and the second processor of the second power inverter for the drive unit of the electric vehicle is detected. At block 166, in response to the detection of a loss of low-voltage DC power supplied to the controllers, high-voltage DC power is converted to low-voltage DC power. At block 168, the same fault action is applied to the first and second power inverters to apply equalized torque to each wheel operatively coupled to the drive unit in response to the detection of a loss of low-voltage DC power supplied to the controllers. Method 160 terminates at block 170.

[0146] In various implementations, control signals can be provided in response to the presence of low-voltage DC power supplied to the controller.

[0147] In various implementations, applying the same fault action to the first and second power inverters in response to detecting a loss of low-voltage DC power supplied to the controller to apply equal torque to each wheel operatively coupled to the drive unit may include applying the same fault action to the first and second power inverters in response to the absence of a control signal to apply equal torque to each wheel operatively coupled to the drive unit.

[0148] In various implementations, a fault action may include short-circuiting a set of three-terminal power semiconductor devices in the first power inverter and the second power inverter.

[0149] Those skilled in the art will recognize that at least a portion of the devices and / or processes described herein can be integrated into a data processing system. Those skilled in the art will recognize that a data processing system typically includes one or more of the following: a system unit housing, a video display device, memory (such as volatile or non-volatile memory), a processor (such as a microprocessor or digital signal processor), a computing entity (such as an operating system), drivers, a graphical user interface and applications, one or more interactive devices (e.g., a touchpad, a touchscreen, an antenna, etc.), and / or a control system including feedback loops and control motors (e.g., feedback for sensing position and / or speed; control motors for moving and / or adjusting components and / or quantities). The data processing system can be implemented using suitable commercially available components, such as those typically found in data computing / communication and / or network computing / communication systems.

[0150] As used in the preceding / following disclosures, the term "module" can refer to a collection of one or more components arranged in a particular manner, or a collection of one or more general components that can be configured to operate in a particular manner at one or more specific points in time and / or also configured to operate in one or more other manners at one or more additional times. For example, the same hardware or the same part of hardware can be configured / reconfigured sequentially / in parallel at different times as a first type of module (e.g., at a first time), a second type of module (e.g., at a second time, which in some cases may coincide with, overlap with, or follow the first time), and / or a third type of module (e.g., at a third time, which in some cases may coincide with, overlap with, or follow the first and / or second times). Reconfigurable and / or controllable components (e.g., general-purpose processors, digital signal processors, field-programmable gate arrays, etc.) can be configured as a first module with a first purpose, then as a second module with a second purpose, then as a third module with a third purpose, and so on. The transformation of reconfigurable and / or controllable components can occur in as little as a few nanoseconds, or over a period of time, such as minutes, hours, or days.

[0151] In some such examples, when a component is configured to perform a secondary purpose, it may no longer be able to perform that primary purpose until it is reconfigured. Components can switch between configurations as different modules in as few nanoseconds. Components can be reconfigured dynamically; for example, a component reconfiguring from a first module to a second module may occur precisely when the second module is needed. Components can be reconfigured in stages; for example, portions of a first module that are no longer needed may be reconfigured into a second module, even before the first module has completed its operation. Such reconfiguration may occur automatically or through prompting from an external source, whether that source is another component, instruction, signal, condition, external stimulus, or similar.

[0152] For example, the central processing unit of a personal computer can operate at various times as a module for displaying graphics on a screen, for writing data to a storage medium, for receiving user input, and for multiplying by two large prime numbers by configuring its logic gates according to its instructions. Such reconfiguration may be invisible to the naked eye and in some implementations may include activation, deactivation, and / or rerouting of various parts of the components (e.g., switches, logic gates, inputs, and / or outputs). Therefore, in examples present in the preceding / following disclosures, if an example includes or describes multiple modules, that example includes the possibility that the same hardware can implement more than one of the described modules simultaneously or in discrete times or timing sequences. Whether more components, fewer components, or the same number of components as the number of modules are used, the implementation of multiple modules is merely an implementation choice and generally does not affect the operation of the modules themselves. Therefore, it should be understood that any description of multiple discrete modules in this disclosure includes implementing these modules as any number of underlying components, including but not limited to a single component that reconfigures itself over time to perform the functions of multiple modules and / or multiple components that are similarly reconfigured, and / or dedicated reconfigurable components.

[0153] In some cases, one or more components may be referred to herein as “configured to,” “configured by,” “configurable to,” “operable / operating as,” “suitable / adaptable to,” “capable of,” “adaptable to,” etc. Those skilled in the art will recognize that, unless the context otherwise requires, such terms (e.g., “configured to”) generally cover active state components and / or passive state components and / or standby state components.

[0154] While specific aspects of the subject matter described herein have been shown and described, it will be apparent to those skilled in the art that changes and modifications may be made based on the teachings herein without departing from the subject matter and its broader aspects, and therefore the appended claims cover all such changes and modifications within their scope, as is the true spirit and scope of the subject matter described herein. Those skilled in the art will understand that, in general, the terminology used herein, particularly in the appended claims (e.g., the body of the appended claims), is intended to denote “open-ended” terms (e.g., the term “comprising” should be interpreted as “including but not limited to,” the term “having” should be interpreted as “at least having,” the term “including” should be interpreted as “comprising but not limited to,” etc.). Those skilled in the art will further understand that if a class intent is a specific number of introduced claim statements, such intent will be explicitly stated in the claims, and if no such statement is present, such intent does not exist. For example, to aid understanding, the following appended claims may contain the use of the introductory phrases “at least one” and “one or more” to introduce claim statements. However, the use of such phrases should not be construed as implying that introducing a claim statement with the indefinite article "a" or "an" limits any particular claim containing such an introduced claim statement to a claim containing only one such statement, even when the same claim includes the introductory phrase "one or more" or "at least one" and indefinite articles such as "a" or "an" (e.g., "a" and / or "an" should generally be interpreted as meaning "at least one" or "one or more"); the same applies to the use of definite articles used to introduce a claim statement. Furthermore, even when a specific number of introduced claim statements are explicitly stated, those skilled in the art will recognize that such a statement should generally be interpreted as meaning at least the number stated (e.g., simply stating "two statements" without further modification generally means at least two statements, or two or more statements). Furthermore, in cases where conventions such as "at least one of A, B, and C" are used, generally speaking, such a construction is intended to mean that a person skilled in the art will understand that the convention (e.g., "a system having at least one of A, B, and C" will include, but is not limited to, systems having only A, having only B, having only C, having A and B, having A and C, having B and C, and / or A, B, and C, etc.). A person skilled in the art will further understand that, unless the context otherwise requires, extractive terms and / or phrases that typically present two or more alternative terms (whether in the specification, claims, or drawings) should be understood to contemplate the possibility of including one, any, or both of the terms. For example, the phrase "A or B" will generally be understood to include the possibility of "A" or "B" or "A and B".

[0155] The specific embodiments described above have illustrated various implementations of the apparatus and / or process using block diagrams, flowcharts, and / or examples. Where such block diagrams, flowcharts, and / or examples contain one or more functions and / or operations, those skilled in the art will understand that each function and / or operation within such block diagrams, flowcharts, or examples can be implemented individually and / or collectively by a wide range of hardware, software (e.g., high-level computer programs used as hardware specifications), firmware, or virtually any combination thereof, limited to the patentable subject matter under 35 USC101. In embodiments, certain portions of the subject matter described herein may be implemented via application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), or other integration formats. However, those skilled in the art will recognize that some aspects of the embodiments disclosed herein can be implemented, in whole or in part, equivalently in an integrated circuit as one or more computer programs (e.g., one or more programs running on one or more computer systems), one or more programs (e.g., one or more programs running on one or more microprocessors), firmware, or virtually any combination thereof, running on one or more computers, limited to the subject matter patentable under 35 USC101, and that designing circuits and / or writing code for software (e.g., high-level computer programs used as hardware specifications) and / or firmware according to this disclosure will be entirely within the skill of those skilled in the art. Furthermore, those skilled in the art will understand that the mechanisms of the subject matter described herein are capable of being distributed as program products in a variety of forms, and that the exemplary embodiments of the subject matter described herein apply regardless of the specific type of signal-bearing medium used for actual distribution. Examples of signal-carrying media include, but are not limited to, the following: recordable media, such as floppy disks, hard disks, optical discs (CDs), digital video discs (DVDs), digital tapes, computer memory, etc.; and transmission media, such as digital and / or analog communication media (e.g., fiber optic cables, waveguides, wired communication links, wireless communication links (e.g., transmitters, receivers, transmission logic, receiving logic, etc.) etc.).

[0156] With respect to the appended claims, those skilled in the art will understand that the operations enumerated herein can generally be performed in any order. Furthermore, although the various operational flows are presented sequentially, it should be understood that the various operations can be performed in any order other than that shown, or can be performed simultaneously. Unless the context otherwise requires, examples of such alternative orderings may include overlapping, interleaving, interruption, reordering, ascending, preparatory, supplementary, simultaneous, reverse, or other variations of ordering. Moreover, unless the context otherwise requires, terms such as “in response to,” “related to,” or other past tense adjectives are generally not intended to exclude such variations.

[0157] Although the subject matter disclosed herein has been described with reference to exemplary embodiments, those skilled in the art will understand that various modifications may be made to the subject matter without departing from the scope of the claimed subject matter set forth in the claims.

Claims

1. A drive unit for an electric vehicle, the drive unit comprising: First electric motor; The first axle is mechanically coupled to the first electric motor; Second electric motor; The second wheel axle is mechanically coupled to the second electric motor; and A dual-power inverter module, which is electrically coupled to a high-voltage DC power source, includes: A first inverter is configured to convert high-voltage DC power into three-phase high-voltage AC power and is electrically coupled to provide the three-phase high-voltage AC power to the first electric motor. A second inverter, configured to convert the high-voltage DC power into three-phase high-voltage AC power, and electrically coupled to provide the three-phase high-voltage AC power to the second electric motor; and A common controller is configured to control the first inverter and the second inverter, wherein a fault associated with either the first inverter or the second inverter causes the common controller to apply the same fault action to both the first inverter and the second inverter to equalize torque distribution between them. The same fault actions include: (1) when the speed of the first electric motor and / or the second electric motor is less than the threshold speed, opening all three-terminal power semiconductor devices of both the first inverter and the second inverter; and (2) when the speed of the first electric motor and / or the second electric motor is greater than the threshold speed, short-circuiting the three-terminal power semiconductor devices of the upper or lower group of the first inverter and the second inverter.

2. The driving unit according to claim 1, further comprising: A first gear set, which is mechanically coupled between the first electric motor and the first axle; and The second gear set is mechanically coupled between the second electric motor and the second axle.

3. The drive unit according to claim 1, wherein the first axle and the second axle are fixedly coupled to the first wheel and the second wheel.

4. The drive unit of claim 1, wherein the first axle and the second axle are removably coupled to the first wheel and the second wheel.

5. The driving unit according to claim 1, wherein: The first electric motor has a first voltage rating and a first current rating; and The second electric motor has a second voltage rating that is the same as the first voltage rating and a second current rating that is the same as the first current rating.

6. The drive unit according to claim 1, wherein the first electric motor and the second electric motor include synchronous electric motors.

7. The drive unit according to claim 6, wherein the synchronous electric motor comprises a permanent magnet electric motor.

8. The drive unit according to claim 1, wherein the first inverter and the second inverter have the same voltage and current output ratings.

9. A drive unit for an electric vehicle, the drive unit comprising: First synchronous electric motor; The first axle is mechanically coupled to the first synchronous electric motor; Second synchronous electric motor; The second wheel axle is mechanically coupled to the second synchronous electric motor; A first gear set, which is mechanically coupled between the first synchronous electric motor and the first wheel axle; The second gear set is mechanically coupled between the second synchronous electric motor and the second axle; and A dual-power inverter module, which is electrically coupled to a high-voltage DC power source, includes: A first inverter is configured to convert high-voltage DC power into three-phase high-voltage AC power and is electrically coupled to provide the three-phase high-voltage AC power to the first synchronous electric motor. A second inverter, configured to convert the high-voltage DC power into three-phase high-voltage AC power, and electrically coupled to provide the three-phase high-voltage AC power to the second synchronous motor; and A common controller is configured to control the first inverter and the second inverter, wherein a fault associated with either the first inverter or the second inverter causes the common controller to apply the same fault action to both the first inverter and the second inverter to equalize torque distribution between them. The same fault actions include: (1) when the speed of the first synchronous electric motor and / or the second synchronous electric motor is less than the threshold speed, opening all three-terminal power semiconductor devices of both the first inverter and the second inverter; and (2) when the speed of the first synchronous electric motor and / or the second synchronous electric motor is greater than the threshold speed, short-circuiting the three-terminal power semiconductor devices of the upper or lower group of the first inverter and the second inverter.

10. The drive unit of claim 9, wherein the first axle and the second axle are fixedly coupled to the first wheel and the second wheel.

11. The drive unit of claim 9, wherein the first axle and the second axle are removably coupled to the first wheel and the second wheel.

12. The drive unit according to claim 10, wherein the first synchronous electric motor and the second synchronous electric motor have the same voltage and current ratings.

13. The drive unit according to claim 9, wherein the synchronous electric motor comprises a permanent magnet electric motor.

14. The drive unit according to claim 9, wherein the first inverter and the second inverter have the same voltage and current output ratings.

15. An electric vehicle, the electric vehicle comprising: Body; A high-voltage DC battery, wherein the high-voltage DC battery is disposed within the vehicle body; and At least one driving unit, the at least one driving unit comprising: First electric motor; The first axle is mechanically coupled to the first electric motor; Second electric motor; The second axle, which is mechanically coupled to the second electric motor; and A dual-power inverter module, which is electrically coupled to a high-voltage DC power source, includes: A first inverter is configured to convert high-voltage DC power into three-phase high-voltage AC power and is electrically coupled to provide the three-phase high-voltage AC power to the first electric motor. A second inverter, configured to convert the high-voltage DC power into three-phase high-voltage AC power, and electrically coupled to provide the three-phase high-voltage AC power to the second electric motor; and A common controller is configured to control the first inverter and the second inverter, wherein a fault associated with either the first inverter or the second inverter causes the common controller to apply the same fault action to both the first inverter and the second inverter to equalize torque distribution between them. The same fault actions include: (1) when the speed of the first electric motor and / or the second electric motor is less than the threshold speed, opening all three-terminal power semiconductor devices of both the first inverter and the second inverter; and (2) when the speed of the first electric motor and / or the second electric motor is greater than the threshold speed, short-circuiting the three-terminal power semiconductor devices of the upper or lower group of the first inverter and the second inverter.

16. The electric vehicle according to claim 15, further comprising: A first gear set, which is mechanically coupled between the first electric motor and the first axle; and The second gear set is mechanically coupled between the second electric motor and the second axle.

17. The electric vehicle of claim 15, wherein the at least one drive unit comprises a drive unit capable of coupling to a wheel selected from the left front wheel and the right front wheel.

18. The electric vehicle of claim 15, wherein the at least one drive unit comprises: A first drive unit, the first drive unit being capable of being coupled to the left front wheel and the right front wheel; and The second drive unit is capable of being coupled to the left rear wheel and the right rear wheel.

19. The electric vehicle of claim 15, wherein at least one axle selected from the first axle and the second axle is fixedly coupled to an associated wheel.

20. The electric vehicle of claim 15, wherein at least one axle selected from the first axle and the second axle is removably coupled to an associated wheel.

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