Temperature sensing method for eliminating remote parasitic resistance and remote temperature sensing chip

Abstract

The present disclosure provides a temperature sensing method for eliminating remote parasitic resistance and a remote temperature sensing chip. The temperature sensing method comprises: generating a clock signal by using a clock signal generation module; outputting a tth bias current according to a t-1th control signal by using a bias current generation module; generating a tth bias voltage according to the tth bias current by using a parasitic resistance elimination module, so as to obtain a tth bias voltage value set according to the tth bias voltage in response to the clock signal; generating a tth quantization voltage ratio according to the tth bias voltage value set; outputting a tth control signal in response to the clock signal by using a bias current control module, the tth control signal being a signal generated according to the tth bias voltage; and generating a tth temperature value and outputting the tth temperature value according to the tth quantization voltage ratio by using a digital processing module.

Description

Technical Field

[0001] This disclosure relates to the field of analog circuit technology, and in particular to a temperature sensing method and a remote temperature sensing chip for eliminating remote parasitic resistance. Background Technology

[0002] As integrated circuits enter the deep submicron era, the monitoring of temperatures in precision systems within integrated circuits has become an increasingly important concern. Precision systems such as telecommunications equipment, servers and personal computers, highly integrated medical devices, precision instruments, and testing equipment require individual temperature monitoring of key components, such as microcontrollers (MCUs), graphics processing units (GPUs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), and central processing units (CPUs). Monitoring of the ambient temperature and package temperature of these key components is also crucial to ensure that the precision system operates stably within the expected temperature range.

[0003] Currently, a common solution is to use remote temperature sensing chips for thermal management of precision systems. In related technologies, the remote temperature sensing chip structure can sample the Vt of a remote transistor under different bias currents. BE Subtracting these values ​​yields a voltage ΔV that is positively correlated with temperature. BE Then, the analog-to-digital converter (ADC) module within the remote temperature sensing chip uses the on-chip reference voltage V to... REF For reference, regarding voltage ΔV BE The reference voltage is digitized and processed by a digital back-end to generate a temperature reading. When the temperature of the remote temperature sensor chip changes, its on-chip reference voltage V... REF This will also change, potentially leading to inaccuracies in on-chip digitization and affecting the accuracy of remote temperature measurement. Summary of the Invention

[0004] In view of this, the present disclosure provides a temperature sensing method and a remote temperature sensing chip for eliminating remote parasitic resistance, in order to at least partially solve at least one of the aforementioned technical problems.

[0005] One aspect of this disclosure provides a temperature sensing method for eliminating remote parasitic resistance. This method is applied to a remote temperature sensing chip.

[0006] The aforementioned remote temperature sensing chip includes: a clock signal generation module, a bias current generation module, a parasitic resistance elimination module, a bias current control module, and a digital processing module.

[0007] The above-mentioned temperature sensing methods include:

[0008] The above-mentioned clock signal generation module generates a clock signal; the above-mentioned bias current generation module outputs the bias current of the tth time according to the control signal of the (t-1)th time; the above-mentioned parasitic resistance elimination module generates the bias voltage of the tth time according to the bias current of the tth time, so as to obtain the bias voltage value set of the tth time according to the bias voltage of the tth time in response to the clock signal; the above-mentioned quantization voltage ratio of the tth time is generated according to the bias voltage value set of the tth time, so as to eliminate the influence of parasitic resistance included in the preset remote device connected to the parasitic resistance elimination module; the above-mentioned bias current control module outputs the control signal of the tth time in response to the clock signal, the control signal of the tth time being a signal generated according to the bias voltage of the tth time; the above-mentioned digital processing module generates and outputs the temperature value of the tth time according to the quantization voltage ratio of the tth time, where t is an integer greater than 1.

[0009] According to embodiments of this disclosure, the bias current generating module includes: a bias current source, a first switch, a second switch, and a third switch.

[0010] The aforementioned bias current includes: a first bias current, a second bias current, and a third bias current.

[0011] One end of the first switch, the second switch, and the third switch is connected to the bias current source, and the other end of the first switch, the second switch, and the third switch is connected to the parasitic resistance elimination module.

[0012] The above-mentioned bias current generation module, which outputs the bias current for the tth time based on the control signal for the (t-1)th time, includes:

[0013] By controlling the states of the first switch, the second switch, and the third switch using the control signal at the (t-1)th time, the following can be achieved: when the first switch is in the on state, the first bias current is transmitted to the parasitic resistance elimination module; when the second switch is in the on state, the second bias current is transmitted to the parasitic resistance elimination module; and when the third switch is in the on state, the third bias current is transmitted to the parasitic resistance elimination module.

[0014] According to an embodiment of this disclosure, the parasitic resistance elimination module is connected to a remote transistor, which includes parasitic resistance.

[0015] The parasitic resistance elimination module described above generates a bias voltage based on the bias current at the t-th time, so that in response to a clock signal, a set of bias voltage values ​​at the t-th time can be obtained based on the bias voltage at the t-th time. This includes:

[0016] The aforementioned bias current for the tth time is applied to the aforementioned distal transistor to obtain the aforementioned bias voltage for the tth time; using the aforementioned parasitic resistance elimination module, the aforementioned bias voltage for the tth time is obtained at the sampling frequency corresponding to the aforementioned clock signal to obtain the aforementioned bias voltage value set for the tth time.

[0017] According to embodiments of this disclosure, the bias current at the t-th time includes the first bias current and the second bias current.

[0018] The above-mentioned parasitic resistance elimination module, using the sampling frequency corresponding to the clock signal to obtain the bias voltage at the t-th time, yields the following set of bias voltage values ​​at the t-th time:

[0019] When transmitting the first bias current to the parasitic resistance elimination module, N samples are taken to obtain N first bias voltages for the tth time; when transmitting the second bias current to the parasitic resistance elimination module, N-1 samples are taken to obtain N-1 second bias voltages for the tth time; based on the N first bias voltages for the tth time and the N-1 second bias voltages for the tth time, a first preset bias voltage value set is obtained, where N is an integer greater than 3.

[0020] According to embodiments of this disclosure, the temperature sensing method further includes:

[0021] The bias current for the tth time mentioned above includes: the first bias current, the second bias current, and the third bias current.

[0022] The above-mentioned method of using the parasitic resistance elimination module to obtain the bias voltage at the sampling frequency corresponding to the clock signal, and obtaining the set of bias voltage values ​​at the t-th time, further includes:

[0023] When transmitting the first bias current to the parasitic resistance elimination module, N-1 samples are performed to obtain N-1 first bias voltages at the t-th time. When transmitting the second bias current to the parasitic resistance elimination module, N-2 samples are performed to obtain N-2 second bias voltages at the t-th time. When transmitting the third bias current to the parasitic resistance elimination module, one sample is performed to obtain one third bias voltage at the t-th time. Based on the N-1 first bias voltages at the t-th time, the N-2 second bias voltages at the t-th time, and the one third bias voltage at the t-th time, a second preset bias voltage value set is obtained, where N is an integer greater than 3.

[0024] According to embodiments of this disclosure, generating the quantization voltage ratio for the t-th time based on the aforementioned set of bias voltage values ​​further includes:

[0025] Based on the first preset bias voltage value set, the target bias voltage for the tth time is obtained; based on the second preset bias voltage value set, the target bias voltage difference for the tth time is obtained; based on the target bias voltage for the tth time and the target bias voltage difference for the tth time, the quantization voltage ratio for the tth time is obtained.

[0026] According to an embodiment of this disclosure, the temperature sensing method further includes: after obtaining the target bias voltage difference at the tth time, amplifying the target bias voltage difference at the tth time by a factor of k and then obtaining the quantized voltage ratio at the tth time, where k is a positive integer.

[0027] According to embodiments of this disclosure, the process of generating and outputting the temperature value at time t based on the quantized voltage ratio at time t using the digital processing module includes:

[0028] Based on the quantized voltage ratio of the tth iteration, the linearization result of the tth iteration is obtained; according to the preset slope value, preset offset value, and the linearization result of the tth iteration, the temperature value of the tth iteration is obtained and output.

[0029] Based on the preset slope value, preset offset value, and the quantization voltage ratio of the above-mentioned t-th time, the temperature value of the above-mentioned t-th time is obtained and output.

[0030] According to an embodiment of this disclosure, the bias current control module described above outputs the control signal for the tth time in response to the clock signal. The control signal for the tth time is a signal generated based on the bias voltage for the tth time, including:

[0031] Under the condition of satisfying the preset bias voltage, the control signal for the tth time controls the output of the bias current for the tth time; wherein, the preset bias voltage condition is as follows: when the first preset bias voltage value set is obtained, before the Nth first bias voltage of the tth time is sampled, the control signal for the tth time controls the output of the first bias current; before the (N-1)th first bias voltage of the tth time is sampled, the control signal for the tth time controls the output of the second bias current; when the second preset bias voltage value set is obtained, before the (N-1)th first bias voltage of the tth time is sampled, the control signal for the tth time controls the output of the first bias current; before the (N-2)th second bias voltage of the tth time is sampled, the control signal for the tth time controls the output of the second bias current; before the first third bias voltage of the tth time is sampled, the control signal for the tth time controls the output of the third bias current.

[0032] Another aspect of this disclosure provides a remote temperature sensing chip.

[0033] The aforementioned remote temperature sensing chip includes:

[0034] A clock signal generation module is used to generate a clock signal; a bias current generation module is used to output a bias current of the tth time according to the control signal of the (t-1)th time; a parasitic resistance elimination module is used to generate a bias voltage of the tth time according to the bias current of the tth time, so as to obtain a set of bias voltage values ​​of the tth time according to the bias voltage of the tth time in response to the clock signal; and is also used to generate a quantization voltage ratio of the tth time according to the set of bias voltage values ​​of the tth time, so as to eliminate the influence of parasitic resistance included in the preset remote device connected to the parasitic resistance elimination module; a bias current control module is used to output a control signal of the tth time in response to the clock signal, the control signal of the tth time being a signal generated according to the bias voltage of the tth time; and a digital processing module is used to generate and output a temperature value according to the quantization voltage ratio, wherein t is an integer greater than 1.

[0035] Based on the above technical solutions, it can be seen that the embodiments of this disclosure have the following beneficial effects compared with the prior art:

[0036] According to the temperature sensing method of this disclosure, a bias current is obtained through a remote temperature sensing chip structure, a set of bias voltage values ​​is obtained based on the bias current, a quantized voltage ratio is generated, and the temperature value is obtained by processing the quantized voltage ratio. In this process, it is not necessary to refer to an external reference voltage, thus eliminating the influence of changes in the external reference voltage with temperature transmission on the temperature measurement and improving the temperature measurement accuracy.

[0037] According to the temperature sensing method of this disclosure, in the process of obtaining a set of bias voltage values ​​based on the bias current and then generating a quantized voltage ratio, the influence of parasitic resistance can be offset by numerical calculation, thereby improving the temperature measurement accuracy. Attached Figure Description

[0038] Figure 1 A flowchart illustrating a temperature sensing method according to an embodiment of the present disclosure is shown schematically.

[0039] Figure 2 A schematic diagram of a remote temperature sensing chip structure according to an embodiment of the present disclosure is shown.

[0040] Figure 3 A schematic diagram of a bias current generating module according to an embodiment of the present disclosure is shown.

[0041] Figure 4a A schematic diagram illustrating the quantization voltage ratio and target quantization voltage ratio according to an embodiment of the present disclosure is shown.

[0042] Figure 4b A schematic diagram illustrating the target linearization result according to an embodiment of the present disclosure is shown.

[0043] Figure 5 A schematic diagram of a remote temperature sensing chip module according to an embodiment of the present disclosure is shown. Detailed Implementation

[0044] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0045] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0046] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0047] When using expressions such as "at least one of A, B, and C", they should generally be interpreted in accordance with the meaning that is commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B, and C, etc.).

[0048] In the process of realizing the concept of this disclosure, it was discovered that at least the following problems exist in the related art:

[0049] In related technologies, the remote temperature sensing chip structure can sample the Vo of the remote transistor under different bias currents. BE Subtracting these values ​​yields a voltage ΔV that is positively correlated with temperature. BE Then, the ADC module within the remote temperature sensing chip uses the on-chip reference voltage V... REF For reference, regarding ΔV BE The temperature is digitized and processed by a digital backend to generate a temperature reading. However, V REF It is easily affected by temperature changes in the remote temperature sensing chip, leading to V REF The temperature changes with the remote temperature sensor chip, which may lead to inaccuracies in the on-chip digitization, affecting the accuracy of remote temperature measurement. This also affects the acquisition of ΔV via the remote transistor. BE During the process, the parasitic resistance of the remote transistor affects ΔV. BE The accuracy of this affects the precision of remote temperature measurement.

[0050] A sensing method is needed that minimizes the influence of temperature on the reference voltage and eliminates the effects of parasitic resistance.

[0051] In order to at least partially solve the technical problems existing in the related art, this disclosure provides a temperature sensing method and a remote temperature sensing chip for eliminating remote parasitic resistance.

[0052] According to embodiments of this disclosure, a temperature sensing method for eliminating remote parasitic resistance is provided. This temperature sensing method for eliminating remote parasitic resistance can be applied to remote temperature sensing chips.

[0053] The remote temperature sensing chip may include: a clock signal generation module, a bias current generation module, a parasitic resistance elimination module, a bias current control module, and a digital processing module.

[0054] Figure 1 A flowchart illustrating a temperature sensing method according to an embodiment of the present disclosure is shown schematically.

[0055] like Figure 1 As shown, the temperature sensing method includes operations S110 to S160.

[0056] When operating S110, a clock signal is generated using the clock signal generation module.

[0057] When operating S120, the bias current generation module is used to output the bias current for the tth time according to the control signal of the (t-1)th time.

[0058] In operation S130, the parasitic resistance elimination module is used to generate the bias voltage of the tth time based on the bias current of the tth time, so as to obtain the bias voltage value set of the tth time based on the bias voltage of the tth time in response to the clock signal.

[0059] In operation S140, based on the set of bias voltage values ​​for the tth time, a quantized voltage ratio for the tth time is generated in order to eliminate the influence of parasitic resistance included in the preset remote device connected to the parasitic resistance elimination module.

[0060] According to embodiments of this disclosure, the preset remote device may be configured to include a remote transistor.

[0061] When operating S150, the bias current control module is used to output the t-th control signal in response to the clock signal.

[0062] According to an embodiment of this disclosure, the control signal for the tth time is a signal generated based on the bias voltage for the tth time.

[0063] In operation S160, the digital processing module generates and outputs the temperature value at time t based on the quantized voltage ratio at time t. Here, t is an integer greater than 1.

[0064] According to embodiments of this disclosure, the sampling frequency of the parasitic resistance elimination module and the output frequency of the bias current control module can be controlled by the clock signal generated by the clock signal generation module, thereby indirectly controlling the overall temperature measurement frequency of the remote temperature sensing chip.

[0065] According to embodiments of this disclosure, the temperature sensing method obtains a bias current through a remote temperature sensing chip structure, obtains a set of bias voltage values ​​based on the bias current, generates a quantized voltage ratio, and obtains the temperature value based on the quantized voltage ratio. In this process, there is no need to refer to an external reference voltage, eliminating the influence of changes in the external reference voltage with temperature transmission on the temperature measurement and improving the temperature measurement accuracy.

[0066] According to embodiments of this disclosure, in the process of obtaining a set of bias voltage values ​​based on the bias current and then generating a quantized voltage ratio, the temperature sensing method can compensate for the influence of parasitic resistance through numerical calculation, thereby improving the temperature measurement accuracy.

[0067] Figure 2 A schematic diagram of a remote temperature sensing chip structure according to an embodiment of the present disclosure is shown.

[0068] like Figure 2 As shown, the remote temperature sensing chip involved in this method may include: a clock signal generation module, a bias current generation module, a parasitic resistance elimination module, a bias current control module, and a digital processing module.

[0069] According to embodiments of this disclosure, the bias voltage can be generated by the bias current generation module based on the bias current of the bias current generation module, taking advantage of the exponential relationship between the base-emitter voltage and the collector current of the transistor.

[0070] According to embodiments of this disclosure, the parasitic resistance elimination module can acquire a bias voltage and generate a quantized voltage ratio based on the bias voltage. The sampling frequency of the parasitic resistance elimination module can be controlled by a clock signal generated by a clock signal generation module. The parasitic resistance elimination module may include an analog-to-digital converter (ADC) to perform the operation of generating the quantized voltage ratio. The clock signal generation module may include an oscillation circuit composed of a resistor-capacitor (RC) frequency-selective network, i.e., an RC oscillation circuit, to generate the clock signal.

[0071] According to embodiments of this disclosure, the parasitic resistance elimination module transmits the obtained bias voltage to the bias current control module so that the bias current control module generates a control signal to control the bias current generation module to generate a bias current.

[0072] Figure 3 A schematic diagram of a bias current generating module according to an embodiment of the present disclosure is shown.

[0073] like Figure 3 As shown, the bias current generation module includes: a bias current source, a first switch, a second switch, and a third switch.

[0074] One end of the first switch S1, the second switch S2, and the third switch S3 is connected to a bias current source, and the other end of the first switch, the second switch, and the third switch is connected to a parasitic resistance elimination module.

[0075] The bias current includes: a first bias current, a second bias current, and a third bias current.

[0076] According to embodiments of this disclosure, a first switch can be connected to the output terminal of the bias current source that generates the first bias current, a second switch can be connected to the output terminal of the bias current source that generates the second bias current, and a third switch can be connected to the output terminal of the bias current source that generates the third bias current. Furthermore, the ratio of the current values ​​of the first bias current, the second bias current, and the third bias current can be set to (N-1):N:1, where N is an integer greater than 3.

[0077] A bias current generation module can be used to output the bias current for the tth time based on the control signal for the (t-1)th time.

[0078] The states of the first, second, and third switches can be controlled by the control signal at the (t-1)th time, so that when the bias current at the tth time is transmitted to the parasitic resistance elimination module: when the first switch is in the on state, the first bias current is transmitted to the parasitic resistance elimination module; when the second switch is in the on state, the second bias current is transmitted to the parasitic resistance elimination module; and when the third switch is in the on state, the third bias current is transmitted to the parasitic resistance elimination module.

[0079] According to embodiments of this disclosure, during a single transmission of bias current to the parasitic resistance elimination module, the durations of outputting the first bias current, the second bias current, and the third bias current can be set to be different, and the number of outputs can also be different.

[0080] According to embodiments of this disclosure, a parasitic resistance elimination module is connected to a remote transistor, which includes parasitic resistance.

[0081] like Figure 3 As shown, after the emitter and base of the remote transistor are connected, they are connected to the parasitic resistance elimination module. In the actual connection line of this temperature sensing method, a parasitic resistance R2 may exist between the emitter and base of the remote transistor and the parasitic resistance elimination module. It can be understood that a parasitic resistance R1 may exist between the collector of the remote transistor and the parasitic resistance elimination module. Since the current flowing through R1 and R2 is the same when the bias current generation module transmits bias current to the parasitic resistance elimination module, the current values ​​can be equivalent to one parasitic resistance R in the R1 and R2 circuit. S .

[0082] Using a parasitic resistance elimination module, a bias voltage of the tth time is generated based on the bias current of the tth time, so that the set of bias voltage values ​​of the tth time can be obtained in response to the clock signal, including:

[0083] Applying the bias current t to the distal transistor for the tth time yields the bias voltage t for the tth time; and

[0084] The bias voltage at the sampling frequency corresponding to the clock signal is obtained at the t-th sampling time, thus obtaining the set of bias voltage values ​​at the t-th sampling time.

[0085] According to embodiments of this disclosure, the bias current at time t may include: a first bias current and a second bias current.

[0086] Using a parasitic resistance elimination module, the bias voltage at the sampling frequency corresponding to the clock signal is obtained at the t-th sampling time. The set of bias voltage values ​​at the t-th sampling time includes:

[0087] When transmitting the first bias current to the parasitic resistance elimination module, N samples are taken to obtain N first bias voltages for the tth time.

[0088] When transmitting a second bias current to the parasitic resistance elimination module, N-1 samples are taken to obtain N first bias voltages at the t-th time.

[0089] Based on N first bias voltages at time t and N-1 second bias voltages at time t, a set of first preset bias voltage values ​​is obtained, where N is an integer greater than 3.

[0090] According to embodiments of this disclosure, during the N sampling process, it can be configured such that while the parasitic resistance elimination module stores each sampled data, it transmits the sampled data to the bias current control module in real time. This allows the bias current control module to obtain the real-time sampling status of the parasitic resistance elimination module based on the sampled data, and to generate a control signal to control the bias current transmitted from the bias current generation module to the parasitic resistance elimination module in real time. This enables rapid information feedback between the parasitic resistance elimination module, the bias current control module, and the current control module.

[0091] According to embodiments of this disclosure, in the case where the first preset bias voltage value set has been obtained as described above, the following operations may also be included.

[0092] The bias current transmitted to the parasitic resistance elimination module for the tth time may also include: a first bias current, a second bias current, and a third bias current;

[0093] Using a parasitic resistance elimination module, the bias voltage at the sampling frequency corresponding to the clock signal is obtained at the t-th sampling time. The set of bias voltage values ​​at the t-th sampling time also includes:

[0094] When transmitting the first bias current to the parasitic resistance elimination module, N-1 samples are taken to obtain N-1 first bias voltages of the tth time.

[0095] When transmitting a second bias current to the parasitic resistance elimination module, N-2 samples are taken to obtain N-2 second bias voltages of the tth time.

[0096] When transmitting the third bias current to the parasitic resistance elimination module, one sampling is performed to obtain a third bias voltage of the tth time.

[0097] The second preset bias voltage value set is obtained based on N-1 first bias voltages at the t-th time, N-2 second bias voltages at the t-th time, and 1 third bias voltage at the t-th time, where N is an integer greater than 3.

[0098] According to embodiments of this disclosure, in the actual process of obtaining the first preset bias voltage value set and the second preset bias voltage value set through the temperature sensing method, the order of acquisition is not limited. Furthermore, in the process of obtaining the first preset bias voltage value set, the order in which the first bias current and the second bias current are transmitted in real time from the bias current generation module to the parasitic resistance elimination module is not limited. The order of bias currents in the process of obtaining the first preset bias voltage value set is similar.

[0099] According to embodiments of this disclosure, a bias current control module is used to output a control signal t-th time in response to a clock signal. The control signal t-th time is a signal generated based on the bias voltage t-th time, including:

[0100] Under the condition that the preset bias voltage is met, the control signal for the tth time controls the output of the bias current for the tth time.

[0101] The preset bias voltage conditions are as follows: when the first preset bias voltage value set is obtained, before the first bias voltage of the Nth time t is sampled, the control signal of the tth time controls the output of the first bias current; before the first bias voltage of the N-1th time t is sampled, the control signal of the tth time controls the output of the second bias current.

[0102] Furthermore, given the second preset bias voltage value set, before sampling the (N-1)th first bias voltage at time t, the control signal at time t controls the output of the first bias current; before sampling the (N-2)th second bias voltage at time t, the control signal at time t controls the output of the second bias current; before sampling the first third bias voltage at time t, the control signal at time t controls the output of the third bias current.

[0103] According to embodiments of this disclosure, during the process of obtaining the t-th temperature value, the clock signal generated by the clock signal generation module controls the time interval at which the bias current control module outputs a control signal to the bias current generation module. This controls the current generation module to generate different bias currents and the time interval at which the different bias currents are transmitted to the parasitic resistance elimination module. The clock signal generated by the clock signal generation module can also control the sampling frequency of the different bias voltages generated by the parasitic resistance elimination module based on the different bias currents. The parasitic resistance elimination module then transmits the sampled different bias voltages to the bias current control module, allowing the bias current control module to obtain the sampling state of the parasitic resistance elimination module, thereby updating the control signal and controlling the current generation module to generate different bias currents.

[0104] According to embodiments of this disclosure, the quantization voltage ratio for the tth time can also be generated based on the set of bias voltage values ​​for the tth time.

[0105] The process of generating the quantization voltage ratio at time t includes: obtaining the target bias voltage at time t based on a first preset bias voltage value set; obtaining the target bias voltage difference at time t based on a second preset bias voltage value set; and obtaining the quantization voltage ratio at time t based on the target bias voltage at time t and the target bias voltage difference at time t.

[0106] According to embodiments of this disclosure, since there is a difference of "1" between the number of samples of the first bias voltage at time t and the second bias voltage at time t in the obtained first preset bias voltage value set, the target bias voltage at time t can be obtained based on N first bias voltages at time t and N first bias voltages at time t. Similarly, based on the number of samples of the first bias voltage, second bias voltage, and third bias voltage in the second preset bias voltage value set, if the number of samples of the first bias voltage is equal to the sum of the number of samples of the second bias voltage and the third bias voltage, the target bias voltage difference at time t can be obtained.

[0107] According to embodiments of this disclosure, the target bias voltage difference obtained at the tth time can be quantized using the target bias voltage obtained at the tth time as a reference voltage to obtain the quantized voltage ratio at the tth time.

[0108] According to embodiments of this disclosure, in obtaining the t-th quantized voltage ratio, the t-th target bias voltage obtained from the remote temperature sensing chip structure is used as the reference voltage. This allows for the acquisition of a reference voltage without introducing an external reference voltage, enabling the quantization of the t-th target bias voltage difference to obtain the t-th quantized voltage ratio. This eliminates measurement errors caused by the external reference voltage changing with temperature.

[0109] According to an embodiment of this disclosure, the temperature sensing method further includes: after obtaining the target bias voltage difference for the tth time, amplifying the target bias voltage difference for the tth time by a factor of k and then obtaining the quantized voltage ratio for the tth time, where k is a positive integer.

[0110] According to embodiments of this disclosure, in the parasitic resistance elimination module, the rate of change between multiple quantized voltage ratios obtained directly from the target bias voltage and the target bias voltage difference may be small. When the rate of change is small, it may occur within the preset dynamic range of the parasitic resistance elimination module, resulting in low resolution accuracy of the multiple quantized voltage ratios. Therefore, the calculated target bias voltage can be amplified by the parasitic resistance elimination module to fully utilize its preset dynamic range and improve the resolution accuracy of the quantized voltage ratios.

[0111] According to embodiments of this disclosure, a digital processing module can be used to generate and output the temperature value at time t based on the quantized voltage ratio at time t.

[0112] Generating the temperature value at time t includes: obtaining the linearization result at time t based on the quantization voltage ratio at time t; and obtaining and outputting the temperature value at time t based on the preset slope value, preset offset value, and the linearization result at time t.

[0113] According to embodiments of this disclosure, a matching preset slope value and a preset offset value can be determined based on the structure and parameter configuration of the overall circuit of the remote temperature sensing chip. The preset slope value can be set to a positive number, and the preset offset value can be set to a negative number. Furthermore, the temperature value can be a decimal value.

[0114] According to embodiments of this disclosure, temperature sensing is performed without considering the effects of parasitic resistance. The bias voltage obtained based on the third bias current can be expressed by the following formula (1):

[0115]

[0116] Among them, V BE I is the bias voltage; S q is the collector current of the transistor; k is the Boltzmann constant, with a value of 1.38 × 10⁻²³; q is the elementary charge, with a value of 1.6 × 10⁻¹⁹; T is the Kelvin temperature; I bias This is the third bias current.

[0117] According to the embodiments of this disclosure, without considering the influence of parasitic resistance, a second bias current and a third bias current are applied to the transistor to generate a bias voltage corresponding to the second bias current and a bias voltage corresponding to the third bias current. The bias voltage difference is obtained by subtracting the bias voltage corresponding to the third bias current from the bias voltage corresponding to the second bias current and subtracting the two bias voltages generated.

[0118] According to embodiments of this disclosure, the bias voltage difference obtained based on the second bias current and the third bias current can be expressed by the following formula (2):

[0119]

[0120] Where, ΔV BE The bias voltage difference is obtained based on the second bias current and the third bias current; N is the ratio of the current value of the second bias current to the current value of the third bias current.

[0121] According to embodiments of this disclosure, the quantization voltage ratio can be expressed by the following formula (3):

[0122] X = ΔV BE / V BE (3)

[0123] Where X is the quantization voltage ratio.

[0124] According to embodiments of this disclosure, the linearization result can be represented by the following formula (4):

[0125]

[0126] Where μ is the quantization voltage ratio and α is the gain factor.

[0127] According to embodiments of this disclosure, the gain factor can be obtained using the following formula (5):

[0128]

[0129] Wherein, the value of α is chosen such that V BE With αΔV BE The temperature coefficients have equal magnitudes but opposite signs.

[0130] According to embodiments of this disclosure, the temperature value can be obtained using the following formula (6):

[0131] D temp =Aμ+B (6)

[0132] Among them, D temp A represents the temperature value, B represents the preset slope value, and C represents the preset misalignment value.

[0133] According to embodiments of this disclosure, a temperature detection is performed while eliminating the influence of parasitic resistance by setting a first preset bias voltage value set and a second preset bias voltage value set, taking into account the influence of parasitic resistance.

[0134] According to embodiments of this disclosure, a first bias current and a second bias current are applied to the transistor. During the application of the first bias current, the bias voltage generated by the first bias current is sampled N times, and the bias voltage generated by the second bias current is sampled N-1 times. The sampled bias voltages are then set as a first preset bias voltage value set. The target bias voltage obtained based on the first preset bias voltage value set can be expressed by the following formula (7):

[0135]

[0136] Among them, V BE ((N-1)I bias V represents the bias voltage generated corresponding to the first bias current. BE (NI bias R is the bias voltage generated corresponding to the second bias current; S Parasitic resistance; The target bias voltage.

[0137] According to embodiments of this disclosure, the numerical term including parasitic resistance in the resulting bias voltage is canceled out, resulting in a bias voltage that eliminates the influence of parasitic resistance.

[0138] According to embodiments of this disclosure, a first bias current, a second bias current, and a third bias current are applied to the transistor. During the application of the first bias current, the bias voltage generated by the first bias current is sampled N-1 times, the bias voltage generated by the second bias current is sampled N-2 times, and the bias voltage generated by the third bias current is sampled once. The sampled bias voltages are then combined into a second preset bias voltage value set. The target bias voltage difference obtained based on the first preset bias voltage value set can be expressed by the following formula (8):

[0139]

[0140] Among them, V BE (I bias ) represents the bias voltage generated corresponding to the third bias current; The target bias voltage difference.

[0141] According to embodiments of this disclosure, the target bias voltage difference is used as ΔV BE The target bias voltage is used as V BESubstituting the values ​​into formulas (3) to (6) yields the temperature value, which allows for temperature detection while eliminating the influence of parasitic resistance.

[0142] According to embodiments of this disclosure, in order to fully utilize the dynamic range of the ADC, the ADC first prescales the sampled target bias voltage value by a factor of n, and then uses the n-fold target bias voltage as a reference voltage to obtain the target quantization voltage ratio. Then, the temperature value is obtained by calculating using formulas (4) to (6), which can improve the utilization rate of the ADC dynamic range, where n is a positive integer. According to embodiments of this disclosure, the target linearization result can be represented by the following formula (9):

[0143]

[0144] Where Y is the target quantization voltage ratio, Y = nΔV BE / V BE .

[0145] Figure 4a A schematic diagram illustrating the quantization voltage ratio and target quantization voltage ratio according to an embodiment of the present disclosure is shown.

[0146] like Figure 4a As shown, n=4 can be set. The quantization voltage ratio curve changes slowly and the value is small in the temperature range of (-55, 145)℃, which wastes the dynamic range of the ADC in measuring ratios greater than 0.3. When switching to the target quantization voltage ratio output, the rate of change of the target quantization voltage ratio curve increases in the temperature range of (-55, 145)℃, and the value is in the range of (0.2, 0.9). This can make full use of the more sensitive dynamic range of the ADC, thereby improving the accuracy of remote temperature measurement.

[0147] Figure 4b A schematic diagram illustrating the target linearization result according to an embodiment of the present disclosure is shown.

[0148] like Figure 4b As shown, when the target quantized voltage ratio is converted into the target linearization result output, the target linearization linearity is good in the temperature range of (-55, 145)℃, which makes it convenient to obtain the decimal temperature value from subsequent readings.

[0149] According to an embodiment of this disclosure, another aspect provides a remote temperature sensing chip.

[0150] Figure 5 A schematic diagram of a remote temperature sensing chip module according to an embodiment of the present disclosure is shown.

[0151] like Figure 5As shown, the remote temperature sensing chip 500 may include: a clock signal generation module 510, a bias current generation module 520, a parasitic resistance elimination module 530, a bias current control module 540, and a digital processing module 550.

[0152] The clock signal generation module 510 is used to generate clock signals.

[0153] The bias current generation module 520 is used to output the bias current for the tth time according to the control signal for the (t-1)th time.

[0154] The parasitic resistance elimination module 530 is used to generate a bias voltage based on the bias current of the tth time, so as to obtain a set of bias voltage values ​​of the tth time based on the bias voltage of the tth time in response to a clock signal; it is also used to generate a quantization voltage ratio of the tth time based on the set of bias voltage values ​​of the tth time, so as to eliminate the influence of parasitic resistance included in the preset remote device connected to the parasitic resistance elimination module.

[0155] The bias current control module 540 is used to output a control signal for the tth time in response to a clock signal. The control signal for the tth time is a signal generated based on the bias voltage for the tth time.

[0156] The digital processing module 550 is used to generate and output a temperature value based on the quantized voltage ratio, where t is an integer greater than 1.

[0157] According to embodiments of this disclosure, based on a remote temperature sensing chip structure, the V of a remote transistor is sampled. BE and ΔV BE The ADC inside the remote temperature sensing chip uses V BE ΔV is directly quantized to the reference voltage. BE With V BE The ratio X (X=ΔV) BE / V BE The temperature information is then processed by the digital processing module 550. This structure eliminates the need for an external reference voltage, thus eliminating the influence of external reference voltage changes caused by temperature variations in the remote temperature sensing chip, and consequently eliminating the impact of external reference voltage changes on the accuracy of remote temperature measurement.

[0158] According to embodiments of this disclosure, by employing parasitic resistance elimination technology, the parasitic resistance present in the leads can be eliminated during the acquisition of the target bias voltage and the target bias voltage difference, thus mitigating the impact on the sampled value ΔV. BE With V BE This reduces the impact of temperature measurement on remote devices, thereby improving the accuracy of remote temperature measurement.

[0159] According to embodiments of this disclosure, when sampling via a parasitic resistance elimination module, the ADC used can first sample the ΔV. BEPre-processing the values ​​can improve the utilization of the ADC's dynamic range.

[0160] According to embodiments of this disclosure, the sampling structure of the remote temperature sensing chip can adopt a single-transistor differential input structure, that is, the V generated at the remote end... BE Connecting the sampling circuit via differential input can reduce the impact of coupling noise on the circuit board on temperature measurement accuracy.

[0161] The flowcharts and block diagrams in the accompanying drawings schematically illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0162] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0163] The embodiments of this disclosure have been described above. However, these embodiments are merely for illustrating the purpose, technical solutions, and beneficial effects of this disclosure, and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Without departing from the scope of this disclosure, various substitutions and modifications can be made by those skilled in the art within the spirit and principles of this disclosure, and all such substitutions and modifications should fall within the protection scope of this disclosure.

Claims

1. A temperature sensing method for eliminating remote parasitic resistance, applied to a remote temperature sensing chip, comprising: a clock signal generation module, a bias current generation module, a parasitic resistance elimination module, a bias current control module and a digital processing module; the method comprising: generating a clock signal by using the clock signal generation module; outputting a tth bias current according to a (t-1) th control signal by using the bias current generation module; generating a tth bias voltage according to the tth bias current by using the parasitic resistance elimination module, so that a tth bias voltage value set is obtained according to the tth bias voltage in response to the clock signal; generating a tth quantized voltage ratio according to the tth bias voltage value set, so as to eliminate the influence of parasitic resistance included in a preset remote device connected to the parasitic resistance elimination module; outputting the tth control signal in response to the clock signal by using the bias current control module, the tth control signal being a signal generated according to the tth bias voltage; and generating a tth temperature value according to the tth quantized voltage ratio and outputting by using the digital processing module, wherein t is an integer greater than 1. The distal temperature sensing chip comprises: The bias current generation module comprises a bias current source, a first switch, a second switch and a third switch. The bias current comprises a first bias current, a second bias current and a third bias current. One end of the first switch, the second switch and the third switch is connected to the bias current source, and the other end of the first switch, the second switch and the third switch is connected to the parasitic resistance elimination module. The bias current generation module outputs a tth bias current according to a (t-1) th control signal, which comprises: controlling the states of the first switch, the second switch and the third switch by the (t-1) th control signal, so that the tth bias current is transmitted to the parasitic resistance elimination module, in the case that the first switch is in a conductive state, the first bias current is transmitted to the parasitic resistance elimination module; in the case that the second switch is in a conductive state, the second bias current is transmitted to the parasitic resistance elimination module; and in the case that the third switch is in a conductive state, the third bias current is transmitted to the parasitic resistance elimination module.

2. The method of claim 1, wherein, The parasitic resistance elimination module is connected to a remote triode, and the remote triode comprises a parasitic resistance. The parasitic resistance elimination module generates a tth bias voltage according to a tth bias current, so that a tth bias voltage value set is obtained according to the tth bias voltage in response to the clock signal, which comprises: applying the tth bias current to the remote triode to obtain the tth bias voltage; and using the parasitic resistance elimination module to obtain the tth bias voltage value set at a sampling frequency corresponding to the clock signal. The tth bias current comprises the first bias current and the second bias current. ​ ​ ​ 3. The method of claim 2, wherein, ​ ​ ​ ​ 4. The method of claim 3, wherein, ​ The utilizing the parasitic resistance elimination module to obtain the tth bias voltage at a sampling frequency corresponding to the clock signal includes: In the case of transmitting the first bias current to the parasitic resistance elimination module, N times of sampling are performed to obtain N first tth bias voltages; In the case of transmitting the second bias current to the parasitic resistance elimination module, N-1 times of sampling are performed to obtain N-1 second tth bias voltages; and According to the N first tth bias voltages and the N-1 second tth bias voltages, a first preset bias voltage value set is obtained, wherein N is an integer greater than 3.

5. The method of claim 4, further comprising: The tth bias current includes the first bias current, the second bias current and the third bias current; The utilizing the parasitic resistance elimination module to obtain the tth bias voltage at a sampling frequency corresponding to the clock signal includes: In the case of transmitting the first bias current to the parasitic resistance elimination module, N-1 times of sampling are performed to obtain N-1 first tth bias voltages; In the case of transmitting the second bias current to the parasitic resistance elimination module, N-2 times of sampling are performed to obtain N-2 second tth bias voltages; In the case of transmitting the third bias current to the parasitic resistance elimination module, 1 time of sampling is performed to obtain 1 third tth bias voltage; and According to the N-1 first tth bias voltages, the N-2 second tth bias voltages and the 1 third tth bias voltage, a second preset bias voltage value set is obtained, wherein N is an integer greater than 3.

6. The method of claim 5, wherein, The generating the tth quantization voltage ratio according to the tth bias voltage value set includes: According to the first preset bias voltage value set, a tth target bias voltage is obtained; According to the second preset bias voltage value set, a tth target bias voltage difference is obtained; and According to the tth target bias voltage and the tth target bias voltage difference, the tth quantization voltage ratio is obtained.

7. The method of claim 6, further comprising: After obtaining the tth target bias voltage difference, the tth target bias voltage difference is amplified by k times before obtaining the tth quantization voltage ratio, wherein k is a positive integer.

8. The method of claim 6 or 7, wherein, The utilizing the digital processing module to generate a tth temperature value and output according to the tth quantization voltage ratio includes: Based on the tth quantization voltage ratio, a tth linearization result is obtained; and According to a preset slope value, a preset offset value and the tth linearization result, the tth temperature value is obtained and output.

9. The method of claim 8, wherein, The utilizing the bias current control module to output a tth control signal in response to the clock signal, the tth control signal being a signal generated according to the tth bias voltage includes: The tth control signal controls output of the tth bias current under the condition of meeting a preset bias voltage condition; The preset bias voltage condition is that, under the condition of obtaining a first preset bias voltage value set, the tth control signal controls output of a first bias current before sampling of the Nth tth first bias voltage, the tth control signal controls output of a second bias current before sampling of the N-1th tth first bias voltage, and Under the condition of obtaining a second preset bias voltage value set, the tth control signal controls output of the first bias current before sampling of the N-1th tth first bias voltage, the tth control signal controls output of the second bias current before sampling of the N-2th tth second bias voltage, and the tth control signal controls output of a third bias current before sampling of the 1th tth third bias voltage.

10. A remote temperature sensing chip, comprising: a clock signal generation module for generating a clock signal; a bias current generation module for outputting a tth bias current according to a t-1th control signal; a parasitic resistance elimination module for generating the tth bias voltage according to the tth bias current, so as to obtain a tth bias voltage value set according to the tth bias voltage in response to the clock signal; and for generating a tth quantized voltage ratio according to the tth bias voltage value set, so as to eliminate the influence of a parasitic resistance included in a preset remote device connected to the parasitic resistance elimination module; a bias current control module for outputting the tth control signal in response to the clock signal, the tth control signal being a signal generated according to the tth bias voltage; and a digital processing module for generating and outputting a temperature value according to the quantized voltage ratio, wherein t is an integer greater than 1.

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