Integrated circuit back-end design optimization method and system
By directly modifying relevant files during the back-end design stage of the integrated circuit, the self-cycle iteration of the back-end design is achieved, which solves the problem that the back-end design solution cannot be passed, significantly speeds up the design process and reduces quality risks.
Patent Information
- Application Number
- CN202110827623.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-07-21
- Publication Date
- 2025-03-18
- Estimated Expiration
- 2041-07-21
AI Technical Summary
In integrated circuit design, physical design solutions in the back-end design stage often cannot be directly passed, resulting in multiple iterations, which consumes a lot of manpower and poses quality risks.
By directly modifying netlists, library exchange files and design exchange files during the back-end design stage, avoiding iterations in the front-end design stage, and realizing self-cyclical iteration of back-end design.
It significantly accelerates the integrated circuit design process, reduces the time-consuming of front and back-end iterations, improves design efficiency and reduces quality risks.
Smart Images
Figure CN115688651B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to integrated circuit design, and more particularly to a back-end design optimization method. Background Art
[0002] like Figure 1 As shown, the integrated circuit design is divided into two steps, front-end design S1 and back-end design S2. The front-end design S1 is designed and simulated according to the specifications, and the gate-level netlist is output to the back-end design. The back-end design S2 mainly includes testability design, layout planning, wiring and other steps. The designer found that the physical design scheme could not pass the design requirements in the back-end design S2. According to the specific physical implementation needs of the integrated circuit, the threading configuration and the beat configuration were output to the front-end design S1. The front-end designer modified the hardware description language code according to the threading configuration and the beat configuration before performing the back-end design S2. It takes multiple iterations to finally converge to a feasible solution. Multiple iterations not only consume a lot of manpower, but also easily lead to quality risks. Summary of the invention
[0003] The present invention provides an optimization method and system for integrated circuit back-end design, which is used in commercial tools of electronic design automation (EDA) to accelerate the design process of integrated circuits. After the back-end determines the threading scheme, it does not return to the front-end iteration, but directly iterates in the back-end by modifying the netlist, library exchange file, and design exchange file.
[0004] The technical solution of the present invention is: an optimization method for integrated circuit back-end design, the method comprising:
[0005] According to the specific physical implementation requirements of the integrated circuit, a specific configuration is obtained;
[0006] Update the netlist file and the design exchange file according to the configuration for the back-end design to re-establish the database;
[0007] Physical verification of the layout. If verification fails, modify the configuration and rebuild the database.
[0008] After verification, enter the front-end design.
[0009] The above configuration is a stringing and beating configuration.
[0010] The netlist file, design exchange file and library exchange file are updated according to the configuration for the back-end design to re-establish the database.
[0011] The above verification is performed by entering the front-end design and modifying the RTL code according to the configuration.
[0012] The above method further includes,
[0013] According to the configuration, a signal needs to pass through a module;
[0014] Modify the netlist file of the module to add input ports and output ports of the signal;
[0015] Modify the design exchange file of the module to add the input port and output port of the signal;
[0016] Modify the library exchange file of the module and add the input port and output port of the signal.
[0017] The present invention also provides a system for optimizing the back-end design of an integrated circuit, wherein the integrated circuit is designed using electronic design automation software, and the system comprises:
[0018] A receiving device, which is designed to receive a specific physical implementation of an integrated circuit,
[0019] a construction device designed to construct a configuration of an integrated circuit;
[0020] A first providing device provides a netlist and a design exchange file according to the configuration
[0021] a second providing device, re-establishing a database based on the netlist and design exchange file provided by the first providing device;
[0022] The verification device is designed for physical verification of the layout. If the verification fails, the configuration is modified and the database is re-established. If the verification passes, the front-end design is entered.
[0023] The above configuration is a stringing and beating configuration.
[0024] The first providing device also provides a library exchange file according to the configuration for the back-end design to re-establish the database.
[0025] The above verification is performed by entering the front-end design and modifying the RTL code according to the configuration.
[0026] The second providing device, according to the design, receives a signal that needs to pass through a module,
[0027] The second providing device modifies the netlist file of the module to add an input port and an output port of the signal;
[0028] The second providing device modifies the design exchange file of the module to add an input port and an output port of the signal;
[0029] The second providing device modifies the library exchange file of the module to add the input port and the output port of the signal.
[0030] In order to make the above features and advantages of the invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1 Steps for integrated circuit design.
[0032] Figure 2 An optimization method designed for the back end of the present invention.
[0033] Figure 3 for Figure 2 Step S22 is a specific embodiment.
[0034] Figure 4 A schematic diagram for the physical implementation of an integrated circuit design.
[0035] Figure 5 A computer system is provided as an embodiment of the present invention. DETAILED DESCRIPTION
[0036] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0037] like Figure 2 The flowchart of the back-end design method of the present invention is shown, and the back-end design S2 includes:
[0038] Step S21, obtaining a specific configuration P according to the specific physical implementation requirements of the integrated circuit, wherein the configuration P is, for example, a threading and beating configuration;
[0039] Step S22, directly exporting a new netlist and design exchange according to the configuration P for the back-end design to re-establish the database, for example, using the tool Innovus / ICC to re-establish the DB;
[0040] Step S23, physical verification of the layout. If the verification fails, execute step S24 and return to step S21. If the verification passes, execute step front-end design S1;
[0041] Step S24, re-modify the configuration P according to the actual situation of physical verification to obtain a configuration that is more in line with the actual physical implementation. Specifically, if it is found that the threading configuration and the beat configuration cannot meet the required performance requirements or area requirements during layout and routing, the layout and routing scheme in the chip will be readjusted, and the threading configuration and the beat configuration will be modified according to the new scheme.
[0042] Front-end design S1 includes:
[0043] Step S11, modify the RTL code according to the configuration P
[0044] The core difference between this method and the traditional method is that in the back-end design S2, when performing layout and routing, if it is found that the configuration P needs to be adjusted, the adjustment test is directly performed within the back-end design S2 process without going through the front-end process.
[0045] Specifically, when backend design S2 is doing layout and routing, if it is found that the wire configuration needs to be adjusted, compared to the traditional method of feeding back information to frontend design S1 and waiting for the frontend to spend 1-4 weeks to adjust and re-output the netlist file, design exchange file, and library exchange file, the new method can directly update the netlist file, design exchange file, and library exchange file, thereby enabling rapid iteration in backend design S2.
[0046] like Figure 3 Shown Figure 2 A specific embodiment of step S22 includes the following steps:
[0047] Step S221, according to configuration P, signal D needs to pass through module A;
[0048] Step S222, modify the netlist of module A to add an input port and an output port of signal D;
[0049] Step S223 modifies the design exchange of module A and adds an input port and an output port of signal D;
[0050] Step S224 modifies the library exchange of module A and adds the input port and output port of signal D.
[0051] The method of modifying the netlist is to add the input and output ports that signal D needs to pass through module A, and connect the input and output ports together inside the netlist. The modification of the library exchange file is also to add the input and output ports that signal D needs to pass through module A. Compared with the netlist file, the library exchange port also needs to define the port coordinate information. This coordinate information is obtained by converting the absolute coordinates of module A and the relative coordinates of the port. The design exchange file adds the input and output ports that signal D needs to pass through module A, and the conversion principle is consistent with the library exchange file.
[0052] In this way, the three modified files can be directly refreshed into the back-end design S2 for iteration, which is the physical verification of the layout, and there is no need to return to the front-end design S1 to wait for the time-consuming front-end and back-end iterations.
[0053] Figure 4A schematic diagram of the physical implementation of an integrated circuit design. The backend engineer found that the IO pins are arranged on the left and are blocked by the module core_alu. The ports of the module core_alu need to be adjusted to connect the IO pins to the module on the right.
[0054] The following uses a clk port as an example to describe the operation of this method:
[0055] For the library exchange file core_alu.lef, two ports clk_feedThroughIn_clk and clk_feedThroughOut_clk need to be added. And the coordinates of the newly added ports need to be calculated. According to the starting coordinates of the module core_alu and the absolute coordinates of the port clk, the relative coordinates of the newly added ports clk_feedThroughIn_clk and clk_feedThroughOut_clk in the library exchange file can be calculated.
[0056] For example: the starting coordinates of the module core_alu are (0,100), and the absolute coordinates of the port clk are (500,500), then the relative coordinates of the port clk in the library exchange file are (500,400).
[0057] For the design exchange file core_alu.def, two new input and output ports should be added according to the same principle, and the coordinate positions of the newly added ports should be calculated. The principle of coordinate calculation is the same as that of the library exchange file.
[0058] For the netlist file core_alu.syn.v, also add two ports clk_feedThroughPinIn_clk and clk_feedThroughPinOut_clk, and use the assign command to connect the two ports.
[0059] The specific syntax is:
[0060] input feedThroughPinIn;
[0061] input feedThroughPinOut;
[0062] assign feedThroughPinOut=feedThroughPinIn;
[0063] The present invention relates to an electronic design automation (EDA) design method, which can be used in commercial tools of electronic design automation (EDA) to accelerate the design process of integrated circuits.
[0064] After the threading scheme is determined on the back end, it does not return to the front end for iteration, but iterates directly on the back end by modifying the netlist, library exchange file, and design exchange file.
[0065] Generate feed-through and pipeline configurations based on the actual physical placement needs of the back-end design, and output the scripts of the electronic design automation (EDA) tool based on the above configurations to export updated netlists and data exchange files. It also supports directly exporting updated netlists and data through self-developed software, and after iterative verification, exporting the configuration to generate the hardware description language used by front-end designers.
[0066] Compared with traditional processes, the threading configuration can be self-looped and iterated within the backend, avoiding time-consuming front-end and back-end iterations, thus significantly speeding up project development.
[0067] Figure 5 A computer system 51 according to one embodiment of the present invention is shown.
[0068] The computer system 51 includes a processor 511 and a memory 512. The computer system 51 may be coupled to a display system 52 and an input system 53. The memory 512 may store instructions and / or data, and when the processor 511 processes these instructions and / or data, it enables the computer system 51 to assist in the design of integrated circuits.
[0069] Specifically, the memory 512 can store EDA software 5122 and other technical files related to integrated circuit design. During operation, the EDA software 5122 can be used to create integrated circuit design. Specifically, after the EDA software 5122 determines the threading scheme in the back-end design, it does not return to the front-end design S1 iteration, but directly iterates in the back-end design S2 by modifying the netlist, library exchange file, design exchange file, etc.
[0070] Figure 5 The modules shown are for illustration purposes only and are not intended to limit the invention to the disclosed form.
[0071] The data structures and codes described in this detailed implementation section are generally stored in a computer-readable memory 512, which can be any device or medium capable of storing code and / or data for use by a computer system. The memory 512 includes, but is not limited to, volatile memory, non-volatile memory, magnetic and optical storage devices (such as disk drives, tapes, CDs (compact disks), DVDs (digital versatile disks or digital video disks)), or other media now known or to be developed capable of storing computer-readable media.
[0072] The methods and processes described in the specific implementation section can be embodied as codes and / or data that can be stored in the above-mentioned memory 512. When the computer system 51 reads and executes the code and / or data stored in the memory 512, the computer system 51 executes the methods and processes implemented as data structures and codes and stored in the memory 512. The method and process realize the optimization of the back-end design of the integrated circuit. Specifically, according to the actual physical placement needs of the back-end design, configurations such as feed-through and pipeline are generated. According to the above configuration, the computer system 51 outputs the script of the electronic design automation (EDA) tool, thereby exporting the updated netlist and data exchange file; it also supports that the computer system 51 can also directly export the updated netlist and data through the self-developed software, and perform iterative verification to determine the final configurations such as feed-through and pipeline. The front-end designer generates the hardware description language used by the front-end designer based on the final configurations such as feed-through and pipeline.
[0073] Compared with the traditional process, the technical problems solved and the advantages of this method are: because the threading configuration can be self-looped and iterated within the backend, time-consuming front-end and back-end iterations are avoided, thus significantly speeding up project development.
[0074] It can be understood that the above specific description of the present invention is only used to illustrate the present invention and is not limited to the technical solutions described in the embodiments of the present invention. Those skilled in the art should understand that the present invention can still be modified or replaced by equivalents to achieve the same technical effects; as long as the use requirements are met, they are within the protection scope of the present invention.
Claims
1. An optimization method for integrated circuit back-end design, characterized in that: The method comprises, Step S1, obtaining a specific configuration according to the specific physical implementation requirements of the integrated circuit, wherein the configuration includes a threading configuration and a beating configuration; Step S2, exporting a new netlist file and a design exchange file according to the configuration, and re-establishing a new database; Step S3, perform physical verification of the layout. If the verification passes, proceed to step S4. If the verification fails, modify the threading configuration and the beat configuration. Specifically, if it is found that the threading configuration and the beat configuration cannot meet the performance requirements or area requirements during layout and routing, the layout and routing scheme in the chip will be readjusted, and the threading configuration and the beat configuration will be modified according to the new scheme. Step S4, if the verification is passed, execute step front-end design S1; The front-end design S1 includes: step S11, modifying the RTL code according to the configuration P; Step S2 also includes: according to the configuration, a signal needs to pass through a module; modifying the netlist file of the module, adding the input port and output port of the signal, and connecting the input and output ports together inside the netlist; modifying the design exchange file of the module, adding the input port and output port of the signal, and defining the coordinates of the port; modifying the library exchange file of the module, adding the input port and output port of the signal, and defining the coordinates of the port.
2. The method according to claim 1, characterized in that The netlist file, design exchange file and library exchange file are updated according to the configuration so as to re-establish the database for the back-end design.
3. An optimization system for back-end design of an integrated circuit, wherein the integrated circuit is designed using electronic design automation software, the system comprising: A receiving device designed to receive a specific physical implementation of an integrated circuit; A construction device designed to construct a configuration of an integrated circuit, the configuration comprising a threading configuration and a beating configuration; a first providing device, providing a netlist file and a design exchange file according to the configuration; A second providing device re-establishes a database based on the netlist file and the design exchange file provided by the first providing device; A verification device, which is designed for physical verification of the layout and, if the verification fails, to modify the threading configuration and the tapping configuration; If the verification is passed, enter the front-end design, which includes: modifying the RTL code according to the configuration P; Specifically, if it is found that the threading configuration and the beat configuration cannot meet the performance requirements or area requirements during layout and routing, the layout and routing scheme within the chip will be readjusted, and the threading configuration and the beat configuration will be modified according to the new scheme; The second providing device receives a requirement that a signal needs to pass through a module; the second providing device modifies the netlist file of the module, adds the input port and output port of the signal, and connects the input and output ports together inside the netlist; the second providing device modifies the design exchange file of the module, adds the input port and output port of the signal, and calculates the coordinates of the newly added ports; the second providing device modifies the library exchange file of the module, adds the input port and output port of the signal.
4. The system according to claim 3, characterized in that The first providing device also provides a library exchange file according to the configuration for the back-end design to re-establish the database.