Pixel circuit and driving method thereof, and display device

Abstract

A pixel circuit includes: a driving subcircuit, a writing subcircuit, a compensation subcircuit, a first reset subcircuit, a second reset subcircuit, a first capacitor and a second capacitor, wherein the writing subcircuit writes a data signal to a second node in response to a signal of a second scanning signal line; the compensation subcircuit writes a first or second reset signal of a third node to a first node in response to a signal of a first scanning signal line to compensate the first node; the first reset subcircuit writes a first reset signal to an anode terminal of a light-emitting element in response to a signal of a first light-emitting control signal line or a second reset control signal line; the second reset subcircuit writes a second reset signal to a first electrode or a second electrode of the driving subcircuit in response to a signal of the first reset control signal line; the first capacitor is connected between the first node and the second scanning signal line; the second capacitor is connected between the first node and the first scanning signal line; and the capacitance value of the first capacitor is greater than the capacitance value of the second capacitor.

Description

[0001] This case is a divisional application of patent application 202180002058.8. The application date of the original application is July 30, 2021, the application number is 202180002058.8, and the name of the invention is "Pixel circuit and its driving method, display device". Technical Field

[0002] The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a pixel circuit and a driving method thereof, and a display device. Background Art

[0003] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. With the continuous development of display technology, flexible display devices (Flexible Display) using OLED or QLED as light-emitting devices and signal control by thin film transistors (TFT) have become the mainstream products in the current display field. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] An embodiment of the present disclosure provides a pixel circuit, including: a driving subcircuit, a first reset subcircuit, a second reset subcircuit and a light-emitting element, wherein: the driving subcircuit is configured to generate a driving current between a second node and a third node in response to a control signal of a first node; the first reset subcircuit is configured to write a first reset signal to an anode terminal of the light-emitting element in response to a signal of a first light-emitting control signal line or a second reset control signal line; the second reset subcircuit is configured to write a second reset signal to a first pole or a second pole of the driving subcircuit in response to a signal of the first reset control signal line; and the second reset signal is greater than the first reset signal.

[0006] In some exemplary embodiments, an absolute value of the second reset signal is greater than 1.5 times a threshold voltage of the driving sub-circuit.

[0007] In some exemplary embodiments, the amplitude of the second reset signal is greater than zero.

[0008] In some exemplary embodiments, the pixel circuit further includes: a writing subcircuit, a compensation subcircuit, a first light-emitting control subcircuit, and a second light-emitting control subcircuit, wherein: the writing subcircuit is configured to write a data signal to the second node in response to a signal of a second scanning signal line; the compensation subcircuit is configured to write a first reset signal or a second reset signal of the third node to the first node in response to a signal of the first scanning signal line; and is also configured to compensate the first node in response to a signal of the first scanning signal line; the first light-emitting control subcircuit is configured to provide a signal of a first power line to the second node in response to a signal of the first light-emitting control signal line; the second light-emitting control subcircuit is configured to write a first reset signal of a fourth node to the third node in response to a signal of the second light-emitting control signal line; and is also configured to allow a driving current to pass between the third node and the fourth node in response to a signal of the second light-emitting control signal line.

[0009] In some exemplary embodiments, the second reset signal is derived from at least one of the following signal lines: the first power line, the first light emission control signal line, the second light emission control signal line, or a third power line.

[0010] In some example embodiments, a pulse width of a signal of the first reset control signal line is substantially the same as a pulse width of a signal of the second scan signal line.

[0011] In some exemplary embodiments, the signal pulse of the first light emitting control signal line differs from the signal pulse of the second light emitting control signal line by one or two time units, and one time unit is the time for scanning a row of sub-pixels.

[0012] In some exemplary embodiments, the first reset subcircuit includes a first transistor, wherein: a control electrode of the first transistor is connected to the first light emitting control signal line or the second reset control signal line, a first electrode of the first transistor is connected to the first reset signal line, and a second electrode of the first transistor is connected to the fourth node.

[0013] In some exemplary embodiments, the compensation subcircuit includes a second transistor and a first capacitor, wherein: a control electrode of the second transistor is connected to the first scanning signal line, a first electrode of the second transistor is connected to a third node, and a second electrode of the second transistor is connected to the first node; one end of the first capacitor is connected to the first node, and the other end of the first capacitor is connected to the first power line.

[0014] In some exemplary embodiments, the driving subcircuit includes a third transistor, wherein: a control electrode of the third transistor is connected to the first node, a first electrode of the third transistor is connected to the second node, and a second electrode of the third transistor is connected to the third node.

[0015] In some exemplary embodiments, the write subcircuit includes a fourth transistor, wherein: a control electrode of the fourth transistor is connected to the second scan signal line, a first electrode of the fourth transistor is connected to the data signal line, and a second electrode of the fourth transistor is connected to the second node.

[0016] In some exemplary embodiments, the first light emitting control subcircuit includes a fifth transistor, wherein: a control electrode of the fifth transistor is connected to the first light emitting control signal line, a first electrode of the fifth transistor is connected to the first power line, and a second electrode of the fifth transistor is connected to the second node.

[0017] In some exemplary embodiments, the second light emitting control subcircuit includes a sixth transistor, wherein: a control electrode of the sixth transistor is connected to the second light emitting control signal line, a first electrode of the sixth transistor is connected to the third node, and a second electrode of the sixth transistor is connected to the fourth node.

[0018] In some exemplary embodiments, the second reset subcircuit includes a seventh transistor, wherein: a control electrode of the seventh transistor is connected to the reset control signal line, a first electrode of the seventh transistor is connected to the second reset signal line, and a second electrode of the seventh transistor is connected to the second node or the third node.

[0019] In some exemplary embodiments, the first reset subcircuit includes a first transistor, the compensation subcircuit includes a second transistor and a first capacitor, the driving subcircuit includes a third transistor, the writing subcircuit includes a fourth transistor, the first light-emitting control subcircuit includes a fifth transistor, the second light-emitting control subcircuit includes a sixth transistor, and the second reset subcircuit includes a seventh transistor, wherein: the control electrode of the first transistor is connected to the first light-emitting control signal line or the second reset control signal line, the first electrode of the first transistor is connected to the first reset signal line, and the second electrode of the first transistor is connected to the fourth node; the control electrode of the second transistor is connected to the first scanning signal line, the first electrode of the second transistor is connected to the third node, and the second electrode of the second transistor is connected to the first node; one end of the first capacitor is connected to the first node, and the other end of the first capacitor is connected to the first power line; the control electrode of the third transistor is connected to the first node, the first electrode of the third transistor is connected to the second node, and the The second electrode of the third transistor is connected to the third node; the control electrode of the fourth transistor is connected to the second scanning signal line, the first electrode of the fourth transistor is connected to the data signal line, and the second electrode of the fourth transistor is connected to the second node; the control electrode of the fifth transistor is connected to the first light-emitting control signal line, the first electrode of the fifth transistor is connected to the first power supply line, and the second electrode of the fifth transistor is connected to the second node; the control electrode of the sixth transistor is connected to the second light-emitting control signal line, the first electrode of the sixth transistor is connected to the third node, and the second electrode of the sixth transistor is connected to the fourth node; the control electrode of the seventh transistor is connected to the reset control signal line, the first electrode of the seventh transistor is connected to the second reset signal line, and the second electrode of the seventh transistor is connected to the second node or the third node.

[0020] In some exemplary embodiments, at least one of the first transistor, the second transistor, and the seventh transistor is a first type transistor, the third transistor to the sixth transistor are all second type transistors, and the first type transistor and the second type transistor are different in transistor type.

[0021] In some exemplary embodiments, the first type transistor is an N-type thin film transistor; and the second type transistor is a P-type thin film transistor.

[0022] In some exemplary embodiments, at least one of the first transistor, the second transistor, and the seventh transistor is an indium gallium zinc oxide thin film transistor, and the third to sixth transistors are low temperature polysilicon thin film transistors.

[0023] An embodiment of the present disclosure further provides a display device, comprising: a pixel circuit as described in any one of the above items.

[0024] The embodiment of the present disclosure also provides a driving method for a pixel circuit, which is used to drive the pixel circuit as described above, wherein the pixel circuit has multiple scanning cycles. Within a scanning cycle, the driving method includes: in a reset stage, a first reset subcircuit responds to a signal of a first light-emitting control signal line or a second reset control signal line to write a first reset signal to an anode terminal of a light-emitting element; in a reset stage, a second reset subcircuit responds to a signal of a first reset control signal line to write a second reset signal to a first pole or a second pole of a driving subcircuit; the second reset signal is greater than the first reset signal; in a light-emitting stage, the driving subcircuit generates a driving current between a second node and a third node in response to a control signal of a first node.

[0025] Other aspects will become apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure. The shapes and sizes of the components in the accompanying drawings do not reflect the actual proportions and are only intended to illustrate the contents of the present disclosure.

[0027] Figure 1 is a circuit structure schematic diagram of a pixel driving circuit in the related art;

[0028] Figure 2 for Figure 1 A timing diagram of each node in a driving method of a pixel driving circuit;

[0029] Figure 3 for Figure 1 The pixel driving circuit in Figure 2 The simulation timing diagram of the first node, the second node and the third node in the driving method shown;

[0030] Figure 4 A schematic structural diagram of an exemplary embodiment of a pixel driving circuit disclosed in the present invention;

[0031] Figure 5 is a structural schematic diagram of another exemplary embodiment of the pixel driving circuit disclosed in the present invention;

[0032] Figure 6 is a structural schematic diagram of another exemplary embodiment of the pixel driving circuit disclosed in the present invention;

[0033] Figure 7is a structural schematic diagram of another exemplary embodiment of the pixel driving circuit disclosed in the present invention;

[0034] Figure 8 for Figure 7 A timing diagram of each node in a driving method of a pixel driving circuit;

[0035] Fig. 9 for Figure 7 The pixel driving circuit in Figure 8 The simulation timing diagram of the first node, the second node and the third node in the driving method shown;

[0036] Fig.10 is a structural diagram of an exemplary embodiment of a pixel driving circuit disclosed in the present invention;

[0037] Fig.11 is a structural schematic diagram of another exemplary embodiment of the pixel driving circuit disclosed in the present invention;

[0038] Fig.12 is a structural schematic diagram of another exemplary embodiment of the pixel driving circuit disclosed in the present invention;

[0039] Fig.13 for Fig.12 A timing diagram of each node in a driving method of a pixel driving circuit;

[0040] Fig.14 is a structural schematic diagram of another exemplary embodiment of the pixel driving circuit disclosed in the present invention;

[0041] Fig.15 A distribution diagram of a pixel driving circuit in an exemplary embodiment of a display panel disclosed herein;

[0042] Fig.16 is a distribution diagram of a pixel driving circuit in another exemplary embodiment of the display panel disclosed herein;

[0043] Fig.17 is a distribution diagram of a pixel driving circuit in another exemplary embodiment of the display panel disclosed herein;

[0044] Fig.18 A partial structural diagram of an exemplary embodiment of the display panel disclosed herein;

[0045] Fig.19 for Fig.18 A structural layout of the first conductive layer;

[0046] Fig. 20 for Fig.18 The structural layout of the second conductive layer;

[0047] Fig.21 for Fig.18 The structural layout of the second active layer;

[0048] Fig. 22 for Fig.18 The structural layout of the third conductive layer;

[0049] Fig.23 for Fig.18 The structural layout of the fourth conductive layer;

[0050] Fig.24 for Fig.18 A structural layout of a first conductive layer, a second conductive layer, and a second active layer;

[0051] Fig.25 for Fig.18 A structural layout of a first conductive layer, a second conductive layer, a second active layer, and a third conductive layer;

[0052] Fig.26 for Fig.18 A partial cross-sectional view along the dotted line A;

[0053] Fig. 27 One of the structural schematic diagrams of the pixel circuit provided in the embodiment of the present disclosure;

[0054] Fig.28 The second structural schematic diagram of the pixel circuit provided by the embodiment of the present disclosure;

[0055] Fig.29 A schematic diagram of the structure of a first reset subcircuit provided in an embodiment of the present disclosure;

[0056] Fig.30 A schematic diagram of the structure of a compensation subcircuit provided in an embodiment of the present disclosure;

[0057] Fig.31 A schematic diagram of the structure of a driving sub-circuit provided in an embodiment of the present disclosure;

[0058] Fig.32 A schematic diagram of the structure of a writing sub-circuit provided in an embodiment of the present disclosure;

[0059] Fig.33 A schematic diagram of the structure of a first light-emitting control subcircuit provided in an embodiment of the present disclosure;

[0060] Fig.34 A schematic diagram of the structure of a second light-emitting control subcircuit provided in an embodiment of the present disclosure;

[0061] Fig.35 One of the structural schematic diagrams of the second reset sub-circuit provided in the embodiment of the present disclosure;

[0062] Fig.36 The second structural schematic diagram of the second reset sub-circuit provided in the embodiment of the present disclosure;

[0063] Fig.37a One of the equivalent circuit diagrams of the pixel circuit provided in the embodiment of the present disclosure;

[0064] Fig.37b The second equivalent circuit diagram of the pixel circuit provided in the embodiment of the present disclosure;

[0065] Fig.38a The third equivalent circuit diagram of the pixel circuit provided in the embodiment of the present disclosure;

[0066] Figure 38b The fourth equivalent circuit diagram of the pixel circuit provided in the embodiment of the present disclosure;

[0067] Fig.39 for Fig.37a or Fig.37b The working timing diagram of the pixel circuit shown in FIG. 1 within a scanning cycle;

[0068] Fig.40 for Fig.38a Or the working timing diagram of the pixel circuit shown in 38b within one scanning cycle;

[0069] Fig.41 for Fig.37a The schematic diagram of the working state of the transistor of the pixel circuit in the reset phase is shown;

[0070] Fig.42 for Fig.37a The schematic diagram of the working state of the transistor of the pixel circuit in the reset phase is shown;

[0071] Fig.43 for Fig.37a The schematic diagram of the working state of the transistor of the pixel circuit in the data writing stage is shown;

[0072] Fig.44 for Fig.37a The schematic diagram of the working state of the transistor of the pixel circuit in the light emitting stage is shown;

[0073] Fig.45 A schematic diagram of a process flow of a driving method for a pixel circuit provided in an embodiment of the present disclosure;

[0074] Fig.46 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0075] Fig.47 is a structural diagram of a pixel circuit according to at least another embodiment of the present disclosure;

[0076] Fig.48 is a structural diagram of a pixel circuit according to at least another embodiment of the present disclosure;

[0077] Fig.49is a structural diagram of a pixel circuit according to at least another embodiment of the present disclosure;

[0078] Fig.50 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0079] Fig.51 This disclosure is Fig.50 An operation timing diagram of at least one embodiment of the pixel circuit shown;

[0080] Fig.52 is a circuit diagram of a pixel circuit according to at least another embodiment of the present disclosure;

[0081] Fig.53 is a circuit diagram of a pixel circuit according to at least another embodiment of the present disclosure;

[0082] Fig.54 is a circuit diagram of a pixel circuit according to at least another embodiment of the present disclosure;

[0083] Fig.55 is a schematic diagram of the electrical connection between two adjacent rows of pixel circuits and a reset voltage line in the same row;

[0084] Fig.56 is a schematic diagram of the electrical connection between two adjacent columns of pixel circuits and a reset voltage line in the same column;

[0085] Fig.57 is a schematic diagram of pixel circuits in adjacent rows and columns sharing a reset voltage line;

[0086] Fig.58 It is a schematic diagram of the connection relationship and position relationship between the reset voltage lines arranged in a grid and a plurality of pixel circuits;

[0087] Fig.59 is a structural diagram of a display device according to at least one embodiment of the present disclosure;

[0088] Fig.60 is a structural diagram of a display device according to at least another embodiment of the present disclosure;

[0089] Fig.61 is a structural diagram of a pixel circuit according to at least another embodiment of the present disclosure;

[0090] Fig.62 is a structural diagram of a pixel circuit according to at least another embodiment of the present disclosure;

[0091] Fig.63 is a structural diagram of a pixel circuit according to at least another embodiment of the present disclosure;

[0092] Fig.64 is a structural diagram of a pixel circuit according to at least another embodiment of the present disclosure;

[0093] Fig.65 is a structural diagram of a pixel circuit according to at least another embodiment of the present disclosure;

[0094] Fig.66 is a structural diagram of a pixel circuit according to at least another embodiment of the present disclosure;

[0095] Fig.67 is a structural diagram of a pixel circuit according to at least another embodiment of the present disclosure;

[0096] Fig.68 is a circuit diagram of a pixel circuit according to at least another embodiment of the present disclosure;

[0097] Fig.69 yes Fig.68 An operation timing diagram of at least one embodiment of the pixel circuit shown;

[0098] Fig.70 yes Fig.68 An operation timing diagram of at least another embodiment of the pixel circuit shown;

[0099] Fig.71 yes Fig.68 An operation timing diagram of at least another embodiment of the pixel circuit shown;

[0100] Fig.72 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0101] Fig.73 yes Fig.72 An operation timing diagram of at least one embodiment of the pixel circuit shown;

[0102] Fig.74 yes Fig.72 An operation timing diagram of at least another embodiment of the pixel circuit shown;

[0103] Fig.75 is a structural diagram of a pixel circuit according to at least another embodiment of the present disclosure;

[0104] Fig.76 yes Fig.75 An operation timing diagram of at least one embodiment of the pixel circuit shown;

[0105] Fig.77 is a structural diagram of a display device according to at least another embodiment of the present disclosure;

[0106] Fig.78 is a structural diagram of a display device according to at least another embodiment of the present disclosure. DETAILED DESCRIPTION

[0107] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the present disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0108] The terms "a", "an", and "the" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to indicate an open-ended inclusive meaning and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.

[0109] like Figure 1FIG. 1 is a schematic diagram of a circuit structure of a pixel driving circuit in the related art. The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. Among them, the gate of the driving transistor T3 is connected to the first node N1, the first electrode is connected to the second node N2, and the second electrode is connected to the third node N3; the first electrode of the fourth transistor T4 is connected to the data signal terminal Da, the second electrode is connected to the second node N2, and the gate is connected to the gate driving signal terminal G2; the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, the second electrode is connected to the second node N2, and the gate is connected to the enable signal terminal EM; the first electrode of the second transistor T2 is connected to the first node N1, the second electrode is connected to the third node N3, and the gate is connected to the gate driving signal terminal G1; the first electrode of the sixth transistor T6 is connected to the third node N3, the second electrode is connected to the first electrode of the seventh transistor T7, the gate is connected to the enable signal terminal EM, the second electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the gate is connected to the second reset signal terminal Re2; the first electrode of the first transistor T1 is connected to the first node N1, the second electrode is connected to the first initial signal terminal Vinit1, and the gate is connected to the first reset signal terminal Re1, and the capacitor C is connected between the first power supply terminal VDD and the first node N1. The pixel driving circuit can be connected to a light-emitting unit OLED, and is used to drive the light-emitting unit OLED to emit light. The light-emitting unit OLED can be connected between the second electrode of the sixth transistor T6 and the power supply terminal VSS. Among them, the first transistor T1 and the second transistor T2 can be N-type transistors, for example, the first transistor T1 and the second transistor T2 can be N-type metal oxide transistors, and the N-type metal oxide transistor has a small leakage current, so that the node N can be prevented from leaking through the first transistor T1 and the second transistor T2 during the light-emitting stage. At the same time, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type transistors, for example, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type low-temperature polycrystalline silicon transistors, and the low-temperature polycrystalline silicon transistor has a high carrier mobility, which is conducive to realizing a display panel with high resolution, high response speed, high pixel density, and high aperture ratio. The first initial signal terminal and the second initial signal terminal can output the same or different voltage signals according to actual conditions.

[0110] like Figure 2 As shown, Figure 1A timing diagram of each node in a driving method of a pixel driving circuit. Among them, G1 represents the timing of the gate driving signal terminal G1, G2 represents the timing of the gate driving signal terminal G2, Re1 represents the timing of the first reset signal terminal Re1, Re2 represents the timing of the second reset signal terminal Re2, EM represents the timing of the enable signal terminal EM, Da represents the timing of the data signal terminal Da, and N1 represents the timing of the first node N1. The driving method of the pixel driving circuit may include a first reset stage t1, a threshold compensation stage t2, a second reset stage t3, and a light emitting stage t4. In the first reset stage t1: the first reset signal terminal Re1 outputs a high level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs an initial signal to the first node N1. In the threshold compensation stage t2: the gate drive signal terminal G1 outputs a high level signal, the gate drive signal terminal G2 outputs a low level signal, the fourth transistor T4 and the second transistor T2 are turned on, and at the same time the data signal terminal Da outputs a drive signal to write a voltage Vdata+Vth to the node N, where Vdata is the voltage of the drive signal, and Vth is the threshold voltage of the drive transistor T3. In the second reset stage t3, the second reset signal terminal Re2 outputs a low level signal, the seventh transistor T7 is turned on, and the second initial signal terminal Vinit2 inputs an initial signal to the second electrode of the sixth transistor T6. Light-emitting stage t4: the enable signal terminal EM outputs a low level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the drive transistor T3 emits light under the action of the voltage Vdata+Vth stored in the capacitor C. According to the output current formula of the drive transistor I=(μWCox / 2L)(Vgs-Vth) 2 , where μ is carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, L is the length of the driving transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor. The output current of the driving transistor in the pixel driving circuit of the present disclosure is I=(μ WCox / 2L)(Vdata+Vth-Vdd-Vth) 2 The pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0111] In the related art, there is a parasitic capacitance between the gate and source of the driving transistor in the pixel driving circuit. In the reset phase of the pixel driving circuit, the gate voltage of the driving transistor is initialized to the initial voltage. Under the coupling effect of the above parasitic capacitance, the source voltage of the driving transistor also changes accordingly. When resetting different grayscales in the reset phase, the change amount of the gate voltage of the driving transistor is different, so the change amount of the source voltage of the driving transistor is also different, which leads to different Vgs (gate-source voltage difference) of the driving transistor after the reset phase is completed. Figure 3 As shown, Figure 1The pixel driving circuit in Figure 2 The simulation timing diagrams of the first node, the second node, and the third node in the driving method shown in the figure, N1 represents the timing diagram of the first node N1, N2 represents the timing diagram of the second node N2, and N3 represents the timing diagram of the third node N3, wherein, Figure 3 Specifically shows Figure 1 The timing diagram of each node of the pixel driving circuit shown in the figure under four data signals, Figure 3 In the reset stage t1, the first node N1 under the four data signals needs to be reset. This exemplary embodiment is described with the timing of each node under two data signals. Figure 3 As shown, under the first data signal, the timing of each node is shown as curve Vda1, and under the second data signal, the timing of each node is shown as curve Vda2. Since the voltages of the first data signal and the second data signal are different, before the reset stage t1, the voltage of the first node N1 is different, the voltage of the third node N3 is also different, and the voltage of the second node is the voltage of the first power supply terminal VDD; in the reset stage t1, the voltage of the first node N1 under both data signals is pulled down to the initial voltage. Since the pull-down change of the first node N1 under the first data signal is less than the pull-down change of the first node N1 under the second data signal, the pull-down change of the second node under the first data signal is less than the pull-down change of the second node N2 under the second data signal, that is, in the reset stage, the voltage of the second node N2 under the first data signal is less than the voltage of the second node N2 under the second data signal, so that under different data signals, the driving transistor Vgs (gate-source voltage difference) is different. At the same time, since the Vgs of the driving transistor will affect its threshold voltage, the display panel will have afterimage and flicker problems. For example, when the display panel changes from a black and white image to the same grayscale image, due to the different threshold voltages of the driving transistors in the corresponding pixels of the black and white images, after changing to the same grayscale image, the area where the previous black and white image is located will display different grayscales, that is, an afterimage problem occurs.

[0112] Based on this, this exemplary embodiment provides a pixel driving circuit, such as Figure 4As shown, it is a structural schematic diagram of an exemplary embodiment of the pixel driving circuit of the present disclosure. The pixel driving circuit may include: a driving circuit 1, a first reset circuit 2, and a second reset circuit 3. The driving circuit 1 is connected to a first node N1 and a second node N2, and is used to output a driving current according to a voltage difference between the first node N1 and the second node N2; the first reset circuit 2 is connected to the first node N1, a first initial signal terminal Vinit1, and a first reset signal terminal Re1, and is used to transmit the signal of the first initial signal terminal Vinit1 to the first node N1 in response to the signal of the first reset signal terminal Re1; the second reset circuit 3 is connected to the second node N2 and a first power supply terminal VGH, and is used to transmit the signal of the first power supply terminal VGH to the second node N2 in response to a control signal.

[0113] In this exemplary embodiment, the pixel driving circuit can use the first reset circuit 2 to transmit the signal of the first initial signal terminal Vinit1 to the first node N1 during the reset stage, and at the same time, use the second reset circuit 3 to transmit the signal of the first power supply terminal VGH to the second node N2, so that under different data signals, the pixel driving circuit can reset the gate-source voltage difference of the driving transistor to the same value, thereby improving the problems of afterimage and flicker of the display panel.

[0114] In this exemplary embodiment, Figure 4 As shown, the driving circuit 1 can also be connected to a third node N3, and the driving circuit 1 can include: a driving transistor T3, the gate of the driving transistor T3 is connected to the first node N1, the first electrode is connected to the second node N2, and the second electrode is connected to the third node N3. The driving transistor T3 can be a P-type transistor, for example, the driving transistor T3 can be a P-type low-temperature polysilicon transistor, and the driving transistor T3 can input a driving current to the third node according to the voltage difference between the first node N1 and the second node N2. It should be understood that in other exemplary embodiments, the driving transistor T3 can also be an N-type transistor. When the driving transistor T3 is an N-type transistor, the driving transistor can input a driving current to the second node according to the voltage difference between the first node N1 and the second node N2. In addition, the driving circuit 1 can also include a plurality of driving transistors, and the plurality of driving transistors can be connected in parallel between the second node and the third node.

[0115] In this exemplary embodiment, Figure 4As shown, the first reset circuit 2 may include: a first transistor T1, the gate of the first transistor T1 is connected to the first reset signal terminal Re1, the first electrode is connected to the first initial signal terminal Vinit1, and the second electrode is connected to the first node N1. The conduction level of the second reset circuit 3 may be the same as the conduction level polarity of the first reset circuit 2, and the second reset circuit 3 may also be connected to the first reset signal terminal Re1. The second reset circuit 3 may be used to transmit the signal of the first power supply terminal VGH to the second node N2 in response to the signal of the first reset signal terminal Re1. Figure 4 As shown, the second reset circuit 3 may include: an eighth transistor T8, a gate of the eighth transistor T8 is connected to the first reset signal terminal Re1, a first electrode is connected to the first power supply terminal VGH, and a second electrode is connected to the second node N2.

[0116] It should be noted that the pixel driving circuit needs to turn on the driving transistor T3 in the threshold compensation stage, so the voltage difference Vinit1-Vgh between the first initial signal terminal Vinit1 and the first power supply terminal VGH needs to be less than the threshold voltage of the driving transistor T3, wherein Vinit1 is the voltage of the first initial signal terminal, and Vgh is the voltage of the first power supply terminal VGH. In addition, in other exemplary embodiments, the second reset circuit 3 can also transmit the signal of other signal terminals to the second node in response to a control signal to reset the second node.

[0117] In this exemplary embodiment, the first transistor T1 and the eighth transistor T8 may be oxide transistors. For example, the semiconductor material of the first transistor T1 and the eighth transistor T8 may be indium gallium zinc oxide. Accordingly, the first transistor T1 and the eighth transistor T8 may be N-type transistors. The oxide transistor has a smaller off-leakage current, thereby reducing the leakage current of the first node N1 through the first transistor T1 and the leakage current of the second node N2 through the eighth transistor T8.

[0118] It should be understood that in other exemplary embodiments, the conduction level of the second reset circuit 3 and the conduction level of the first reset circuit 2 may also have opposite polarities. Figure 5As shown, it is a structural schematic diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure. The second reset circuit 3 can also be connected to the second reset signal terminal Re2, and the second reset circuit 3 can be used to transmit the signal of the first power supply terminal VGH to the second node N2 in response to the signal of the second reset signal terminal Re2; wherein the signal of the second reset signal terminal Re2 and the signal polarity of the first reset signal terminal Re1 can be opposite. The first reset circuit 2 may include: an N-type first transistor T1, the gate of the first transistor T1 is connected to the first reset signal terminal Re1, the first electrode is connected to the first initial signal terminal Vinit1, and the second electrode is connected to the first node N1. The second reset circuit 3 may include: a P-type eighth transistor T8, the gate of the eighth transistor T8 is connected to the second reset signal terminal Re2, the first electrode is connected to the first power supply terminal VGH, and the second electrode is connected to the second node N2.

[0119] In this exemplary embodiment, Figure 6 , which is a schematic diagram of the structure of another exemplary embodiment of the pixel driving circuit of the present disclosure. The pixel driving circuit may further include: a control circuit 5 and a coupling circuit 6, wherein the control circuit 5 is connected to the second power supply terminal VDD, the second node N2, the third node N3, the fourth node N4, and the enable signal terminal EM, and is used to transmit the signal of the second power supply terminal VDD to the second node N2 in response to the signal of the enable signal terminal EM, and is used to connect the third node N3 and the fourth node N4 in response to the signal of the enable signal terminal EM; the coupling circuit 6 is connected between the second power supply terminal VDD and the first node N1.

[0120] In this exemplary embodiment, Figure 6As shown, the pixel driving circuit may further include: a data writing circuit 7 and a threshold compensation circuit 8, wherein the data writing circuit 7 is connected to the second node N2, the data signal terminal Vdata, and the first gate driving signal terminal G1, and is used to transmit the signal of the data signal terminal Vdata to the second node N2 in response to the signal of the first gate driving signal terminal G1; the threshold compensation circuit 8 may be connected to the first node N1 and the third node N3, and is used to connect the first node N1 and the third node N3 in response to a control signal. The data writing circuit 7 and the threshold compensation circuit 8 are used to be turned on in the threshold compensation stage to write the compensation voltage Vdata+Vth to the first node N1, wherein Vdata is the voltage of the data signal terminal, and Vth is the threshold voltage of the driving transistor. It should be understood that in other exemplary embodiments, there are other ways to write the compensation voltage to the first node N1. For example, the data writing circuit can be connected to the third node N3, the data signal terminal Vdata, and the first gate drive signal terminal G1. The data writing circuit is used to respond to the signal of the first gate drive signal terminal G1 and transmit the signal of the data signal terminal Vdata to the third node N3. At the same time, the threshold compensation circuit 8 can be connected to the first node N1 and the second node N2. The threshold compensation circuit 8 can be used to respond to a control signal to connect the first node N1 and the second node N2. When the data writing circuit 7 and the threshold compensation circuit 8 are turned on, the pixel driving circuit can also write the compensation voltage Vdata+Vth to the first node N1.

[0121] In this exemplary embodiment, Figure 6 As shown, the fourth node N4 can be used to connect a light-emitting unit OLED, which can be a light-emitting diode. Another electrode of the light-emitting unit OLED can be connected to a fourth power supply terminal VSS, and the voltage of the fourth power supply terminal VSS is less than the voltage of the second power supply terminal VDD. The pixel driving circuit can also include: a third reset circuit 4, which is connected to the fourth node N4 and the second initial signal terminal Vinit2, and is used to respond to a control signal to transmit the signal of the second initial signal terminal Vinit2 to the fourth node N4. Among them, writing the initial signal to the fourth node N4 can eliminate the carriers that have not been recombined on the light-emitting interface inside the light-emitting diode, and alleviate the aging of the light-emitting diode.

[0122] In this exemplary embodiment, Figure 6As shown, the control circuit 5 may include: a fifth transistor T5 and a sixth transistor T6, wherein the gate of the fifth transistor T5 is connected to the enable signal terminal EM, the first electrode is connected to the second power supply terminal VDD, and the second electrode is connected to the second node N2; the gate of the sixth transistor T6 is connected to the enable signal terminal EM, the first electrode is connected to the third node N3, and the second electrode is connected to the fourth node N4. The coupling circuit 6 may include: a third capacitor C3, and the third capacitor C3 is connected between the second power supply terminal VDD and the first node N1.

[0123] In this exemplary embodiment, Figure 6 As shown, the conduction level of the threshold compensation circuit 8 and the conduction level polarity of the data writing circuit 7 can be opposite; the threshold compensation circuit 8 can also be connected to the second gate drive signal terminal G2, and the threshold compensation circuit 8 is used to respond to the signal of the second gate drive signal terminal G2 to connect the first node N1 and the third node N3; wherein, the signal of the first gate drive signal terminal G1 and the signal of the second gate drive signal terminal G2 can have opposite polarities. The data writing circuit 7 may include: a fourth transistor T4, the gate of the fourth transistor T4 is connected to the first gate driving signal terminal G1, the first electrode is connected to the data signal terminal Vdata, and the second electrode is connected to the second node N2; the threshold compensation circuit 8 may include: a second transistor T2, the gate of the second transistor T2 is connected to the second gate driving signal terminal G2, the first electrode is connected to the first node N1, and the second electrode is connected to the third node N3; wherein the fourth transistor T4 may be a P-type transistor, for example, the fourth transistor T4 may be a P-type low temperature polycrystalline silicon transistor, and the low temperature polycrystalline silicon transistor has a higher carrier mobility, thereby improving the response speed of the fourth transistor T4; the second transistor T2 may be an N-type transistor, for example, the second transistor T2 may be an oxide transistor, and the semiconductor material of the second transistor T2 may be indium gallium zinc oxide. Setting the second transistor T2 as an oxide transistor can reduce the leakage current of the pixel driving circuit through the second transistor at the first light emitting node N1.

[0124] It should be understood that in other exemplary embodiments, the fourth transistor T4 and the second transistor T2 may also be N-type transistors or P-type transistors, and accordingly, the fourth transistor T4 and the second transistor T2 may also share the same gate drive signal terminal.

[0125] In this exemplary embodiment, Figure 6As shown, the third reset circuit 4 can also be connected to the third reset signal terminal Re3, and the third reset circuit 4 can be used to transmit the signal of the second initial signal terminal Vinit2 to the fourth node N4 in response to the signal of the third reset signal terminal Re3. The third reset circuit 4 can include: a seventh transistor T7, the gate of the seventh transistor T7 is connected to the third reset signal terminal Re3, the first electrode is connected to the second initial signal terminal Vinit2, and the second electrode is connected to the fourth node N4. The seventh transistor T7 can be a P-type transistor, for example, the seventh transistor T7 can be a P-type low-temperature polycrystalline silicon transistor, and the low-temperature polycrystalline silicon transistor has a higher carrier mobility, so that the seventh transistor T7 has a faster response speed.

[0126] In this exemplary embodiment, Figure 6 As shown, the first electrode of the eighth transistor T8 and the first electrode of the fifth transistor T5 are connected to different power supply terminals respectively. It should be understood that in other exemplary embodiments, such as Figure 7 As shown, it is a structural diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure, the first electrode of the eighth transistor T8 and the first electrode of the fifth transistor T5 can be connected to the same power supply terminal, that is, the second power supply terminal VDD can share the first power supply terminal VGH.

[0127] like Figure 8 As shown, Figure 7A timing diagram of each node in a driving method of a pixel driving circuit, wherein G1 represents the timing of the first gate driving signal terminal, G2 represents the timing of the second gate driving signal terminal, Re1 represents the timing of the first reset signal terminal, Re3 represents the timing of the third reset signal terminal, and EM represents the timing of the enable signal terminal. The pixel driving circuit driving method may include four stages: reset stage t1, threshold compensation stage t2, buffer stage t3, and light-emitting stage t4. In the reset stage t1: the enable signal terminal EM, the first reset signal terminal Re1, and the first gate driving signal terminal output high-level signals, the second gate driving signal terminal G2 and the third reset signal terminal Re3 output low-level signals, the first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned on, the first initial signal terminal Vinit1 inputs the first initial signal to the first node N1, the first power supply terminal VDD inputs the power supply signal to the second node N2, and the second initial signal terminal Vinit2 inputs the second initial signal to the fourth node, wherein the voltages of the first initial signal and the second initial signal may be the same or different. In the threshold compensation stage t2: the enable signal terminal EM, the second gate drive signal terminal G2, and the third reset signal terminal output high-level signals, the first reset signal terminal Re1 and the first gate drive signal terminal G1 output low-level signals, the second transistor T2 and the fourth transistor T4 are turned on, and the data signal terminal Vdata writes the compensation voltage Vdata+Vth to the first node N1, where Vdata is the voltage of the data signal terminal and Vth is the threshold voltage of the driving transistor. In the buffer stage t3: the enable signal terminal EM, the third reset signal terminal Re3, and the first gate drive signal terminal G1 output high-level signals, the second gate drive signal terminal G2 and the first reset signal terminal Re1 output low-level signals, and all transistors are turned off. In the light-emitting stage t4: the third reset signal terminal Re3 and the first gate drive signal terminal G1 output high-level signals, the enable signal terminal EM, the second gate drive signal terminal G2, and the first reset signal terminal Re1 output low-level signals, the fifth transistor T5 and the sixth transistor T6 are turned on, and the driving transistor T3 emits light under the action of the voltage Vdata+Vth stored in the third capacitor C3. It should be understood that in other exemplary embodiments, the driving method may not include a buffering stage; the first transistor T1 and the seventh transistor T7 may also be turned on at different stages. In the threshold compensation stage t2, the effective level (low level) duration of the first gate drive signal terminal G1 may be less than the effective level (high level) duration of the second gate drive signal terminal G2. In the threshold compensation stage t2, the first gate drive signal terminal G1 may scan a row of pixel drive circuits, and the second gate drive signal terminal G2 may scan multiple rows of pixel drive circuits, such as two rows of pixel drive circuits, row by row.

[0128] like Fig. 9 As shown, Figure 7 The pixel driving circuit in Figure 8 The simulation timing diagrams of the first node, the second node, and the third node in the driving method shown in the figure, N1 represents the timing diagram of the first node N1, N2 represents the timing diagram of the second node N2, and N3 represents the timing diagram of the third node N3, wherein, Fig. 9 Specifically shows Figure 7 The timing diagram of each node of the pixel driving circuit shown in the figure under four data signals, Fig. 9 In the reset stage t1, the first node N1 under the four data signals needs to be reset. This exemplary embodiment is described with the timing of each node under two data signals. Fig. 9 As shown, under the first data signal, the timing of each node is shown as curve Vda1, and under the second data signal, the timing of each node is shown as curve Vda2. Fig. 9 As shown, since the voltages of the first data signal and the second data signal are different, before the reset stage t1, the voltages of the first node N1 are different, the voltages of the third node N3 are also different, and the voltages of the second nodes are both the voltages of the first power supply terminal VDD; in the reset stage t1, the voltages of the first node N1 under the two data signals are pulled down to the voltage of the first initial signal, and at the same time, the voltage of the second node N2 is also initialized to the voltage of the first power supply terminal VDD, so that at the end of the reset stage, the gate-source voltage difference of the driving transistor under the first data signal is equal to the gate-source voltage difference of the driving transistor under the second data signal, so that the pixel driving circuit can improve the afterimage problem caused by the different gate-source voltage differences of the driving transistor under different data signals.

[0129] This exemplary embodiment further provides a pixel driving circuit driving method, which is used to drive the above-mentioned pixel driving circuit, wherein the method includes:

[0130] In the reset phase, the first reset circuit 2 transmits the signal of the first initial signal terminal Vinit1 to the first node N1, and the second reset circuit 3 transmits the signal of the first power terminal VGH to the second node N2. The pixel driving method has been described in detail in the above content and will not be repeated here.

[0131] This exemplary embodiment also provides a display panel, which may include the above-mentioned pixel driving circuit, wherein the display panel may be applied to display devices such as mobile phones, tablet computers, and televisions.

[0132] like Figure 1 As shown, in the related art, there is a parasitic capacitance between the first node N1 and the gate drive signal terminal G1, such as Figure 2As shown, at the end of the threshold compensation stage t2, the signal of the gate drive signal terminal G1 changes from a high level to a low level. Under the action of the parasitic capacitance coupling, the voltage of the first node N1 is pulled down by the gate drive signal terminal G1, so that the maximum voltage of the data signal terminal cannot achieve the display of 0 gray scale (black screen), or in other words, if 0 gray scale needs to be displayed normally, the data signal terminal needs to provide a larger voltage signal.

[0133] Based on this, this exemplary embodiment provides a pixel driving circuit, such as Fig.10 As shown, it is a structural diagram of an exemplary embodiment of the pixel driving circuit of the present invention, wherein the pixel driving circuit may include: a driving transistor T3, a data writing circuit 7, a threshold compensation circuit 8, a first capacitor C1, and a second capacitor C2, wherein the gate of the driving transistor T3 is connected to the first node N1, the first electrode is connected to the second node N2, and the second electrode is connected to the third node N3; the data writing circuit 7 is connected to the second node N2 and the data signal terminal Vdata, and is used to respond to the signal of the first gate driving signal terminal G1 to transmit the signal of the data signal terminal Vdata to the second node N2; the threshold compensation circuit 8 is connected to the first node N1, the third node N3, and the second gate driving signal terminal G2, and is used to respond to the signal of the second gate driving signal terminal G2 to connect the first node N1 and the third node N3; the first capacitor C1 is connected between the first node N1 and the first gate driving signal terminal G1; the second capacitor C2 Connected between the first node N1 and the second gate drive signal terminal G2; wherein, the conduction level of the data writing circuit 7 is a low level, the conduction level of the threshold compensation circuit 8 is a high level, and the capacitance value of the first capacitor C1 is greater than the capacitance value of the second capacitor C2.

[0134] In this exemplary embodiment, in the threshold compensation stage, the first gate drive signal terminal G1 can output a low level signal, and the second gate drive signal terminal G2 can output a high level signal, so as to write the compensation voltage Vdata+Vth to the first node N1, where Vdata is the voltage of the data signal terminal and Vth is the threshold voltage of the driving transistor T3. After the threshold compensation stage, the signal of the first gate drive signal terminal G1 changes from a low level to a high level, and under the coupling effect of the first capacitor C1, the first node N1 is pulled up by the first gate drive signal terminal G1; the signal of the second gate drive signal terminal G2 changes from a high level to a low level, and under the coupling effect of the second capacitor C2, the first node N1 is pulled down by the second gate drive signal terminal G2. Since the capacitance value of the first capacitor C1 is greater than the capacitance value of the second capacitor C2, the first node N1 is pulled up as a whole. Therefore, the source drive circuit corresponding to the pixel drive circuit only needs to provide a small voltage signal to the data signal terminal to realize the extreme grayscale (minimum grayscale or maximum grayscale) display of the pixel drive circuit, that is, the display panel using the pixel drive circuit can have a small power consumption.

[0135] In this exemplary embodiment, the driving transistor T3 may be a P-type transistor, for example, the driving transistor may be a P-type low temperature polysilicon transistor. When the driving transistor T3 is a P-type transistor, the larger the voltage of the first node N1, the smaller the output current of the driving transistor T3, that is, the pixel driving circuit can reduce the data signal voltage output by the source driving circuit at grayscale 0. It should be understood that in other exemplary embodiments, the driving transistor T3 may also be an N-type transistor. When the driving transistor T3 is an N-type transistor, the larger the voltage of the first node N1, the larger the output current of the driving transistor T3, that is, the pixel driving circuit can reduce the data signal voltage output by the source driving circuit at the maximum grayscale.

[0136] In this exemplary embodiment, the capacitance value of the first capacitor C1 is C1, the capacitance value of the second capacitor C2 is C2, C1 / C2 may be greater than or equal to 1.5 and less than or equal to 4, for example, C1 / C2 may be 1.5, 2, 2.3, 2.5, 3, 3.5, 4. The larger the value of C1 / C2, the more obvious the effect of pulling up the first node N1.

[0137]

[0138] As shown in the above table, Vdata-L0 represents the voltage of the data signal required for each color sub-pixel at 0 grayscale, ΔV represents the difference between the maximum output voltage of the source driver circuit and the voltage of the maximum data signal required at 0 grayscale, wherein the maximum output voltage of the source driver circuit is 6.89 V. Among them, the multiple sets of data corresponding to C1 / C2 of 1.35, 1.73, 2.05, and 2.3 are multiple sets of data under the same design structure (except that C1 / C2 is different, other structures are the same), and the data corresponding to C1 / C2 of 2.2 is data under another design structure. According to the table, under the same design structure, the larger the C1 / C2, the more obvious the effect of the first node N1 being pulled up, so that the voltage of the data signal required at 0 grayscale is smaller.

[0139] In this exemplary embodiment, Fig.10 As shown, the data writing circuit 7 may include: a P-type fourth transistor T4, for example, the fourth transistor T4 may be a P-type low-temperature polycrystalline silicon transistor, the gate of the fourth transistor T4 is connected to the first gate drive signal terminal G1, the first electrode is connected to the second node N2, and the second electrode is connected to the data signal terminal Vdata; the threshold compensation circuit 8 may include: an N-type second transistor T2, for example, the second transistor T2 may be an N-type oxide transistor, the semiconductor material of the oxide transistor may be indium gallium zinc oxide, the gate of the second transistor T2 is connected to the second gate drive signal terminal G2, the first electrode is connected to the first node N1, and the second electrode is connected to the third node N3.

[0140] In this exemplary embodiment, Fig.11 As shown, it is a structural schematic diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure, and the pixel driving circuit may also include: a control circuit 5, a coupling circuit 6, the control circuit 5 may be connected to the second power supply terminal VDD, the second node N2, the third node N3, the fourth node N4, and the enable signal terminal EM, the control circuit 5 may be used to respond to the signal of the enable signal terminal EM to transmit the signal of the second power supply terminal VDD to the second node N2, and to respond to the signal of the enable signal terminal EM to connect the third node N3 and the fourth node N4; the coupling circuit 6 may be connected between the first node N1 and the second power supply terminal VDD. It should be understood that in other exemplary embodiments, the control circuit 5 may also be used to respond to the signal of the enable signal terminal EM to transmit the signal of the second power supply terminal VDD to the third node N3, and to respond to the signal of the enable signal terminal EM to connect the second node N2 and the fourth node N4.

[0141] In this exemplary embodiment, Fig.11As shown, the pixel driving circuit may further include: a first reset circuit 2, which may be connected to the first node N1, the first initial signal terminal Vinit1, and the first reset signal terminal Re1, and the first reset circuit 2 may be used to transmit the signal of the first initial signal terminal Vinit1 to the first node N1 in response to the signal of the first reset signal terminal Re1.

[0142] In this exemplary embodiment, Fig.11 As shown, the fourth node N4 can be used to connect a light-emitting unit OLED, and the pixel driving circuit can also include: a third reset circuit 4, the third reset circuit 4 is connected to the fourth node N4, the second initial signal terminal Vinit2, and the third reset signal terminal Re3, and the third reset circuit 4 can be used to respond to the signal of the third reset signal terminal Re3 and transmit the signal of the second initial signal terminal Vinit2 to the fourth node N4. The other end of the light-emitting unit OLED can be connected to the third power supply terminal VSS, and the light-emitting unit OLED can be a light-emitting diode. Writing the initial signal to the fourth node N4 can eliminate the carriers that are not recombined on the light-emitting interface inside the light-emitting diode, and alleviate the aging of the light-emitting diode.

[0143] In this exemplary embodiment, Fig.11As shown, the coupling circuit 6 may include: a third capacitor C3, the third capacitor C3 is connected between the first node N1 and the second power supply terminal VDD; wherein the capacitance value of the third capacitor C3 may be greater than the capacitance value of the first capacitor C1, and the capacitance value of the third capacitor C3 may be greater than the capacitance value of the second capacitor C2. Setting the third capacitor C3 to a larger capacitance value can increase the storage charge capacity of the third capacitor C3, thereby increasing the maximum duration of the light-emitting stage. The control circuit 5 may include: a fifth transistor T5 and a sixth transistor T6, the gate of the fifth transistor T5 is connected to the enable signal terminal EM, the first electrode is connected to the second power supply terminal VDD, and the second electrode is connected to the second node N2; the gate of the sixth transistor T6 is connected to the enable signal terminal EM, the first electrode is connected to the third node N3, and the second electrode is connected to the fourth node N4. The first reset circuit 2 may include: a first transistor T1, the gate of the first transistor T1 is connected to the first reset signal terminal Re1, the first electrode is connected to the first initial signal terminal Vinit1, and the second electrode is connected to the first node N1; the third reset circuit 4 may include: a seventh transistor T7, the gate of the seventh transistor T7 is connected to the third reset signal terminal Re3, the first electrode is connected to the second initial signal terminal Vinit2, and the second electrode is connected to the fourth node N4. Wherein, the first transistor T1 and the second transistor T2 may be N-type transistors, the semiconductor material of the N-type transistor may be indium gallium zinc oxide, and the oxide transistor has a small off leakage current, so that the leakage current of the first node N1 through the first transistor T1 and the second transistor T2 in the light-emitting stage can be reduced. The fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors, for example, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type low-temperature polycrystalline silicon transistors, and the low-temperature polycrystalline silicon transistors have a high carrier mobility, which is conducive to realizing a display panel with high resolution, high response speed, high pixel density, and high aperture ratio.

[0144] like Fig.12As shown, it is a structural schematic diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure. The pixel driving circuit may further include: a second reset circuit 3, the second reset circuit 3 may be connected to the second node N2 and the first power supply terminal VGH, and the second reset circuit 3 may be used to transmit the signal of the first power supply terminal VGH to the second node N2 in response to a control signal. In this exemplary embodiment, the conduction level of the first reset circuit and the conduction level of the third reset circuit may have opposite polarities, the signal of the first reset signal terminal Re1 and the third reset signal terminal Re3 may have opposite polarities, and the conduction level of the second reset circuit 3 and the conduction level of the first reset circuit 2 may have opposite polarities; the second reset circuit 3 may also be connected to the third reset signal terminal Re3, and the second reset circuit 3 may be used to transmit the signal of the first power supply terminal VGH to the second node N2 in response to the signal of the third reset signal terminal Re3.

[0145] In this exemplary embodiment, there is a parasitic capacitance between the gate and source of the driving transistor in the pixel driving circuit. In the reset phase of the pixel driving circuit, the gate voltage of the driving transistor is initialized to the initial voltage. Under the above-mentioned parasitic capacitance coupling, the source voltage of the driving transistor also changes accordingly. When resetting different grayscales in the reset phase, the change amount of the gate voltage of the driving transistor is different, so the change amount of the source voltage of the driving transistor is also different, which leads to different Vgs (gate-source voltage difference) of the driving transistor after the reset phase is completed. At the same time, since the Vgs of the driving transistor will affect its threshold voltage, the display panel will have an afterimage problem. For example, when the display panel changes from a black and white picture to the same grayscale picture, since the threshold voltage of the driving transistor in the corresponding pixel point of the black and white picture is different, after the change to the same grayscale picture, the area where the previous frame of the black and white picture is located will display different grayscales, that is, the afterimage problem occurs. In this exemplary embodiment, the pixel driving circuit can use the first reset circuit 2 to transmit the signal of the first initial signal terminal Vinit1 to the first node N1 during the reset stage, and at the same time, use the second reset circuit 3 to transmit the signal of the first power supply terminal VGH to the second node N2, so that under different data signals, the pixel driving circuit can reset the gate-source voltage difference of the driving transistor to the same value, thereby improving the problem of afterimage of the display panel.

[0146] In this exemplary embodiment, the second reset circuit 3 may include: an eighth transistor T8, the gate of the eighth transistor T8 is connected to the third reset signal terminal Re3, the first electrode is connected to the first power supply terminal VGH, and the second electrode is connected to the second node N2; wherein the eighth transistor T8 may be a P-type transistor. It should be understood that in other exemplary embodiments, the conduction level of the second reset circuit may be the same as the conduction level polarity of the first reset circuit, the second reset circuit may be connected to the first reset signal terminal, and the second reset circuit may be used to transmit the signal of the first power supply terminal VGH to the second node in response to the signal of the first reset signal terminal. Accordingly, the eighth transistor may be an N-type transistor, and the semiconductor material of the N-type transistor may be indium gallium zinc oxide. The first power supply terminal VGH may also share the second power supply terminal VDD, for example, the second reset circuit may be connected to the second power supply terminal VDD.

[0147] like Fig.13 As shown, Fig.12A timing diagram of each node in a driving method of a pixel driving circuit. Among them, G1 represents the timing of the first gate driving signal terminal, G2 represents the timing of the second gate driving signal terminal, Re1 represents the timing of the first reset signal terminal, Re3 represents the timing of the third reset signal terminal, and EM represents the timing of the enable signal terminal. The pixel driving circuit driving method may include four stages: reset stage t1, threshold compensation stage t2, buffer stage t3, and light-emitting stage t4. Among them, in the reset stage t1: the enable signal terminal EM, the first reset signal terminal Re1, and the first gate driving signal terminal output high-level signals, the second gate driving signal terminal G2 and the third reset signal terminal Re3 output low-level signals, the first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned on, the first initial signal terminal Vinit1 inputs the first initial signal to the first node N1, the first power supply terminal VDD inputs the power supply signal to the second node N2, and the second initial signal terminal Vinit2 inputs the second initial signal to the fourth node, wherein the voltages of the first initial signal and the second initial signal may be the same or different. In the threshold compensation stage t2: the enable signal terminal EM, the second gate drive signal terminal G2, and the third reset signal terminal output high-level signals, the first reset signal terminal Re1 outputs a low-level signal, the first gate drive signal terminal G1 outputs a low-level signal during at least part of the threshold compensation stage t2, the second transistor T2 and the fourth transistor T4 are turned on, and the data signal terminal Vdata writes a compensation voltage Vdata+Vth to the first node N1, where Vdata is the voltage of the data signal terminal and Vth is the threshold voltage of the driving transistor. In the buffer stage t3: the enable signal terminal EM, the third reset signal terminal Re3, and the first gate drive signal terminal G1 output high-level signals, the second gate drive signal terminal G2 and the first reset signal terminal Re1 output low-level signals, and all transistors are turned off. In the light-emitting stage t4: the third reset signal terminal Re3 and the first gate drive signal terminal G1 output high-level signals, the enable signal terminal EM, the second gate drive signal terminal G2, and the first reset signal terminal Re1 output low-level signals, the fifth transistor T5 and the sixth transistor T6 are turned on, and the driving transistor T3 emits light under the action of the voltage Vdata+Vth stored in the capacitor C. In this exemplary embodiment, in the threshold compensation stage t2, the effective level (low level) duration of the first gate drive signal terminal G1 can be less than the effective level (high level) duration of the second gate drive signal terminal G2. In this threshold compensation stage t2, the first gate drive signal terminal G1 can scan a row of pixel drive circuits, and the second gate drive signal terminal G2 can scan multiple rows of pixel drive circuits row by row. For example, the second gate drive signal terminal G2 can scan two rows of pixel drive circuits row by row. It should be understood that in other exemplary embodiments, the driving method may not include a buffer stage; the first transistor T1 and the seventh transistor T7 may also be turned on at different stages.The effective level (low level) duration of the first gate driving signal terminal G1 may also be equal to the effective level (high level) duration of the second gate driving signal terminal G2.

[0148] like Fig.14 As shown, it is a structural schematic diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure, the pixel driving circuit may also include a fourth capacitor C4, the first electrode of the fourth capacitor C4 may be connected to the second node N2, the second power supply terminal VDD may charge the fourth capacitor C4 in the light-emitting stage of the pixel driving circuit, and at the beginning of the reset stage, the fourth capacitor C4 may maintain the high level of the second node N2, so that the setting may speed up the speed of writing the high-level signal from the first power supply terminal VGH to the second node N2 in the reset stage. The second electrode of the fourth capacitor C4 may be connected to the fifth node N5, and when the equipotential conductive part of the fifth node N5 has a pull-down action before the threshold compensation stage or in the starting stage, the fifth node N5 will have a pull-down effect on the second node N2, thereby causing the second node N2 voltage at different positions of the display panel to be different. For example, the equipotential conductive part of the fifth node N5 can be a first gate line for providing the first gate drive signal terminal G1, and the first gate line can overlap with the equipotential conductive part of the second node N2, so that the partial structure of the first gate line can be used to form the second electrode of the fourth capacitor C4, and the first gate line changes from a high level to a low level at the beginning of the threshold compensation stage, so that the first gate line can pull down the voltage of the second node N2. This exemplary embodiment can minimize the overlapping area of ​​the equipotential conductive part of the second node N2 and the first gate line to reduce the pull-down effect of the first gate line on the second node N2. Among them, the capacitance value C4 of the fourth capacitor C4 can be less than the capacitance value of the second capacitor C2, and the fourth capacitor C4 can be 0.5fF-4fF, for example, 0.5fF, 2fF, 4fF. The capacitance value C4 of the fourth capacitor C4 can also be less than half of the capacitance value of the first capacitor C1, for example, the capacitance value C4 of the fourth capacitor C4 can be 1 / 3, 1 / 4, 1 / 5, etc. of the capacitance value of the first capacitor C1.

[0149] In this exemplary embodiment, Fig.12 , 14As shown, the pixel driving circuit needs to turn on the driving transistor T3 in the threshold compensation stage. Therefore, the voltage difference Vinit1-Vgh between the first initial signal terminal Vinit1 and the first power supply terminal VGH needs to be less than the threshold voltage Vth of the driving transistor T3, wherein Vinit1 is the voltage of the first initial signal terminal, and Vgh is the voltage of the first power supply terminal VGH. Wherein, Vinit1 can be -2 to -6V, for example, -2V, -3V, -4V, -5V, -6V, etc. Vinit1-Vgh can be less than a*Vth, a can be 2 to 7, for example, a can be 2, 4, 6, 7; Vth can be -2 to -5V, for example, -2V, -3V, -5V, etc. Vgh can be greater than 1.5 times of Vth, for example, Vgh can be 1.6 times, 1.8 times, 2 times, etc. of Vth.

[0150] like Fig.15 , which is a distribution diagram of a pixel driving circuit in an exemplary embodiment of the display panel of the present disclosure. Two adjacent columns of pixel circuits can be connected to a first power line VGH extending in the same column direction, and the first power line VGH is used to provide a first power terminal to the pixel driving circuit, and the first power line VGH can be located between the two adjacent columns of pixel driving circuits. Fig.15 As shown, in the same pixel row, two pixel circuits in adjacent columns can be mirrored to facilitate wiring.

[0151] like Fig.16 , which is a distribution diagram of the pixel driving circuit in another exemplary embodiment of the display panel disclosed in the present invention. Two adjacent rows of pixel circuits can be connected to a first power line VGH extending in the same row direction, and the first power line VGH is used to provide a first power terminal to the pixel driving circuit, and the first power line VGH can be located between the two adjacent rows of pixel driving circuits. Fig.16 As shown, in the same pixel row, two pixel circuits in adjacent columns can be mirrored to facilitate wiring.

[0152] like Fig.17 As shown in FIG. 1 , a distribution diagram of a pixel driving circuit in another exemplary embodiment of a display panel of the present disclosure is shown. The display panel may include a plurality of pixel driving circuits P distributed in an array, a plurality of first power lines VGH11, VGH12, VGH21, and VGH22, and the first power lines VGH11, VGH12, VGH21, and VGH22 may all be used to provide a first power terminal. Fig.17As shown, the first power lines VGH11 and VGH12 extend in the column direction, the first power lines VGH21 and VGH22 extend in the row direction, two adjacent rows of pixel circuits can be connected to the first power line extending in the same row direction, the first power line VGH can be located between the above two adjacent rows of pixel driving circuits, and the first power line extending in the column direction can be connected to and intersect with multiple first power lines extending in the row direction, so that multiple power lines can form a grid structure. Among them, the first power line extending in the column direction can be located in the area where the red pixel driving circuit is located. In addition, in the same pixel row, two pixel circuits in adjacent columns can be mirrored to facilitate wiring.

[0153] This exemplary embodiment also provides a pixel driving circuit driving method, which is used to drive the above-mentioned pixel driving circuit, and includes:

[0154] In the reset stage, a high level signal is input to the enable signal terminal EM, the first reset signal terminal Re1, and the first gate drive signal terminal G1, and a low level signal is input to the second gate drive signal terminal G2 and the third reset signal terminal Re3;

[0155] In the threshold compensation stage: a high level signal is input to the enable signal terminal EM, the second gate drive signal terminal G2, and the third reset signal terminal Re3, and a low level signal is input to the first reset signal terminal Re1 and the first gate drive signal terminal G1;

[0156] In the light emitting stage: a high level signal is input to the third reset signal terminal Re3 and the first gate drive signal terminal G1, and a low level signal is input to the enable signal terminal EM, the second gate drive signal terminal G2 and the first reset signal terminal Re1.

[0157] The driving method has been described in detail in the above content and will not be repeated here.

[0158] This exemplary embodiment also provides a display panel, wherein the display panel may include the above-mentioned pixel driving circuit. The display panel may be applied to display devices such as mobile phones, tablet computers, and televisions. The pixel driving circuit in the display panel may be as follows: Fig.10 As shown, the display panel may include a base substrate, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, and a fourth conductive layer stacked in sequence, wherein an insulating layer may be disposed between the above-mentioned hierarchical structures. Figure 18-25 As shown, Fig.18 This is a partial structural diagram of an exemplary embodiment of the display panel disclosed in the present invention. Fig.19 for Fig.18 The structural layout of the first conductive layer in Fig. 20 for Fig.18 The structural layout of the second conductive layer in Fig.21 for Fig.18 The structural layout of the second active layer, Fig. 22 for Fig.18 The structural layout of the third conductive layer in Fig.23 for Fig.18 The structural layout of the fourth conductive layer in Fig.24 for Fig.18 The structural layout of the first conductive layer, the second conductive layer, and the second active layer, Fig.25 for Fig.18 The structural layout of the first conductive layer, the second conductive layer, the second active layer and the third conductive layer.

[0159] like Fig.18 , 19 As shown in FIG. 24 , the first conductive layer may include a first conductive portion 11 and the first gate line G1. The first conductive portion 11 may be used to form a gate of the driving transistor T3. The orthographic projection of the first gate line G1 on the substrate may extend along the first direction X. The first gate line G1 may be connected to a gate of the fourth transistor T4. For example, a partial structure of the first gate line G1 may be used to form a gate of the fourth transistor.

[0160] like Fig.18 , 20 As shown in FIG. 24 , the second conductive layer may include the second gate line 2G2, the orthographic projection of the second gate line 2G2 on the substrate may extend along the first direction X, and the second gate line 2G2 may be connected to the gate of the second transistor. For example, a partial structure of the second gate line 2G2 may be used to form a bottom gate of the second transistor.

[0161] like Fig.18 , 21 24, the second active layer may include a first active portion 71, a second active portion 72, and a third active portion 73, the second active portion 72 is connected between the first active portion 71 and the third active portion 73, the first active portion 71 may be used to form a channel region of the second transistor T2, and the orthographic projection of the second gate line 2G2 on the base substrate may cover the orthographic projection of the first active portion 71 on the base substrate. The material of the second active layer may be indium gallium zinc oxide.

[0162] like Fig.18 , 22As shown in Figures 25, the third conductive layer may include the third gate line 3G2, the orthographic projection of the third gate line 3G2 on the substrate may extend along the first direction X, the orthographic projection of the third gate line 3G2 on the substrate may cover the orthographic projection of the first active portion 71 on the substrate, and a partial structure of the third gate line 3G2 may be used to form the top gate of the second transistor. The display panel may use the third conductive portion as a mask to perform conductor processing on the second active layer, that is, the area of ​​the second active layer covered by the third conductive layer forms the channel area of ​​the transistor, and the area of ​​the second active layer not covered by the third conductive layer forms a conductor structure.

[0163] like Fig.18 , 23 As shown, the fourth conductive layer may include a connecting portion 41 , and the connecting portion 41 may be connected to the first conductive portion 11 through a via hole H1 , and connected to the third active portion 73 through a via hole H2 .

[0164] like Fig.26 As shown, Fig.18 In the partial cross-sectional view along the dotted line A in FIG. 1 , the display panel may further include a first insulating layer 92, a second insulating layer 93, a third insulating layer 94, and a dielectric layer 95, wherein the substrate 91, the first conductive layer, the first insulating layer 92, the second conductive layer, the second insulating layer 93, the second active layer, the third insulating layer 94, the third conductive layer, the dielectric layer 95, and the fourth conductive layer are stacked in sequence. The first insulating layer 92, the second insulating layer 93, and the third insulating layer 94 may include a silicon oxide layer. The dielectric layer 95 may include a silicon nitride layer. The material of the fourth conductive layer may include a metal material, for example, molybdenum, aluminum, copper, titanium, niobium, one of them or an alloy, or a molybdenum / titanium alloy or a laminate, or may be a titanium / aluminum / titanium laminate. The materials of the first conductive layer, the second conductive layer, and the third conductive layer may be molybdenum, aluminum, copper, titanium, niobium, one of them or an alloy, or a molybdenum / titanium alloy or a laminate, or may be a titanium / aluminum / titanium laminate.

[0165] like Figure 18-26As shown, the first gate line G1 may include a first extension portion G11, the orthographic projection of the first extension portion G11 on the substrate may coincide with the orthographic projection of the third active portion 73 on the substrate, the first extension portion G11 may be used to form a first electrode of the first capacitor C1, and the third active portion 73 may be used to form a second electrode of the first capacitor C1. The second gate line 2G2 may include a second extension portion 2G22, the orthographic projection of the second extension portion 2G22 on the substrate may coincide with the orthographic projection of the second active portion 72 on the substrate, and the orthographic projection of the third gate line 3G2 on the substrate is located on one side of the orthographic projection of the second active portion 72 on the substrate, that is, the orthographic projection of the third gate line 3G2 on the substrate does not overlap with the orthographic projection of the second active portion 72 on the substrate, for example, as Fig.18As shown, the orthographic projection of the third gate line 3G2 on the substrate may be located on one side of the orthographic projection of the second active portion 72 on the substrate in the second direction Y, and the second direction Y may intersect with the first direction X, for example, the second direction Y may be perpendicular to the first direction X. The second extension portion 2G22 may be used to form a portion of the first electrode of the second capacitor C2, and the second active portion 72 may be used to form a portion of the second electrode of the second capacitor C2; the third gate line 3G2 may include a third extension portion 3G23, and the connecting portion 41 may include a fourth extension portion 414, the orthographic projection of the third extension portion 3G23 on the substrate may overlap with the orthographic projection of the fourth extension portion 414 on the substrate, the third extension portion 3G23 may be used to form a portion of the first electrode of the second capacitor C2, and the fourth extension portion 414 may be used to form a portion of the second electrode of the second capacitor C2. The size of the orthographic projection of the third active portion 73 on the substrate in the first direction X may be greater than the size of the orthographic projection of the second active portion 72 on the substrate in the first direction X. This setting may increase the capacitance value of the first capacitor C1. In this exemplary embodiment, the capacitance value of the first capacitor may be adjusted by adjusting the size of the orthographic projection of the third active portion 73 on the substrate in the first direction X. The size of the orthographic projection of the third active portion 73 on the substrate in the first direction X may be 5um-20um, for example, 5um, 9.7um, 12um, 15.55um, 50um. In addition, in this exemplary embodiment, the capacitance value of the first capacitor C1 may be adjusted by adjusting the thickness of the first insulating layer 92 and the second insulating layer 93 at the third active portion 73. For example, in this exemplary embodiment, the thickness of the first insulating layer 92 and / or the second insulating layer 93 at the third active portion 73 may be thinned to increase the capacitance value of the first capacitor C1. This exemplary embodiment can also adjust the capacitance value of the second capacitor by adjusting the size of the orthogonal projection of the fourth extension portion 414 on the substrate substrate in the first direction X. The smaller the size of the orthogonal projection of the fourth extension portion 414 on the substrate substrate in the first direction X, the smaller the capacitance value of the second capacitor. The size of the orthogonal projection of the fourth extension portion 414 on the substrate substrate in the first direction can be 2um-4um, for example, 4um, 3.7um, 3.5um, 2.95um, 2.2um, 2um. In addition, this exemplary embodiment can also adjust the capacitance value of the second capacitor by adjusting the size of the orthogonal projection of the second extension portion 2G22 on the substrate substrate in the second direction Y. The smaller the size of the orthogonal projection of the second extension portion 2G22 on the substrate substrate in the second direction Y, the smaller the capacitance value of the second capacitor.

[0166] It should be noted that if Fig.18 ,26 As shown, in the region where the fourth extension portion 414 is located, the orthographic projection of the third gate line 3G2 on the substrate substrate covers the orthographic projection of the second gate line 2G2 on the substrate substrate. Although the orthographic projection of the second gate line 2G2 on the substrate substrate in the region overlaps with the orthographic projection of the fourth extension portion 414 on the substrate substrate, due to the shielding effect of the third gate line 3G2, the area change of the orthographic projection of the second gate line 2G2 on the substrate substrate in the region does not affect the capacitance value of the second capacitor. Similarly, in the region where the first extension portion G11 is located, the orthographic projection of the third active portion 73 on the substrate substrate covers the orthographic projection of the connecting portion 41 on the substrate substrate. Although the orthographic projection of the connecting portion 41 on the substrate substrate in the region overlaps with the orthographic projection of the first extension portion G11 on the substrate substrate, due to the shielding effect of the third active portion 73, the area change of the orthographic projection of the connecting portion 41 on the substrate substrate in the region does not affect the capacitance value of the first capacitor.

[0167] like Figure 27-45 , which are illustrations of another set of exemplary embodiments of the pixel driving circuit disclosed in the present invention.

[0168] In the embodiments of the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0169] Those skilled in the art will appreciate that the transistors used in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics. In this specification, the first electrode may be a drain electrode, the second electrode may be a source electrode, or the first electrode may be a source electrode, and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0170] In this specification, "connection" includes the case where the components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0171] Fig. 27 and Fig.28 Schematic diagram of the structure of two pixel circuits according to exemplary embodiments of the present disclosure. Fig. 27 and Fig.28 As shown, the pixel circuit provided by the embodiment of the present disclosure includes: a driving subcircuit, a first reset subcircuit, a second reset subcircuit and a light-emitting element.

[0172] The driving sub-circuit is connected to the first node N1, the second node N2 and the third node N3 respectively, and is configured to generate a driving current between the second node N2 and the third node N3 in response to a control signal of the first node N1;

[0173] The first reset subcircuit is connected to the first reset signal line INIT1 and the anode terminal of the light emitting element respectively, and is also connected to the first light emitting control signal line EM1 or the second reset control signal line Reset2, and is configured to respond to the signal of the first light emitting control signal line EM1 or the second reset control signal line Reset2, and write the first reset signal provided by the first reset signal line INIT1 to the anode terminal of the light emitting element;

[0174] The second reset sub-circuit is respectively connected to the first reset control signal line Reset1 and the second reset signal line INIT2, and is also connected to the second node N2 or the third node N3, and is configured to respond to the signal of the first reset control signal line Reset1 and write the second reset signal provided by the second reset signal line INIT2 to the first pole or the second pole of the driving sub-circuit; the second reset signal is greater than the first reset signal.

[0175] In some exemplary embodiments, an absolute value of the second reset signal is greater than 1.5 times a threshold voltage of the driving sub-circuit.

[0176] In some exemplary embodiments, the amplitude of the second reset signal is greater than zero.

[0177] Exemplarily, the second reset signal is generally a reset voltage of 4 to 10V, the first reset signal is generally a reset voltage of -2V to -6V, the threshold voltage of the driving subcircuit is generally -5V to -2V, and optionally, the threshold voltage of the driving subcircuit may be -3V.

[0178] In some exemplary embodiments, Fig. 27 and Fig.28 As shown, the pixel circuit further includes a writing subcircuit, a compensation subcircuit, a first light-emitting control subcircuit and a second light-emitting control subcircuit.

[0179] The writing subcircuit is connected to the second scanning signal line G2, the data signal line Data and the second node N2 respectively, and is configured to write the data signal of the data signal line Data into the second node N2 in response to the signal of the second scanning signal line G2.

[0180] The compensation sub-circuit is respectively connected to the first power line VDD, the first scan signal line G1, the first node N1 and the third node N3, and is configured to write the first reset signal or the second reset signal of the third node N3 into the first node N1 in response to the signal of the first scan signal line G1; and is also configured to compensate the first node N1 in response to the signal of the first scan signal line G1.

[0181] The first light emission control subcircuit is connected to the first light emission control signal line EM1, the first power line VDD and the second node N2 respectively, and is configured to provide a signal of the first power line VDD to the second node N2 in response to a signal of the first light emission control signal line EM1.

[0182] The second light-emitting control subcircuit is respectively connected to the second light-emitting control signal line EM2, the third node N3 and the fourth node N4, and is configured to write the first reset signal of the fourth node N4 into the third node N3 in response to the signal of the second light-emitting control signal line EM2; and is also configured to allow a driving current to pass between the third node N3 and the fourth node N4 in response to the signal of the second light-emitting control signal line EM2.

[0183] In some exemplary embodiments, when the second reset sub-circuit writes the second reset signal to the second node N2, the driving sub-circuit is further configured to write the second reset signal of the second node N2 to the third node N3 in response to the control signal of the first node N1.

[0184] In some exemplary embodiments, Fig. 27 and Fig.28 As shown, one end of the light emitting element is connected to the fourth node N4, and the other end of the light emitting element is connected to the second power line VSS.

[0185] In some exemplary embodiments, Fig.29 As shown, the first reset sub-circuit includes a first transistor T1.

[0186] Among them, the control electrode of the first transistor T1 is connected to the first light emitting control signal line EM1 or the second reset control signal line Reset2 (not shown in the figure), the first electrode of the first transistor T1 is connected to the first reset signal line INIT1, and the second electrode of the first transistor T1 is connected to the fourth node N4.

[0187] Fig.29An exemplary structure of the first reset sub-circuit is shown in FIG. Those skilled in the art will readily appreciate that the implementation of the first reset sub-circuit is not limited thereto, as long as its function can be achieved.

[0188] In some exemplary embodiments, Fig.30 As shown, the compensation sub-circuit includes a second transistor T2 and a first capacitor C1.

[0189] The control electrode of the second transistor T2 is connected to the first scanning signal line G1 , the first electrode of the second transistor T2 is connected to the third node N3 , and the second electrode of the second transistor T2 is connected to the first node N1 .

[0190] One end of the first capacitor C1 is connected to the first node N1 , and the other end of the first capacitor C1 is connected to the first power line VDD.

[0191] Fig.30 An exemplary structure of the compensation sub-circuit is shown in FIG. Those skilled in the art will readily appreciate that the implementation of the compensation sub-circuit is not limited thereto, as long as its function can be achieved.

[0192] In some exemplary embodiments, Fig.31 As shown, the driving sub-circuit includes a third transistor T3.

[0193] The control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.

[0194] Fig.31 An exemplary structure of the driving sub-circuit is shown in FIG. Those skilled in the art will readily appreciate that the implementation of the driving sub-circuit is not limited thereto, as long as its function can be achieved.

[0195] In some exemplary embodiments, Fig.32 As shown, the writing sub-circuit includes a fourth transistor T4.

[0196] The control electrode of the fourth transistor T4 is connected to the second scan signal line G2, the first electrode of the fourth transistor T4 is connected to the data signal line Data, and the second electrode of the fourth transistor T4 is connected to the second node N2.

[0197] Fig.32 An exemplary structure of the writing sub-circuit is shown in FIG. Those skilled in the art will readily appreciate that the implementation of the writing sub-circuit is not limited thereto, as long as its function can be achieved.

[0198] In some exemplary embodiments, Fig.33As shown, the first light emitting control subcircuit includes a fifth transistor T5.

[0199] The control electrode of the fifth transistor T5 is connected to the first light emitting control signal line EM1, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2.

[0200] Fig.33 An exemplary structure of the first light-emitting control subcircuit is shown in FIG. Those skilled in the art can easily understand that the implementation of the first light-emitting control subcircuit is not limited thereto, as long as its function can be achieved.

[0201] In some exemplary embodiments, Fig.34 As shown, the second light emitting control subcircuit includes a sixth transistor T6.

[0202] The control electrode of the sixth transistor T6 is connected to the second light emitting control signal line EM2, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0203] Fig.34 An exemplary structure of the second light emitting control subcircuit is shown in FIG. Those skilled in the art can easily understand that the implementation of the second light emitting control subcircuit is not limited thereto, as long as its function can be achieved.

[0204] In some exemplary embodiments, Fig.35 As shown, the second reset sub-circuit includes a seventh transistor T7.

[0205] The control electrode of the seventh transistor T7 is connected to the reset control signal line Reset, the first electrode of the seventh transistor T7 is connected to the second reset signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the second node N2.

[0206] In some exemplary embodiments, Fig.36 As shown, the second reset sub-circuit includes a seventh transistor T7.

[0207] The control electrode of the seventh transistor T7 is connected to the reset control signal line Reset, the first electrode of the seventh transistor T7 is connected to the second reset signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the third node N3.

[0208] Fig.35 and Fig.36 Two exemplary structures of the second reset subcircuit are shown in FIG. Those skilled in the art will readily appreciate that the implementation of the second reset subcircuit is not limited thereto, as long as its function can be achieved.

[0209] In some exemplary embodiments, Fig.37a or Fig.37b As shown, the first reset subcircuit includes a first transistor T1, the compensation subcircuit includes a second transistor T2 and a first capacitor C1, the driving subcircuit includes a third transistor T3, the writing subcircuit includes a fourth transistor T4, the first light-emitting control subcircuit includes a fifth transistor T5, the second light-emitting control subcircuit includes a sixth transistor T6, and the second reset subcircuit includes a seventh transistor T7.

[0210] The control electrode of the first transistor T1 is connected to the first light emitting control signal line EM1, the first electrode of the first transistor T1 is connected to the first reset signal line INIT1, and the second electrode of the first transistor T1 is connected to the fourth node N4.

[0211] A control electrode of the second transistor T2 is connected to the first scanning signal line G1 , a first electrode of the second transistor T2 is connected to the third node N3 , and a second electrode of the second transistor T2 is connected to the first node N1 .

[0212] One end of the first capacitor C1 is connected to the first node N1 , and the other end of the first capacitor C1 is connected to the first power line VDD.

[0213] A control electrode of the third transistor T3 is connected to the first node N1 , a first electrode of the third transistor T3 is connected to the second node N2 , and a second electrode of the third transistor T3 is connected to the third node N3 .

[0214] A control electrode of the fourth transistor T4 is connected to the second scan signal line G2 , a first electrode of the fourth transistor T4 is connected to the data signal line Data, and a second electrode of the fourth transistor T4 is connected to the second node N2 .

[0215] A control electrode of the fifth transistor T5 is connected to the first light emitting control signal line EM1 , a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2 .

[0216] A control electrode of the sixth transistor T6 is connected to the second light emitting control signal line EM2 , a first electrode of the sixth transistor T6 is connected to the third node N3 , and a second electrode of the sixth transistor T6 is connected to the fourth node N4 .

[0217] A control electrode of the seventh transistor T7 is connected to the first reset control signal line Reset1 , a first electrode of the seventh transistor T7 is connected to the second reset signal line INIT2 , and a second electrode of the seventh transistor T7 is connected to the second node N2 or the third node N3 .

[0218] Fig.37a and Fig.37b Two exemplary structures of a first reset subcircuit, a compensation subcircuit, a drive subcircuit, a write subcircuit, a first light-emitting control subcircuit, a second light-emitting control subcircuit, and a second reset subcircuit are shown. It is easy for a person skilled in the art to understand that the implementation of the above subcircuits is not limited to this, as long as their respective functions can be achieved. Since the number of transistors in the pixel circuit of the present disclosure is small, the pixel circuit occupies less space, thereby improving the pixel resolution of the display device.

[0219] In some exemplary embodiments, the second reset signal line INIT2 may be the same voltage line as at least one of the following: the first power line VDD, the first light-emitting control signal line EM1, the second light-emitting control signal line EM2, or a third power line, the third power line providing a third power supply voltage, and the third power supply voltage is greater than the first reset voltage provided by the first reset signal line INIT1.

[0220] In some exemplary embodiments, a pulse width of a signal of the reset control signal line Reset is substantially the same as a pulse width of a signal of the second scan signal line G2 .

[0221] In some exemplary embodiments, a signal pulse of the first light emitting control signal line EM1 differs from a signal pulse of the second light emitting control signal line EM2 by one or two time units h, where one time unit h is the time for scanning a row of sub-pixels.

[0222] In some exemplary embodiments, Fig.38a or Figure 38b As shown, the first reset subcircuit includes a first transistor T1, the compensation subcircuit includes a second transistor T2 and a first capacitor C1, the driving subcircuit includes a third transistor T3, the writing subcircuit includes a fourth transistor T4, the first light-emitting control subcircuit includes a fifth transistor T5, the second light-emitting control subcircuit includes a sixth transistor T6, and the second reset subcircuit includes a seventh transistor T7.

[0223] The control electrode of the first transistor T1 is connected to the second reset control signal line Reset2, the first electrode of the first transistor T1 is connected to the first reset signal line INIT1, and the second electrode of the first transistor T1 is connected to the fourth node N4.

[0224] A control electrode of the second transistor T2 is connected to the first scanning signal line G1 , a first electrode of the second transistor T2 is connected to the third node N3 , and a second electrode of the second transistor T2 is connected to the first node N1 .

[0225] One end of the first capacitor C1 is connected to the first node N1 , and the other end of the first capacitor C1 is connected to the first power line VDD.

[0226] A control electrode of the third transistor T3 is connected to the first node N1 , a first electrode of the third transistor T3 is connected to the second node N2 , and a second electrode of the third transistor T3 is connected to the third node N3 .

[0227] A control electrode of the fourth transistor T4 is connected to the second scan signal line G2 , a first electrode of the fourth transistor T4 is connected to the data signal line Data, and a second electrode of the fourth transistor T4 is connected to the second node N2 .

[0228] A control electrode of the fifth transistor T5 is connected to the first light emitting control signal line EM1 , a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2 .

[0229] A control electrode of the sixth transistor T6 is connected to the second light emitting control signal line EM2 , a first electrode of the sixth transistor T6 is connected to the third node N3 , and a second electrode of the sixth transistor T6 is connected to the fourth node N4 .

[0230] A control electrode of the seventh transistor T7 is connected to the first reset control signal line Reset1 , a first electrode of the seventh transistor T7 is connected to the second reset signal line INIT2 , and a second electrode of the seventh transistor T7 is connected to the second node N2 or the third node N3 .

[0231] Fig.38a and Figure 38b Two other exemplary structures of the first reset subcircuit, the compensation subcircuit, the drive subcircuit, the write subcircuit, the first light-emitting control subcircuit, the second light-emitting control subcircuit, and the second reset subcircuit are shown. It is easy for those skilled in the art to understand that the implementation of the above subcircuits is not limited to this, as long as their respective functions can be achieved.

[0232] In some exemplary embodiments, the light emitting element EL may be an organic light emitting diode (OLED), or may be a sub-millimeter light emitting diode (Mini Light Emitting Diodes), a micro light emitting diode (Micro Light Emitting Diodes), a quantum dot light emitting diode (Quantum-dot Light Emitting Diodes, QLED) and other types of light emitting diodes. In practical applications, the structure of the light emitting element EL needs to be designed and determined according to the actual application environment, and is not limited here. The following description is taken as an example that the light emitting element EL is an organic light emitting diode.

[0233] In some exemplary embodiments, at least one of the first transistor T1, the second transistor T2, and the seventh transistor T7 is a first type transistor, the first type transistor includes an N-type transistor or a P-type transistor, the third transistor T3 to the sixth transistor T6 are all second type transistors, the second type transistor includes a P-type transistor or an N-type transistor, and the second type transistor is different from the first type transistor in transistor type, that is, when the first type transistor is an N-type transistor, the second type transistor is a P-type transistor, and when the first type transistor is a P-type transistor, the second type transistor is an N-type transistor.

[0234] In some exemplary embodiments, Fig.37a and Fig.37b As shown, the first transistor T1 and the second transistor T2 are both N-type thin film transistors, and the third transistor T3 to the seventh transistor T7 are all P-type thin film transistors.

[0235] In some exemplary embodiments, the first transistor T1 , the second transistor T2 , and the seventh transistor T7 are all N-type thin film transistors, and the third transistor T3 to the sixth transistor T6 are all P-type thin film transistors.

[0236] In some exemplary embodiments, Fig.38a and Figure 38b As shown, the second transistor T2 is an N-type thin film transistor, and the first transistor T1 and the third transistor T3 to the seventh transistor T7 are all P-type thin film transistors.

[0237] In some exemplary embodiments, the N-type thin film transistor may be a low temperature polysilicon (LTPS) thin film transistor (TFT), and the P-type thin film transistor may be an indium gallium zinc oxide (IGZO) thin film transistor; or, the N-type thin film transistor may be an IGZO thin film transistor, and the P-type thin film transistor may be an LTPS thin film transistor.

[0238] In some exemplary embodiments, the first transistor T1 and the second transistor T2 are both IGZO thin film transistors, and the third transistor T3 to the seventh transistor T7 are all LTPS thin film transistors.

[0239] In the present embodiment, the indium gallium zinc oxide thin film transistor generates less leakage current than the low-temperature polysilicon thin film transistor. Therefore, setting the first transistor T1 and the second transistor T2 as indium gallium zinc oxide thin film transistors can significantly reduce the leakage of the control electrode of the driving transistor during the light-emitting stage, thereby improving the problem of low-frequency and low-brightness flickering of the display panel.

[0240] In some exemplary embodiments, the first transistor T1 , the second transistor T2 , and the seventh transistor T7 are all IGZO thin film transistors, and the third transistor T3 to the sixth transistor T6 are all LTPS thin film transistors.

[0241] In some exemplary embodiments, the second transistor T2 is an IGZO thin film transistor, and the first transistor T1 and the third transistor T3 to the seventh transistor T7 are all LTPS thin film transistors. In some exemplary embodiments, the first capacitor C1 may be a liquid crystal capacitor formed by a pixel electrode and a common electrode, or may be an equivalent capacitor formed by a liquid crystal capacitor formed by a pixel electrode and a common electrode and a storage capacitor, which is not limited in the present disclosure.

[0242] Fig.39 for Fig.37a or Fig.37b The following is an example of a pixel circuit provided in an embodiment of the present disclosure in which the first transistor T1 and the second transistor T2 are N-type transistors and the third transistor T3 to the seventh transistor T7 are all P-type transistors. Fig.39 The working timing diagram shown in FIG. 1 describes the working process of a pixel circuit in a frame period. Fig.37a As shown, the pixel circuit provided by the embodiment of the present disclosure includes 7 transistor units (T1-T7), 1 capacitor unit (C1) and 3 voltage lines (VDD, VSS, INIT1, since the second reset signal line INIT2 can be the same voltage line as the first power line VDD, the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2, the second reset signal line INIT2 is not counted in the above 3 voltage lines), wherein the first power line VDD continuously provides a high-level signal, the second power line VSS continuously provides a low-level signal, and the first reset signal line INIT1 provides a first reset voltage (initial voltage signal). Fig.39 As shown, its working process includes:

[0243] In the first stage t1, i.e., the reset stage, the first scanning signal line G1, the second scanning signal line G2, the first reset control signal line Reset1 and the first light-emitting control signal line EM1 are at a high level, and the second light-emitting control signal line EM2 is at a low level. The first light-emitting control signal line EM1 is at a high level, turning on the first transistor T1, and resetting the fourth node N4 (i.e., the anode end of the light-emitting element EL) to the first reset voltage of the first reset signal line INIT1. The second light-emitting control signal line EM2 is at a low level, turning on the sixth transistor T6; the first scanning signal line G1 is at a high level, turning on the second transistor T2, and resetting the first node N1 (i.e., the gate of the third transistor T3 and one end of the first capacitor C1) and the third node N3 to the first reset voltage of the first reset signal line INIT1. In this stage, the fourth transistor T4, the fifth transistor T5 and the seventh transistor T7 remain turned off. Fig.41 shown.

[0244] In the second stage t2, i.e., the reset stage, the first scanning signal line G1, the second scanning signal line G2, the first light control signal line EM1 and the second light control signal line EM2 are at high levels, the first reset control signal line Reset is at a low level, and the second light control signal line EM2 is at a high level, turning off the sixth transistor T6. The first reset control signal line Reset1 is at a low level, so that the seventh transistor T7 is turned on (this timing sequence is explained by taking the seventh transistor T7 as a P-type thin film transistor as an example. When the seventh transistor T7 is an N-type thin film transistor, the first reset control signal line Reset1 provides a high-level signal in the second stage t2 and provides a low-level signal in other stages), and the second node N2 is reset to a second reset voltage, wherein the second reset voltage can be a voltage signal provided by the first power line VDD, the first light-emitting control signal line EM1, the second light-emitting control signal line EM2 or the third power line, and the second reset voltage is greater than the first reset voltage. Since the first node N1 is the first reset voltage of the first reset signal line INIT1, the third transistor T3 is turned on, the first scanning signal line G1 is at a high level, the second transistor T2 is turned on, and the voltage of the second node N2 is transmitted to the first node N1 through the third transistor T3 and the second transistor T2. In this stage, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 remain turned off, such as Fig.42 shown.

[0245] In the third stage t3, i.e., the data writing stage, the first scanning signal line G1, the first reset control signal line Reset1, the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 are at a high level, and the second scanning signal line G2 is at a low level. At this time, the second scanning signal line G2 is at a low level, so that the fourth transistor T4 is turned on, and the data voltage signal Vdata output by the data signal line Data is provided to the first node N1 through the turned-on fourth transistor T4, the third transistor T3 and the second transistor T2, and the sum of the data voltage signal Vdata output by the data signal line Data and the threshold voltage Vth of the third transistor T3 is stored in the first capacitor C1. In this stage, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 remain turned off, as shown in FIG. Fig.43 shown.

[0246] In the fourth stage t4, i.e., the light-emitting stage, the second scanning signal line G2 and the first reset control signal line Reset1 are at high levels, and the first scanning signal line G1, the first light-emitting control signal line EM1, and the second light-emitting control signal line EM2 are at low levels. The first light-emitting control signal line EM1 is at a low level, so that the fifth transistor T5 is turned on and the first transistor T1 is turned off. The second light-emitting control signal line EM2 is at a low level, so that the sixth transistor T6 is turned on. The power supply voltage output by the first power supply line VDD provides a driving voltage to the fourth node N4 (i.e., the anode end of the light-emitting element EL) through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, so as to drive the light-emitting element EL to emit light. In this stage, the first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 remain turned off, as shown in FIG. Fig.44 shown.

[0247] Fig.40 for Fig.38a or Figure 38b The following is an example of a pixel circuit provided in an embodiment of the present disclosure in which the second transistor T2 is an N-type transistor, the first transistor T1 and the third transistor T3 to the seventh transistor T7 are all P-type transistors. Fig.38a The pixel circuit shown and Fig.40 The working timing diagram shown in FIG. 1 describes the working process of a pixel circuit in a frame period. Fig.38aAs shown, the pixel circuit provided by the embodiment of the present disclosure includes 7 transistor units (T1-T7), 1 capacitor unit (C1) and 3 voltage lines (VDD, VSS, INIT1, since the second reset signal line INIT2 can be the same voltage line as the first power line VDD, the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2, the second reset signal line INIT2 is not counted in the above 3 voltage lines), wherein the first power line VDD continuously provides a high-level signal, the second power line VSS continuously provides a low-level signal, and the first reset signal line INIT1 provides a first reset voltage (initial voltage signal). Fig.40 As shown, its working process includes:

[0248] In the first stage A1, i.e., the reset stage, the first scanning signal line G1, the second scanning signal line G2, the first reset control signal line Reset1 and the first light-emitting control signal line EM1 are at a high level, and the second reset control signal line Reset2 and the second light-emitting control signal line EM2 are at a low level. The first transistor T1, the sixth transistor T6 and the second transistor T2 are turned on, and the fourth node N4 (i.e., the anode end of the light-emitting element EL), the third node N3 and the first node N1 (i.e., the gate of the third transistor T3 and one end of the first capacitor C1) are reset to the first reset voltage of the first reset signal line INIT1. In this stage, the fourth transistor T4, the fifth transistor T5 and the seventh transistor T7 remain turned off.

[0249] In the second stage A2, i.e., the reset stage, the first scanning signal line G1, the second scanning signal line G2, the second reset control signal line Reset2, the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 are at high levels, the first reset control signal line Reset1 is at a low level, and the second light-emitting control signal line EM2 is at a high level, so that the sixth transistor T6 is turned off. The first reset control signal line Reset1 is at a low level, so that the seventh transistor T7 is turned on (this timing sequence is explained by taking the seventh transistor T7 as a P-type thin film transistor as an example. When the seventh transistor T7 is an N-type thin film transistor, the first reset control signal line Reset1 provides a high-level signal in the second stage A2 and provides a low-level signal in other stages), and the second node N2 is reset to a second reset voltage, wherein the second reset voltage can be a voltage signal provided by the first power line VDD, the first light-emitting control signal line EM1, the second light-emitting control signal line EM2 or the third power line, and the second reset voltage is greater than the first reset voltage. Since the first node N1 is the first reset voltage of the first reset signal line INIT1, the third transistor T3 is turned on, the first scanning signal line G1 is at a high level, the second transistor T2 is turned on, and the voltage of the second node N2 is transmitted to the first node N1 through the third transistor T3 and the second transistor T2. In this stage, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 remain turned off.

[0250] In the third stage A3, i.e., the data writing stage, the first scanning signal line G1, the second reset control signal line Reset2, the first reset control signal line Reset1, the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 are at a high level, and the second scanning signal line G2 is at a low level. At this time, the second scanning signal line G2 is at a low level, so that the fourth transistor T4 is turned on, and the data voltage signal Vdata output by the data signal line Data is provided to the first node N1 through the turned-on fourth transistor T4, the third transistor T3 and the second transistor T2, and the sum of the data voltage signal Vdata output by the data signal line Data and the threshold voltage Vth of the third transistor T3 is stored in the first capacitor C1. In this stage, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 remain turned off.

[0251] In the fourth stage A4, i.e., the light-emitting stage, the second scanning signal line G2, the second reset control signal line Reset2 and the first reset control signal line Reset1 are at a high level, and the first scanning signal line G1, the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 are at a low level. The first light-emitting control signal line EM1 is at a low level, so that the fifth transistor T5 is turned on, and the second reset control signal line Reset2 is at a high level. The first transistor T1 is turned off, the second light-emitting control signal line EM2 is at a low level, so that the sixth transistor T6 is turned on, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the fourth node N4 (i.e., the anode end of the light-emitting element EL) through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the light-emitting element EL to emit light. In this stage, the first transistor T1, the second transistor T2, the fourth transistor T4 and the seventh transistor T7 remain turned off.

[0252] During the pixel circuit driving process, the driving current flowing through the third transistor T3 (ie, the driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the first node N1 is Vdata+Vth, the driving current of the third transistor T3 is:

[0253] I=K*(Vgs-Vth)2=K*[(Vdata+Vth-Vdd)-Vth]2=K*[(Vdata-Vdd)]2

[0254] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting element EL, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the first power supply line VDD.

[0255] It can be seen from the above formula that the current I flowing through the light emitting element EL has nothing to do with the threshold voltage Vth of the third transistor T3, thereby eliminating the influence of the threshold voltage Vth of the third transistor T3 on the current I and ensuring the uniformity of brightness.

[0256] Since the response time of the LTPO (LTPS low-temperature polysilicon transistor + oxide oxide transistor) pixel circuit is relatively long, the brightness of the screen flickers when switching at low frequencies. The pixel circuit of the embodiment of the present disclosure improves hysteresis by adding a large bias voltage to the third transistor T3 (driving transistor) during the reset phase of the driving transistor, so that the brightness of the screen can be maintained during high-low frequency switching, reducing the risk of flicker.

[0257] In a column of sub-pixels, for at least two adjacent sub-pixels, the second light-emitting control signal line EM2 in the previous row of sub-pixels is electrically connected to the first light-emitting control signal line EM1 in the next row of sub-pixels, and the second scanning signal line G2 in the previous row of sub-pixels is electrically connected to the first reset control signal line Reset1 in the next row of sub-pixels.

[0258] The embodiment of the present disclosure also provides a method for driving a pixel circuit, which is used to drive the pixel circuit as described above, wherein the pixel circuit has multiple scanning cycles. In one scanning cycle, Fig.45 As shown, the driving method includes steps 100 to 400.

[0259] Wherein, step 100 includes: in the reset phase, the first reset subcircuit writes a first reset signal to the anode terminal (ie, the fourth node) of the light emitting element in response to a signal of the first light emitting control signal line or the second reset control signal line.

[0260] In some exemplary embodiments, step 100 also includes: the second light-emitting control subcircuit writes the first reset signal of the fourth node into the third node in response to the signal of the second light-emitting control signal line; and the compensation subcircuit writes the first reset signal of the third node into the first node in response to the signal of the first scanning signal line.

[0261] Step 200 includes: in the reset phase, the second reset subcircuit responds to the signal of the first reset control signal line to write a second reset signal to the first pole (ie, the second node) or the second pole (ie, the third node) of the driving subcircuit; the second reset signal is greater than the first reset signal.

[0262] In some exemplary embodiments, step 100 further includes: the compensation sub-circuit writes a second reset signal of the third node into the first node in response to a signal of the first scan signal line.

[0263] In some exemplary embodiments, the second reset signal may be a signal derived from a voltage line of at least one of the following: a first power line, a first light emission control signal line, a second light emission control signal line, or a third power line.

[0264] Step 300 includes: in the light emitting stage, the driving sub-circuit generates a driving current between the second node and the third node in response to the control signal of the first node.

[0265] In some exemplary embodiments, before step 300, the method further includes: in the data writing phase, the writing subcircuit writes the data signal to the second node in response to the signal of the second scanning signal line; and the compensation subcircuit compensates the first node in response to the signal of the first scanning signal line.

[0266] In some exemplary embodiments, step 300 also includes: in the light-emitting stage, the first light-emitting control subcircuit responds to the signal of the first light-emitting control signal line to provide the signal of the first power line to the second node; the second light-emitting control subcircuit responds to the signal of the second light-emitting control signal line to allow the driving current to pass between the third node and the fourth node.

[0267] The pixel circuit and driving method and display device of the disclosed embodiment respond to the signal of the first reset control signal line through the second reset subcircuit to write the second reset signal to the first pole or the second pole of the driving subcircuit, and increase the bias voltage of the driving subcircuit to improve the hysteresis, so that the brightness of the picture can be maintained when switching between high and low frequencies, the risk of screen flickering is reduced, and the display effect of the display device at high and low grayscales is improved. In addition, since the number of transistors in the pixel circuit of the disclosed embodiment is small, the pixel circuit occupies less space, thereby improving the pixel resolution of the display device.

[0268] There are a few points to note:

[0269] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0270] In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0271] like Figure 46-60 , which are illustrations of another set of exemplary embodiments of the pixel driving circuit disclosed in the present invention.

[0272] The transistors used in all embodiments of the present disclosure may be triodes, thin film transistors, field effect transistors or other devices with the same characteristics. In the embodiments of the present disclosure, in order to distinguish the two electrodes of the transistor except the control electrode, one of the electrodes is called the first electrode and the other is called the second electrode.

[0273] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0274] like Fig.46 As shown, the pixel circuit described in the embodiment of the present disclosure includes a driving circuit 11, a first control circuit 12, a compensation control circuit 13 and a first initialization circuit 14;

[0275] The first control circuit 12 is electrically connected to the first scan line S1, the control end of the drive circuit 11 and the connection node N0 respectively, and is used to control the connection between the control end of the drive circuit 11 and the connection node N0 under the control of the first scan signal provided by the first scan line S1;

[0276] The compensation control circuit 13 is electrically connected to the second scan line S2, the connection node N0 and the first end of the drive circuit 11 respectively, and is used to control the connection node N0 to be connected to the first end of the drive circuit 11 under the control of the second scan signal provided by the second scan line S2;

[0277] The first initialization circuit 14 is electrically connected to the initialization control line R1, the first initialization voltage line and the connection node N0 respectively, and is used to write the first initialization voltage Vi1 provided by the first initialization voltage line into the connection node N0 under the control of the initialization control signal provided by the initialization control line R1;

[0278] The driving circuit 11 is used to control the connection between the first end of the driving circuit 11 and the second end of the driving circuit 11 under the control of the potential of the control end thereof.

[0279] exist Fig.46 In at least one embodiment shown, the first node N1 is a node connected to the control terminal of the driving circuit 11 .

[0280] In the pixel circuit described in the embodiment of the present disclosure, the first control circuit 12 is directly electrically connected to the first node N1, and the first initialization circuit 14 and the compensation control circuit 13 are not directly electrically connected to the first node N1, so as to reduce the leakage path of the first node N1, so as to ensure the stability of the voltage of the first node during low-frequency operation, which is beneficial to improving display quality, improving display uniformity, and reducing Flicker.

[0281] This disclosure Fig.46 When the embodiment of the pixel circuit shown is in operation, the display cycle includes an initialization phase and a data writing phase; the driving method includes:

[0282] In the initialization stage, the first control circuit 12 controls the connection between the control end of the driving circuit 11 and the connection node N0 under the control of the first scanning signal, and the first initialization circuit 14 writes the first initialization voltage Vi1 into the connection node N0 under the control of the initialization control signal, thereby writing the first initialization voltage Vi1 into the control end of the driving circuit 11, so that the driving circuit 11 can control the connection between its first end and the second end of the driving circuit at the beginning of the data writing stage;

[0283] In the data writing stage, the first control circuit 12 controls the control end of the driving circuit 11 to be connected to the connection node N0 under the control of the first scanning signal, and the compensation control circuit 13 controls the connection node N0 to be connected to the first end of the driving circuit 11 under the control of the second scanning signal, so that the control end of the driving circuit 11 is connected to the first end of the driving circuit 11.

[0284] Optionally, the first control circuit includes a first transistor;

[0285] The control electrode of the first transistor is electrically connected to the first scan line, the first electrode of the first transistor is electrically connected to the control terminal of the driving circuit, and the second electrode of the first transistor is electrically connected to the connection node;

[0286] The first control transistor is an oxide thin film transistor.

[0287] In at least one embodiment of the present disclosure, the first transistor included in the control circuit is an oxide thin film transistor.

[0288] Oxide transistors have good hysteresis characteristics, low leakage current, and low mobility. Therefore, at least one embodiment of the present disclosure sets the first transistor as an oxide thin film transistor to achieve low leakage current and ensure the stability of the potential of the control terminal of the driving circuit.

[0289] Optionally, the compensation control circuit includes a second transistor;

[0290] The control electrode of the second transistor is electrically connected to the second scan line, the first electrode of the second transistor is electrically connected to the connection node, and the second electrode of the second transistor is electrically connected to the first end of the driving circuit.

[0291] In at least one embodiment of the present disclosure, the second transistor may be a low temperature polysilicon thin film transistor, but is not limited thereto. In a specific implementation, the second transistor may also be other types of transistors.

[0292] Optionally, the first initialization circuit includes a third transistor;

[0293] The control electrode of the third transistor is electrically connected to the initialization control line, the first electrode of the third transistor is electrically connected to the first initialization voltage line, and the second electrode of the third transistor is electrically connected to the connection node.

[0294] In at least one embodiment of the present disclosure, the third transistor is a low temperature polysilicon thin film transistor. In specific implementations, the third transistor may also be other types of transistors.

[0295] like Fig.47 As shown, in Fig.46 On the basis of the pixel circuit shown, the pixel circuit described in at least one embodiment of the present disclosure may further include a reset circuit 20;

[0296] The reset circuit 20 is electrically connected to the third scan line S3, the reset voltage line DR and the second end of the drive circuit 11 respectively, and is used to write the reset voltage provided by the reset voltage line DR into the second end of the drive circuit 11 under the control of the third scan signal provided by the third scan line S3.

[0297] This disclosure Fig.47 At least one embodiment of the pixel circuit shown is additionally provided with a reset circuit 20. Under the control of the third scanning signal, the reset circuit 20 writes a reset voltage to the second end of the driving circuit 11 during a non-luminous period before the data voltage is written to the second end of the driving circuit 11, so as to provide a bias voltage to the driving transistor in the driving circuit 11 (at this time, the gate potential of the driving transistor is also initialized to Vi1), so that the driving transistor maintains a reset state, thereby improving the hysteresis of the driving transistor and facilitating the FFR (first frame response time) of the display screen.

[0298] In a specific implementation, the hysteresis of the driving transistor may cause the characteristic response of the driving transistor to be relatively slow. However, at least one embodiment of the present disclosure quickly resets the gate-source voltage of the driving transistor before writing the data voltage, which helps to accelerate the recovery speed of the driving transistor. Therefore, the hysteresis phenomenon of the driving transistor is improved and the hysteresis recovery speed is increased.

[0299] This disclosure Fig.47 When at least one embodiment of the pixel circuit shown is in operation, during a non-luminous time period (the non-luminous time period may refer to a time period other than the luminous stage included in the display cycle), before the data voltage is written to the second end of the driving circuit 11, the time for resetting the second end of the driving circuit 11 can be increased by increasing the duty cycle of the third scanning signal, so that the resetting effect of the potential of the second end of the driving circuit 11 is better.

[0300] This disclosure Fig.47 When at least one embodiment of the pixel circuit shown is in operation, in the initialization phase, the reset circuit writes a reset voltage into the second end of the driving circuit under the control of the third scanning signal.

[0301] In at least one embodiment of the present disclosure, the reset voltage is a DC voltage signal to provide a fixed bias voltage for the driving transistor to improve the hysteresis phenomenon.

[0302] Optionally, the reset voltage may be a high voltage, but is not limited thereto.

[0303] In at least one embodiment of the present disclosure, a separate third scan signal generating module may be used to provide a third scan signal to the third scan line, so as to facilitate resetting the potential of the second end of the driving circuit.

[0304] In at least one embodiment of the present disclosure, the reset voltage line and the first voltage line may be the same voltage line, so that the number of signal lines used can be reduced. The voltage value of the reset voltage is greater than the voltage value of the first initialization voltage; the first voltage line is used to provide a first voltage signal (the first voltage line may be a high voltage line). The voltage value of the first voltage signal may be greater than 0V and less than or equal to 5V. For example, the voltage value of the first voltage signal may be 4.6V, but is not limited thereto. The first initialization voltage may be a DC voltage, and the voltage value of the first initialization voltage may be greater than or equal to -7V and less than or equal to 0V; for example, the voltage value of the first initialization voltage may be -6V, -5V, -4V, -3V or -2V, but is not limited thereto.

[0305] In at least one embodiment of the present disclosure, the threshold voltage Vth of the driving transistor in the driving circuit may be greater than or equal to -5V and less than or equal to -2V. Preferably, Vth may be greater than or equal to -4V and less than or equal to -2.5V. For example, Vth may be -4V, -3.5V, -3V or -2.5V, but is not limited thereto.

[0306] The absolute value of the reset voltage may be greater than 1.5 times the absolute value of the threshold voltage to ensure that the bias effect can be achieved quickly in a short time. For example, the absolute value of the reset voltage may be greater than 2, 2.5 or 3 times the absolute value of the threshold voltage, but is not limited thereto.

[0307] Optionally, the reset circuit includes a fourth transistor;

[0308] The control electrode of the fourth transistor is electrically connected to the third scan line, the first electrode of the fourth transistor is electrically connected to the reset voltage line, and the second electrode of the fourth transistor is electrically connected to the second end of the driving circuit.

[0309] In at least one embodiment of the present disclosure, the fourth transistor may be a low-temperature polysilicon thin film transistor, but is not limited thereto.

[0310] like Fig.48 As shown, the pixel circuit described in at least one embodiment of the present disclosure may further include a light emitting element 30, a light emitting control circuit 31 and a second initialization circuit 32;

[0311] The light-emitting control circuit 31 is electrically connected to the light-emitting control line E1, the first voltage line V1, the second end of the driving circuit 11, the first end of the driving circuit 11 and the first pole of the light-emitting element 30 respectively, and is used to control the first voltage line V1 to be connected to the second end of the driving circuit 11 and to control the first end of the driving circuit 11 to be connected to the first pole of the light-emitting element 30 under the control of the light-emitting control signal provided by the light-emitting control line E1;

[0312] The second initialization circuit 32 is electrically connected to the fourth scan line S4, the second initialization voltage line and the first electrode of the light-emitting element 30 respectively, and is used to write the second initialization voltage Vi2 provided by the second initialization voltage line into the first electrode of the light-emitting element 30 under the control of the fourth scan signal provided by the fourth scan line S4;

[0313] The second electrode of the light emitting element 30 is electrically connected to the second voltage line V2.

[0314] In at least one embodiment of the present disclosure, the first voltage line V1 may be a high voltage line, and the second voltage line V2 may be a low voltage line, but is not limited thereto;

[0315] The light emitting element 30 may be an OLED (organic light emitting diode), the first electrode of the light emitting element 30 may be an anode of the OLED, and the second electrode of the light emitting element 30 may be a cathode of the OLED, but the present invention is not limited thereto.

[0316] In this disclosure Fig.48 In at least one embodiment of the pixel circuit shown, a fourth scan signal can be provided to the fourth scan line by a separate fourth scan signal generating module, which is beneficial to the freedom of switching the switching frequency under low-frequency flicker (the switching frequency is the switching frequency of the transistor included in the second initialization circuit 32). When the display panel to which the pixel circuit is applied works at a low frequency, when the light emitting control circuit 31 controls the first voltage line V1 to be disconnected from the second end of the driving circuit 11, and controls the first end of the driving circuit 11 to be disconnected from the first pole of the light emitting element 30, the frequency of the fourth scan signal can be increased to reduce flicker.

[0317] In at least one embodiment of the present disclosure, the third scanning signal and the fourth scanning signal may be the same scanning signal, and the third scanning signal generating module and the fourth scanning signal generating module may be the same module, but the present invention is not limited thereto.

[0318] This disclosure Fig.48When at least one embodiment of the pixel circuit shown is working, the first scanning signal and the light-emitting control signal can be the same signal, but considering that when PWM (pulse width modulation) controls the light-emitting function, EM may provide a high voltage signal during the light-emitting process, a separate first scanning signal generating module is used to provide the first scanning line with the first scanning signal, and a light-emitting control signal is provided to the light-emitting control line through a light-emitting control signal generating module.

[0319] In at least one embodiment of the present disclosure, when the reset voltage line is a first voltage line, a voltage value of the reset voltage may be greater than a voltage value of the second initialization voltage.

[0320] The voltage value of the second initialization voltage may be greater than or equal to -7 V and less than or equal to 0 V. For example, the voltage value of the second initialization voltage may be -6 V, -5 V, -4 V, -3 V or -2 V.

[0321] Optionally, the light emitting control circuit includes a fifth transistor and a sixth transistor;

[0322] The control electrode of the fifth transistor is electrically connected to the light emitting control line, the first electrode of the fifth transistor is electrically connected to the first voltage line, and the second electrode of the fifth transistor is electrically connected to the second end of the driving circuit;

[0323] The control electrode of the sixth transistor is electrically connected to the light emitting control line, the first electrode of the sixth transistor is electrically connected to the first end of the driving circuit, and the second electrode of the sixth transistor is electrically connected to the first electrode of the light emitting element;

[0324] The second initialization circuit includes a seventh transistor;

[0325] The control electrode of the seventh transistor is electrically connected to the fourth scan line, the first electrode of the seventh transistor is electrically connected to the second initialization voltage line, and the second electrode of the seventh transistor is electrically connected to the first electrode of the light emitting element.

[0326] Optionally, the seventh transistor may be an oxide thin film transistor.

[0327] In at least one embodiment of the present disclosure, the seventh transistor may be configured as an oxide thin film transistor, which may reduce leakage and ensure the stability of the potential of the first electrode of the light emitting element.

[0328] like Fig.49 As shown, in Fig.48 Based on at least one embodiment of the pixel circuit shown, the pixel circuit described in at least one embodiment of the present disclosure may further include a data writing circuit 41 and an energy storage circuit 42;

[0329] The data writing circuit 41 is electrically connected to the second scan line S2, the data line D1 and the second end of the driving circuit 11 respectively, and is used to write the data voltage on the data line D1 into the second end of the driving circuit 11 under the control of the second scan signal provided by the second scan line S2;

[0330] The energy storage circuit 42 is electrically connected to the control end of the driving circuit 11 and is used for storing electric energy.

[0331] This disclosure Fig.49 When at least one embodiment of the pixel circuit shown is in operation, the display cycle further includes a light emitting phase arranged after the data writing phase;

[0332] In the initialization stage, the second initialization circuit 32 writes the second initialization voltage Vi2 provided by the second initialization voltage line into the first electrode of the light emitting element 30 under the control of the fourth scan signal provided by the fourth scan line S4;

[0333] In the data writing stage, the data writing circuit 41 writes the data voltage Vdata on the data line D1 into the second end of the driving circuit 11 under the control of the second scanning signal;

[0334] At the beginning of the data writing phase, the driving circuit 11 controls the first terminal thereof to be connected to the second terminal of the driving circuit 11, so as to charge the energy storage circuit 42 through the data voltage Vdata, and change the potential of the control terminal of the driving circuit 11 until the potential of the control terminal of the driving circuit 11 becomes Vdata+Vth, where Vth is the threshold voltage of the driving transistor of the driving circuit 11;

[0335] In the light-emitting stage, the light-emitting control circuit 31 controls the first voltage line V1 to be connected to the second end of the driving circuit 11, and controls the first end of the driving circuit 11 to be connected to the first pole of the light-emitting element 30 under the control of the light-emitting control signal, and the driving circuit 11 drives the light-emitting element 30 to emit light.

[0336] Optionally, the data writing circuit includes an eighth transistor, and the energy storage circuit includes a storage capacitor;

[0337] The control electrode of the eighth transistor is electrically connected to the second scan line, the first electrode of the eighth transistor is electrically connected to the data line, and the second electrode of the eighth transistor is electrically connected to the second end of the driving circuit;

[0338] A first end of the storage capacitor is electrically connected to a control end of the driving circuit, and a second end of the storage capacitor is electrically connected to the first voltage line.

[0339] In at least one embodiment of the present disclosure, the driving circuit may include a driving transistor;

[0340] The driving transistor is a single-gate transistor, the gate of the driving transistor is electrically connected to the control terminal of the driving circuit, the first electrode of the driving transistor is electrically connected to the first terminal of the driving circuit, and the second electrode of the driving transistor is electrically connected to the second terminal of the driving circuit; or

[0341] The driving transistor is a dual-gate transistor, the first gate of the driving transistor is electrically connected to the control end of the driving circuit, the second gate of the driving transistor is electrically connected to the first voltage line, the first electrode of the driving transistor is electrically connected to the first end of the driving circuit, and the second electrode of the driving transistor is electrically connected to the second end of the driving circuit; the first gate is a top gate, and the second gate is a bottom gate.

[0342] Optionally, the driving transistor may be a single-gate transistor or a double-gate transistor. When the driving transistor is a double-gate transistor, the first gate of the driving transistor is electrically connected to the control terminal of the driving circuit, the second gate of the driving transistor is electrically connected to the first voltage line, the first gate is a top gate, and the second gate is a bottom gate, so that the substrate of the driving transistor is biased to improve the hysteresis phenomenon of the driving transistor.

[0343] like Fig.50 As shown, in Fig.49 Based on at least one embodiment of the pixel circuit shown, the first control circuit 12 includes a first transistor T1; the driving circuit 11 includes a driving transistor T0; the light emitting element is an organic light emitting diode O1;

[0344] The gate of the first transistor T1 is electrically connected to the first scan line S1, the drain of the first transistor T1 is electrically connected to the gate of the driving transistor T0, and the source of the first transistor T1 is electrically connected to the connection node N0;

[0345] The compensation control circuit 13 includes a second transistor T2;

[0346] The gate of the second transistor T2 is electrically connected to the second scan line S2, the drain of the second transistor T2 is electrically connected to the connection node N0, and the source of the second transistor T2 is electrically connected to the drain of the driving transistor T0;

[0347] The first initialization circuit 14 includes a third transistor T3;

[0348] The gate of the third transistor T3 is electrically connected to the initialization control line R1, the drain of the third transistor T3 is electrically connected to the first initialization voltage line, and the source of the third transistor T3 is electrically connected to the connection node N0; the first initialization voltage line is used to provide a first initialization voltage Vi1;

[0349] The reset circuit 20 includes a fourth transistor T4;

[0350] The gate of the fourth transistor T4 is electrically connected to the third scan line S3, the drain of the fourth transistor T4 is electrically connected to the reset voltage line DR, and the source of the fourth transistor T4 is electrically connected to the source of the driving transistor T0;

[0351] The light emitting control circuit includes a fifth transistor T5 and a sixth transistor T6;

[0352] The gate of the fifth transistor T5 is electrically connected to the light emitting control line E1, the drain of the fifth transistor T5 is electrically connected to the high voltage line, and the source of the fifth transistor T5 is electrically connected to the source of the driving transistor T0; the high voltage line is used to provide a high voltage signal VDD;

[0353] The gate of the sixth transistor T6 is electrically connected to the light emitting control line E1, the drain of the sixth transistor T6 is electrically connected to the drain of the driving transistor T0, and the source of the sixth transistor T6 is electrically connected to the anode of the organic light emitting diode O1;

[0354] The second initialization circuit 32 includes a seventh transistor T7;

[0355] The gate of the seventh transistor T7 is electrically connected to the fourth scan line S4, the drain of the seventh transistor T7 is electrically connected to the second initialization voltage line, and the source of the seventh transistor T7 is electrically connected to the anode of the organic light emitting diode O1; the second initialization voltage line is used to provide a second initial voltage Vi2;

[0356] The data writing circuit 41 includes an eighth transistor T8, and the energy storage circuit 42 includes a storage capacitor C;

[0357] The gate of the eighth transistor T8 is electrically connected to the second scan line S2, the drain of the eighth transistor T8 is electrically connected to the data line D1, and the source of the eighth transistor T8 is electrically connected to the source of the driving transistor T0;

[0358] A first end of the storage capacitor C is electrically connected to the gate of the driving transistor T0, and a second end of the storage capacitor C is electrically connected to the high voltage line;

[0359] The cathode of O1 is electrically connected to a low voltage line, which is used to provide a low voltage VSS.

[0360] exist Fig.50 Among them, the node labeled N1 is the first node, and the first node N1 is electrically connected to the gate of T0;

[0361] The node labeled N2 is the second node, and the node labeled N3 is the third node; N2 is electrically connected to the source of T0, and N3 is electrically connected to the drain of T0.

[0362] exist Fig.50 In at least one embodiment shown, the first voltage line is a high voltage line, and the second voltage line is a low voltage line.

[0363] exist Fig.50 In at least one embodiment of the pixel circuit shown, T1 may be an oxide thin film transistor, T0, T2, T3, T4, T5, T6, T7 and T8 may all be low-temperature polysilicon thin film transistors, T1 is an n-type transistor, T0, T2, T3, T4, T5, T6, T7 and T8 are p-type transistors, and T0 is a single-gate transistor, but is not limited thereto.

[0364] exist Fig.50 In at least one embodiment of the pixel circuit shown, N1 is only directly electrically connected to T1, and N1 is not directly electrically connected to T2 and T3, so as to reduce leakage of N1 and stabilize the potential stability of the gate of T0.

[0365] exist Fig.50 In at least one embodiment of the pixel circuit shown, T1 is an oxide thin film transistor, which can reduce leakage and ensure the stability of the potential of N1.

[0366] Optionally, T2 and T3 may be single-gate transistors to save space.

[0367] In such Fig.50 In at least one embodiment of the pixel circuit shown, the initialization control signal provided by the initialization control line R1 and the second scanning signal provided by the second scanning line can both be provided by a second scanning signal generating module.

[0368] Optionally, in at least one embodiment of the pixel circuit, each transistor included in the pixel circuit can be arranged on a substrate, and the overlap area between the orthographic projection of the conductive pattern on the substrate and the orthographic projection of the fourth scan line S4 on the substrate is as small as possible, and the overlap area between the orthographic projection of the conductive pattern on the substrate and the orthographic projection of the initialization control line R1 on the substrate is as small as possible to reduce parasitic capacitance. In a preferred case, the capacitance between the conductive pattern and the fourth scan line S4 is less than 0.3Cz, and the capacitance between the conductive pattern for electrically connecting the source of T0 and the source of T5 and the initialization control line R1 is less than 0.3Cz; wherein Cz is the capacitance value of the storage capacitor C.

[0369] The conductive pattern includes a source of T0, a source of T5, and a connecting conductive pattern for electrically connecting the source of T0 and the source of T5.

[0370] like Fig.51 As shown, the present disclosure is Fig.50 When at least one embodiment of the pixel circuit shown is in operation, a display cycle includes an initialization phase t1, a data writing phase t2 and a light emitting phase t3 which are arranged successively;

[0371] In the initialization phase t1, E1 provides a high voltage signal, S1 provides a high voltage signal, T1 is turned on, R1 provides a low voltage signal, S2 provides a high voltage signal, T2 is turned on, T3 is turned off, and Vi1 is written into N1, so that T0 is turned on at the beginning of the data writing phase t2; S3 and S4 provide low voltage signals, T7 is turned on, and T4 is turned on to write the reset voltage provided by DR into N2, and write Vi2 into the anode of O1, so that O1 does not emit light and the residual charge on the anode of O1 is cleared;

[0372] In the data writing phase t2, E1 provides a high voltage signal, S1 provides a high voltage signal, T1 is turned on, R1 provides a high voltage signal, S2 provides a high voltage signal, T2 is turned on, T3 is turned off, T8 is turned on, S3 and S4 provide high voltage signals, T7 and T4 are turned off, and the data voltage Vdata on the data line D1 is written into N2;

[0373] At the beginning of the data writing phase t2, T0 is turned on to pass Vdata, and C is charged through the turned-on T8, T0, T2, and T1 to increase the potential of N1 until T0 is turned off. At this time, the potential of N1 is Vdata+Vth, where Vth is the threshold voltage of T0;

[0374] In the light-emitting stage t3, E1 provides a low voltage signal, R1 provides a high voltage signal, S1 provides a low voltage signal, S2, S3 and S4 provide high voltage signals, T1, T2, T3, T4, T7 and T8 are turned off, T5 and T6 are turned on, and T0 is turned on to drive O1 to emit light.

[0375] exist Fig.50 In at least one embodiment of the pixel circuit shown, T4 is added to provide a high voltage to N2 to initialize the potential of N2 during the non-luminous period, which is beneficial to improving the stability of T0; and T7 is provided to initialize the potential of the anode of O1, which is beneficial to the freedom of switching frequency under low-frequency flicker.

[0376] like Fig.52 As shown, in Fig.49 Based on at least one embodiment of the pixel circuit shown, the first control circuit 12 includes a first transistor T1; the driving circuit 11 includes a driving transistor T0; the light emitting element is an organic light emitting diode O1;

[0377] The gate of the first transistor T1 is electrically connected to the first scan line S1, the drain of the first transistor T1 is electrically connected to the gate of the driving transistor T0, and the source of the first transistor T1 is electrically connected to the connection node N0;

[0378] The compensation control circuit 13 includes a second transistor T2;

[0379] The gate of the second transistor T2 is electrically connected to the second scan line S2, the drain of the second transistor T2 is electrically connected to the connection node N0, and the source of the second transistor T2 is electrically connected to the drain of the driving transistor T0;

[0380] The first initialization circuit 14 includes a third transistor T3;

[0381] The gate of the third transistor T3 is electrically connected to the initialization control line R1, the drain of the third transistor T3 is electrically connected to the first initialization voltage line, and the source of the third transistor T3 is electrically connected to the connection node N0; the first initialization voltage line is used to provide a first initialization voltage Vi1;

[0382] The reset circuit 20 includes a fourth transistor T4;

[0383] The gate of the fourth transistor T4 is electrically connected to the third scan line S3, the drain of the fourth transistor T4 is electrically connected to the reset voltage line DR, and the source of the fourth transistor T4 is electrically connected to the source of the driving transistor T0;

[0384] The light emitting control circuit includes a fifth transistor T5 and a sixth transistor T6;

[0385] The gate of the fifth transistor T5 is electrically connected to the light emitting control line E1, the drain of the fifth transistor T5 is electrically connected to the high voltage line, and the source of the fifth transistor T5 is electrically connected to the source of the driving transistor T0; the high voltage line is used to provide a high voltage signal VDD;

[0386] The gate of the sixth transistor T6 is electrically connected to the light emitting control line E1, the drain of the sixth transistor T6 is electrically connected to the drain of the driving transistor T0, and the source of the sixth transistor T6 is electrically connected to the anode of the organic light emitting diode O1;

[0387] The second initialization circuit 32 includes a seventh transistor T7;

[0388] The gate of the seventh transistor T7 is electrically connected to the fourth scan line S4, the drain of the seventh transistor T7 is electrically connected to the second initialization voltage line, and the source of the seventh transistor T7 is electrically connected to the anode of the organic light emitting diode O1; the second initialization voltage line is used to provide a second initial voltage Vi2;

[0389] The data writing circuit 41 includes an eighth transistor T8, and the energy storage circuit 42 includes a storage capacitor C;

[0390] The gate of the eighth transistor T8 is electrically connected to the second scan line S2, the drain of the eighth transistor T8 is electrically connected to the data line D1, and the source of the eighth transistor T8 is electrically connected to the source of the driving transistor T0;

[0391] A first end of the storage capacitor C is electrically connected to the gate of the driving transistor T0, and a second end of the storage capacitor C is electrically connected to the high voltage line;

[0392] The cathode of O1 is electrically connected to a low voltage line, which is used to provide a low voltage VSS.

[0393] exist Fig.52 Among them, the node labeled N1 is the first node, and the first node N1 is electrically connected to the gate of T0;

[0394] The node labeled N2 is the second node, and the node labeled N3 is the third node; N2 is electrically connected to the source of T0, and N3 is electrically connected to the drain of T0.

[0395] exist Fig.52 In at least one embodiment shown, the first voltage line is a high voltage line, and the second voltage line is a low voltage line.

[0396] exist Fig.52 In at least one embodiment of the pixel circuit shown, T1 and T7 may be oxide thin film transistors, T0, T2, T3, T4, T5, T6 and T8 may all be low-temperature polysilicon thin film transistors, T1 and T7 are n-type transistors, T0, T2, T3, T4, T5, T6 and T8 are p-type transistors, and T0 is a single-gate transistor, but is not limited thereto.

[0397] The Disclosure Fig.52 At least one embodiment of the pixel circuit shown in the present disclosure Fig.50 The difference of at least one embodiment of the pixel circuit shown is that T7 is an oxide thin film transistor.

[0398] exist Fig.52 In at least one embodiment of the pixel circuit shown, N1 is only directly electrically connected to T1, and N1 is not directly electrically connected to T2 and T3, so as to reduce leakage of N1 and stabilize the potential stability of the gate of T0.

[0399] exist Fig.52 In at least one embodiment of the pixel circuit shown, T1 and T7 are oxide thin film transistors to reduce leakage, ensure the stability of the potential of N1, and ensure the stability of the potential of the anode of O1.

[0400] exist Fig.52 In at least one embodiment of the pixel circuit shown, a fourth scan signal can be provided to the fourth scan line by a separate fourth scan signal generating module, which is beneficial to the freedom of switching the switching frequency under low-frequency flicker (the switching frequency is the switching frequency of the transistor included in the second initialization circuit 32). When the display panel to which the pixel circuit is applied works at a low frequency, when the light-emitting control circuit 31 controls the first voltage line V1 to be disconnected from the second end of the driving circuit 11, and controls the first end of the driving circuit 11 to be disconnected from the first pole of the light-emitting element 30, the frequency of the fourth scan signal can be increased to reduce flicker; or,

[0401] The fourth scanning line may be the light-emitting control line, so that in the low-frequency refresh stage, only the light-emitting control signal provided by the light-emitting control line needs to be periodically controlled, that is, the light-emitting element can be reset / brightness adjusted periodically, thereby achieving brightness balance.

[0402] like Fig.53 As shown, in Fig.49 Based on at least one embodiment of the pixel circuit shown, the first control circuit 12 includes a first transistor T1; the driving circuit 11 includes a driving transistor T0; the light emitting element is an organic light emitting diode O1;

[0403] The gate of the first transistor T1 is electrically connected to the first scan line S1, the drain of the first transistor T1 is electrically connected to the gate of the driving transistor T0, and the source of the first transistor T1 is electrically connected to the connection node N0;

[0404] The compensation control circuit 13 includes a second transistor T2;

[0405] The gate of the second transistor T2 is electrically connected to the second scan line S2, the drain of the second transistor T2 is electrically connected to the connection node N0, and the source of the second transistor T2 is electrically connected to the drain of the driving transistor T0;

[0406] The first initialization circuit 14 includes a third transistor T3;

[0407] The gate of the third transistor T3 is electrically connected to the initialization control line R1, the drain of the third transistor T3 is electrically connected to the first initialization voltage line, and the source of the third transistor T3 is electrically connected to the connection node N0; the first initialization voltage line is used to provide a first initialization voltage Vi1;

[0408] The reset circuit 20 includes a fourth transistor T4;

[0409] The gate of the fourth transistor T4 is electrically connected to the third scan line S3, the drain of the fourth transistor T4 is electrically connected to the high voltage line, and the source of the fourth transistor T4 is electrically connected to the source of the driving transistor T0; the high voltage line is used to provide a high voltage signal VDD;

[0410] The light emitting control circuit includes a fifth transistor T5 and a sixth transistor T6;

[0411] The gate of the fifth transistor T5 is electrically connected to the light emitting control line E1, the drain of the fifth transistor T5 is electrically connected to the high voltage line, and the source of the fifth transistor T5 is electrically connected to the source of the driving transistor T0;

[0412] The gate of the sixth transistor T6 is electrically connected to the light emitting control line E1, the drain of the sixth transistor T6 is electrically connected to the drain of the driving transistor T0, and the source of the sixth transistor T6 is electrically connected to the anode of the organic light emitting diode O1;

[0413] The second initialization circuit 32 includes a seventh transistor T7;

[0414] The gate of the seventh transistor T7 is electrically connected to the fourth scan line S4, the drain of the seventh transistor T7 is electrically connected to the second initialization voltage line, and the source of the seventh transistor T7 is electrically connected to the anode of the organic light emitting diode O1; the second initialization voltage line is used to provide a second initial voltage Vi2;

[0415] The data writing circuit 41 includes an eighth transistor T8, and the energy storage circuit 42 includes a storage capacitor C;

[0416] The gate of the eighth transistor T8 is electrically connected to the second scan line S2, the drain of the eighth transistor T8 is electrically connected to the data line D1, and the source of the eighth transistor T8 is electrically connected to the source of the driving transistor T0;

[0417] A first end of the storage capacitor C is electrically connected to the gate of the driving transistor T0, and a second end of the storage capacitor C is electrically connected to the high voltage line;

[0418] The cathode of O1 is electrically connected to a low voltage line, which is used to provide a low voltage VSS.

[0419] exist Fig.53 Among them, the node labeled N1 is the first node, and the first node N1 is electrically connected to the gate of T0;

[0420] The node labeled N2 is the second node, and the node labeled N3 is the third node; N2 is electrically connected to the source of T0, and N3 is electrically connected to the drain of T0.

[0421] exist Fig.53 In at least one embodiment shown, the first voltage line is a high voltage line, and the second voltage line is a low voltage line.

[0422] exist Fig.53 In at least one embodiment of the pixel circuit shown, T1 may be an oxide thin film transistor, T0, T2, T3, T4, T5, T6, T7 and T8 may all be low-temperature polysilicon thin film transistors, T1 is an n-type transistor, T0, T2, T3, T4, T5, T6, T7 and T8 are p-type transistors, and T0 is a single-gate transistor, but is not limited thereto.

[0423] exist Fig.53 In at least one embodiment of the pixel circuit shown, N1 is only directly electrically connected to T1, and N1 is not directly electrically connected to T2 and T3, so as to reduce leakage of N1 and stabilize the potential stability of the gate of T0;

[0424] T1 is an oxide thin film transistor to reduce leakage of N1 and stabilize the potential of the gate of T0.

[0425] The Disclosure Fig.53 At least one embodiment of the pixel circuit shown in the present disclosure Fig.50 The difference of at least one embodiment of the pixel circuit shown is that the reset voltage line DR is the high voltage line, which can reduce the number of signal lines used.

[0426] In this disclosure Fig.53 In at least one embodiment of the pixel circuit shown, the voltage value of VDD may be 4.6V, the voltage value of VDD is greater than the voltage value of Vi1, and the voltage value of VDD is greater than the voltage value of Vi2.

[0427] In this disclosure Fig.53 In at least one embodiment of the pixel circuit shown, T7 may also be replaced by an oxide thin film transistor, and T0 may also be replaced by a dual-gate transistor, but the present invention is not limited thereto.

[0428] like Fig.54 As shown, in Fig.49 Based on at least one embodiment of the pixel circuit shown, the first control circuit 12 includes a first transistor T1; the driving circuit 11 includes a driving transistor T0; the light emitting element is an organic light emitting diode O1;

[0429] The gate of the first transistor T1 is electrically connected to the first scan line S1, the drain of the first transistor T1 is electrically connected to the first gate of the driving transistor T0, and the source of the first transistor T1 is electrically connected to the connection node N0;

[0430] The compensation control circuit 13 includes a second transistor T2;

[0431] The gate of the second transistor T2 is electrically connected to the second scan line S2, the drain of the second transistor T2 is electrically connected to the connection node N0, and the source of the second transistor T2 is electrically connected to the drain of the driving transistor T0;

[0432] The first initialization circuit 14 includes a third transistor T3;

[0433] The gate of the third transistor T3 is electrically connected to the initialization control line R1, the drain of the third transistor T3 is electrically connected to the first initialization voltage line, and the source of the third transistor T3 is electrically connected to the connection node N0; the first initialization voltage line is used to provide a first initialization voltage Vi1;

[0434] The reset circuit 20 includes a fourth transistor T4;

[0435] The gate of the fourth transistor T4 is electrically connected to the third scan line S3, the drain of the fourth transistor T4 is electrically connected to the reset voltage line DR, and the source of the fourth transistor T4 is electrically connected to the source of the driving transistor T0;

[0436] The light emitting control circuit includes a fifth transistor T5 and a sixth transistor T6;

[0437] The gate of the fifth transistor T5 is electrically connected to the light emitting control line E1, the drain of the fifth transistor T5 is electrically connected to the high voltage line, and the source of the fifth transistor T5 is electrically connected to the source of the driving transistor T0; the high voltage line is used to provide a high voltage signal VDD;

[0438] The gate of the sixth transistor T6 is electrically connected to the light emitting control line E1, the drain of the sixth transistor T6 is electrically connected to the drain of the driving transistor T0, and the source of the sixth transistor T6 is electrically connected to the anode of the organic light emitting diode O1;

[0439] The second initialization circuit 32 includes a seventh transistor T7;

[0440] The gate of the seventh transistor T7 is electrically connected to the fourth scan line S4, the drain of the seventh transistor T7 is electrically connected to the second initialization voltage line, and the source of the seventh transistor T7 is electrically connected to the anode of the organic light emitting diode O1; the second initialization voltage line is used to provide a second initial voltage Vi2;

[0441] The data writing circuit 41 includes an eighth transistor T8, and the energy storage circuit 42 includes a storage capacitor C;

[0442] The gate of the eighth transistor T8 is electrically connected to the second scan line S2, the drain of the eighth transistor T8 is electrically connected to the data line D1, and the source of the eighth transistor T8 is electrically connected to the source of the driving transistor T0;

[0443] The first end of the storage capacitor C is electrically connected to the first gate of the driving transistor T0, and the second end of the storage capacitor C is electrically connected to the high voltage line;

[0444] The second gate of the driving transistor T0 is electrically connected to the high voltage line;

[0445] The cathode of O1 is electrically connected to a low voltage line, which is used to provide a low voltage VSS.

[0446] exist Fig.54 Among them, the node labeled N1 is the first node, and the first node N1 is electrically connected to the gate of T0;

[0447] The node labeled N2 is the second node, and the node labeled N3 is the third node; N2 is electrically connected to the source of T0, and N3 is electrically connected to the drain of T0.

[0448] exist Fig.54 In at least one embodiment shown, the first voltage line is a high voltage line, and the second voltage line is a low voltage line.

[0449] exist Fig.54 In at least one embodiment of the pixel circuit shown, T1 may be an oxide thin film transistor, T0, T2, T3, T4, T5, T6, T7 and T8 may all be low-temperature polysilicon thin film transistors, T1 is an n-type transistor, T0, T2, T3, T4, T5, T6, T7 and T8 are p-type transistors, and T0 is a dual-gate transistor, but is not limited thereto.

[0450] exist Fig.54 In at least one embodiment of the pixel circuit shown, N1 is only directly electrically connected to T1, and N1 is not directly electrically connected to T2 and T3, so as to reduce leakage of N1 and stabilize the potential stability of the gate of T0.

[0451] exist Fig.54 In at least one embodiment of the pixel circuit shown, T1 is an oxide thin film transistor, which can reduce leakage and ensure the stability of the potential of N1.

[0452] exist Fig.54 In at least one embodiment of the pixel circuit shown, T0 is a dual-gate transistor, the first gate of T0 is a top gate, the second gate of T0 is a bottom gate, and the second gate of T0 is electrically connected to the high voltage line to bias the substrate of T0, which is beneficial to improving the hysteresis phenomenon of T0.

[0453] This disclosure Fig.54 At least one embodiment of the pixel circuit shown in FIG. Fig.50 The difference of at least one embodiment of the pixel circuit shown is that T0 is a dual-gate transistor.

[0454] In this disclosure Fig.54 In at least one embodiment of the pixel circuit shown, T7 may be replaced by an oxide thin film transistor, and DR may be a first voltage line, but the present invention is not limited thereto.

[0455] In this disclosure Fig.50 , Fig.52 , Fig.53 , Fig.54In at least one embodiment of the pixel circuit shown, in a non-luminous time period (the non-luminous time period may refer to a time period other than the luminous stage included in the display cycle), before the data voltage Vdata is written into N2, the on-time of T4 can be increased by increasing the duty cycle of the third scanning signal, so as to achieve a better resetting effect on the potential of N2.

[0456] like Fig.55 As shown, two adjacent rows of pixel circuits can be electrically connected to the same row of reset voltage lines. In FIG55 , the reset voltage line labeled DRn is the nth row (n is a positive integer); and two pixel circuits located in adjacent columns are mirrored to facilitate wiring.

[0457] like Fig.56 As shown, two adjacent columns of pixel circuits can be electrically connected to the same column of reset voltage line. In FIG56 , the reset voltage line labeled DRm is the mth column (m is a positive integer); and two pixel circuits located in adjacent columns are mirrored to facilitate wiring.

[0458] like Fig.57 As shown, two adjacent rows of pixel circuits can be electrically connected to the same row of reset voltage lines, two adjacent columns of pixel circuits can be electrically connected to the same column of reset voltage lines, and two pixel circuits located in adjacent columns are mirror-imaged, and multiple reset voltage lines are arranged in a grid shape to facilitate wiring.

[0459] exist Fig.57 , the line labeled DR11 is the first row reset voltage line, the line labeled DR12 is the second row reset voltage line, the line labeled DR21 is the first column reset voltage line, the line labeled DR22 is the second column reset voltage line, and the line labeled DR23 is the third column reset voltage line.

[0460] exist Fig.58 , the reset voltage line labeled DR11 is the first row, the reset voltage line labeled DR12 is the second row, the reset voltage line labeled DR13 is the third row, the reset voltage line labeled DR14 is the fourth row, the reset voltage line labeled DR21 is the first column, and the reset voltage line labeled DR22 is the second column.

[0461] like Fig.58 As shown, the pixel circuits in the first row are electrically connected to the first row reset voltage line DR11, the pixel circuits in the second row are electrically connected to the second row reset voltage line DR12, the pixel circuits in the third row are electrically connected to the third row reset voltage line DR13, and the pixel circuits in the fourth row are electrically connected to the fourth row reset voltage line DR14;

[0462] A reset voltage line extending vertically is provided, so that a plurality of reset voltage lines are arranged in a grid shape; and a column of reset voltage lines can be provided every several columns of pixel circuits to save wiring space.

[0463] In a specific implementation, a reset voltage line extending vertically may be provided on one side of the red pixel circuit column.

[0464] The driving method described in the embodiment of the present disclosure is applied to the above-mentioned pixel circuit, and the display cycle includes an initialization phase and a data writing phase; the driving method includes:

[0465] In the initialization phase, the first control circuit controls the connection between the control end of the driving circuit and the connection node under the control of the first scanning signal, and the first initialization circuit writes the first initialization voltage into the connection node under the control of the initialization control signal, thereby writing the first initialization voltage into the control end of the driving circuit, so that the driving circuit can control the connection between its first end and the second end of the driving circuit at the beginning of the data writing phase;

[0466] In the data writing stage, the first control circuit controls the connection between the control end of the driving circuit and the connection node under the control of the first scanning signal, and the compensation control circuit controls the connection between the connection node and the first end of the driving circuit under the control of the second scanning signal, so that the control end of the driving circuit is connected to the first end of the driving circuit.

[0467] In the driving method described in the embodiment of the present disclosure, the first control circuit controls the connection between the control end of the driving circuit and the connection node, the first initialization circuit writes the first initialization voltage into the connection node under the control of the initialization control signal, the compensation control circuit controls the connection between the connection node and the first end of the driving circuit under the control of the second scanning signal, the first control circuit is directly electrically connected to the control end of the driving circuit, the first initialization circuit and the compensation control circuit are not directly electrically connected to the control end of the driving circuit, so as to reduce the leakage path of the first node (the node electrically connected to the control end of the driving circuit), so as to ensure the stability of the voltage of the first node during low-frequency operation, which is beneficial to improving display quality, improving display uniformity, and reducing Flicker.

[0468] In a specific implementation, the pixel circuit may further include a reset circuit; and the driving method may further include:

[0469] In the initialization stage, the reset circuit writes a reset voltage into the second end of the driving circuit under the control of the third scanning signal.

[0470] Optionally, the pixel circuit may further include a light emitting element and a second initialization circuit; and the driving method may further include:

[0471] Under the control of the fourth scanning signal, the second initialization circuit writes a second initialization voltage into the first electrode of the light-emitting element to control the light-emitting element not to emit light.

[0472] In a specific implementation, the pixel circuit further includes a light emitting control circuit, a data writing circuit and an energy storage circuit, the display cycle includes a light emitting phase arranged after the data writing phase, and the driving method further includes:

[0473] In the data writing stage, the data writing circuit writes the data voltage Vdata on the data line into the second end of the driving circuit under the control of the second scanning signal;

[0474] At the beginning of the data writing phase, the driving circuit controls the first terminal thereof to be connected to the second terminal of the driving circuit, so as to charge the energy storage circuit through the data voltage Vdata, and change the potential of the control terminal of the driving circuit until the potential of the control terminal of the driving circuit becomes Vdata+Vth, where Vth is the threshold voltage of the driving transistor included in the driving circuit;

[0475] In the light-emitting stage, the light-emitting control circuit controls the connection between the first voltage line and the second end of the driving circuit, and controls the connection between the first end of the driving circuit and the first pole of the light-emitting element under the control of the light-emitting control signal, and the driving circuit drives the light-emitting element to emit light.

[0476] The display device described in the embodiment of the present disclosure includes the above-mentioned pixel circuit.

[0477] Optionally, the pixel circuit includes a reset circuit and a second initialization circuit, the reset circuit is electrically connected to the third scan line, and the second initialization circuit is electrically connected to the fourth scan line; the display device also includes a third scan signal generation module and a fourth scan signal generation module;

[0478] The third scanning signal generating module is electrically connected to the third scanning line, and is used to provide a third scanning signal for the third scanning line;

[0479] The fourth scanning signal generating module is electrically connected to the fourth scanning line, and is used for providing a fourth scanning signal to the fourth scanning line.

[0480] In at least one embodiment of the present disclosure, the third scanning signal and the fourth scanning signal may be the same scanning signal, and the third scanning signal generating module and the fourth scanning signal generating module may be the same module.

[0481] like Fig.59 As shown, the display device described in at least one embodiment of the present disclosure includes a display panel, the display panel includes a pixel module P0, and the pixel module P0 includes a plurality of rows and columns of the above-mentioned pixel circuits; the pixel module P0 is arranged in an effective display area of ​​the display panel;

[0482] The display panel further includes a light emitting control signal generating module 70, a first scanning signal generating module 71, a first second scanning signal generating module 721, a second second scanning signal generating module 722, a third scanning signal generating module 73 and a fourth scanning signal generating module 74;

[0483] The light emitting control signal generating module 70 is used to provide a light emitting control signal, the first scanning signal generating module 71 is used to provide a first scanning signal, the first second scanning signal generating module 721 and the second second scanning signal generating module 722 are used to provide a second scanning signal, the third scanning signal generating module 73 is used to provide a third scanning signal, and the fourth scanning signal generating module 74 is used to provide a fourth scanning signal;

[0484] The light emitting control signal generating module 70, the first scanning signal generating module 71 and the first second scanning signal generating module 721 are arranged on the left side of the display panel.

[0485] The second second scanning signal generating module 722 , the third scanning signal generating module 73 and the fourth scanning signal generating module 74 are disposed on the right side of the display panel.

[0486] like Fig.60 As shown, the display device described in at least one embodiment of the present disclosure includes a display panel, the display panel includes a pixel module P0, and the pixel module P0 includes a plurality of rows and columns of the above-mentioned pixel circuits; the pixel module P0 is arranged in an effective display area of ​​the display panel;

[0487] The display panel further includes a light emitting control signal generating module 70, a first first scanning signal generating module 711, a second first scanning signal generating module 712, a first second scanning signal generating module 721, a second second scanning signal generating module 722 and a fourth scanning signal generating module 74;

[0488] The light emitting control signal generating module 70 is used to provide a light emitting control signal, the first scanning signal generating module 711 and the second first scanning signal generating module 712 are used to provide a first scanning signal, and the first second scanning signal generating module 721 and the second second scanning signal generating module 722 are used to provide a second scanning signal;

[0489] The third scanning signal and the fourth scanning signal are the same scanning signal;

[0490] The fourth scanning signal generating module 74 is used to provide a third scanning signal and a fourth scanning signal;

[0491] The light emitting control signal generating module 70, the first first scanning signal generating module 711 and the first second scanning signal generating module 721 are arranged on the left side of the display panel.

[0492] The second first scanning signal generating module 712 , the second second scanning signal generating module 722 and the fourth scanning signal generating module 74 are disposed on the right side of the display panel.

[0493] exist Fig.55 and Fig.56 In the figure, Vi1 is a first initialization voltage, Vi2 is a second initialization voltage, VDD is a high voltage signal, D1 is a data line, and DR is a reset voltage line.

[0494] The display device provided in the embodiments of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

[0495] like Figure 61-78 , which are illustrations of another set of exemplary embodiments of the pixel driving circuit disclosed in the present invention.

[0496] The transistors used in all embodiments of the present disclosure may be triodes, thin film transistors, field effect transistors or other devices with the same characteristics. In the embodiments of the present disclosure, in order to distinguish the two electrodes of the transistor except the control electrode, one of the electrodes is called the first electrode and the other is called the second electrode.

[0497] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0498] The pixel circuit described in the embodiment of the present disclosure includes a driving circuit, a first initialization circuit and a reset circuit;

[0499] The first initialization circuit is electrically connected to the initialization control line, the first end of the driving circuit and the first initial voltage end respectively, and is used to write the first initial voltage provided by the first initial voltage end into the first end of the driving circuit under the control of the initialization control signal provided by the initialization control line;

[0500] The reset circuit is electrically connected to the second scan line and the reset voltage terminal respectively, and is also electrically connected to the second terminal of the drive circuit or the first terminal of the drive circuit, and is used to control the reset voltage provided by the reset voltage terminal to be written into the second terminal of the drive circuit or the first terminal of the drive circuit under the control of the second scan signal provided by the second scan line;

[0501] The driving circuit is used to control the connection between the first end of the driving circuit and the second end of the driving circuit under the control of the potential of the control end thereof.

[0502] At least one embodiment of the pixel circuit disclosed in the present disclosure includes a first initialization circuit and a reset circuit. The first initialization circuit writes a first initial voltage into the first end of the driving circuit before the data voltage is written into the second end of the driving circuit, so as to cooperate with the compensation control circuit included in the pixel circuit to write the first initial voltage into the control end of the driving circuit; the reset circuit, under the control of the second scanning signal, writes a reset voltage into the second end of the driving circuit or the first end of the driving circuit during a non-luminous period before the data voltage is written into the second end of the driving circuit, so as to provide a bias voltage to the driving transistor in the driving circuit (at this time, the gate potential of the driving transistor is also initialized to Vi1), so that the driving transistor maintains a reset state, so as to improve the hysteresis of the driving transistor, which is beneficial to the FFR (first frame response time) of the display screen.

[0503] In a specific implementation, the hysteresis of the driving transistor may cause the characteristic response of the driving transistor to be relatively slow. However, at least one embodiment of the present disclosure quickly resets the gate-source voltage of the driving transistor before writing the data voltage, which helps to accelerate the recovery speed of the driving transistor. Therefore, the hysteresis phenomenon of the driving transistor is improved and the hysteresis recovery speed is increased.

[0504] In at least one embodiment of the present disclosure, a separate second scan signal generating module may be used to provide a second scan signal to the second scan line, so as to facilitate resetting the potential of the second end of the driving circuit.

[0505] In at least one embodiment of the present disclosure, the reset voltage is a constant voltage to provide a fixed bias voltage for the driving transistor and improve the hysteresis phenomenon.

[0506] Optionally, the first initial voltage is a low potential constant voltage, and the voltage value of the first initial voltage is greater than or equal to -6V and less than or equal to -2V; for example, the voltage value of the first initialization voltage can be -6V, -5V, -4V, -3V or -2V, but is not limited to this.

[0507] In a specific implementation, the reset voltage may be a high potential constant voltage to ensure that the driving transistor in the driving circuit can be quickly turned on at the beginning of the data writing phase; the voltage value of the reset voltage is greater than or equal to 4V and less than or equal to 10V; or,

[0508] The reset voltage may be a low potential constant voltage, and a voltage value of the reset voltage is greater than or equal to -6V and less than or equal to -2V.

[0509] Optionally, when the reset voltage is a high potential constant voltage, the voltage value of the reset voltage may be, for example, 4V, 5V, 6V, 7V, 8V, 9V or 10V, but is not limited thereto;

[0510] When the reset voltage is a low potential constant voltage, the voltage value of the reset voltage may be, for example, -6V, -5V, -4V, -3V or -2V, but is not limited thereto.

[0511] In at least one embodiment of the present disclosure, when the reset voltage is a low-potential constant voltage, the voltage value of the reset voltage is substantially the same as the voltage value of the first initial voltage, so that when the reset voltage is written to the second end of the driving circuit through the reset circuit and the first initial voltage is written to the first end of the driving circuit through the first initialization circuit at the same time, the driving transistor in the driving circuit will not fail.

[0512] The voltage value of the reset voltage is substantially the same as the voltage value of the first initial voltage when the absolute value of the difference between the voltage value of the reset voltage and the voltage value of the first initial voltage is less than a predetermined voltage difference. For example, the predetermined voltage difference may be 0.1V or 0.05V, but is not limited thereto.

[0513] In at least one embodiment of the present disclosure, the threshold voltage Vth of the driving transistor in the driving circuit may be greater than or equal to -5V and less than or equal to -2V. Preferably, Vth may be greater than or equal to -4V and less than or equal to -2.5V. For example, Vth may be -4V, -3.5V, -3V or -2.5V, but is not limited thereto.

[0514] Optionally, the driving circuit includes a driving transistor, and the absolute value of the voltage value of the reset voltage is greater than 1.5 times the absolute value of the threshold voltage to ensure that the bias effect can be quickly achieved in a short time. The threshold voltage is the threshold voltage of the driving transistor. For example, the absolute value of the voltage value of the reset voltage can be greater than 2 times, 2.5 times or 3 times the absolute value of the threshold voltage, but is not limited thereto.

[0515] like Fig.61As shown, the pixel circuit described in the embodiment of the present disclosure includes a driving circuit 11, a first initialization circuit 13 and a reset circuit 20;

[0516] The first initialization circuit 13 is electrically connected to the initialization control line R1, the first end of the driving circuit 11 and the first initial voltage end, respectively, and is used to write the first initial voltage Vi1 provided by the first initial voltage end into the first end of the driving circuit 11 under the control of the initialization control signal provided by the initialization control line R1;

[0517] The reset circuit 20 is electrically connected to the second scan line S2 and the reset voltage terminal DR respectively, and is also electrically connected to the second terminal of the drive circuit 11, and is used to control the reset voltage provided by the reset voltage terminal DR to be written into the second terminal of the drive circuit 11 under the control of the second scan signal provided by the second scan line S2;

[0518] The driving circuit 11 is used to control the connection between the first end of the driving circuit 11 and the second end of the driving circuit 12 under the control of the potential of the control end thereof.

[0519] exist Fig.61 Among them, the node labeled N1 is the first node, and the first node N1 is electrically connected to the control end of the driving circuit 11.

[0520] This disclosure Fig.61 When at least one embodiment of the pixel circuit shown is in operation, the display cycle may include an initialization phase and a reset phase;

[0521] In the initialization stage, the first initialization circuit 13 writes the first initial voltage Vi1 into the first end of the driving circuit 11 under the control of the initialization control signal;

[0522] In the reset phase, the reset circuit 20 writes a reset voltage into the second end of the driving circuit 11 under the control of the second scanning signal.

[0523] like Fig.62 As shown, the pixel circuit described in at least one embodiment of the present disclosure may include a driving circuit 11, a first initialization circuit 13 and a reset circuit 20;

[0524] The first initialization circuit 13 is electrically connected to the initialization control line R1, the first end of the driving circuit 11 and the first initial voltage end, respectively, and is used to write the first initial voltage Vi1 provided by the first initial voltage end into the first end of the driving circuit 11 under the control of the initialization control signal provided by the initialization control line R1;

[0525] The reset circuit 20 is electrically connected to the second scan line S2 and the reset voltage terminal DR respectively, and is also electrically connected to the first end of the drive circuit 11, and is used to control the reset voltage provided by the reset voltage terminal DR to be written into the first end of the drive circuit 11 under the control of the second scan signal provided by the second scan line S2.

[0526] This disclosure Fig.62 When at least one embodiment of the pixel circuit shown is in operation, the display cycle may include an initialization phase and a reset phase;

[0527] In the initialization stage, the first initialization circuit 13 writes the first initial voltage Vi1 into the first end of the driving circuit 11 under the control of the initialization control signal;

[0528] In the reset phase, the reset circuit 20 writes a reset voltage into the first end of the driving circuit 11 under the control of the second scanning signal.

[0529] Optionally, the first initialization circuit includes a second transistor;

[0530] The control electrode of the second transistor is electrically connected to the initialization control line, the first electrode of the second transistor is electrically connected to the first initial voltage terminal, and the second electrode of the second transistor is electrically connected to the first terminal of the driving circuit.

[0531] In at least one embodiment of the present disclosure, the second transistor may be a low temperature polysilicon thin film transistor, but is not limited thereto.

[0532] Optionally, the reset circuit includes a third transistor;

[0533] The control electrode of the third transistor is electrically connected to the second scan line, the first electrode of the third transistor is electrically connected to the reset voltage terminal, and the second electrode of the third transistor is electrically connected to the second terminal of the drive circuit or the first terminal of the drive circuit.

[0534] In at least one embodiment of the present disclosure, the pixel circuit may include a compensation control circuit;

[0535] The compensation control circuit is electrically connected to the first scan line, the control end of the drive circuit and the first end of the drive circuit respectively, and is used to control the connection between the control end of the drive circuit and the first end of the drive circuit under the control of the first scan signal provided by the first scan line.

[0536] When the pixel circuit described in at least one embodiment of the present disclosure is in operation, the display cycle may include an initialization phase; in the initialization phase, the first initialization circuit writes a first initial voltage into the first end of the driving circuit under the control of an initialization control signal, and the compensation control circuit controls the connection between the control end of the driving circuit and the first end of the driving circuit under the control of a first scanning signal to write the first initial voltage into the control end of the driving circuit, so that at the beginning of the data writing phase, the driving circuit can control the connection between the first end of the driving circuit and the second end of the driving transistor under the control of the potential of its control end.

[0537] In the pixel circuit described in at least one embodiment of the present disclosure, the control end of the driving circuit is only directly electrically connected to the compensation control circuit, and the first initialization circuit is directly electrically connected to the first end of the driving circuit, so as to initialize the potential of the control end of the driving circuit through the compensation control circuit and the first initialization circuit, thereby reducing the leakage path of the control end of the driving circuit. Under the condition that the complexity of the pixel circuit design is not significantly increased, the stability of the voltage of the first node can be guaranteed, which is beneficial to improving the display quality, improving the display uniformity, and reducing Flicker.

[0538] Optionally, the compensation control circuit includes a first transistor;

[0539] The control electrode of the first transistor is electrically connected to the first scan line, the first electrode of the first transistor is electrically connected to the control terminal of the drive circuit, and the second electrode of the first transistor is electrically connected to the first terminal of the drive circuit;

[0540] The first transistor is an oxide thin film transistor.

[0541] In an embodiment of the present disclosure, the compensation control circuit may include a first transistor, and the first transistor is an oxide thin film transistor. The oxide transistor has good hysteresis characteristics, low leakage current, and low mobility. Therefore, at least one embodiment of the present disclosure sets the first transistor as an oxide thin film transistor to achieve low leakage current and ensure the stability of the potential of the control terminal of the drive circuit.

[0542] like Fig.63 As shown, in Fig.61 Based on at least one embodiment of the pixel circuit shown, the pixel circuit described in at least one embodiment of the present disclosure may further include a compensation control circuit 12;

[0543] The compensation control circuit 12 is electrically connected to the first scan line S1, the control end of the drive circuit 11 and the first end of the drive circuit 11 respectively, and is used to control the connection between the control end of the drive circuit 11 and the first end of the drive circuit 11 under the control of the first scan signal provided by the first scan line S1.

[0544] This disclosure Fig.63 When at least one embodiment of the pixel circuit is in operation, the display cycle may include an initialization phase. In the initialization phase, the compensation control circuit 12 controls the control end of the driving circuit 11 to be connected to the first end of the driving circuit 11 under the control of the first scanning signal.

[0545] like Fig.64 As shown, in Fig.62 Based on at least one embodiment of the pixel circuit shown, the pixel circuit described in at least one embodiment of the present disclosure may further include a compensation control circuit 12;

[0546] The compensation control circuit 12 is electrically connected to the first scan line S1, the control end of the drive circuit 11 and the first end of the drive circuit 11 respectively, and is used to control the connection between the control end of the drive circuit 11 and the first end of the drive circuit 11 under the control of the first scan signal provided by the first scan line S1.

[0547] This disclosure Fig.64 When at least one embodiment of the pixel circuit is in operation, the display cycle may include an initialization phase. In the initialization phase, the compensation control circuit 12 controls the control end of the driving circuit 11 to be connected to the first end of the driving circuit 11 under the control of the first scanning signal.

[0548] In at least one embodiment of the present disclosure, the pixel circuit may further include a light-emitting element, a storage circuit, a second initialization circuit, a data writing circuit, and a light-emitting control circuit;

[0549] The energy storage circuit is electrically connected to the control end of the drive circuit and is used to store electrical energy;

[0550] The second initialization circuit is electrically connected to the third scan line, the second initial voltage terminal and the first electrode of the light-emitting element respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the third scan signal provided by the third scan line;

[0551] The data writing circuit is electrically connected to the fourth scan line, the data line and the second end of the driving circuit respectively, and is used to write the data voltage provided by the data line into the second end of the driving circuit under the control of the fourth scan signal provided by the fourth scan line;

[0552] The light-emitting control circuit is electrically connected to the light-emitting control line, the first voltage terminal, the second terminal of the driving circuit, the first terminal of the driving circuit and the first electrode of the light-emitting element respectively, and is used to control the first voltage terminal to be connected to the second terminal of the driving circuit, and to control the first terminal of the driving circuit to be connected to the first electrode of the light-emitting element under the control of the light-emitting control signal provided by the light-emitting control line;

[0553] The second electrode of the light emitting element is electrically connected to the second voltage terminal.

[0554] In at least one embodiment of the present disclosure, the pixel circuit may further include a light-emitting element, a storage circuit, a second initialization circuit, a data writing circuit and a light-emitting control circuit, wherein the second initialization circuit initializes the first pole of the light-emitting element, the data writing circuit writes the data voltage into the second end of the driving circuit, and the light-emitting control circuit, under the control of a light-emitting control signal, controls the connection between the first voltage end and the second end of the driving circuit, and controls the connection between the first end of the driving circuit and the first pole of the light-emitting element.

[0555] Optionally, the light-emitting element may be an organic light-emitting diode, the first electrode of the light-emitting element may be an anode of the organic light-emitting diode, and the second electrode of the light-emitting element may be a cathode of the organic light-emitting diode;

[0556] The first voltage terminal may be a high voltage terminal, and the second voltage terminal may be a low voltage terminal;

[0557] But it is not limited to this.

[0558] like Fig.65 As shown, in Fig.63 Based on at least one embodiment of the pixel circuit shown, the pixel circuit described in at least one embodiment of the present disclosure may further include a light emitting element 40, a storage circuit 41, a second initialization circuit 42, a data writing circuit 43 and a light emitting control circuit 44;

[0559] The energy storage circuit 41 is electrically connected to the control end of the drive circuit 11 and is used to store electrical energy;

[0560] The second initialization circuit 42 is electrically connected to the third scan line S3, the second initial voltage terminal and the first electrode of the light emitting element 40 respectively, and is used to write the second initial voltage Vi2 provided by the second initial voltage terminal into the first electrode of the light emitting element 40 under the control of the third scan signal provided by the third scan line S3;

[0561] The data writing circuit 43 is electrically connected to the fourth scan line S4, the data line D1 and the second end of the driving circuit 11 respectively, and is used to write the data voltage provided by the data line D1 into the second end of the driving circuit 11 under the control of the fourth scan signal provided by the fourth scan line S4;

[0562] The light emitting control circuit 44 is electrically connected to the first voltage terminal V1 of the light emitting control line E1, the second terminal of the driving circuit 11, the first terminal of the driving circuit 11 and the first electrode of the light emitting element 40, respectively, and is used to control the first voltage terminal V1 to be connected to the second terminal of the driving circuit 11, and to control the first terminal of the driving circuit 11 to be connected to the first electrode of the light emitting element 40 under the control of the light emitting control signal provided by the light emitting control line E1;

[0563] The second electrode of the light emitting element 40 is electrically connected to the second voltage terminal V2.

[0564] This disclosure Fig.65 When at least one embodiment of the pixel circuit shown is in operation, the display cycle further includes a data writing phase and a light emitting phase which are arranged after the initialization phase;

[0565] In the data writing stage, the data writing circuit 43 writes the data voltage Vdata provided by the data line D1 into the second end of the driving circuit 11 under the control of the fourth scanning signal; the compensation control circuit 12 controls the control end of the driving circuit 11 to be connected to the first end of the driving circuit 11 under the control of the first scanning signal;

[0566] At the beginning of the data writing phase, the driving circuit 11, under the control of its control terminal, turns on the connection between the first terminal of the driving circuit 11 and the second terminal of the driving circuit 11 to charge the energy storage circuit 41 through the data voltage Vdata, thereby changing the potential of the control terminal of the driving circuit 11 until the potential of the control terminal of the driving circuit 11 becomes Vdata+Vth, where Vth is the threshold voltage of the driving transistor included in the driving circuit 11;

[0567] In the light-emitting stage, the light-emitting control circuit 44 controls the connection between the first voltage terminal V1 and the second terminal of the driving circuit 11, and controls the connection between the first terminal of the driving circuit 11 and the first pole of the light-emitting element 40 under the control of the light-emitting control signal, and the driving circuit 11 drives the light-emitting element 40 to emit light.

[0568] In a specific implementation, the reset phase may be arranged between the initialization phase and the data writing phase, but is not limited thereto.

[0569] like Fig.66 As shown, in Fig.64 Based on at least one embodiment of the pixel circuit shown, the pixel circuit described in at least one embodiment of the present disclosure may further include a light emitting element 40, a storage circuit 41, a second initialization circuit 42, a data writing circuit 43 and a light emitting control circuit 44;

[0570] The energy storage circuit 41 is electrically connected to the control end of the drive circuit 11 and is used to store electrical energy;

[0571] The second initialization circuit 42 is electrically connected to the third scan line S3, the second initial voltage terminal and the first electrode of the light emitting element 40 respectively, and is used to write the second initial voltage Vi2 provided by the second initial voltage terminal into the first electrode of the light emitting element 40 under the control of the third scan signal provided by the third scan line S3;

[0572] The data writing circuit 43 is electrically connected to the fourth scan line S4, the data line D1 and the second end of the driving circuit 11 respectively, and is used to write the data voltage provided by the data line D1 into the second end of the driving circuit 11 under the control of the fourth scan signal provided by the fourth scan line S4;

[0573] The light-emitting control circuit 44 is electrically connected to the light-emitting control line E1, the first voltage terminal V1, the second terminal of the driving circuit 11, the first terminal of the driving circuit 11 and the first electrode of the light-emitting element 40, respectively, and is used to control the first voltage terminal V1 to be connected to the second terminal of the driving circuit 11, and to control the first terminal of the driving circuit 11 to be connected to the first electrode of the light-emitting element 40 under the control of the light-emitting control signal provided by the light-emitting control line E1;

[0574] The second electrode of the light emitting element 40 is electrically connected to the second voltage terminal V2.

[0575] This disclosure Fig.66 When at least one embodiment of the pixel circuit shown is in operation, the display cycle further includes a data writing phase and a light emitting phase which are arranged after the initialization phase;

[0576] In the data writing stage, the data writing circuit 43 writes the data voltage Vdata provided by the data line D1 into the second end of the driving circuit 11 under the control of the fourth scanning signal; the compensation control circuit 12 controls the control end of the driving circuit 11 to be connected to the first end of the driving circuit 11 under the control of the first scanning signal;

[0577] At the beginning of the data writing phase, the driving circuit 11, under the control of its control terminal, turns on the connection between the first terminal of the driving circuit 11 and the second terminal of the driving circuit 11 to charge the energy storage circuit 41 through the data voltage Vdata, thereby changing the potential of the control terminal of the driving circuit 11 until the potential of the control terminal of the driving circuit 11 becomes Vdata+Vth, where Vth is the threshold voltage of the driving transistor included in the driving circuit 11;

[0578] In the light-emitting stage, the light-emitting control circuit 44 controls the connection between the first voltage terminal V1 and the second terminal of the driving circuit 11, and controls the connection between the first terminal of the driving circuit 11 and the first pole of the light-emitting element 40 under the control of the light-emitting control signal, and the driving circuit 11 drives the light-emitting element 40 to emit light.

[0579] like Fig.67 As shown, the pixel circuit described in at least one embodiment of the present disclosure may include a driving circuit 11, a compensation control circuit 12, a first initialization circuit 13, a light-emitting element 40, an energy storage circuit 41, a second initialization circuit 42, a data writing circuit 43 and a light-emitting control circuit 44;

[0580] The compensation control circuit 12 is electrically connected to the first scan line S1, the control end of the drive circuit 11 and the first end of the drive circuit 11 respectively, and is used to control the control end of the drive circuit 11 to be connected to the first end of the drive circuit 11 under the control of the first scan signal provided by the first scan line S1;

[0581] The first initialization circuit 13 is electrically connected to the initialization control line R1, the first end of the driving circuit 11 and the first initial voltage end, respectively, and is used to write the first initial voltage Vi1 provided by the first initial voltage end into the first end of the driving circuit 11 under the control of the initialization control signal provided by the initialization control line R1;

[0582] The driving circuit 11 is used to control the connection between the first end of the driving circuit 11 and the second end of the driving circuit 12 under the control of the potential of the control end thereof;

[0583] The energy storage circuit 41 is electrically connected to the control end of the drive circuit 11 and is used to store electrical energy;

[0584] The second initialization circuit 42 is electrically connected to the third scan line S3, the second initial voltage terminal and the first electrode of the light emitting element 40 respectively, and is used to write the second initial voltage Vi2 provided by the second initial voltage terminal into the first electrode of the light emitting element 40 under the control of the third scan signal provided by the third scan line S3;

[0585] The data writing circuit 43 is electrically connected to the fourth scan line S4, the data line D1 and the second end of the driving circuit 11 respectively, and is used to write the data voltage provided by the data line D1 into the second end of the driving circuit 11 under the control of the fourth scan signal provided by the fourth scan line S4;

[0586] The light-emitting control circuit 44 is electrically connected to the light-emitting control line E1, the first voltage terminal V1, the second terminal of the driving circuit 11, the first terminal of the driving circuit 11 and the first electrode of the light-emitting element 40, respectively, and is used to control the first voltage terminal V1 to be connected to the second terminal of the driving circuit 11, and to control the first terminal of the driving circuit 11 to be connected to the first electrode of the light-emitting element 40 under the control of the light-emitting control signal provided by the light-emitting control line E1;

[0587] The second electrode of the light emitting element 40 is electrically connected to the second voltage terminal V2.

[0588] This disclosure Fig.67 When at least one embodiment of the pixel circuit shown is in operation, a display cycle includes an initialization phase, a data writing phase, and a light emitting phase that are arranged in sequence;

[0589] In the initialization phase, the first initialization circuit 13 writes the first initial voltage Vi1 into the first end of the driving circuit 11 under the control of the initialization control signal, and the compensation control circuit 12 controls the control end of the driving circuit 11 to be connected with the first end of the driving circuit 11 under the control of the first scanning signal, so as to write the first initial voltage Vi1 into the control end of the driving circuit 11, so that at the beginning of the data writing phase, the driving circuit 11 can control the first end of the driving circuit 11 to be connected with the second end of the driving transistor 11 under the control of the potential of the control end thereof;

[0590] In the data writing stage, the data writing circuit 43 writes the data voltage Vdata provided by the data line D1 into the second end of the driving circuit 11 under the control of the fourth scanning signal; the compensation control circuit 12 controls the control end of the driving circuit 11 to be connected to the first end of the driving circuit 11 under the control of the first scanning signal;

[0591] At the beginning of the data writing phase, the driving circuit 11, under the control of its control terminal, turns on the connection between the first terminal of the driving circuit 11 and the second terminal of the driving circuit 11 to charge the energy storage circuit 41 through the data voltage Vdata, thereby changing the potential of the control terminal of the driving circuit 11 until the potential of the control terminal of the driving circuit 11 becomes Vdata+Vth, where Vth is the threshold voltage of the driving transistor included in the driving circuit 11;

[0592] In the light-emitting stage, the light-emitting control circuit 44 controls the connection between the first voltage terminal V1 and the second terminal of the driving circuit 11, and controls the connection between the first terminal of the driving circuit 11 and the first pole of the light-emitting element 40 under the control of the light-emitting control signal, and the driving circuit 11 drives the light-emitting element 40 to emit light.

[0593] exist Fig.65 , Fig.66 , Fig.67 In at least one embodiment of the pixel circuit shown, a third scanning signal can be provided to the third scanning line S3 by a separate third scanning signal generating module, which is beneficial to the freedom of switching the switching frequency under low-frequency flicker (the switching frequency is the switching frequency of the transistor included in the second initialization circuit), but it is not limited thereto. In a specific implementation, the third scanning signal can also be the same scanning signal as the fourth scanning signal.

[0594] When the display panel to which the pixel circuit is applied operates at a low frequency, when the light-emitting control circuit 44 controls the first voltage terminal V1 to be disconnected from the second terminal of the driving circuit 11, and controls the first terminal of the driving circuit 11 to be disconnected from the first pole of the light-emitting element 40, the frequency of the third scanning signal can be increased to reduce flicker.

[0595] In at least one embodiment of the present disclosure, the second scanning signal and the third scanning signal can be the same scanning signal, and the second scanning signal generating module and the third scanning signal generating module can be the same module, but not limited thereto. In a specific implementation, the second scanning signal can also be a different scanning signal from the third scanning signal.

[0596] This disclosure Fig.65 , Fig.66 , Fig.67When at least one embodiment of the pixel circuit shown is in operation, during a non-luminous time period, before the data voltage is written to the second end of the driving circuit 11, the second initialization circuit 42, under the control of the third scanning signal provided by the third scanning line S3, writes the second initial voltage Vi2 provided by the second initial voltage end into the first electrode of the light-emitting element 40 to control the light-emitting element 40 not to emit light and clear the residual charge at the first electrode of the light-emitting element 40.

[0597] In at least one embodiment of the present disclosure, the time interval between the initialization phase and the data writing phase is greater than a predetermined time interval, so as to improve the hysteresis of the driving transistor and reduce high and low frequency flicker of the pixel circuit by initializing the gate potential of the driving transistor in advance.

[0598] During specific implementation, the predetermined time interval may be selected according to actual conditions.

[0599] In this disclosure Fig.65 , Fig.66 , Fig.67 In at least one embodiment of the pixel circuit shown, the initialization control signal and the fourth scan signal provided by the initialization control line R1 can be generated by the same fourth scan signal generating module, the fourth scan signal can be the Nth level fourth scan signal generated by the fourth scan signal generating module, and the initialization control signal can be the NMth level fourth scan signal generated by the fourth scan signal generating module, so as to initialize the potential of the gate of the driving transistor in advance; N is a positive integer, and M can be a positive integer greater than 6, for example, M can be 14, but is not limited to this.

[0600] Optionally, the data writing circuit includes a fourth transistor;

[0601] The control electrode of the fourth transistor is electrically connected to the fourth scan line, the first electrode of the fourth transistor is electrically connected to the data line, and the second electrode of the fourth transistor is electrically connected to the second end of the driving circuit;

[0602] The light emitting control circuit includes a fifth transistor and a sixth transistor;

[0603] The control electrode of the fifth transistor is electrically connected to the light emitting control line, the first electrode of the fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth transistor is electrically connected to the second terminal of the driving circuit;

[0604] The control electrode of the sixth transistor is electrically connected to the light emitting control line, the first electrode of the sixth transistor is electrically connected to the first end of the driving circuit, and the second electrode of the sixth transistor is electrically connected to the first electrode of the light emitting element;

[0605] The second initialization circuit includes a seventh transistor;

[0606] The control electrode of the seventh transistor is electrically connected to the third scan line, the first electrode of the seventh transistor is electrically connected to the second initial voltage terminal, and the second electrode of the seventh transistor is electrically connected to the first electrode of the light emitting element;

[0607] The driving circuit comprises a driving transistor; a control electrode of the driving transistor is electrically connected to a control terminal of the driving circuit, a first electrode of the driving transistor is electrically connected to a first terminal of the driving circuit, and a second electrode of the driving circuit is electrically connected to a second terminal of the driving circuit;

[0608] The energy storage circuit includes a storage capacitor; a first end of the storage capacitor is electrically connected to the control end of the drive circuit, and a second end of the storage capacitor is connected to the first voltage end.

[0609] like Fig.68 As shown, in Fig.65 Based on at least one embodiment of the pixel circuit shown, the light emitting element is an organic light emitting diode O1; the compensation control circuit 12 includes a first transistor T1; the driving circuit 11 includes a driving transistor T0;

[0610] The gate of the first transistor T1 is electrically connected to the first scan line S1, the drain of the first transistor T1 is electrically connected to the gate of the driving transistor T0, and the source of the first transistor T1 is electrically connected to the drain of the driving transistor T1;

[0611] The first initialization circuit 13 includes a second transistor T2;

[0612] The gate of the second transistor T2 is electrically connected to the initialization control line R1, the drain of the second transistor T2 is electrically connected to the first initial voltage terminal, the source of the second transistor T2 is electrically connected to the drain of the driving transistor T0; the first initial voltage terminal is used to provide a first initial voltage Vi1;

[0613] The reset circuit 20 includes a third transistor T3;

[0614] The gate of the third transistor T3 is electrically connected to the second scan line S2, the drain of the third transistor T3 is electrically connected to the reset voltage terminal DR, and the source of the third transistor T3 is electrically connected to the source of the driving transistor T0;

[0615] The data writing circuit 43 includes a fourth transistor T4;

[0616] The gate of the fourth transistor T4 is electrically connected to the fourth scan line S4, the drain of the fourth transistor T4 is electrically connected to the data line D1, and the source of the fourth transistor T4 is electrically connected to the source of the driving transistor T0;

[0617] The light emitting control circuit includes a fifth transistor T5 and a sixth transistor T6;

[0618] The gate of the fifth transistor T5 is electrically connected to the light emitting control line E1, the drain of the fifth transistor T5 is electrically connected to the high voltage terminal, and the source of the fifth transistor T5 is electrically connected to the source of the driving transistor T0; the high voltage terminal is used to provide a high voltage signal VDD;

[0619] The gate of the sixth transistor T6 is electrically connected to the light emitting control line E1, the drain of the sixth transistor T6 is electrically connected to the drain of the driving transistor T0, and the source of the sixth transistor T6 is electrically connected to the anode of the organic light emitting diode O1; the cathode of O1 is electrically connected to a low voltage terminal, and the low voltage terminal is used to provide a low voltage signal VSS;

[0620] The second initialization circuit 42 includes a seventh transistor T7;

[0621] The gate of the seventh transistor T7 is electrically connected to the third scan line S3, the drain of the seventh transistor T7 is electrically connected to the second initial voltage terminal, and the source of the seventh transistor T7 is electrically connected to the anode of the organic light emitting diode O1; the second initial voltage terminal is used to provide a second initial voltage Vi2;

[0622] The energy storage circuit 41 includes a storage capacitor C; a first end of the storage capacitor C is electrically connected to the gate of the driving transistor T0, and a second end of the storage capacitor C is connected to the high voltage end.

[0623] exist Fig.68 In at least one embodiment of the pixel circuit shown, T1 is an oxide thin film transistor, T2, T3, T4, T5, T6 and T7 are low temperature polysilicon thin film transistors, T1 is an n-type transistor, and T2, T3, T4, T5, T6 and T7 are p-type transistors.

[0624] exist Fig.68 In at least one embodiment of the pixel circuit shown, N1 is a first node electrically connected to the gate of T0, N2 is a second node electrically connected to the source of T0, and N3 is a third node electrically connected to the drain of T0.

[0625] exist Fig.68In at least one embodiment of the pixel circuit shown, the initialization control signal and the fourth scanning signal can be provided by the same fourth scanning signal generating module.

[0626] In specific implementation, when the reset voltage provided by DR is a high voltage, the reset phase and the initialization phase are different phases to avoid gate-source short circuit of T0; when the reset voltage provided by DR is a low voltage, the reset phase and the initialization phase can be the same phase.

[0627] like Fig.69 As shown, the present disclosure is Fig.68 When at least one embodiment of the pixel circuit shown is in operation, when the reset voltage provided by DR is a high voltage, the display cycle may include an initialization phase t1, a reset phase t2, a data writing phase t3 and a light emitting phase t4 which are arranged successively;

[0628] In the initialization phase t1, E1 provides a high voltage signal, R1 provides a low voltage signal, S4 provides a high voltage signal, S1 provides a high voltage signal, S2 and S3 both provide high voltage signals, T1 and T2 are turned on to write Vi1 into N1, and the potential of the gate of T0 is initialized so that T0 can be turned on when the data writing phase t3 begins;

[0629] In the reset phase t2, E1 provides a high voltage signal, R1 provides a high voltage signal, S4 provides a high voltage signal, S1 provides a low voltage signal, S2 and S3 both provide low voltage signals, T3 and T7 are turned on, and the high voltage provided by DR is used as the potential of N2 for initialization to reset the gate-source voltage of T0, which is conducive to accelerating the recovery speed of T0, thereby improving the hysteresis phenomenon of T0 and increasing the hysteresis recovery speed; Vi2 is written to the anode of O1 to make O1 non-luminous and clear the residual charge of the anode of O1;

[0630] In the data writing phase t3, E1 provides a high voltage signal, R1 provides a high voltage signal, S4 provides a low voltage signal, S1 provides a high voltage signal, S2 and S3 both provide high voltage signals, T1 is turned on, and T4 is turned on;

[0631] At the beginning of the data writing phase t3, T0 is turned on, and the data voltage Vdata provided by D1 charges C to increase the potential of N1, until T0 is turned off, and the potential of N1 is Vdata+Vth, where Vth is the threshold voltage of T0;

[0632] In the light-emitting stage, E1 provides a low voltage signal, R1 provides a high voltage signal, S4 provides a high voltage signal, S1 provides a low voltage signal, S2 and S3 both provide high voltage signals, T5, T0 and T6 are turned on, and T0 drives O1 to emit light.

[0633] like Fig.70 As shown, the present disclosure is Fig.68 When at least one embodiment of the pixel circuit shown is in operation, when the reset voltage provided by DR is a low voltage, the display cycle may include an initialization phase t1, a data writing phase t3 and a light emitting phase t4 which are arranged successively;

[0634] In the initialization phase t1, E1 provides a high voltage signal, R1 provides a low voltage signal, S4 provides a high voltage signal, S1 provides a high voltage signal, S2 and S3 both provide low voltage signals, T1 and T2 are turned on to write Vi1 into N1, so that T0 can be turned on at the beginning of the data writing phase t3; T3 and T7 are turned on, the reset voltage provided by DR is written into N2, and Vi2 is written into the anode of O1 to reset the gate-source voltage of T0, which is conducive to accelerating the recovery speed of T0, thereby improving the hysteresis phenomenon of T0 and increasing the hysteresis recovery speed; Vi2 is written into the anode of O1 to make O1 non-luminous and clear the residual charge of the anode of O1;

[0635] In the data writing phase t3, E1 provides a high voltage signal, R1 provides a high voltage signal, S4 provides a low voltage signal, S1 provides a high voltage signal, S2 and S3 both provide high voltage signals, T1 is turned on, and T4 is turned on;

[0636] At the beginning of the data writing phase t3, T0 is turned on, and the data voltage Vdata provided by D1 charges C to increase the potential of N1, until T0 is turned off, and the potential of N1 is Vdata+Vth, where Vth is the threshold voltage of T0;

[0637] In the light-emitting stage, E1 provides a low voltage signal, R1 provides a high voltage signal, S4 provides a high voltage signal, S1 provides a low voltage signal, S2 and S3 both provide high voltage signals, T5, T0 and T6 are turned on, and T0 drives O1 to emit light.

[0638] like Fig.71 As shown, the present disclosure is Fig.68 At least one embodiment of the pixel circuit shown is in operation, when the initialization control signal provided by R1 is the fourth scanning signal of the N-14th level, and the fourth scanning signal provided by S4 is the fourth scanning signal of the Nth level, the display cycle may include an initialization phase t1, a reset phase t2, a data writing phase t3, and a light emitting phase t4 which are successively arranged; in the initialization phase t1, E1 provides a high voltage signal, S1 provides a high voltage signal, R1 provides a low voltage signal, S2 and S3 both provide high voltage signals, S4 provides a high voltage signal, T1 and T2 are turned on to write Vi1 into N1, so that T0 can be turned on at the beginning of the data writing phase t3;

[0639] In the reset phase t2, E1 provides a high voltage signal, S1 provides a high voltage signal, R1 provides a high voltage signal, S2 and S3 both provide low voltage signals, S4 provides a high voltage signal, T3 and T7 are turned on, and the high voltage provided by DR is used as the potential of N2 for initialization to reset the gate-source voltage of T0, which is conducive to accelerating the recovery speed of T0, thereby improving the hysteresis phenomenon of T0 and increasing the hysteresis recovery speed; Vi2 is written to the anode of O1 to make O1 non-luminous and clear the residual charge of the anode of O1; T1 is turned on, T2 is turned off, and T5 and T6 are turned off;

[0640] In the data writing phase t3, E1 provides a high voltage signal, S1 provides a high voltage signal, R1 provides a high voltage signal, S2 and S3 both provide high voltage signals, S4 provides a low voltage signal, T1 and T4 are turned on to write Vdata into N2, and N1 and N3 are connected to charge C through the data voltage Vdata on D1, raising the potential of N1 until T0 is turned off, at which time the potential of the gate of T0 is Vdata+Vth;

[0641] In the light-emitting stage t4, E1 provides a low voltage signal, S1 provides a low voltage signal, R1 provides a high voltage signal, S2 and S3 both provide high voltage signals, S4 provides a high voltage signal, T5, T6 and T0 are turned on, and T0 drives O1 to emit light.

[0642] exist Fig.68 In at least one embodiment of the pixel circuit shown, the reset voltage provided by DR may be VDD, or DR and E1 may be the same signal terminal; or the reset voltage provided by D4 may be the third initialization voltage; but the present invention is not limited thereto.

[0643] like Fig.72 As shown, in Fig.67 Based on at least one embodiment of the pixel circuit shown, the light emitting element is an organic light emitting diode O1; the compensation control circuit 12 includes a first transistor T1; the driving circuit 11 includes a driving transistor T0;

[0644] The gate of the first transistor T1 is electrically connected to the first scan line S1, the drain of the first transistor T1 is electrically connected to the gate of the driving transistor T0, and the source of the first transistor T1 is electrically connected to the drain of the driving transistor T1;

[0645] The first initialization circuit 13 includes a second transistor T2;

[0646] The gate of the second transistor T2 is electrically connected to the initialization control line R1, the drain of the second transistor T2 is electrically connected to the first initial voltage terminal, the source of the second transistor T2 is electrically connected to the drain of the driving transistor T0; the first initial voltage terminal is used to provide a first initial voltage Vi1;

[0647] The data writing circuit 43 includes a fourth transistor T4;

[0648] The gate of the fourth transistor T4 is electrically connected to the fourth scan line S4, the drain of the fourth transistor T4 is electrically connected to the data line D1, and the source of the fourth transistor T4 is electrically connected to the source of the driving transistor T0;

[0649] The light emitting control circuit includes a fifth transistor T5 and a sixth transistor T6;

[0650] The gate of the fifth transistor T5 is electrically connected to the light emitting control line E1, the drain of the fifth transistor T5 is electrically connected to the high voltage terminal, and the source of the fifth transistor T5 is electrically connected to the source of the driving transistor T0; the high voltage terminal is used to provide a high voltage signal VDD;

[0651] The gate of the sixth transistor T6 is electrically connected to the light emitting control line E1, the drain of the sixth transistor T6 is electrically connected to the drain of the driving transistor T0, and the source of the sixth transistor T6 is electrically connected to the anode of the organic light emitting diode O1; the cathode of O1 is electrically connected to a low voltage terminal, and the low voltage terminal is used to provide a low voltage signal VSS;

[0652] The second initialization circuit 42 includes a seventh transistor T7;

[0653] The gate of the seventh transistor T7 is electrically connected to the third scan line S3, the drain of the seventh transistor T7 is electrically connected to the second initial voltage terminal, and the source of the seventh transistor T7 is electrically connected to the anode of the organic light emitting diode O1; the second initial voltage terminal is used to provide a second initial voltage Vi2;

[0654] The energy storage circuit 41 includes a storage capacitor C; a first end of the storage capacitor C is electrically connected to the gate of the driving transistor T0, and a second end of the storage capacitor C is connected to the high voltage end.

[0655] exist Fig.72 In at least one embodiment of the pixel circuit shown, T1 is an oxide thin film transistor, T2, T4, T5, T6 and T7 are low temperature polysilicon thin film transistors, T1 is an n-type transistor, and T2, T4, T5, T6 and T7 are p-type transistors.

[0656] exist Fig.72 In at least one embodiment of the pixel circuit shown, N1 is a first node electrically connected to the gate of T0, N2 is a second node electrically connected to the source of T0, and N3 is a third node electrically connected to the drain of T0.

[0657] exist Fig.72 In at least one embodiment of the pixel circuit shown, the third scanning signal and the fourth scanning signal are the same scanning signal, but the present invention is not limited thereto.

[0658] like Fig.73 As shown, the present disclosure is Fig.72 When at least one embodiment of the pixel circuit shown is in operation, a display cycle may include an initialization phase t1, a data writing phase t3 and a light emitting phase t4 which are arranged successively;

[0659] In the initialization phase t1, E1 provides a high voltage signal, R1 provides a low voltage signal, S3 and S4 both provide high voltage signals, S1 provides a high voltage signal, T1 and T2 are turned on to write Vi1 into N1, so that T0 can be turned on when the data writing phase t3 begins;

[0660] In the data writing phase t3, E1 provides a high voltage signal, R1 provides a high voltage signal, S3 and S4 both provide low voltage signals, S1 provides a high voltage signal, T7 is turned on to write Vi2 into the anode of O1, T1 and T4 are turned on to write the data voltage Vdata on D1 into N2, and N1 is connected to N3;

[0661] At the beginning of the data writing phase t3, T0 is turned on, and C is charged through Vdata to increase the potential of the gate of T0 until the potential of the gate of T0 becomes Vdata+Vth, where Vth is the threshold voltage of T0, and T0 is turned off;

[0662] In the light-emitting stage t4, E1 provides a low voltage signal, R1 provides a high voltage signal, S3 and S4 both provide high voltage signals, S1 provides a low voltage signal, T5, T6 and T0 are turned on, and T0 drives O1 to emit light.

[0663] like Fig.74 As shown, the present disclosure is Fig.72 When at least one embodiment of the pixel circuit shown is in operation, when the initialization control signal provided by R1 is the fourth scanning signal of the N-14th level and the fourth scanning signal provided by S4 is the fourth scanning signal of the Nth level, the display cycle may include an initialization phase t1, a data writing phase t3 and a light emitting phase t4 which are successively arranged;

[0664] In the initialization phase t1, E1 provides a high voltage signal, R1 provides a low voltage signal, S3 and S4 both provide high voltage signals, S1 provides a high voltage signal, T1 and T2 are turned on to write Vi1 into N1, so that T0 can be turned on when the data writing phase t3 begins;

[0665] In the data writing phase t3, E1 provides a high voltage signal, R1 provides a high voltage signal, S3 and S4 both provide low voltage signals, S1 provides a high voltage signal, T7 is turned on to write Vi2 into the anode of O1, T1 and T4 are turned on to write the data voltage Vdata on D1 into N2, and N1 is connected to N3;

[0666] At the beginning of the data writing phase t3, T0 is turned on, and C is charged through Vdata to increase the potential of the gate of T0 until the potential of the gate of T0 becomes Vdata+Vth, where Vth is the threshold voltage of T0, and T0 is turned off;

[0667] In the light-emitting stage t4, E1 provides a low voltage signal, R1 provides a high voltage signal, S3 and S4 both provide high voltage signals, S1 provides a low voltage signal, T5, T6 and T0 are turned on, and T0 drives O1 to emit light.

[0668] like Fig.74 As shown, the time interval between the initialization stage t1 and the data writing stage t3 is relatively large, so that the potential of N1 can be reset in advance, which is beneficial to improving the hysteresis phenomenon of T0.

[0669] like Fig.75 As shown, in Fig.66 Based on at least one embodiment of the pixel circuit shown, the light emitting element is an organic light emitting diode O1; the compensation control circuit 12 includes a first transistor T1; the driving circuit 11 includes a driving transistor T0;

[0670] The gate of the first transistor T1 is electrically connected to the first scan line S1, the drain of the first transistor T1 is electrically connected to the gate of the driving transistor T0, and the source of the first transistor T1 is electrically connected to the drain of the driving transistor T1;

[0671] The first initialization circuit 13 includes a second transistor T2;

[0672] The gate of the second transistor T2 is electrically connected to the initialization control line R1, the drain of the second transistor T2 is electrically connected to the first initial voltage terminal, and the source of the second transistor T2 is electrically connected to the first electrode of the driving transistor T0; the first initial voltage terminal is used to provide a first initial voltage Vi1;

[0673] The reset circuit 20 includes a third transistor T3;

[0674] The gate of the third transistor T3 is electrically connected to the second scan line S2, the drain of the third transistor T3 is electrically connected to the reset voltage terminal DR, and the source of the third transistor T3 is electrically connected to the second electrode of the driving transistor T0;

[0675] The data writing circuit 43 includes a fourth transistor T4;

[0676] The gate of the fourth transistor T4 is electrically connected to the fourth scan line S4, the drain of the fourth transistor T4 is electrically connected to the data line D1, and the source of the fourth transistor T4 is electrically connected to the second electrode of the driving transistor T0;

[0677] The light emitting control circuit 44 includes a fifth transistor T5 and a sixth transistor T6;

[0678] The gate of the fifth transistor T5 is electrically connected to the light emitting control line E1, the drain of the fifth transistor T5 is electrically connected to the high voltage terminal, and the source of the fifth transistor T5 is electrically connected to the second electrode of the driving transistor T0; the high voltage terminal is used to provide a high voltage signal VDD;

[0679] The gate of the sixth transistor T6 is electrically connected to the light emitting control line E1, the drain of the sixth transistor T6 is electrically connected to the first electrode of the driving transistor T0, and the source of the sixth transistor T6 is electrically connected to the anode of the organic light emitting diode O1; the cathode of O1 is electrically connected to a low voltage terminal, and the low voltage terminal is used to provide a low voltage signal VSS;

[0680] The second initialization circuit 42 includes a seventh transistor T7;

[0681] The gate of the seventh transistor T7 is electrically connected to the third scan line S3, the drain of the seventh transistor T7 is electrically connected to the second initial voltage terminal, and the source of the seventh transistor T7 is electrically connected to the anode of the organic light emitting diode O1; the second initial voltage terminal is used to provide a second initial voltage Vi2;

[0682] The energy storage circuit 41 includes a storage capacitor C; a first end of the storage capacitor C is electrically connected to the gate of the driving transistor T0, and a second end of the storage capacitor C is connected to the high voltage end.

[0683] exist Fig.75In at least one embodiment of the pixel circuit shown, T1 is an oxide thin film transistor, T2, T3, T4, T5, T6 and T7 are low temperature polysilicon thin film transistors, T1 is an n-type transistor, and T2, T3, T4, T5, T6 and T7 are p-type transistors.

[0684] exist Fig.75 In at least one embodiment of the pixel circuit shown, N1 is a first node electrically connected to the gate of T0, N2 is a second node electrically connected to the second electrode of T0, and N3 is a third node electrically connected to the first electrode of T0.

[0685] exist Fig.75 In at least one embodiment of the pixel circuit shown, the first electrode of T0 may be a drain, and the first electrode of T0 may be a source; or, the first electrode of T0 may be a source, and the second electrode of T0 may be a drain.

[0686] This disclosure Fig.75 In at least one embodiment of the pixel circuit shown, the initialization control signal provided by R1 may be the fourth scanning signal of the N-14th level, and the fourth scanning signal provided by S4 may be the fourth scanning signal of the Nth level, but the present invention is not limited thereto.

[0687] like Fig.76 As shown, the present disclosure is Fig.75 When at least one embodiment of the pixel circuit shown is in operation, a display cycle may include an initialization phase t1, a reset phase t2, a data writing phase t3 and a light emitting phase t4 which are arranged successively;

[0688] In the initialization phase t1, E1 provides a high voltage signal, S1 provides a high voltage signal, R1 provides a low voltage signal, S2 and S3 both provide high voltage signals, S4 provides a high voltage signal, T1 and T2 are turned on to write Vi1 to N1, so that T0 can be turned on when the data writing phase t3 begins;

[0689] In the reset phase t2, E1 provides a high voltage signal, S1 provides a high voltage signal, R1 provides a high voltage signal, S2 and S3 both provide low voltage signals, S4 provides a high voltage signal, T3 and T7 are turned on, and the high voltage provided by DR is used as the potential of N2 for initialization to reset the gate-source voltage of T0, which is conducive to accelerating the recovery speed of T0, thereby improving the hysteresis phenomenon of T0 and increasing the hysteresis recovery speed; Vi2 is written to the anode of O1 to make O1 non-luminous and clear the residual charge of the anode of O1; T1 is turned on, T2 is turned off, and T5 and T6 are turned off;

[0690] In the data writing phase t3, E1 provides a high voltage signal, S1 provides a high voltage signal, R1 provides a high voltage signal, S2 and S3 both provide high voltage signals, S4 provides a low voltage signal, T1 and T4 are turned on to write Vdata into N2, and N1 and N3 are connected to charge C through the data voltage Vdata on D1, raising the potential of N1 until T0 is turned off, at which time the potential of the gate of T0 is Vdata+Vth;

[0691] In the light-emitting stage t4, E1 provides a low voltage signal, S1 provides a low voltage signal, R1 provides a high voltage signal, S2 and S3 both provide high voltage signals, S4 provides a high voltage signal, T5, T6 and T0 are turned on, and T0 drives O1 to emit light.

[0692] The driving method described in at least one embodiment of the present disclosure is applied to the above-mentioned pixel circuit, and the display period includes an initialization phase and a reset phase; the driving method includes:

[0693] In the initialization stage, the first initialization circuit writes the first initial voltage into the first end of the driving circuit under the control of the initialization control signal;

[0694] In the reset phase, the reset circuit writes a reset voltage into the second end of the drive circuit or the first end of the drive circuit under the control of the second scan signal.

[0695] In at least one embodiment of the driving method described in the present disclosure, the reset circuit, under the control of the second scanning signal, writes a reset voltage to the second end of the driving circuit or the first end of the driving circuit during a non-luminous period before the data voltage is written to the second end of the driving circuit, so as to provide a bias voltage to the driving transistor in the driving circuit (at this time, the gate potential of the driving transistor is also initialized to Vi1), so that the driving transistor maintains a reset state, thereby improving the hysteresis of the driving transistor and facilitating the FFR (first frame response time) of the display screen.

[0696] In at least one embodiment of the present disclosure, when in the reset phase, the reset circuit writes the reset voltage to the second end of the driving circuit under the control of the second scanning signal,

[0697] The reset voltage is a high potential constant voltage, the first initial voltage is a low potential constant voltage, the initialization phase and the reset phase are in different time periods; or,

[0698] The reset voltage and the first initial voltage are low potential constant voltages, and the initialization phase and the reset phase are in the same time period or different time periods.

[0699] Optionally, when in the reset phase, the reset circuit writes the reset voltage to the first end of the driving circuit under the control of the second scanning signal, the reset phase and the initialization phase are different time periods, so that in the initialization phase, the first initialization voltage is written to the first end of the driving circuit, and in the reset phase, the reset voltage is written to the first end of the driving circuit.

[0700] In a specific implementation, the pixel circuit may further include a compensation control circuit, and the driving method may further include:

[0701] In the initialization stage, the compensation control circuit controls the control end of the driving circuit to be connected to the first end of the driving circuit under the control of the first scanning signal, so as to write the first initial voltage into the control end of the driving circuit.

[0702] In the driving method described in the embodiment of the present disclosure, the compensation control circuit controls the connection between the control end of the driving circuit and the first end of the driving circuit under the control of the first scanning signal, and the control end of the driving circuit is only directly electrically connected to the compensation control circuit. The first initialization circuit writes the first initial voltage to the first end of the driving circuit under the control of the initialization control signal, and the first initialization circuit is directly electrically connected to the first end of the driving circuit to initialize the potential of the control end of the driving circuit through the compensation control circuit and the first initialization circuit, thereby reducing the leakage path of the control end of the driving circuit. Under the condition that the complexity of the pixel circuit design is not significantly increased, the stability of the voltage of the first node can be guaranteed, which is beneficial to improving the display quality, improving the display uniformity, and reducing Flicker.

[0703] In a specific implementation, the pixel circuit further includes a data writing circuit and an energy storage circuit; the display cycle further includes a data writing phase arranged after the initialization phase; and the driving method further includes:

[0704] In the data writing stage, the data writing circuit writes the data voltage Vdata provided by the data line into the second end of the driving circuit under the control of the fourth scanning signal; the compensation control circuit controls the control end of the driving circuit to be connected to the first end of the driving circuit under the control of the first scanning signal;

[0705] At the beginning of the data writing phase, the driving circuit, under the control of its control end, turns on the connection between the first end of the driving circuit and the second end of the driving circuit to charge the energy storage circuit through the data voltage Vdata, thereby changing the potential of the control end of the driving circuit until the potential of the control end of the driving circuit becomes Vdata+Vth, where Vth is the threshold voltage of the driving transistor included in the driving circuit.

[0706] In a specific implementation, the data writing phase may be arranged after the resetting phase.

[0707] Optionally, the time interval between the initialization phase and the data writing phase is greater than a predetermined time interval, so as to improve the hysteresis phenomenon of the driving transistor and reduce high and low frequency flicker of the pixel circuit by initializing the gate potential of the driving transistor in advance.

[0708] In at least one embodiment of the present disclosure, the pixel circuit further includes a light emitting control circuit, the display period further includes a light emitting phase arranged after the data writing phase; and the driving method includes:

[0709] In the light-emitting stage, the light-emitting control circuit controls the connection between the first voltage terminal and the second terminal of the driving circuit, controls the connection between the first terminal of the driving circuit and the first pole of the light-emitting element under the control of the light-emitting control signal, and the driving circuit drives the light-emitting element to emit light.

[0710] A display device described in at least one embodiment of the present disclosure includes the above-mentioned pixel circuit.

[0711] Optionally, the pixel circuit includes a reset circuit and a second initialization circuit; the display device also includes a second scanning signal generating module and a third scanning signal generating module;

[0712] The reset circuit is electrically connected to the second scan line, and the second initialization circuit is electrically connected to the third scan line;

[0713] The second scanning signal generating module is electrically connected to the second scanning line, and is used for providing a second scanning signal to the second scanning line;

[0714] The third scanning signal generating module is electrically connected to the third scanning line and is used for providing a third scanning signal to the third scanning line.

[0715] Optionally, the second scanning signal and the third scanning signal are the same control signal;

[0716] The second scanning signal generating module and the third scanning signal generating module are the same module.

[0717] like Fig.77 As shown, the display device described in at least one embodiment of the present disclosure includes a display panel, the display panel includes a pixel module P0, and the pixel module P0 includes a plurality of rows and columns of the above-mentioned pixel circuits; the pixel module P0 is arranged in an effective display area of ​​the display panel;

[0718] The display panel further includes a light emitting control signal generating module 70, a first scanning signal generating module 71, a first fourth scanning signal generating module 721, a second fourth scanning signal generating module 722, a second scanning signal generating module 73 and a third scanning signal generating module 74;

[0719] The light emitting control signal generating module 70 is used to provide a light emitting control signal, the first scanning signal generating module 71 is used to provide a first scanning signal, the first fourth scanning signal generating module 721 and the second fourth scanning signal generating module 722 are used to provide a fourth scanning signal, the second scanning signal generating module 73 is used to provide a second scanning signal, and the third scanning signal generating module 74 is used to provide a third scanning signal;

[0720] The light emitting control signal generating module 70, the first scanning signal generating module 71 and the first fourth scanning signal generating module 721 are arranged on the left side of the display panel.

[0721] The second fourth scanning signal generating module 722 , the second scanning signal generating module 73 and the third scanning signal generating module 74 are disposed on the right side of the display panel.

[0722] like Fig.78 As shown, the display device described in at least one embodiment of the present disclosure includes a display panel, the display panel includes a pixel module P0, and the pixel module P0 includes a plurality of rows and columns of the above-mentioned pixel circuits; the pixel module P0 is arranged in an effective display area of ​​the display panel;

[0723] The display panel further includes a light emitting control signal generating module 70, a first first scanning signal generating module 711, a second first scanning signal generating module 712, a first fourth scanning signal generating module 721, a second fourth scanning signal generating module 722 and a third scanning signal generating module 74;

[0724] The light emitting control signal generating module 70 is used to provide a light emitting control signal, the first scanning signal generating module 71 is used to provide a first scanning signal, the first fourth scanning signal generating module 721 and the second fourth scanning signal generating module 722 are used to provide a fourth scanning signal, and the third scanning signal generating module 74 is used to provide a second scanning signal and a third scanning signal;

[0725] The light emitting control signal generating module 70, the first first scanning signal generating module 711 and the first fourth scanning signal generating module 721 are arranged on the left side of the display panel.

[0726] The second fourth scanning signal generating module 722 , the second first scanning signal generating module 712 and the third scanning signal generating module 74 are disposed on the right side of the display panel.

[0727] exist Fig.77 and Fig.78 In the figure, Vi1 is a first initialization voltage, Vi2 is a second initialization voltage, VDD is a high voltage signal, D1 is a data line, and DR is a reset voltage terminal.

[0728] In the embodiments of the present disclosure, reference Figure 6 , Figure 7 , Fig.12 , Fig.14 For example, the width-to-length ratio W / L of the eighth transistor T8 may be approximately equal to the width-to-length ratio W / L of the seventh transistor T7; for another example, the width-to-length ratio W / L of the eighth transistor T8 may be greater than the width-to-length ratio W / L of the seventh transistor T7, that is, the width-to-length ratio W / L of T8 may be slightly larger, so that the N2 node can be quickly reset.

[0729] In the embodiments of the present disclosure, reference Figure 6 , Figure 7 , Fig.12 , Fig.14 The channel width W of the eighth transistor T8 is 1.5-3.5, for example, it can be 1.6, 1.8, 1.9, 2.0, 2.2, 2.5, 3.0, etc.; the channel length L is 2.0-4.5; for example, it can be 2.5, 2.7, 3.0, 3.2, 3.5, 4.0, etc.; the channel width W of the seventh transistor T7 is 1.5-3.5, for example, it can be 1.6, 1.8, 1.9, 2.0, 2.2, 2.5, 3.0, etc.; the channel length L is 2.0-4.5; for example, it can be 2.5, 2.7, 3.0, 3.2, 3.5, 4.0, etc.

[0730] It should be noted that the reference Fig.38a , Fig.50 The above transistor design is also applicable to the seventh transistor T7 and the first thin-body transistor T1 in the embodiment of FIG. 38a; and Fig.50 The fourth transistor T4 and the seventh transistor T7 in the above embodiments.

[0731] In the embodiments of the present disclosure, reference Figure 6 , Figure 7 , Fig.12 , Fig.14For example, the width-to-length ratio W / L of the eighth transistor T8 may be substantially equal to the width-to-length ratio W / L of the first transistor T1; for another example, the width-to-length ratio W / L of the eighth transistor T8 may be smaller than the width-to-length ratio W / L of the first transistor T1, thereby balancing the reset capabilities of the N1 node and the N2 node.

[0732] In the embodiments of the present disclosure, reference Figure 6 , Figure 7 , Fig.12 , Fig.14 The width-to-length ratio W / L of the eighth transistor T8 may be greater than the width-to-length ratio W / L of the first transistor T1 , thereby improving the reset capability of the N2 node.

[0733] In the embodiments of the present disclosure, reference Figure 6 , Figure 7 , Fig.12 , Fig.14 The channel width W of the eighth transistor T8 is 1.5-3.5, for example, it can be 1.6, 1.8, 1.9, 2.0, 2.2, 2.5, 3.0, etc.; the channel length L is 2.0-4.5; for example, it can be 2.5, 2.7, 3.0, 3.2, 3.5, 4.0, etc.; the channel width W of the first transistor T1 is 1.5-3.5, for example, it can be 1.6, 1.8, 1.9, 2.0, 2.2, 2.5, 3.0, etc.; the channel length L is 2.0-4.5; for example, it can be 2.5, 2.7, 3.0, 3.2, 3.5, 4.0, etc.

[0734] It should be noted that the reference Fig.50 The above transistor design also applies Fig.50 The fourth transistor T4 and the third transistor T3 in the above embodiments.

[0735] The display device provided in the embodiments of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

[0736] It should be noted that Figure 1-Figure 78 In all the embodiments shown, the names and numbers of the functional modules / electrical components do not limit the specific functions of the functional modules / electrical components. Figure 3-26 The driving circuit in 1. Figure 27-45 The driving subcircuit in Figure 46-60 The driving circuit 11, Figure 61-48 The driving circuits 11 in all have the same function; for example, Figure 3-26 The second reset circuit 3, Figure 27-45 The second reset subcircuit in Figure 46-60 The reset circuit 20, Figure 61-48The reset circuits 20 in the embodiment all have the same function; for example, Figure 3-26 The third reset circuit 4, Figure 27-45 The first reset subcircuit in Figure 46-60 The second initialization circuit 32, Figure 60-78 The second initialization circuits 42 in all have the same function; for example, Figure 3-26 Threshold compensation circuit 8, Figure 27-45 The second transistor T2 in Figure 46-60 The compensation control circuit 13 and the compensation control circuit 12 have the same function; for example, Figure 3-26 Data writing circuit 7, Figure 27-45 The writing subcircuit in Figure 46-60 Data writing circuit 41, Figure 60-78 The data writing circuits 43 in all have the same function; for example, Figure 3-26 Control circuit 5, Figure 27-45 a first light emitting control subcircuit and a second light emitting control subcircuit, Figure 46-60 The light-emitting control circuit 31 in FIG. 61-78 and the light-emitting control circuit 44 in FIG. 61-78 have the same function; for example, Figure 3-26 Coupling circuit 6, Figure 27-45 The first capacitor C1 in Figure 46-60 Energy storage circuit 42, Figure 61-78 The energy storage circuits 41 in the embodiment all have the same function; for example, Figure 3-26 The driving transistor T3 in Figure 27-45 The driving transistor T3 in Figure 46-60 The driving transistor T0 in Figure 61-78 The driving transistors T0 in the embodiment all have the same function. The functional modules / electrical devices having the same function can be replaced with each other to form a new embodiment, wherein the replacement of the functional modules / electrical devices can include the replacement of the structure of the functional modules / electrical devices themselves and the replacement of the voltage state of the signal terminal connected to the functional modules / electrical devices.

[0737] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and embodiments are to be considered merely as exemplary, and the true scope and spirit of the present disclosure are indicated by the claims.

[0738] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A pixel circuit, characterized in that: include: A driving subcircuit, a writing subcircuit, a compensation subcircuit, a first reset subcircuit, a second reset subcircuit, a first capacitor, a second capacitor and a light-emitting element, wherein: The driving subcircuit is configured to generate a driving current between a first electrode and a second electrode of the driving subcircuit in response to a control signal of a first node; The writing sub-circuit is configured to write a data signal to the second node in response to a signal of the second scanning signal line; The compensation subcircuit is configured to compensate the first node in response to a signal of the first scanning signal line; The first reset subcircuit is configured to write a first reset signal to the anode terminal of the light emitting element; The second reset subcircuit is configured to write a second reset signal to the first pole or the second pole of the driving subcircuit; The second reset signal is greater than the first reset signal; The first capacitor is connected between the first node and the second scanning signal line; The second capacitor is connected between the first node and the first scanning signal line; and the capacitance value of the first capacitor is greater than the capacitance value of the second capacitor.

2. The pixel circuit according to claim 1, characterized in that: A pulse width of a signal of the first reset control signal line is smaller than a pulse width of a signal of the first scanning signal line.

3. The pixel circuit according to claim 1, characterized in that: The capacitance value of the first capacitor is C1, the capacitance value of the second capacitor is C2, and C1 / C2 is greater than or equal to 1.5 and less than or equal to 4.

4. A pixel circuit according to claim 1, characterized in that: Also includes: A first light emission control subcircuit and a second light emission control subcircuit, wherein: The first light emission control subcircuit is configured to provide a signal of the first power supply line to the second node in response to a signal of the first light emission control signal line; The second light-emitting control subcircuit is configured to write a first reset signal of the fourth node into the third node in response to a signal of the second light-emitting control signal line; and is also configured to allow a driving current to pass between the third node and the fourth node in response to a signal of the second light-emitting control signal line.

5. The pixel circuit according to claim 4, characterized in that: The second reset signal is derived from at least one of the following signal lines: the first power line, the first light-emitting control signal line, the second light-emitting control signal line, or a third power line.

6. The pixel circuit according to claim 4, characterized in that: The compensation subcircuit includes a third capacitor, one end of the third capacitor is connected to the first node, the other end of the third capacitor is connected to the first power line, the capacitance value of the third capacitor is greater than the capacitance value of the first capacitor, and the capacitance value of the third capacitor is greater than the capacitance value of the second capacitor.

7. The pixel circuit according to claim 1, characterized in that: Also included is a fourth capacitor, wherein: One end of the fourth capacitor is connected to the second node, and the other end of the fourth capacitor is connected to a fifth node. The equipotential conductive portion of the fifth node is the second scanning signal line.

8. The pixel circuit according to claim 1, characterized in that: The voltage of the second reset signal is a high-potential constant voltage, and the voltage value of the second reset signal is greater than or equal to 4V and less than or equal to 10V; or, the voltage of the second reset signal is a low-potential constant voltage, and the voltage value of the second reset signal is greater than or equal to -6V and less than or equal to -2V.

9. The pixel circuit according to claim 1, characterized in that: The driving subcircuit comprises a third transistor, wherein: The control electrode of the third transistor is connected to the first node, the first electrode of the third transistor is connected to the second node, and the second electrode of the third transistor is connected to the third node; A threshold voltage of the third transistor is greater than or equal to -5V and less than or equal to -2V.

10. The pixel circuit according to claim 1, characterized in that: The driving subcircuit comprises a third transistor, wherein: The control electrode of the third transistor is connected to the first node, the first electrode of the third transistor is connected to the second node, and the second electrode of the third transistor is connected to the third node; An absolute value of a voltage value of the second reset signal is greater than 1.5 times an absolute value of a threshold voltage of the third transistor.

11. The pixel circuit according to claim 1, characterized in that: The pixel circuits in two adjacent rows are electrically connected to the second reset signal line in the same row; the two pixel circuits in adjacent columns are mirror-imaged, and the second reset signal line is a signal line for providing the second reset signal.

12. The pixel circuit according to claim 1, characterized in that: The pixel circuits in two adjacent columns are electrically connected to the second reset signal line in the same column. The two pixel circuits in the adjacent columns are mirror-imaged. The second reset signal line is a signal line that provides the second reset signal.

13. The pixel circuit according to claim 1, characterized in that: The pixel circuits in two adjacent rows are electrically connected to the second reset signal line in the same row, and the pixel circuits in two adjacent columns are electrically connected to the second reset signal line in the same column. The two pixel circuits in adjacent columns are mirror-arranged, and multiple second reset signal lines are arranged in a grid shape. The second reset signal line is a signal line for providing the second reset signal.

14. The pixel circuit according to claim 1, characterized in that: Each row of the pixel circuits is electrically connected to a row of second reset signal lines, a column of second reset signal lines is arranged between multiple columns of the pixel circuits, multiple second reset signal lines are arranged in a grid shape, and the second reset signal lines are signal lines that provide the second reset signals.

15. The pixel circuit according to claim 14, characterized in that: The pixel circuit includes a red pixel circuit column, a green pixel circuit column and a blue pixel circuit column which are arranged in sequence, and the second reset signal line extending along the column direction is arranged at one side of the red pixel circuit column.

16. A display device, characterized in that: Comprising the pixel circuit as claimed in any one of claims 1 to 15.

17. A method for driving a pixel circuit, characterized in that: Used to drive the pixel circuit according to any one of claims 1 to 15, wherein the pixel circuit has multiple scanning cycles, and within one scanning cycle, the driving method comprises: In the reset stage, the first reset subcircuit writes a first reset signal to the anode terminal of the light emitting element; In the reset phase, the second reset subcircuit writes a second reset signal to the first pole or the second pole of the driving subcircuit; the second reset signal is greater than the first reset signal; In the data writing phase, the writing subcircuit writes the data signal to the second node in response to the signal of the second scanning signal line; the compensation subcircuit compensates the first node in response to the signal of the first scanning signal line; In the light emitting stage, the driving sub-circuit generates a driving current between a first electrode and a second electrode of the driving sub-circuit in response to a control signal of the first node.

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