Multi-site multiply-accumulate logic method, multi-site multiply-accumulate and parallel xor computation circuit

Abstract

This invention relates to a point product operation logic method, a multi-point product, and a parallel XOR calculation circuit. The multi-point product operation logic method includes the following steps: a 4-bit operand voltage signal is synchronously input through word lines WL1-WL4 to a memory cell pre-stored with a 1-bit operand; the voltage signals of bit lines BL1-2 and BLB1-2 of the memory cell are acquired and converted into binary numbers representing the voltage signals respectively; the binary number representing the BL1-2 voltage signal is used as the minuend and its difference is calculated with a binary number representing the number of high-level signals in WL1-2, resulting in a binary number representing the difference result of BL1-2; the binary number representing the difference result is then shifted left by two bits and added to the binary number representing the result of the BLB1-2 operation to obtain the desired result. This invention can simultaneously perform multi-point product operations on different word lines to achieve 4'b multiplication.

Description

Technical Field

[0001] This invention relates to the field of in-memory computing technology, and in particular to a multi-point product operation logic method, a multi-point product and parallel XOR calculation circuit. Background Technology

[0002] With the development of in-memory computing, it is now possible to directly use the values ​​in the memory array to perform simulated dot product calculations. This operation method can be applied in a variety of environments, such as applications like machine learning that require a large number of repetitive dot product operations. Using multi-bit vector matrix multiplication (VMM) can increase the efficiency and speed of deep neural network (DNN) inference.

[0003] Given that SRAM is a non-volatile memory structure, it has proven to be one of the mature structures in the CIM system. In-memory computing based on SRAM can significantly reduce data movement, thereby saving the time and energy costs required for data movement.

[0004] Existing multi-bit multiplication designs perform multiplication operations on both sides. The principle is to precharge the bit lines on the left and right sides to obtain different voltages. The multiplication on the left side is implemented through bit line charging logic, and the multiplication on the right side is implemented through discharging logic. At this time, charge transfer occurs simultaneously on both sides of the storage node, and the voltage of the same column is accumulated on the bit line to obtain the analog result. The analog voltage can be quantized by the ADC unit at the bottom to obtain the desired result.

[0005] However, this method will result in spurious writes when all word lines are turned on at the same time. Due to the threshold voltage loss of NMOS, the linearity of the left bit line charging logic is poor, which in turn leads to the final quantization result being unusable due to large errors. Summary of the Invention

[0006] Therefore, it is necessary to provide a multi-point product operation logic method and a multi-point product and parallel XOR calculation circuit to address the problem of large quantization error caused by word line pseudo-writing in existing multi-bit multiplication operations.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] A multi-point product arithmetic logic method is applied to an in-memory computing circuit. The in-memory computing circuit includes a memory array consisting of multiple memory cells. Each memory cell is an 8TSRAM memory cell composed of eight transistors. Each memory cell is connected to four independent word lines WL1 to WL4. Each column of memory cells shares bit lines BL1, BL2, BLB1, and BLB2. Each column of bit lines BL1, BL2 and BLB1, BLB2 are respectively connected to four analog-to-digital converters ADC1, ADC2, ADC3, and ADC4.

[0009] The logical method for multi-point product operation includes the following steps:

[0010] A voltage signal for a 4-bit operand is synchronously input to a memory cell that pre-stores a 1-bit operand via word lines WL1, WL2, WL3, and WL4.

[0011] The voltage signals of the bit lines BL1, BL2 and BLB1, BLB2 of the memory cell are acquired and converted into binary numbers representing the operation results represented by the voltage signals.

[0012] The difference between a binary number representing the voltage signals BL1 and BL2 and a binary number representing the number of high-level signals in WL1 and WL2 is calculated to obtain a binary number representing the difference between BL1 and BL2.

[0013] After shifting the binary number representing the difference result two bits to the left, it is added to the binary number representing the result of the BLB1 and BLB2 operations to obtain the dot product of the 4-bit operand and the 1-bit operand.

[0014] Furthermore, before the voltage signals of the 4-bit operands are input to the memory cell, the voltage signals of bit lines BL1, BL2 and BLB1, BLB2 must be precharged to a high level. The value of the high level is at least 1.2V.

[0015] Furthermore, in the in-memory computing circuit, the tail ends of each column bit line BL1, BL2 and BLB1, BLB2 are respectively connected to a sensitive amplifier SA. The sensitive amplifier SA is connected to the analog-to-digital converters ADC1 to ADC4 through a function selection switch to control the on / off state between each column bit line BL1, BL2 and BLB1, BLB2 and the analog-to-digital converters ADC1 to ADC4.

[0016] Furthermore, the 8TSRAM memory cell includes NMOS transistors N0-N5 and PMOS transistors P0-P1. P0 and N0 form an inverter, and P1 and N1 form another inverter. The two inverters form a cross-coupled structure to latch the data in memory nodes Q and QB. The sources of P0 and P1 are electrically connected to VCC, enabling the power supply path for memory nodes Q and QB. The sources of N0 and N1 are connected to VSS, enabling the ground path for memory nodes Q and QB. N2, N3, N4, and N5 act as transmission transistors, each located on the left and right sides of the cross-coupled structure as dual-port data paths for the SRAM. N2 and N4 form the left path, and N3 and N5 form the right path.

[0017] Furthermore, the gate lengths of transmission tubes N2, N3, N4, and N5 are all the same. The gate widths of transmission tubes N2, N3, N4, and N5 are all the same.

[0018] Furthermore, all memory cells implement SRAM mode, including hold, write, and read operations. During a hold operation, WL1 to WL4 are all held low. The latch structure consisting of P0, N0, P1, and N1 latches the data in memory nodes Q and QB. During a write operation, write word lines WL1 and WL3 are pulled high, and the data to be written is loaded onto the write bit lines. During a read operation, read bit lines BL1 and BLB1 are precharged high, and either read word line WL1 or WL3 is pulled high. After the level signal on read bit lines BL1 and BLB1 is amplified by the sensitive amplifier SA, the result is read.

[0019] Furthermore, the specific method for implementing a write operation in the storage unit is as follows: Before the write operation, if storage node Q is high and QB is low, meaning the stored data is "1", when writing data "0", the write word lines WL1 and WL3 are pulled high, and the data "0" to be written is loaded onto the write bit lines, i.e., BL1 is low and BLB1 is high. BL1 pulls down storage node Q through N2, and BLB1 pulls up storage node QB through N3. The latch structure formed by P0, N0, P1, and N1 is broken, and the data "0" is written into storage nodes Q and QB.

[0020] If, before a write operation, memory node Q is low and QB is high, the stored data is "0". When writing data "1", write word lines WL1 and WL3 are pulled high, and the data "1" to be written is loaded onto the write bit lines, i.e., BL1 is high and BLB1 is low. BL1 pulls up memory node Q through N2, and BLB1 pulls down memory node QB through N3. The latch structure formed by P0, N0, P1, and N1 is broken, and the data "1" is written into memory nodes Q and QB.

[0021] Furthermore, the specific method for implementing a read operation in the storage unit is as follows: Before the read operation, if the storage node Q is high and QB is low, the stored data is "1". At the start of the read operation, read bit lines BL1 and BLB1 are precharged to high, read word lines WL1 or WL3 are pulled high, and N2 or N3 is enabled. Read bit line BL1 remains high, while the level of read bit line BLB1 is pulled low due to the influence of storage node QB. After amplification by the sensitive amplifier SA, the read result is "1".

[0022] If, before a read operation, the storage node Q is low and QB is high, the stored data is "0". At the start of the read operation, read bit lines BL1 and BLB1 are precharged high, read word lines WL1 or WL3 are pulled high, and N2 or N3 is enabled. Read bit line BLB1 remains high, but its level is pulled low by the storage node Q. After amplification by the sensitive amplifier SA, the read result is "0".

[0023] The present invention also relates to a multi-point product and parallel XOR calculation circuit, including a storage array, word line group, bit line group, row and column decoder, word line driver module, precharge module, read and write circuit module, timing control module, ADC module, and shift calculation module.

[0024] The storage array consists of N 2 An N×N array consisting of identical storage cells. Each storage cell contains storage nodes Q and QB that are opposite to each other.

[0025] The word line group includes N 2 Word lines WL1 to WL4. Each memory cell is connected to a set of word lines WL1 to WL4.

[0026] The bit line group consists of N groups BL1, BLB1, BL2, and BLB1. Each memory cell in each column is connected to the same group of bit lines BL1, BLB1, BL2, and BLB1.

[0027] Row and column decoders are used to convert externally input address signals into row and column control timing signals.

[0028] The word line driver module is used to control the word line of any memory cell to drive the on / off state of the transmission tube connected to the word line.

[0029] The precharge module is used to precharge the bit lines of each column of memory cells in the memory array with level signals.

[0030] The read / write circuit module is used to control the read and write operations of each memory cell in the memory array in SRAM mode.

[0031] The timing control module is used to provide the timing signals required for the circuit to operate.

[0032] The ADC module is used to convert the calculation results of each column of storage cells in the storage array into digital quantities.

[0033] The shift calculation module is used to perform subtraction and shift operations on the digital quantity output by the ADC module, and output the calculation result.

[0034] In particular, when multi-point product and parallel XOR calculation circuits perform multi-point product operations, they employ the multi-point product operation logic method described above.

[0035] Furthermore, the multi-point product and parallel XOR calculation circuits implement parallel XOR in the following ways:

[0036] The three 1-bit operands to be XORed are denoted as XOR values ​​A, B, and XORed value C. The voltage signal of the XORed value C is pre-written into the memory cell to be XORed using SRAM write data mode, and its bit lines BL1, BL2 and BLB1, BLB2 are pre-charged to high level.

[0037] The XOR value A and its inverse voltage signal are input to the memory cell through a symmetrical pair of word lines, and the XOR value B and its inverse voltage signal are input to the memory cell through another symmetrical pair of word lines. The two symmetrical pairs of bit lines are WL1 and WL3, and WL2 and WL4, respectively.

[0038] The XOR result of bit lines BL1 and BLB1 of the memory cell is obtained by adding the values ​​output by analog-to-digital converters ADC1 and ADC3 respectively. The XOR result of bit line BL2 and BLB2 is obtained by adding the values ​​output by analog-to-digital converters ADC2 and ADC4 respectively.

[0039] The technical solution provided by this invention has the following beneficial effects:

[0040] The dual-port memory cell array structure designed in this invention enables simultaneous multiplication operations on the left and right paths by using different encoding logics for the left and right sides, avoiding the single-sided linearity difference introduced by traditional simultaneous left and right multiplication operations. Furthermore, since both sides are pre-charged to the same potential simultaneously, the spurious write phenomenon of traditional structures is also avoided. Multi-point product operations can be implemented through external circuitry and control signals, increasing the efficiency and speed of deep neural network inference. By reducing the bit line voltage and using the same type of transmission transistor for all memory cells, the memory cells are made more stable and maintain a certain degree of linearity. Attached Figure Description

[0041] Figure 1 This is a circuit structure diagram of an 8TSRAM memory cell in Embodiment 1 of the present invention;

[0042] Figure 2 For based on Figure 1 A schematic diagram of a parallel XOR computation structure implemented using 4×4 8T-SRAM cells;

[0043] Figure 3 For based on Figure 2 A schematic diagram of a parallel XOR computation structure implemented by a single-column 8T-SRAM cell;

[0044] Figure 4 For based on Figure 3 A timing diagram illustrating parallel XOR computation;

[0045] Figure 5 This is a schematic diagram of the overall architecture of the multi-point multiplication and parallel XOR calculation circuit with 64×64 8T-SRAM cells in Example 2;

[0046] Figure 6 For based on Figure 1 A schematic diagram of a structure that enables simultaneous multiplication of 4'b data based on 2×2 8T-SRAM cells;

[0047] Figure 7 This is a flowchart of the multi-point product operation logic method in Example 1. Detailed Implementation

[0048] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0049] Example 1

[0050] This embodiment introduces a multi-point product operation logic method applied to an in-memory computing circuit. First, a brief description of the in-memory computing circuit is given. This in-memory computing circuit includes a memory array composed of multiple memory cells. Each memory cell is connected to four independent word lines WL1 to WL4. Each column of memory cells shares bit lines BL1, BL2, BLB1, and BLB2. Each column of bit lines BL1, BL2 and BLB1, BLB2 are respectively connected to analog-to-digital converters ADC1, ADC2, ADC3, and ADC4.

[0051] Each memory cell includes four NMOS transmission transistors N2 to N5 and two memory nodes Q and QB. The gates of N2 to N5 are connected to four word lines WL1 to WL4, and the sources of N2 to N5 are connected to four bit lines BL1, BL2, BLB1, and BLB2. N2 and N4 are connected to memory node Q, and N3 and N5 are connected to memory node QB. Q and QB are inverses of each other.

[0052] Please see Figure 7 Based on in-memory computing circuits, the multi-point product operation logic method includes the following steps:

[0053] A voltage signal for a 4-bit operand is synchronously input into a memory cell that pre-stores a 1-bit operand through word lines WL1, WL2, WL3, and WL4.

[0054] The voltage signals of the bit lines BL1, BL2 and BLB1, BLB2 of the memory cell are acquired and converted into binary numbers representing the operation results represented by the voltage signals.

[0055] The difference between a binary number representing the voltage signals BL1 and BL2 and a binary number representing the number of high levels in WL1 and WL2 is calculated to obtain a binary number representing the difference between BL1 and BL2.

[0056] After shifting the binary number representing the difference result two bits to the left, it is added to the binary number representing the result of the BLB1 and BLB2 operations to obtain the dot product of the 4-bit operand and the 1-bit operand.

[0057] The method in this embodiment is used to output the dot product result of four weighted operands according to their weight order to obtain the final dot product result. Specifically, the binary numbers obtained by subtracting BL1 and BL2 on the left are taken as the high-order bits, and the binary numbers obtained by converting BLB1 and BLB2 on the right are taken as the low-order bits. Therefore, a left shift operation of two bits is required on the left side to achieve this high-order output.

[0058] To facilitate understanding of the specific computational steps for multi-point product operations in this embodiment, a detailed description is provided below for one of the storage cells in the storage array:

[0059] Please combine Figure 1 Understand the circuit structure of this embodiment. Figure 1This is a circuit diagram of a single 8TSRAM memory cell. The four word lines WL1-WL4 of the memory cell serve as input ports for a four-bit operand. The memory cell stores a one-bit operand. Before performing an operation, the four bit lines BL1, BL2, BLB1, and BLB2 are pre-charged to a high level. The input four-bit operand is converted into appropriate high and low word line voltages, for example, VDD represents signal "1" and GND represents signal "0," and applied to the four word lines WL1, WL2, WL3, and WL4 respectively. If the input is high, the transmission transistor connected to that word line is turned on; if the input is low, the transmission transistor connected to that word line is turned off, thus controlling the on / off state of the transmission transistors. For example, WL1 and WL2 are located on the left side of the memory cell and connected to memory node Q via transmission transistors N2 and N4 respectively, and WL3 and WL4 are located on the left side of the memory cell and connected to memory node QB via transmission transistors N3 and N5 respectively. BL1 and BL2 output the product of the operands represented by WL1 and WL2 and the data of storage node Q, respectively. BLB1 and BLB2 output the product of the operands represented by WL3 and WL4 and the data of storage node Q, respectively. Since the outputs of BL1 and BL2 are not the final desired result, a subtraction operation is required to obtain the desired result, which is then combined with the outputs of BLB1 and BLB2 to form the final dot product result.

[0060] To further understand the implementation of multi-point product operation in this embodiment, a specific random numerical operation will be used for explanation. Assume the data stored in the memory cell is "1", i.e., Q = 1, QB = 0, and the external input operand is (1, 1, 1, 1). A high level is applied to WL1 to WL4, at which point transmission transistors N2 to N5 are all turned on. Since BL1, BL2, BLB1, and BLB2 are all pre-charged to a high level, and Q is at a high level, the voltage on BL1 and BL2 remains unchanged; therefore, the outputs of BL1 and BL2 are 0. Because QB is at a low level while BLB1 and BLB2 are at a high voltage, charge transfer occurs, causing a voltage drop in BLB1 and BLB2, decreasing by ΔV respectively, resulting in the outputs of BLB1 and BLB2 being 1.

[0061] In the above calculations, voltage drops occur in BL1 and BL2 only when Q is 0, therefore, the WL1 and WL2 side actually performs a 1×0 operation. Conversely, voltage drops occur in BLB1 and BLB2 only when QB = 0, therefore, the WL3 and WL4 side actually performs a 1×1 operation. Since any number multiplied by 0 equals 0, the final dot product is all 1×1 numbers. Therefore, a subtraction operation is needed on the outputs of BL1 and BL2, i.e., counting the total number of high-level values ​​in WL1 and WL2. Since it is a binary multiplication calculation, this total count includes the sum of 1×1 and 1×0 results from the WL1 and WL2 side. Subtracting this total count from the digital outputs of BL1 and BL2 yields the 1×1 operation result from the WL1 and WL2 side. As shown in the equation, N input1 =N 1×1 +N 1×0 => N 1×1 =N input1 -N 1×0 , where N input1 N is the number of high-level signals on WL1 and WL2. 1×0 N is the digital value of the output results of BL1 and BL2. 1×1 This is the result of a 1×1 operation on the required WL1 and WL2 sides. Taking the above values ​​as an example, we can obtain N. 1×0 =0, N input1 =2, therefore >N 1×1 =N input1 -N 1×0 =2, and the values ​​on both sides are added together to get 4, which is the dot product of (1, 1, 1, 1) and 1.

[0062] In the above operation, the operands are random numbers. In actual calculations, the operands have weights, i.e., X3X2X1X0 = 1111. Therefore, the quantized results on both sides cannot be added together. After the voltage signal of the 4-bit operand passes through WL1, WL2, WL3 and WL4, the operation process is the same as above. However, after acquiring the voltage signals of BL1, BL2 and BLB1, BLB2, the voltage signals of BL1 and BL2 are quantized into one binary number, and the voltage signals of BLB1 and BLB2 are quantized into another binary number. Since the output of BL1 and BL2 is the high bit, the quantized result needs to be shifted left by two bits. Then, it is added to the quantized result of BLB1 and BLB2 to obtain the final result.

[0063] The specific connection structure of the 8TSRAM memory cell used in this embodiment is described in detail below: The 8TSRAM memory cell includes NMOS transistors N0-N5 and PMOS transistors P0-P1. P0 and N0 form an inverter, and P1 and N1 form another inverter. The two inverters form a cross-coupled structure to latch the data of memory nodes Q and QB. The source of P0 and the source of P1 are electrically connected to VCC, enabling the power supply path of memory nodes Q and QB. The source of N0 and the source of N1 are connected to VSS, enabling the ground path of memory nodes Q and QB. N2, N3, N4, and N5 serve as transmission transistors, each located on the left and right sides of the cross-coupled structure as SRAM dual-port data paths. N2 and N4 form the left path, and N3 and N5 form the right path. The drain of P0 is electrically connected to the gate of P1, the drain of N0, the drain of N2, the gate of N1, and the drain of N4. The gate of P0 is electrically connected to the drain of P1, the drain of N1, the drain of N3, the gate of N0, and the drain of N5. It is important to emphasize that all transfer transistors in all 8TS RAM memory cells use the same type and specification, thereby enhancing the stability of the memory cells.

[0064] Taking an 8TSRAM memory cell as an example, the SRAM mode is explained in detail. The SRAM mode includes hold operations, write operations, and read operations. The specific steps are as follows:

[0065] (1) Maintain operation

[0066] During the data retention period in the memory cell, write word lines WL1, WL2, WL3, and WL4 are all kept at a low level. At this time, NMOS transistors N2, N3, N4, and N5 are all turned off, and write bit lines BL1, BL2, BLB1, and BLB2 do not affect memory nodes Q or QB. The latch structure composed of PMOS transistor P0, NMOS transistor N0, PMOS transistor P1, and NMOS transistor N1 will latch the data in memory nodes Q and QB.

[0067] (2) Write operation

[0068] Assuming that before the write operation, memory node Q is high and QB is low, meaning the stored data is "1", when writing data "0", the write operation word lines WL1 and WL3 are pulled high to select the cell, and the data "0" to be written is loaded onto the write bit lines, i.e., BL1 is low and BLB1 is high. BL1 pulls down node Q through NMOS transistor N2, and BLB1 pulls up node QB through NMOS transistor N3. The feedback loop of the storage structure is broken, and the data "0" is written into memory nodes Q and QB.

[0069] Assume that before the write operation, memory node Q is low and QB is high, meaning the stored data is "0". When writing data "1", write word lines WL1 and WL3 are pulled high, and the data "1" to be written is loaded onto the write bit lines, i.e., BL1 is high and BLB1 is low. BL1 pulls up memory node Q through N2, and BLB1 pulls down memory node QB through N3. The latch structure formed by P0, N0, P1, and N1 is broken, and the data "1" is written into memory nodes Q and QB.

[0070] (3) Read operation

[0071] Assume that before the read operation, the storage node Q is high and QB is low, meaning the stored data is "1". At the start of the read operation, read bit lines BL1 and BLB1 are pre-charged to high, read word lines WL1 or WL3 are pulled high, and NMOS transistor N2 or NMOS transistor N3 is turned on. Read bit line BL1 remains high, while read bit line BLB1 is pulled low due to the voltage inside the storage node. The read result is "1".

[0072] Assume that before the read operation, the storage node Q is low and QB is high, meaning the stored data is "0". At the start of the read operation, read bit lines BL1 and BLB1 are precharged high, read word lines WL1 or WL3 are pulled high, and N2 or N3 is enabled. Read bit line BLB1 remains high, but its level is pulled low by the influence of storage node Q, resulting in a read value of "0".

[0073] The storage array in this embodiment can be distributed as N×N, such as 2×2, 4×4, etc. Figure 6 This illustrates an 8TSRAM memory array with a 2×2 array configuration. (By...) Figure 6 As can be seen, the word lines of each 8TSRAM memory cell are not shared. An external control circuit controls the high and low levels of the word lines of all 8TSRAM memory cells. The bit lines of each column of 8TSRAM memory cells are shared, and an external pre-charge circuit controls their high and low levels. The bit lines are converted to digital by an analog-to-digital converter (ADC), which outputs the multiplication results on both sides. A subsequent calculation yields the final dot product. This memory array structure can achieve 4'b multiplication operations without increasing the number of transistors. It adapts well to SRAM read / write methods, increases structural reusability, and significantly improves data interference immunity, making it suitable for various complex application scenarios.

[0074] It should be noted that the tail ends of each column bit line BL1, BL2 and BLB1, BLB2 are respectively connected to the sensitive amplifier SA. The sensitive amplifier SA is connected to the analog-to-digital converters ADC1 to ADC4 through a function selection switch to control the on / off state between each column bit line BL1, BL2 and BLB1, BLB2 and the analog-to-digital converters ADC1 to ADC4.

[0075] Based on the above design, the dual-port 8T-SRAM array architecture designed in this embodiment can be configured as a multi-point multiplication engine similar to that in memory. Without sacrificing parallel computing efficiency, it can perform 4'b data multiplication operations simultaneously. It adds two ports to the original 6T SRAM bit cell, and by using different encoding logics for the left and right paths, multiplication operations can be performed simultaneously on both paths, avoiding the poor linearity of one side introduced by traditional simultaneous left and right multiplication operations. Because both sides are precharged to the same potential simultaneously, the pseudo-write phenomenon of traditional structures is also avoided. Multi-point product operations can be implemented through external circuitry and control signals, increasing the efficiency and speed of deep neural network inference. By reducing the bit line voltage and using the same type of transmission transistor and precharge level for both sides, the memory cell becomes more stable and maintains a certain degree of linearity.

[0076] Example 2

[0077] Please see Figure 5 This embodiment introduces a multi-point product and parallel XOR calculation circuit, including a memory array, word line group, bit line group, row decoder, word line driver module, precharge control module, peripheral read-write circuit module, timing control module, ADC module, and shift calculation module.

[0078] The storage array consists of N 2 An N×N array consisting of identical storage cells. Each storage cell contains storage nodes Q and QB that are opposite to each other.

[0079] The word line group includes N 2 Word lines WL1 to WL4. Each memory cell is connected to a set of word lines WL1 to WL4.

[0080] The bit line group consists of N groups BL1, BLB1, BL2, and BLB1. Each memory cell in each column is connected to the same group of bit lines BL1, BLB1, BL2, and BLB1.

[0081] Row and column decoders are used to convert externally input address signals into row and column control timing signals.

[0082] The word line driver module is used to control the word line of any memory cell to drive the on / off state of the transmission tube connected to the word line.

[0083] The precharge module is used to precharge the bit lines of each column of memory cells in the memory array with level signals.

[0084] The read / write circuit module is used to control the read and write operations of each memory cell in the memory array in SRAM mode.

[0085] The timing control module is used to provide the timing signals required for the circuit to operate.

[0086] The ADC module is used to convert the calculation results of each column of storage cells in the storage array into digital quantities.

[0087] The shift calculation module is used to perform subtraction and shift operations on the digital quantity output by the ADC module, and output the calculation result.

[0088] Specifically, when the multi-point product and parallel XOR calculation circuit performs the multi-point product operation, it employs the multi-point product operation logic method as described above. Therefore, this embodiment can implement the multi-point product and parallel XOR operation of Embodiment 1.

[0089] The in-memory computing circuit of this embodiment performs parallel XOR operations as follows: The three 1-bit operands to be XORed are denoted as XOR values ​​A and B, and the XORed value C. The voltage signal of the XORed value C is pre-written into the memory cell to be XORed via SRAM write data mode, and its bit lines BL1, BL2 and BLB1, BLB2 are pre-charged to VDD.

[0090] The voltage signals of the XOR value A and its inverse are input into the memory cell through a pair of symmetrical word lines, respectively. The voltage signals of the XOR value B and its inverse are input into the memory cell through another pair of symmetrical word lines. The two pairs of symmetrical bit lines are WL1 and WL3, and WL2 and WL4, respectively.

[0091] The XOR result of bit lines BL1 and BLB1 of the memory cell is obtained by adding the values ​​output by analog-to-digital converters ADC1 and ADC3 respectively. The XOR result of bit line BL2 and BLB2 is obtained by adding the values ​​output by analog-to-digital converters ADC2 and ADC4 respectively.

[0092] To further understand the parallel XOR calculation described above, the operation method is explained in detail with specific numerical values: Please refer to [link / reference]. Figure 2 and Figure 3 , Figure 2A memory array with a 4×4 array configuration is shown. Figure 3 for Figure 2 Taking the first storage cell in the storage array as an example, in one column of the storage cells, WL1 and WL3 are used as input terminals for the XOR value A and its inverse, and WL2 and WL4 are used as input terminals for the XOR value B and its inverse. Assume that the data inputting the XOR value A (i.e., XOR value 0) and the stored data (i.e., XOR value 1) are XORed. Then, the value stored in the storage cell is "1", meaning the storage node Q is high and QB is low (Q = VDD, QB = 0V). The left word line WL1 port inputs the XOR value to be calculated (0), which is a low-level signal, and the right word line WL3 port inputs the inverted XOR value (1), which is a high-level signal. At this time, NMOS transistor N2 is off, so BL1 cannot affect the charge of node Q through N2. BLB1 pulls up node QB through NMOS transistor N3, resulting in a voltage drop on bit line BLB1. Using the bottom-end ADC1 and ADC3, the analog values ​​of the corresponding left and right bit lines (BL1 and BLB1) are quantized into digital values ​​and added together to obtain the result of the XOR operation of the XOR value "1" and the XORed value "0". It is worth noting that the above is only an example of a one-bit XOR operation. This design has two ports and four independent bit lines (BL1, BLB1, BL2, BLB2) and word lines (WL1, WL3, WL2, WL4). Therefore, it can be configured as a 2-bit XOR operation engine. The other XOR operation in the same memory cell is implemented by port B (WL2 and WL4), and the principle is the same as that of port A. The timing of the XOR operation is as follows: Figure 4 As shown.

[0093] The following is combined Figure 5 The circuit structure of this embodiment will be described in detail below. Figure 5 In this configuration, the 8TSRAM storage array is 64×64. Each column of 8TSRAM storage cells is connected to a set of bit lines BL1, BLB1, BL2, BLB1. Each 8TSRAM storage cell in each row has a set of word lines WL1 to WL4, so the word lines are not shared.

[0094] Based on the above circuit structure, the principle of implementing the storage function is the same: word lines locate each storage cell, and bit lines retrieve the data stored in the storage nodes of the storage cells. The following section provides a detailed explanation of multi-point product operations and parallel XOR operations.

[0095] 1. Multi-dot product operation

[0096] The storage array provided in this embodiment is an 8TSRAM storage array with a 64×64 distribution. Multiplication is performed by converting an external four-bit operand into corresponding high and low levels and multiplying it with a single operand pre-stored in storage node Q of the 8TSRAM storage cell. It is important to emphasize that when a storage cell performs a dot product operation, only one side actually performs the multiplication and outputs the result. This is because storage nodes Q and QB are inverse complements of each other, and the result is obtained based on the voltage drop of the bit lines. Therefore, only one side of the bit lines BL1, BL2 or BLB1, BLB2 will experience a voltage drop. Since the dot product operation in this embodiment uses the data stored in storage node Q as a single operand, a voltage drop will only occur in BLB1 and BLB2 when storage node QB is low (i.e., Q = 1). Therefore, the output result of BLB1 and BLB2 will only be 1×1. Conversely, on the BL1 and BL2 side, a voltage drop only occurs on the bit line when Q is low (i.e., Q is 0). Therefore, the output of the BL1 and BL2 side will only be 1×0. However, the result of 1×0 is 0, while the dot product ultimately yields 1×1. Therefore, BL1 and BL2 need to perform an additional subtraction operation. The number of times word lines WL1 and WL2 are set to high level within one cycle is subtracted from the original result of BL1 and BL2 to obtain the required 1×1 result. This is because when word lines WL1 and WL2 are high level, it represents that the external input operand is 1. Regardless of whether the storage node Q stores 1 or 0, a multiplication operation will still occur. However, a voltage drop only occurs on the bit line when Q is 0. Therefore, the number of times WL1 and WL2 are set to high level represents the sum of 1×0 and 1×1 on that side.

[0097] When the four operands are random numbers, the result of the left column of any column of 8TSRAM memory cells is amplified by SA and converted by ADC, and then subtracted. This result is then added to the result of the right column of 8TSRAM memory cells after SA amplification and ADC conversion. This sums up the result of the right column of 8TSRAM memory cells after SA amplification and ADC conversion. This sums up the results of all columns. This sums up the result of the dot product operation of all the 8TSRAM memory cells that are located.

[0098] When the four operands have weights, the results of BL1, BL2 and BLB1, BLB2 need to be converted by ADC and then shifted according to the weight order of the operands in order to obtain the corresponding dot product result.

[0099] 2. Parallel XOR computation

[0100] In this embodiment, by outputting operands that are inverses of each other on the left and right sides of each 8TSRAM memory cell, a two-bit XOR operation can be performed simultaneously. According to Figure 2As shown, taking the XOR operation of 4×4 adjacent 8TSRAMs in the memory array as an example, the word line control module controls the word lines of four 8TSRAMs in a row through two inverters. The word line control module inputs the word line signal to the word lines WL1 and WL2 on the left side of the 8TSRAM through two inverters, and to the word lines WL3 and WL4 on the right side of the 8TSRAM through one inverter, so that the output signals of the word lines on both sides of the 8TSRAM memory cell are inversely related. Since the result of the XOR calculation is output through the bit line, in order to obtain the final XOR result, the output results of the four bit lines in each column need to be amplified by SA and converted by ADC, and then added by adder to obtain the XOR result of one column. The results of all columns are accumulated to obtain the final result of the XOR operation of all the memory cells located in the memory array.

[0101] It is important to emphasize that in practical applications, the high-level voltages of the bit lines and word lines are not the same. The high-level voltage of the bit lines is more than four times that of the word lines. The voltage supplied to the word lines should just be enough to turn on the transmission transistors. On the same bit line, the ΔV value generated by each voltage drop is small. Therefore, even if all the transmission transistors on a bit line are turned on, the output result on a bit line will still be within the allowable error range because the high voltage on the bit lines is much greater than that on the word lines.

[0102] It should be noted that the 4×4 and 64×64 storage arrays are merely examples used to illustrate the solution in this embodiment, and are not intended to limit the scope of this case.

[0103] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0104] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A logical method for multi-point product operation, characterized in that, It is applied to in-memory computing circuits; the in-memory computing circuits include a memory array composed of multiple memory cells; the memory cells are 8TSRAM memory cells composed of eight transistors; each memory cell is connected to four independent word lines WL1~WL4; each column of memory cells shares bit lines BL1, BL2, BLB1, and BLB2; each column of bit lines BL1, BL2 and BLB1, BLB2 are respectively connected to four analog-to-digital converters ADC1, ADC2, ADC3, and ADC4; The multi-point product operation logic method includes the following steps: A voltage signal for a 4-bit operand is synchronously input into a memory cell that pre-stores a 1-bit operand through word lines WL1, WL2, WL3, and WL4. The voltage signals of the bit lines BL1, BL2 and BLB1, BLB2 of the memory cell are acquired and converted into binary numbers representing the operation results represented by the voltage signals. The difference between a binary number representing the voltage signals BL1 and BL2 and a binary number representing the number of high levels in WL1 and WL2 is calculated to obtain a binary number representing the difference between BL1 and BL2. After shifting the binary number representing the difference result two bits to the left, add it to the binary number representing the result of BLB1 and BLB2 to obtain the dot product of the 4-bit operand and the 1-bit operand. The 8TSRAM memory cell includes NMOS transistors N0~N5 and PMOS transistors P0~P1; the gates of N2~N5 are connected to four word lines WL1~WL4, and the sources of N2~N5 are connected to four bit lines BL1, BL2, BLB1, and BLB2, respectively; N2 and N4 are connected to memory node Q, and N3 and N5 are connected to memory node QB; P0 and N0 form an inverter, and P1 and N1 form another inverter. The device forms a cross-coupled structure to latch the data of storage nodes Q and QB. The source of P0 and the source of P1 are electrically connected to VCC, enabling the power supply path of storage nodes Q and QB. The source of N0 and the source of N1 are connected to VSS, enabling the ground path of storage nodes Q and QB. N2, N3, N4 and N5 are transmission transistors, each located on the left and right sides of the cross-coupled structure as SRAM dual-port data paths. N2 and N4 form the left path, and N3 and N5 form the right path.

2. The multi-point product operation logic method according to claim 1, characterized in that, Before the voltage signals of the 4-bit operands are input to the storage unit, the voltage signals of bit lines BL1, BL2 and BLB1, BLB2 need to be precharged to a high level; the value of the high level is at least 1.2V.

3. The multi-point product operation logic method according to claim 2, characterized in that, In the in-memory computing circuit, the tail ends of each column bit line BL1, BL2 and BLB1, BLB2 are respectively connected to a sensitive amplifier SA. The sensitive amplifier SA is connected to the analog-to-digital converters ADC1~ADC4 through a function selection switch to control the on / off state between each column bit line BL1, BL2 and BLB1, BLB2 and the analog-to-digital converters ADC1~ADC4.

4. The multi-point product operation logic method according to claim 1, characterized in that, The gate lengths of transmission tubes N2, N3, N4, and N5 are all the same; the gate widths of transmission tubes N2, N3, N4, and N5 are all the same.

5. The multi-point product operation logic method according to claim 1, characterized in that, All memory cells implement SRAM mode, including hold, write, and read operations. When a memory cell performs a hold operation, WL1 to WL4 are all kept low. The latch structure composed of P0, N0, P1, and N1 latches the data of memory nodes Q and QB. When a memory cell performs a write operation, the write word lines WL1 and WL3 are pulled high, and the data to be written is loaded onto the write bit lines. When a memory cell performs a read operation, the read bit lines BL1 and BLB1 are precharged to high, and the read word line WL1 or WL3 is pulled high. After the level signal on the read bit lines BL1 and BLB1 is amplified by the sensitive amplifier SA, the result is read.

6. The multi-point product operation logic method according to claim 5, characterized in that, The specific method for implementing the write operation in the storage unit is as follows: If the storage node Q is high and QB is low before the write operation, that is, the stored data is "1"; when writing the data "0", the write word lines WL1 and WL3 are pulled to high level, and the data "0" to be written is loaded onto the write bit line, that is, BL1 is low level and BLB1 is high level; BL1 pulls down the storage node Q through N2, and BLB1 pulls up the storage node QB through N3. The latch structure formed by P0, N0, P1 and N1 is broken, and the data "0" is written into the storage nodes Q and QB; If, before the write operation, the storage node Q is at a low level and QB is at a high level, meaning the stored data is "0", when writing the data "1", the write word lines WL1 and WL3 are pulled high, and the data "1" to be written is loaded onto the write bit lines, meaning BL1 is high and BLB1 is low. BL1 pulls up the storage node Q through N2, and BLB1 pulls down the storage node QB through N3. The latch structure formed by P0, N0, P1, and N1 is broken, and the data "1" is written into the storage nodes Q and QB.

7. The multi-point product operation logic method according to claim 6, characterized in that, The specific method for implementing the read operation in the storage unit is as follows: If the storage node Q is high and QB is low before the read operation, that is, the stored data is "1"; at the start of the read operation, the read bit line BL1 and BLB1 are precharged to high level, the read word line WL1 or WL3 is pulled to high level, and N2 or N3 is turned on; the read bit line BL1 remains high level, and the level of the read bit line BLB1 is pulled low by the influence of the storage node QB. After being amplified by the sensitive amplifier SA, the read result is "1"; If the storage node Q is low and QB is high before the read operation, the stored data is "0". At the start of the read operation, the read bit lines BL1 and BLB1 are precharged to high, the read word lines WL1 or WL3 are pulled high, and N2 or N3 is enabled. The read bit line BLB1 remains high. The level of the read bit line BL1 is pulled low by the storage node Q. After being amplified by the sensitive amplifier SA, the read result is "0".

8. A multi-point product and parallel XOR calculation circuit, comprising: Storage array, which consists of N 2 An N×N array consisting of identical storage units; Each storage unit contains storage nodes Q and QB that are opposite to each other; Word line group, which includes N 2 Word lines WL1~WL4; each memory cell is connected to a set of word lines WL1~WL4; Bit line groups, which include N groups BL1, BLB1, BL2, and BLB1; each memory cell in each column is connected to the same group of bit lines BL1, BLB1, BL2, and BLB1; A row and column decoder is used to convert externally input address signals into row and column control timing signals; Word line driver module, which is used to control the word line of any memory cell to drive the on / off state of the transmission tube connected to the word line; The precharge module is used to precharge the bit lines of each column of memory cells in the memory array with level signals. The read / write circuit module is used to control the read and write operations of each memory cell in the memory array in SRAM mode. The timing control module is used to provide the timing signals required for the circuit to operate. The ADC module is used to convert the calculation results of each column of storage cells in the storage array into digital quantities; The shift calculation module is used to perform subtraction and shift operations on the digital quantity output by the ADC module, and output the calculation result. The feature is that when the multi-point product and parallel XOR calculation circuit performs the multi-point product operation, it adopts the multi-point product operation logic method as described in any one of claims 1-7.

9. The multi-point product and parallel XOR calculation circuit according to claim 8, characterized in that, The multi-point product and parallel XOR calculation circuit implements parallel XOR in the following way: The three 1-bit operands that need to be XORed are denoted as XOR value A, B and XORed value C respectively; the voltage signal of XORed value C is written into the memory cell that needs to be XORed through SRAM write data mode, and its bit lines BL1, BL2 and BLB1, BLB2 are precharged to high level. The voltage signals of the XOR value A and its inverse are input to the memory cell through a pair of symmetrical word lines, and the voltage signals of the XOR value B and its inverse are input to the memory cell through another pair of symmetrical word lines; wherein the two pairs of symmetrical bit lines are WL1, WL3 and WL2, WL4 respectively. The XOR result of the bit line BL1 and BLB1 of the memory cell is obtained by adding the values ​​output by analog-to-digital converters ADC1 and ADC3 respectively. The XOR result of the bit line BL2 and BLB2 is obtained by adding the values ​​output by analog-to-digital converters ADC2 and ADC4 respectively.

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