System and method for non-modal read threshold voltage estimation

Abstract

Embodiments provide a scheme to process reduced use of deep neural networks (DNNs) to estimate an optimal read threshold voltage. A controller includes a combined neural network that receives a first cumulative distribution function (CDF) value and a second cumulative distribution function (CDF) value, each CDF value corresponding to a program voltage (PV) level associated with a read operation to a cell. The combined neural network generates a first connection vector and a second connection vector based on the first CDF value and the second CDF value and a first weight value, and estimates the optimal read threshold voltage based on the first connection vector and the second connection vector and a second weight value.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a scheme for determining the optimal read threshold voltage in a memory system. Background Technology

[0002] The computing environment paradigm has shifted to ubiquitous computing systems that can be used anytime, anywhere. Consequently, the use of portable electronic devices such as mobile phones, digital cameras, and laptops has increased rapidly. These portable electronic devices typically use memory systems with memory devices, also known as data storage devices. Data storage devices serve as either the main memory or secondary memory devices in portable electronic devices.

[0003] Memory systems using memory devices offer superior stability, durability, high data access speeds, and low power consumption due to the absence of moving parts. Examples of memory systems with these advantages include Universal Serial Bus (USB) memory devices, memory cards with various interfaces such as Universal Flash Memory (UFS), and solid-state drives (SSDs). The optimal read threshold voltage for a memory system can be determined from various schemes. Summary of the Invention

[0004] Aspects of the present invention include a system and method for modally estimating the optimal readout threshold voltage.

[0005] In one aspect of the invention, a memory system includes a memory device comprising a plurality of cells and a controller comprising a combined neural network. The combined neural network receives a first cumulative distribution function (CDF) value and a second cumulative distribution function (CDF) value, each CDF value corresponding to a programming voltage (PV) level associated with a read operation on a cell. The combined neural network generates a first connection vector and a second connection vector based on the first CDF value, the second CDF value, and a first weight value, and estimates an optimal read threshold voltage based on the first connection vector, the second connection vector, and the second weight value.

[0006] In another aspect of the invention, a method of operating a memory system including a memory device comprising a plurality of cells and a controller comprising a combined neural network, the method comprising: receiving a first cumulative distribution function (CDF) value and a second cumulative distribution function (CDF) value, each CDF value corresponding to a programming voltage (PV) level associated with a read operation on a cell; generating a first connection vector and a second connection vector based on the first CDF value, the second CDF value, and a first weight value; and estimating an optimal read threshold voltage based on the first connection vector, the second connection vector, and the second weight value.

[0007] Other aspects of the invention will become apparent from the following description. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating a data processing system according to an embodiment of the present invention.

[0009] Figure 2 This is a block diagram illustrating a memory system according to an embodiment of the present invention.

[0010] Figure 3 This is a circuit diagram illustrating a memory block of a memory device according to an embodiment of the present invention.

[0011] Figure 4 This is a diagram illustrating the state distribution of different types of cells in a memory device according to an embodiment of the present invention.

[0012] Figure 5A This is a diagram illustrating an example of encoding a multilayer cell (MLC) according to an embodiment of the present invention.

[0013] Figure 5B This is a diagram illustrating the state distribution of pages in a multi-layer cell (MLC) according to an embodiment of the present invention.

[0014] Figure 6A This is a diagram illustrating an example of Gray encoding of a three-layer cell (TLC) according to an embodiment of the present invention.

[0015] Figure 6B This is a diagram illustrating the state distribution of a page in a three-layer cell (TLC) according to an embodiment of the present invention.

[0016] Figure 7 This is a flowchart illustrating the error recovery algorithm in a memory system according to an embodiment of the present invention.

[0017] Figure 8 This is a diagram illustrating the operation of estimating the optimal read threshold voltage using various eBoost algorithms according to embodiments of the present invention.

[0018] Figure 9A and Figure 9B The distribution of read threshold voltage (Vt) of a memory cell according to an embodiment of the present invention is shown.

[0019] Figure 10 This is a diagram illustrating a memory system according to an embodiment of the present invention.

[0020] Figure 11 This is a diagram illustrating a neural network according to an embodiment of the present invention.

[0021] Figure 12 This is a diagram illustrating a training component according to an embodiment of the present invention.

[0022] Figure 13 This is a diagram illustrating a reasoning component according to an embodiment of the present invention.

[0023] Figure 14 The operation for determining the optimal read threshold voltage according to an embodiment of the present invention is illustrated.

[0024] Figure 15 A graph showing an example voltage readout threshold estimated by an optimal readout threshold determiner according to an embodiment of the present invention is provided.

[0025] Figure 16 This is a diagram illustrating an optimal reading threshold determination device according to an embodiment of the present invention. Detailed Implementation

[0026] Various embodiments of the invention are described in more detail below with reference to the accompanying drawings. However, this aspect may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure is thorough and complete, and fully conveys the scope of the invention to those skilled in the art. Furthermore, references herein to “embodiment,” “another embodiment,” etc., are not necessarily directed to only one embodiment, and different references to any such phrases are not necessarily directed to the same embodiment. The term “embodiment” as used herein does not necessarily refer to all embodiments. Throughout this disclosure, the same reference numerals refer to the same parts in the drawings and embodiments of the invention.

[0027] This invention can be embodied in a variety of ways, including as a process, apparatus, system, computer program product implemented on a computer-readable storage medium; and / or a processor, such as a processor adapted to execute instructions stored in and / or provided by memory linked to the processor. In this specification, these embodiments or any other form in which the invention may take place can be referred to as technology. Generally, the order of operations of the disclosed processes can be varied within the scope of this invention. Unless otherwise stated, components such as processors or memory described as suitable for performing tasks can be implemented as general components temporarily configured to perform tasks at a given time or manufactured as specific components for performing tasks. As used herein, the term "processor," etc., refers to one or more means, circuits, and / or processing cores suitable for processing data such as computer program instructions.

[0028] The methods, processes, and / or operations described herein can be executed by code or instructions to be run by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device can be those described herein or other than those described herein. Because the algorithms underlying the methods (or the operation of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the method embodiments can convert a computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods herein.

[0029] When implemented at least in part as software, the controller, processor, device, module, unit, multiplexer, generator, logic circuit, interface, decoder, driver, generator, and other signal generation and signal processing features may include, for example, memory or other storage devices for storing, for example, code or instructions to be executed by a computer, processor, microprocessor, controller, or other signal processing device.

[0030] The following provides a detailed description of embodiments of the invention, along with accompanying drawings illustrating aspects of the invention. The invention is described in conjunction with these embodiments, but is not limited to any particular embodiment. The scope of the invention is limited only by the claims. The invention includes many alternatives, modifications, and equivalents within the scope of the claims. Numerous specific details are set forth in the following description to provide a thorough understanding of the invention. These details are provided for illustrative purposes; the invention may be practiced without some or all of these specific details. For clarity, technical materials known in the art related to the invention have not been described in detail so as not to unnecessarily obscure the invention.

[0031] Figure 1 This is a block diagram illustrating a data processing system 2 according to an embodiment of the present invention.

[0032] Reference Figure 1 The data processing system 2 may include a host device 5 and a memory system 10. The memory system 10 may receive requests from the host device 5 and operate in response to the received requests. For example, the memory system 10 may store data to be accessed by the host device 5.

[0033] The host device 5 can be implemented using any of a variety of electronic devices. In various embodiments, the host device 5 may include electronic devices such as: a desktop computer, a workstation, a 3D television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, and / or a digital video recorder and a digital video player. In various embodiments, the host device 5 may include portable electronic devices such as: a mobile phone, a smartphone, an e-book reader, an MP3 player, a portable multimedia player (PMP), and / or a portable game console.

[0034] The memory system 10 can be implemented using any of a variety of storage devices such as solid-state drives (SSDs) and memory cards. In various embodiments, the memory system 10 can be configured as one of a variety of components in electronic devices such as: computers, ultra-mobile personal computers (PCs) (UMPCs), workstations, netbook computers, personal digital assistants (PDAs), portable computers, network tablet PCs, wireless phones, mobile phones, smartphones, e-book readers, portable multimedia players (PMPs), portable gaming devices, navigation devices, black boxes, digital cameras, digital multimedia broadcasting (DMB) players, 3D televisions, smart televisions, digital audio recorders, digital audio players, digital picture recorders, digital picture players, digital video recorders, digital video players, storage devices for data centers, devices capable of receiving and transmitting information in a wireless environment, radio frequency identification (RFID) devices, and one of a variety of electronic devices in home networks, one of a variety of electronic devices in computer networks, one of a variety of electronic devices in telematics networks, or one of a variety of components in computing systems.

[0035] The memory system 10 may include a memory controller 100 and a semiconductor memory device 200. The memory controller 100 can control the overall operation of the semiconductor memory device 200.

[0036] The semiconductor memory device 200 can perform one or more erase, program, and read operations under the control of the memory controller 100. The semiconductor memory device 200 can receive commands (CMD), addresses (ADDR), and data (DATA) via input / output lines. The semiconductor memory device 200 can receive power (PWR) via power lines and control signals (CTRL) via control lines. Depending on the design and configuration of the memory system 10, the control signal CTRL may include command latch enable signals, address latch enable signals, chip enable signals, write enable signals, read enable signals, and other operation signals.

[0037] The memory controller 100 and the semiconductor memory device 200 can be integrated into a single semiconductor device, such as a solid-state drive (SSD). The SSD may include a storage device for storing data therein. When the semiconductor memory system 10 is used in an SSD, the performance of host devices coupled to the memory system 10 (e.g., Figure 1 The operating speed of the main unit 5).

[0038] The memory controller 100 and the semiconductor memory device 200 can be integrated into a single semiconductor device, such as a memory card. For example, the memory controller 100 and the semiconductor memory device 200 can be integrated to configure PC cards, compact flash memory (CF) cards, smart media (SM) cards, memory sticks, multimedia cards (MMC), miniaturized multimedia cards (RS-MMC), micro-versions of MMC (micro MMC), secure digital cards (SD cards), mini secure digital cards (mini SD cards), micro secure digital cards (micro SD cards), secure digital mass storage (SDHC) and / or universal flash memory (UFS).

[0039] Figure 2 This is a block diagram illustrating a memory system according to an embodiment of the present invention. For example, Figure 2 The memory system can be described Figure 1 The memory system 10 shown.

[0040] Reference Figure 2 The memory system 10 may include a memory controller 100 and a semiconductor memory device 200. The memory system 10 can respond to input from a host device (e.g., Figure 1 The host device 5) operates upon request and, in particular, stores data to be accessed by the host device.

[0041] The memory device 200 can store data to be accessed by the host device.

[0042] The memory device 200 may be implemented using volatile memory devices such as dynamic random access memory (DRAM) and / or static random access memory (SRAM) or non-volatile memory devices such as read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric random access memory (FRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM) and / or resistive RAM (RRAM).

[0043] The controller 100 can control the storage of data in the memory device 200. For example, the controller 100 can control the memory device 200 in response to a request from a host device. The controller 100 can provide the host device with data read from the memory device 200, and can store the data provided by the host device into the memory device 200.

[0044] The controller 100 may include a storage device 110 connected via a bus 160, a control component 120 which may be implemented as a processor such as a central processing unit (CPU), an error correction code (ECC) component 130, a host interface (I / F) 140, and a memory interface (I / F) 150.

[0045] Storage device 110 can be used as working memory for memory system 10 and controller 100, and stores data for driving memory system 10 and controller 100. When controller 100 controls the operation of memory device 200, storage device 110 can store data for operations such as read operations, write operations, programming operations and erase operations performed by controller 100 and memory device 200.

[0046] Storage device 110 can be implemented using volatile memory such as static random access memory (SRAM) or dynamic random access memory (DRAM). As described above, storage device 110 can store data used by the host device in storage device 200 for read and write operations. To store data, storage device 110 may include program memory, data memory, write buffer, read buffer, map buffer, etc.

[0047] Control component 120 can control the general operation of memory system 10 and, in response to write or read requests from host device, control write or read operations on memory device 200. Control component 120 can drive firmware called a flash translation layer (FTL) to control the general operation of memory system 10. For example, FTL can perform operations such as logical-to-physical (L2P) mapping, wear leveling, garbage collection, and / or bad block handling. L2P mapping is called logical block addressing (LBA).

[0048] ECC component 130 can detect and correct errors in data read from memory device 200 during a read operation. When the number of error bits is greater than or equal to the threshold number of correctable error bits, ECC component 130 may not correct the error bits, but instead outputs an error correction failure signal indicating that the correction of error bits has failed.

[0049] In various embodiments, ECC component 130 may perform error correction operations based on coding modulation such as low-density parity-check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbine codes, turbine product codes (TPC), Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), or block-coded modulation (BCM). However, error correction is not limited to these techniques. Thus, ECC component 130 may include any and all circuitry, systems, or means for appropriate error correction operations.

[0050] The host interface 140 can communicate with the host device through one or more of the following communication standards or interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), High-Speed ​​Peripheral Component Interconnect (PCI-e or PCIe), Small Computer System Interface (SCSI), Serial SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Enhanced Small Disk Interface (ESDI), and Electronic Integrated Drive (IDE).

[0051] Memory interface 150 provides an interface between controller 100 and memory device 200, allowing controller 100 to control memory device 200 in response to requests from host device. Memory interface 150 can generate control signals for memory device 200 and process data under the control of control component 120. When memory device 200 is flash memory such as NAND flash memory, memory interface 150 can generate control signals for memory and process data under the control of control component 120.

[0052] Memory device 200 may include a memory cell array 210, control circuitry 220, voltage generation circuitry 230, row decoder 240, page buffer 250 (which may be in the form of a page buffer array), column decoder 260, and input / output (I / O) circuitry 270. The memory cell array 210 may include multiple memory blocks 211 capable of storing data. The voltage generation circuitry 230, row decoder 240, page buffer array 250, column decoder 260, and I / O circuitry 270 may form peripheral circuitry for the memory cell array 210. The peripheral circuitry may perform programming, reading, or erasing operations on the memory cell array 210. The control circuitry 220 may control the peripheral circuitry.

[0053] The voltage generation circuit 230 can generate operating voltages of various levels. For example, in an erase operation, the voltage generation circuit 230 can generate operating voltages of various levels, such as erase voltage and pass voltage.

[0054] The line decoder 240 can be electrically connected to the voltage generation circuit 230 and a plurality of memory blocks 211. The line decoder 240 can select at least one memory block among the plurality of memory blocks 211 in response to a line address generated by the control circuit 220, and transmit the operating voltage provided by the voltage generation circuit 230 to the selected memory block.

[0055] Page buffer 250 can be accessed via bit line BL (e.g. Figure 3 (As shown) is connected to the memory cell array 210. The page buffer 250 can precharge the bit line BL with a positive voltage in response to the page buffer control signal generated by the control circuit 220, and transfer data to and from the selected memory block during programming and reading operations, or temporarily store the transferred data.

[0056] The column decoder 260 can transmit data to and receive data from the page buffer 250, or transmit data to and receive data from the input / output circuit 270.

[0057] Input / output circuit 270 can input from external devices (e.g., Figure 1 The memory controller 100 receives commands and addresses and transmits them to the control circuit 220 to transmit data from the external device to the column decoder 260, or the input / output circuit 270 can be used to output data from the column decoder 260 to the external device.

[0058] The control circuit 220 can control the peripheral circuits in response to commands and addresses.

[0059] Figure 3 This is a circuit diagram illustrating a memory block of a semiconductor memory device according to an embodiment of the present invention. For example, Figure 3 The storage block can be Figure 2 Any one of the storage blocks 211 in the memory cell array 210 shown.

[0060] Reference Figure 3 Storage block 211 may include multiple word lines WL0 to WLn-1, drain select line DSL, and source select line SSL connected to line decoder 240. These lines may be arranged in parallel, with multiple word lines arranged between DSL and SSL.

[0061] The memory block 211 may further include multiple cell strings 221 respectively connected to bit lines BL0 to BLm-1. Each column of cell strings may include one or more drain-select transistors (DSTs) and one or more source-select transistors (SSTs). In the illustrated embodiment, each cell string has one DST and one SST. In the cell string, multiple memory cells or memory cell transistors MC0 to MCn-1 may be connected in series between the select transistors DST and SST. Each of the memory cells may be formed as a multi-level cell. For example, each of the memory cells may be formed as a single-level cell (SLC) storing 1 bit of data. Each of the memory cells may be formed as a multi-level cell (MLC) storing 2 bits of data. Each of the memory cells may be formed as a three-level cell (TLC) storing 3 bits of data. Each of the memory cells may be formed as a four-level cell (QLC) storing 4 bits of data.

[0062] The source of each SST in a cell string can be connected to the common source line CSL, and the drain of each DST can be connected to the corresponding bit line. The gate of an SST in a cell string can be connected to SSL, and the gate of a DST in a cell string can be connected to DSL. The gates of memory cells on multiple cell strings can be connected to the corresponding word lines. That is, the gate of memory cell MC0 is connected to the corresponding word line WL0, the gate of memory cell MC1 is connected to the corresponding word line WL1, and so on. A group of memory cells connected to a specific word line can be called a physical page. Therefore, the number of physical pages in memory block 211 can correspond to the number of word lines.

[0063] Page buffer array 250 may include multiple page buffers 251 connected to bit lines BL0 to BLm-1. Page buffers 251 may operate in response to page buffer control signals. For example, page buffers 251 may temporarily store data received through bit lines BL0 to BLm-1 or sense the voltage or current of the bit lines during read or verification operations.

[0064] In some embodiments, memory block 211 may include NAND flash memory cells. However, memory block 211 is not limited to this cell type, but may include NOR flash memory cells. Memory cell array 210 may be implemented as a hybrid flash memory combining two or more types of memory cells, or as a 1-NAND flash memory with the controller embedded within the memory chip.

[0065] Figure 4 This is a diagram illustrating the state or programming voltage (PV) level distribution of different types of cells in a memory device according to an embodiment of the present invention.

[0066] Reference Figure 4Each memory cell can be implemented using a specific type of cell, such as a single-level cell (SLC) for storing 1 bit of data, a multi-level cell (MLC) for storing 2 bits of data, a three-level cell (TLC) for storing 3 bits of data, or a four-level cell (QLC) for storing 4 bits of data. Typically, all memory cells in a particular memory device are of the same type, but that is not necessary.

[0067] An SLC can include two states, P0 and P1. P0 indicates an erase state, and P1 indicates a programmable state. Since an SLC can be set to one of two different states, each SLC can be programmed or store one bit according to a set encoding method. An MLC can include four states, P0, P1, P2, and P3. Among these states, P0 can indicate an erase state, and P1 through P3 can indicate a programmable state. Since an MLC can be set to one of four different states, each MLC can be programmed or store two bits according to a set encoding method. A TLC can include eight states, P0 through P7. Among these states, P0 can indicate an erase state, and P1 through P7 can indicate a programmable state. Since a TLC can be set to one of eight different states, each TLC can be programmed or store three bits according to a set encoding method. A QLC can include 16 states, P0 through P15. Among these states, P0 can indicate an erase state, and P1 through P15 can indicate a programmable state. Since a QLC can be set to one of 16 different states, each QLC can be programmed or store four bits according to a set encoding method.

[0068] Return to reference Figure 2 and Figure 3 The memory device 200 may include multiple memory cells (e.g., NAND flash memory cells). Figure 3As shown, memory cells are arranged in an array of rows and columns. Cells in each row are connected to word lines (e.g., WL0), while cells in each column are connected to bit lines (e.g., BL0). These word lines and bit lines are used for read and write operations. During a write operation, when a word line is asserted, the data to be written ("1" or "0") is provided at the bit line. During a read operation, the word line is asserted again, and the threshold voltage for each cell can then be obtained from the bit line. Multiple pages can share memory cells belonging to (i.e., connected to) the same word line. When the memory cells are implemented using MLC, the multiple pages include a most significant bit (MSB) page and a least significant bit (LSB) page. When the memory cells are implemented using TLC, the multiple pages include an MSB page, a middle significant bit (CSB) page, and an LSB page. When the memory cells are implemented using QLC, the multiple pages include an MSB page, a middle most significant bit (CMSB) page, a middle least significant bit (CLSB) page, and an LSB page. The memory cells can be programmed using an encoding scheme (e.g., Gray encoding) to increase the capacity of a memory system 10 such as an SSD.

[0069] Figure 5A This is a diagram illustrating an example of encoding a multilayer cell (MLC) according to an embodiment of the present invention.

[0070] Reference Figure 5A The MLC can be programmed using a specified encoding type. The MLC can have four programming states: erase state E (or PV0) and first programming states PV1 through third programming states PV3. Erase state E (or PV0) can correspond to "11". First programming state PV1 can correspond to "10". Second programming state PV2 can correspond to "00". Third programming state PV3 can correspond to "01".

[0071] In MLC, such as Figure 5B As shown, there are two types of pages: LSB and MSB pages. One or two thresholds can be applied to retrieve data from the MLC. For MSB pages, the single threshold is VT1. VT1 distinguishes between the first programming state PV1 and the second programming state PV2. For LSB pages, the two thresholds include a first threshold VT0 and a second threshold VT2. VT0 distinguishes between the erase state E and the first programming state PV1. VT2 distinguishes between the second programming state PV2 and the third programming state PV3.

[0072] Figure 6A This is a diagram illustrating an example of Gray encoding of a three-layer cell (TLC) according to an embodiment of the present invention.

[0073] Reference Figure 6AGray coding can be used to program a TLC. A TLC can have eight programming states, including an erase state E (or PV0) and first programming states PV1 through seventh programming states PV7. Eraser state E (or PV0) can correspond to "111". First programming state PV1 can correspond to "011". Second programming state PV2 can correspond to "001". Third programming state PV3 can correspond to "000". Fourth programming state PV4 can correspond to "010". Fifth programming state PV5 can correspond to "110". Sixth programming state PV6 can correspond to "100". Seventh programming state PV7 can correspond to "101".

[0074] In TLC, such as Figure 6B As shown, there are three types of pages: LSB, CSB, and MSB. Two or three thresholds can be applied to retrieve data from the TLC. For MSB pages, the two thresholds include threshold VT0, which distinguishes between erase state E and first programming state PV1, and threshold VT4, which distinguishes between fourth programming state PV4 and fifth programming state PV5. For CSB pages, the three thresholds include VT1, VT3, and VT5. VT1 distinguishes between first programming state PV1 and second programming state PV2. VT3 distinguishes between third programming state PV3 and fourth programming state PV4. VT5 distinguishes between fifth programming state PV5 and sixth programming state PV6. For LSB pages, the two thresholds include VT2 and VT6. VT2 distinguishes between second programming state PV2 and third programming state PV3. VT6 distinguishes between sixth programming state PV6 and seventh programming state PV7.

[0075] In such Figure 5A and Figure 6A After programming a memory array comprising multiple memory cells, the state of an individual memory cell is determined by comparing its charge level (e.g., the threshold voltage level of the memory cell's transistor) with one or more reference voltages when a read operation is performed on the memory array using a specific reference voltage such as a read threshold voltage (also referred to as a "read voltage level" or "read threshold"). For example, when a specific read threshold is applied to the memory array, those memory cells with threshold voltage levels higher than the specific reference voltage are turned on and detected as "on" cells, while those memory cells with threshold voltage levels lower than the specific reference voltage are turned off and detected as "off" cells. Therefore, each read threshold is arranged between adjacent threshold voltage distribution windows corresponding to different programming states, such that each read threshold can distinguish these programming states by turning the memory cell transistors on or off.

[0076] When performing a read operation on a memory cell in a data storage device using MLC technology, the threshold voltage level of the memory cell is compared with more than one read threshold level to determine the state of an individual memory cell. Read errors can be caused by distorted or overlapping threshold voltage distributions. Ideal memory cell threshold voltage distributions can be significantly distorted or overlapping due to factors such as program / erase (P / E) cycles, inter-cell interference, and / or data retention errors. For example, as program / erase cycles increase, the margin between adjacent threshold voltage distributions of different programming states decreases, eventually leading to overlapping distributions. Therefore, a memory cell with a threshold voltage falling into the overlapping region of adjacent distributions can be read as having been programmed to a value different from the original target value, resulting in a read error. In most cases, these read errors can be managed using error correction codes (ECC). A read operation using a set read threshold voltage fails when the number of bit errors in a read operation exceeds the data storage's ECC correction capability. The set read threshold voltage can be a previously used read threshold voltage (i.e., a historical read threshold voltage). The historical read threshold voltage can be the read threshold voltage used during the last successful decoding, i.e., the read voltage used in a successful read operation performed before the read retry operation. When a read operation using the set read threshold voltage fails, the controller 120 can control... Figure 7 The error recovery algorithm shown.

[0077] Reference Figure 7 The controller 120 may perform one or more read retry operations on memory cells using one or more read threshold voltages applied in a set order (S100). For example, the read threshold voltages may include N read threshold voltages (or read voltage levels) including a first read threshold voltage to an Nth read threshold voltage (e.g., N is 5 or 10). The first read threshold voltage may be a previously used read threshold voltage (i.e., a historical read threshold voltage). The historical read threshold voltage may be the read threshold voltage used during the last successful decoding, i.e., the read voltage used in a read operation that passed before the read retry operation. The controller 120 may perform read retry operations until it is determined that the decoding associated with the corresponding read retry operation was successful.

[0078] When all read retry operations using the read threshold voltage fail, the controller 120 may perform additional recovery operations. For example, additional recovery operations may include optimal read threshold voltage search (S200), soft decoding using error correction codes (ECC) (S300), and independent disk redundant array (RAID) recovery (S400).

[0079] As described above, in memory systems such as NAND flash memory systems, upon receiving a read command, a series of data recovery steps are performed with the goal of retrieving noise-free data from the memory device (i.e., the NAND flash memory device). In the first attempt, a read operation using a historical read threshold voltage (i.e., a historical read) is performed. Historical reads can be maintained individually for each physical block, and can be updated if decoding associated with that historical read fails. If a historical read fails, a read retry attempt called a high-priority read retrieval (HRR) is performed. HRR is a series of read threshold voltages (i.e., Vt) that always remain constant. The read retry threshold voltage does not change based on NAND conditions or the physical location of the data to be read. Typically, there are 5 to 10 HRR read attempts. If all HRR reads fail, an optimal read threshold voltage is found through an optimal read level search (i.e., the eBoost algorithm), and soft read and soft decode operations are performed. The eBoost algorithm can perform multiple reads to find the optimal center Vt for the soft read. There are many different eBoost algorithms, such as Gaussian modeling (GM), cumulative cell counting search (CCS), and advanced valley search (AVA).

[0080] Figure 8 This is a diagram illustrating the operation of eBoost algorithms such as GM, CCS, and AVA algorithms to estimate the optimal read threshold voltage according to an embodiment of the present invention.

[0081] Reference Figure 8 This illustrates a comparison between the read threshold voltage obtained through each of the GM, CCS, and AVA algorithms and the optimal read threshold voltage OPT. Assuming all PV states (i.e., PV11, PV12) follow a Gaussian distribution with a known / constant variance and an unknown mean, the GM algorithm attempts to find the read threshold voltage (Vt). The CCS algorithm attempts to find Vt such that the number of cells falling on either side is equal. The AVA algorithm attempts to find the lowest point in the overall distribution around the trough, as Vt. Figure 8 As shown, when one of the two PV states (e.g., PV12) is asymmetrical and has a heavier tail than the other, all these algorithms estimate the read threshold voltage (i.e., GM, CCS, AVA) offset from the optimal read threshold voltage OPT.

[0082] Figure 9A and Figure 9B Examples of threshold voltage (Vt) distributions or programming states for three-layer cell (TLC) and four-layer cell (QLC) according to embodiments of the present invention are shown respectively.

[0083] exist Figure 9A and Figure 9BIn the example shown, one or more of the multiple PV states are asymmetric and have heavier tails than the other states. Figure 9A In the example, three states PV25 through PV27 are asymmetrical and have heavy tails. Figure 9B In the example, state PV315 among PV301 to PV315 is asymmetric and has a heavy tail. In these cases, all three of the existing algorithms described above give an estimate of the offset Vt. Therefore, it is desirable to provide a scheme for estimating the readout threshold voltage to overcome the shortcomings of all existing algorithms.

[0084] The embodiments use deep learning and provide a parameter framework for modeling programming voltage or programming verification (PV) levels and estimating the optimal read threshold voltage (Vt).

[0085] Figure 10 This is a diagram illustrating a memory system 10 according to an embodiment of the present invention.

[0086] Reference Figure 10 The memory system 10 may include a controller 100 and a memory device 200. The memory device 200 may include a plurality of memory cells (e.g., NAND flash memory cells) 210. Figure 3 As shown, memory cells are arranged in an array of rows and columns. Cells in each row are connected to word lines (e.g., WL0), while cells in each column are connected to bit lines (e.g., BL0). These word lines and bit lines are used for read and write operations. During a write operation, when a word line is specified, the data to be written ("1" or "0") is provided at the bit line. During a read operation, the word line is specified again, and the threshold voltage for each cell can then be obtained from the bit line. Multiple pages can share memory cells belonging to (i.e., connected to) the same word line. When the memory cells are implemented using MLC, the multiple pages include a most significant bit (MSB) page and a least significant bit (LSB) page. When the memory cells are implemented using TLC, the multiple pages include an MSB page, a middle significant bit (CSB) page, and an LSB page. When the memory cells are implemented using QLC, the multiple pages include an MSB page, a middle most significant bit (CMSB) page, a middle least significant bit (CLSB) page, and an LSB page. The memory cells can be programmed using an encoding scheme (e.g., Gray encoding) to increase the capacity of a memory system 10 such as an SSD.

[0087] Controller 100 may include a read processor 1010, a decoder 1020, and an optimal read threshold determiner 1030. Although the components of controller 100 shown are implemented separately, these components can utilize... Figure 2The control component 120 is implemented using its internal components (i.e., firmware (FW)). Although Figure 10 Not shown, but the controller 100 and memory device 200 may include, for example... Figure 2 The various other components shown.

[0088] The read processor 1010 can respond to data from the host (e.g., Figure 1 The host 5) controls one or more read operations on the memory device 200 based on read requests. The read processor 1010 can use various read thresholds to control the read operations. The decoder 1020 can decode the data associated with the read operations.

[0089] In some embodiments, the read processor 1010 may use a selected read threshold from a set read level table to control read operations on memory cells. In some embodiments, the read level table may include multiple read thresholds, and the selected read threshold may include a default read threshold. When performing a read operation on an MSB page of a TLC, the selected read threshold may include, for example... Figure 6B The diagram shows a pair of first and second read thresholds [VT0, VT4]. The first read threshold VT0 distinguishes between the erase state (i.e., E) and the first programming state (i.e., PV1), while the second read threshold VT4 distinguishes between the fourth programming state (i.e., PV4) and the fifth programming state (i.e., PV5). When performing a read operation on an LSB page of a TLC, the selection of the read thresholds can include, for example... Figure 6B The first read threshold and the second read threshold [VT2, VT6] are shown. The first read threshold VT2 is used to distinguish between the second programming state (i.e., PV2) and the third programming state (i.e., PV3), while the second read threshold VT6 is used to distinguish between the sixth programming state (i.e., PV6) and the seventh programming state (i.e., PV7).

[0090] Based on the decoding result of decoder 1020, it can be determined whether the read operation using the read threshold selected from the read threshold set succeeded or failed. When the read operation using the selected read threshold fails, read processor 1010 can use read retry entries to control one or more read retry operations on the memory cell, such as... Figure 7 As shown.

[0091] The optimal read threshold determiner 1030 can provide a parameter framework for modeling the programming voltage or programming verification (PV) level and estimating the optimal read threshold voltage (Vt). The optimal read threshold determiner 1030 can be implemented using one or more deep neural networks (DNNs). For the parameter DNN framework, the optimal read threshold determiner 1030 may include a training component 1030A and an inference component 1030B.

[0092] Figure 11 This is a diagram illustrating an example of a neural network 1100 according to an embodiment of the present invention. In some embodiments, the neural network 1100 may include... Figure 10 In the controller 100 of the memory system 10.

[0093] Reference Figure 11 A feature map 1102 associated with one or more input conditions can be input into a neural network 1100. The neural network 1100 can then output information 1104. As shown, the neural network 1100 includes an input layer 1110, one or more hidden layers 1120, and an output layer 1130. Features from the feature map 1102 can be connected to input nodes in the input layer 1110. Information 1104 can be generated by output nodes in the output layer 1130. One or more hidden layers 1120 can exist between the input layer 1110 and the output layer 1130. The neural network 1100 can be pre-trained to process features from the feature map 1102 through different layers 1110, 1120, and 1130 to output information 1104.

[0094] Neural network 1100 can be a multi-layer neural network, which represents a network of interconnected nodes, such as an artificial deep neural network, where knowledge about nodes (e.g., information about specific features represented by nodes) is shared across layers and also retains knowledge specific to each layer. Each node represents a piece of information. Knowledge can be exchanged between nodes through node-to-node interconnections. Input to neural network 1100 can activate a set of nodes. This set of nodes can then activate other nodes, thereby propagating knowledge about the input. This activation process can be repeated on other nodes until a node in output layer 1130 is selected and activated.

[0095] As shown in the figure, the neural network 1100 includes a hierarchical structure of layers, which represents a hierarchy of nodes interconnected in a feedforward manner. The input layer 1110 can exist at the lowest hierarchical level. The input layer 1110 can include a set of nodes referred to herein as input nodes. When the feature map 1102 is input to the neural network 1100, each of the input nodes in the input layer 1110 can be connected to each feature of the feature map 1102. Each connection can have weights. These weights can be a set of parameters obtained from training the neural network 1100. The input nodes can transform the features by applying activation functions to these features. Information derived from the transformations can be passed to nodes at higher hierarchical levels.

[0096] Output layer 1130 can exist at the highest level of the hierarchy. Output layer 1130 can include one or more output nodes. Each output node can provide a specific value of output information 1104. The number of output nodes can depend on the amount of output information 1104 required. In other words, there is a one-to-one correspondence or mapping between the number of output nodes and the amount of output information.

[0097] Hidden layer 1120 may exist between input layer 1110 and output layer 1130. Hidden layer 1120 may include "N" hidden layers, where "N" is an integer greater than or equal to 1. Each of hidden layers 1120 may include a set of nodes referred to herein as hidden nodes. Example hidden layers may include upsampling layers, convolutional layers, fully connected layers, and / or data transformation layers.

[0098] In the lowest-level hidden layer 1120, the hidden nodes of this layer can be interconnected with the input nodes. In the highest-level hidden layer 1120, the hidden nodes of this layer can be interconnected with the output nodes. Input nodes may not be directly interconnected with output nodes. If multiple hidden layers exist, the input nodes are interconnected with the hidden nodes of the lowest-level hidden layer. In turn, these hidden nodes are interconnected with the hidden nodes of the next hidden layer. The interconnection can represent a piece of learned information about the two interconnected nodes. The interconnection can have numerical weights that can be adjusted (e.g., based on the training dataset) so that the neural network 1100 adapts to the input and is able to learn.

[0099] Typically, hidden layer 1120 allows knowledge about the input nodes of input layer 1110 to be shared among the output nodes of output layer 1130. To do this, a transformation f can be applied to the input nodes via hidden layer 1120. In this example, the transformation f is non-linear. Different non-linear transformations f can be used, including, for example, the rectifier function f(x) = max(0,x). In this example, the specific non-linear transformation f is selected based on cross-validation. For example, given a known pair of examples (x,y), where x∈X and y∈Y, the function f∶X→Y is chosen when it produces the best match.

[0100] For example, neural network 1100 can be a deep learning neural network for a memory system including a NAND flash memory device. A deep learning neural network can be created using "K" input nodes and one output node, where "K" is the number of factors (e.g., features) defining the input conditions of the memory system. The output node can be used to execute an activation function for a specific combination of the input conditions. The number of layers in neural network 1100 and the size of each layer can depend on the NAND flash memory device and the amount of data that the memory can store.

[0101] The inventors observed that in some cases (e.g., by means of) Figure 9A and Figure 9B The curves indicated by PV26 and PV27 in the figure, the cell level distribution corresponding to a specific threshold voltage range of PV levels, can be modeled using a skewed normal distribution. Typically, a skewed normal distribution is defined as a continuous probability distribution that generalizes to a normal distribution to allow for non-zero skewness. Each cumulative distribution function (CDF) value can represent a skewed normal distribution model for a specific PV level. To describe the properties of the skewed normal distribution, the probability distribution parameters can be a set of parameters including position ξ, scale ω, and shape α.

[0102] In some embodiments, the neural network 1100 can be Figure 12 and / or Figure 13 The first deep neural network (DNN1) or the second deep neural network (DNN2) in the diagram. For DNN1, one or more input conditions can be CDF values ​​and the output information 1104 can be probability distribution parameters. For example, a neural network 1100 (e.g., DNN1) can be pre-trained to process features (e.g., CDF values) from feature map 1102 through different layers 1110, 1120, and 1130, thereby outputting probability distribution parameters 1104. For DNN2, one or more input conditions can be probability distribution parameters and the output information 1104 can be probability density function (PDF) values.

[0103] Figure 12 This is a diagram illustrating a training component 1030A according to an embodiment of the present invention.

[0104] Reference Figure 12 Training component 1030A may include a synthetic model 1210 for training a first deep neural network (DNN1) 1200. To train this network 1200, a synthetic dataset (or data) may be collected by the synthetic model 1210. The synthetic dataset may be any production data suitable for a given situation, which is not obtained through direct measurement. In some embodiments, the deep neural network 1200 may be used in a memory system including a NAND flash memory device. As described above, the threshold voltage (Vt) distribution (i.e., PV level) of a memory cell can be modeled by a parametric distribution (i.e., a skewed normal distribution). The skewed normal distribution has a cumulative distribution function (CDF), as follows:

[0105]

[0106]

[0107] As the equation above indicates, the skewed normal distribution has three parameters: position ξ, scale ω, and shape α. In other words, for the range of readout threshold voltages corresponding to each PV level, these three probability distribution parameters can be used to describe the probability distribution of each PV level. In the equation above, x represents the sampled readout threshold voltage (i.e., the PV level), and T(h,a) defines Owen's T function.

[0108] The synthetic model 1210 can generate a synthetic dataset (x, CDF(x)) based on a probability distribution parameter p that commonly represents three parameters (i.e., ξ, ω, and α). The DNN1 1200 can be trained on this synthetic dataset, which includes CDF values ​​(CDF(x)) from the parameter distribution under various sampled voltages x, and outputs the probability distribution parameter p′ as the training result. The probability distribution parameter p′ can be used to determine the characteristics of the voltage range curve of the memory cell.

[0109] The training results of DNN1 1200 can be provided to loss function component 1220. Loss function component 1220 can use a loss function (or cost function) to find the optimal solution for the trained probability distribution parameters p′. DNN1 1200 can be trained to improve the probability distribution parameters, minimizing the difference (or error) between the actual probability distribution parameters p of the synthetic model 1210 and the probability distribution parameters p′ predicted by DNN1 1200.

[0110] In this way, the relationship between the CDF value CDF(x) and the probability distribution parameter Θ can be trained using DNN1 1200. Once trained, the inference component 1030B can use the training results.

[0111] Figure 13 This is a diagram illustrating the inference component 1030B according to an embodiment of the present invention.

[0112] Reference Figure 13 The inference component 1030B may include a first deep neural network (DNN1) 1200A, 1200B, a second deep neural network (DNN2) 1300A, 1300B, and a crossover calculation component 1310. It can be as follows: Figure 12 The training diagram shows each DNN11200A and 1200B. Each of DNN1 and DNN2 can be implemented in a SoC or FW depending on the size of the DNN used.

[0113] exist Figure 13 In the middle, PV A and PV B (For example, Figure 15 In the CDF, 1502 and 1504 represent two adjacent PV levels. A (xi ) indicates that at voltage x i PV of the downsampled threshold voltage distribution A CDF value. B (x i ) indicates that at voltage x i PV of the downsampled threshold voltage distribution B CDF value. p A PV A The probability distribution parameters of p. B PV B The probability distribution parameters. The optimal read threshold voltage Vt_opt represents PV. A and PV B The voltage at the crossover point between the threshold voltage distributions.

[0114] The threshold voltage distribution of cells at PV levels can be modeled using a parametric distribution (i.e., a skewed normal distribution). This parametric distribution models the relationship between the CDF value and the probability distribution parameter p for each PV level. A and PV B The skewed normal distributions are respectively used with probability distribution parameters p A and p B Modeling is performed.

[0115] For an n-bit multi-cell NAND flash memory, the threshold voltage of each cell can be programmed to be 2. n There are several possible values. In an ideal multi-cell NAND flash memory, each value corresponds to a non-overlapping threshold voltage range. However, in many systems, due to operating conditions, the threshold voltage ranges of each value may partially overlap. Figures 8 to 9B An example of this overlap is shown in the image.

[0116] The DNN1 1200A can receive the first CDF value of a skewed normal distribution model representing the first threshold voltage range. A (x i First CDF value CDF A (x i ) can be generated through iterative modeling to determine the parameter representation for the threshold voltage range, such as Figure 12 As shown. First CDF value CDF A (x i This can correspond to the first level of a multi-level cell NAND flash memory. Each multi-level cell has multiple levels based on the number of bits stored in the cell. In one example, each multi-level cell of a three-level cell (TLC) stores three bits and has 2... n One level, or eight levels. Each of the eight levels in a three-bit TLC corresponds to a value that can be determined by the first CDF value.A (x i The voltage range is represented by (). The DNN1 1200B can receive the second CDF value of the skewed normal distribution model representing the second threshold voltage range. B (x i Second CDF value CDF B (x i This can correspond to the second level of a multilayer cell.

[0117] Each DNN1 1200A, 1200B can estimate the probability distribution parameter p based on the CDF value, which is given by measurements of memory cells. For example, DNN1 1200A can estimate the probability distribution parameter p based on the first CDF value. A (x i To estimate the probability distribution parameter p A DNN1 1200B can be based on the second CDF sample CDF. B (x i To estimate the probability distribution parameter p B The probability distribution parameter is represented as p. A =(ξ A ,ω A ,α A ) and p B =(ξ B ,ω B ,α B ).

[0118] Each DNN2 1300A, 1300B can determine the PDF value of the distribution of each candidate readout threshold voltage based on the estimated probability distribution parameter p. For example, the DNN2 1300A can receive the estimated probability distribution parameter p. A And based on the estimated probability distribution parameter p A Determine PDF values A The DNN2 1300B can receive the estimated probability distribution parameters p. B And based on the estimated probability distribution parameter p B Determine PDF values B In some embodiments, each DNN2 1300A, 1300B can determine the PDF value of the distribution of each candidate readout threshold voltage based on the estimated probability distribution parameter p using the following equation:

[0119] Where ξ represents position, ω represents scale, and α represents shape, they are probability distribution parameters p.

[0120] In some embodiments, each DNN2 1300A, 1300B may include a lookup table (LUT) that stores the relationship between probability distribution parameters and PDF values.

[0121] The crossover point calculation component 1310 can find two candidate read threshold voltages that produce approximately equal PDF values. Furthermore, the crossover point calculation component 1310 can determine the crossover point of the two candidate read threshold voltages as the optimal read threshold voltage Vt_opt.

[0122] Thus, the inference component 1030B can estimate the crossover points of potential PDF values ​​based on some noisy samples of the CDF values.

[0123] Figure 14 The operation of obtaining ICMF samples for estimating the optimal readout threshold voltage is illustrated according to an embodiment of the present invention. This operation can be performed by... Figure 10 The read processor 1010 of the controller 100 performs this operation. For example, ICMF samples can be obtained to estimate the optimal read threshold voltage for the LSB pages of the TLC.

[0124] exist Figure 14 In the diagram, 1410 represents the parameter distribution corresponding to the threshold voltage distribution of the PV level of the TLC, such as... Figure 6A As shown in the figure, the TLC distribution consists of 8 zones, from Zone 0 to Zone 7, and each zone corresponds to a programming state or PV level.

[0125] In operation S1410, controller 100 can read the LSB page, MSB page, and CSB page to generate PV state counts. Further, controller 100 can generate a first ICMF sample set for PV2, PV3, PV6, and PV7 based on the PV state counts. Here, ICMF represents the reciprocal of the Cumulative Quality Function (CMF). In some embodiments, for each read threshold voltage, the Cumulative Quality Function (CMF) value can be determined based on the number of cells (cell count) and the number of specific binary values ​​(1 or 0) among the cells associated with a read operation using each read threshold voltage. For example, each CMF value can be determined as {the number of 1s or 0s (e.g., 1) / cell count}, i.e., the percentage of 1s or 0s.

[0126] 1420 represents the first ICMF sample set of PV2, PV3, PV6, and PV7 generated in S1410. The samples for each page in the first ICMF sample set are generated from the parameter distribution under different read threshold voltages. In the example shown, for the MSB page, the ICMF samples are generated under read threshold voltages Vt0 and Vt4. The ICMF samples under read threshold voltage Vt0 indicate 75% 1s and 25% 0s, while the ICMF samples under read threshold voltage Vt4 indicate 80% 1s and 20% 0s. For the CSB page, the ICMF samples are generated under read threshold voltages Vt1, Vt3, and Vt5. The ICMF samples under read threshold voltage Vt1 indicate 10% 1s and 90% 0s, the ICMF samples under read threshold voltage Vt3 indicate 30% 0s and 70% 1s, while the ICMF samples under read threshold voltage Vt5 indicate 30% 1s and 70% 0s. For the LSB page, the ICMF samples are generated under read threshold voltages Vt2 and Vt6. Reading ICMF samples at threshold voltage Vt2 indicates 40% 1s and 60% 0s, while reading ICMF samples at threshold voltage Vt6 indicates 40% 0s and 60% 1s.

[0127] In operation S1420, controller 100 can read one or more LSB pages and CSB pages to generate a second ICMF sample set and a third ICMF sample set for PV2, PV3, PV6, and PV7. In the embodiment shown in 1430, two LSB pages and CSB pages can be read. This embodiment considers a distribution based on a skewed normal model (SNM). The number of LSB pages and CSB pages to be read can vary depending on the distribution model. For an improved Gaussian model (IGM) distribution, one LSB page and CSB page can be read. For a non-centralized model (NCTM) distribution, three LSB pages and CSB pages can be read.

[0128] 1430 represents the second and third ICMF sample sets PV2, PV3, PV6, and PV7 generated in S1420. The samples for each page in the second ICMF sample set are generated from the parameter distribution at different read threshold voltages. In the example shown, for the CSB page, the ICMF samples are generated at read threshold voltages Vt'3 and Vt'5. For the LSB page, the ICMF samples are generated at read threshold voltages Vt'2 and Vt'6. The samples for each page in the third ICMF sample set are generated from the parameter distribution at different read threshold voltages. In the example shown, for the CSB page, the ICMF samples are generated at read threshold voltages Vt'3 and Vt'5. For the LSB page, the ICMF samples are generated at read threshold voltages Vt'2 and Vt'6. Although not shown, each ICMF sample in the second and third ICMF sample sets indicates a percentage of 0 and a percentage of 1.

[0129] Thus, operations S1410 and S1420 are performed to estimate the distribution of a specific page (i.e., the LSB page) and eliminate other components (e.g., noise). In operation S1430, the controller 100 may provide ICMF samples to the DNN1 1200A, 1200B to estimate the optimal read threshold voltage. In some embodiments, CDF values ​​corresponding to the ICMF samples (or CMF samples) may be provided to the DNN1 1200A, 1200B.

[0130] Figure 15 A graph 1500 showing an example voltage readout threshold estimated by the optimal readout threshold determiner 1030 according to an embodiment of the present invention is shown.

[0131] Reference Figure 15 Graph 1500 depicts the first curve 1502 (i.e., f(x; Θ)) representing the probability distribution of the first voltage range 1608. L =(ξ L ,ω L ,α L ))) and the second curve 1504 representing the second voltage range 1510 (i.e., f(x; Θ) R =(ξ R ,ω R ,α R The optimal read threshold voltage (i.e., -0.29151) 1506 was determined to be the intersection point between the first voltage range 1508 and the second voltage range 1510, indicated by the intersection of the first curve 1502 and the second curve 1504. Figure 15In the example shown, the first curve 1502 and the second curve 1504 depict the logarithmic function of the probability distribution parameter p = (ξ, ω, α) over two voltage ranges. Specifically, the first curve 1502 corresponds to f(x; Θ). L =(ξ L =-1.0,ω L =0.4,α L =0.0), the second curve 1504 corresponds to f(x; Θ) R =(ξ R =1.0,ω R =0.7,α R =-2.0). Each of the first voltage range 1508 and the second voltage range 1510 is modeled by a set of skewed normal distribution parameters, as shown in the legend of curve 1500.

[0132] As described above, in order to estimate the optimal read threshold voltage, the controller 10 can utilize, for example... Figure 13 The components shown are used to implement this embodiment. This embodiment is described in U.S. Patent Application No. 17 / 233,167, entitled "Systems and Methods for Parametric PV-Level Modeling and Readthreshold Voltage Estimation," which is incorporated herein by reference in its entirety. Figure 13 In the illustrated implementation, controller 10 performs a three-step process to estimate the optimal read threshold voltage Vt_opt via DNN1 1200A and 1200B, DNN2 1300A and 1300B, and crosspoint component 1310.

[0133] Another implementation of the controller is described in U.S. Patent Application No. 17 / 011,983, entitled "Effective Read-Threshold Calculation Method for Parametric PV-Level Modeling" (hereinafter referred to as the '983 patent application), which is incorporated herein by reference. The '983 patent application provides a computer system 500 whose architecture includes a neural network 506, a voltage readout threshold generator 510, a floating-point unit (FPU) 512, and an approximation generator 516, as shown in Figure 5. The voltage readout threshold generator 510, the floating-point unit 512, and the approximation generator 516 correspond to a firmware implementation to calculate the crossover voltage based on parameters estimated by the neural network 506.

[0134] Figure 13 The implementations of the optimal read threshold determiner 1030 in the '983 patent application and the computer system 500 require an explicit model of the parameter distribution (e.g., a skewed normal distribution) that models the distribution of threshold voltages of cells in the PV level. Furthermore, the above embodiments should perform two or three processing stages to estimate the optimal read threshold voltage based on CDF measurements (i.e., CDF values). Therefore, it is desirable to provide a scheme for estimating the optimal read threshold voltage with fewer processing stages.

[0135] Figure 16 This is a diagram illustrating an optimal reading threshold determination device 1600 according to an embodiment of the present invention.

[0136] Reference Figure 16 The optimal reading threshold determination device 1600 can be implemented using a combined deep neural network (CDNN). The CDNN 1600 may include a first internal deep neural network (IDNN1) 1610A, a second internal deep neural network (IDNN2) 1610B, and a third internal deep neural network (IDNN3) 1620. In this architecture, the weights in the two internal stages can be designed jointly rather than separately. The first internal deep neural network (IDNN1) 1610A and the second internal deep neural network (IDNN2) 1610B can have the same structure and perform the same operations except for different inputs and outputs. In other words, the CDNN 1600 can have an architecture that combines IDNN1, IDNN2, and IDNN3 into a single network, which can be trained end-to-end to achieve better accuracy. The CDNN does not assume any explicit parameter distribution to model the threshold voltage distribution of PV levels. There are no restrictions on the architecture of IDNN1, IDNN2, and IDNN3 themselves.

[0137] exist Figure 16 In the middle, PV L and PV R These are two adjacent PV levels. CDF L (x i ) is at voltage x i PV of the downsampled threshold voltage distribution L The cumulative density function (CDF) value. R (x j ) is at voltage x j PV of the downsampled threshold voltage distribution R The CDF value. Vt_opt is related to PV. L and PV R The optimal read threshold voltage (Vt) corresponding to the crossover point voltage between the threshold voltage distributions. Θ R* and Θ L * can represent PV L and PV R The two connected vectors of the threshold voltage distribution values. Θ L *CDF can be used based on input features L (x i ) and x i And the weights in IDNN1 are used to calculate Θ. R *CDF can be used based on input features R (x j ) and x j And the weights in IDNN2 are used for calculation. The calculation details are described below. In the embodiment, Θ R * and Θ L * is represented as: Θ R *=[α R ,β R ,γ R ,δ R ] and Θ L *=[α L ,β L ,γ L ,δ L Although the number of values ​​in each connection vector is 4 in this embodiment, the number of values ​​in each connection vector is not fixed at 4, but is determined during the design process to optimize performance. There is no value that can be used to determine the value based on the connection vector Θ. R * and Θ L * A predefined mathematical formula for reconstructing the threshold voltage distribution. Connecting vector Θ R * and Θ L The length (or width) of a * is usually very small.

[0138] CDNN 1600 can be trained on a single dataset, which includes CDF values ​​and sampled voltages x, which serve as input features corresponding to the CDF values. i And the optimal readout threshold voltage as the output. For training the CDNN 1600, a differentiable loss function can be defined to measure the CDNN Vt. DNN The output and the optimal reading threshold voltage Vt of the data points in the dataset Opt The error between them. For example, the mean square error (Vt) can be used. DNN -Vt Opt ) 2 / n (where n is the number of data points in the subset of the training data of the dataset). The loss function is not limited to the mean squared error function.

[0139] Stochastic gradient descent (SGD), its variants, and / or other algorithms can be used to obtain the weights of a CDNN 1600, thereby minimizing the loss function. The obtained weights (weight values) can then be used to process the input features (vectors) to obtain the optimal readout threshold voltage. For example, the weights obtained by IDNN1 can be multiple matrices A. IDNN1,0 A IDNN1,1 A IDNN1,M Sum of deviation vector b IDNN1,0 b IDNN1,1 ... b IDNN1,M The weights obtained by IDNN2 can be the same as those obtained by IDNN1. The weights obtained by IDNN3 can be multiple matrices A. IDNN3,0 A IDNN3,1 A IDNN3,N Sum of deviation vectors b IDNN3,0 b IDNN3,1 ... b IDNN3,N In the form of.

[0140] The IDNN1 1610A can receive input vector CDF. L (x i And based on the input vector CDF L (x i The connection vector Θ is generated using the weights (weight values). L * The IDNN2 1610B can accept the input vector CDF. R (x i And based on the input vector CDF R (x i ) and weights generate connection vector Θ R * The IDNN3 1620 can receive the connection vector Θ. L * and Θ R *and based on the connection vector Θ L * and Θ R *And weights are used to generate the optimal read threshold voltage Vt_opt. Specifically, the connection vector Θ L * and Θ R *And the optimal readout threshold voltage OptVt is expressed as follows:

[0141]

[0142]

[0143]

[0144] In the equation above, I A CDF represents the input vector (features) of IDNN1 1610A. L (xi ), I B CDF represents the input vector of IDNN21610B. R (x i ), where R represents the activation function. For example, the rectified linear unit (ReLU) activation function can be used. Other activation functions may be applicable. M and N can be the same or different. Θ R * / Θ L The activation function R used in * and the R used in the OptVt calculation can be the same or different. This example is only one implementation, and other implementations are possible and applicable. Therefore, IDNN1, IDNN3, and Θ R * / Θ L * Jointly designed.

[0145] Therefore, CDNN 1600 has a stage between CDF measurement and optimal Vt prediction. The accuracy of CDNN is measured only by its best predicted Vt. Since no model assumptions are manually made, the network can learn to represent various distributions that appear in the training data in an unsupervised manner, and learn to estimate the best Vt for each distribution.

[0146] As described above, the embodiments provide a scheme for estimating the optimal read threshold voltage using a stage between CDF measurement and optimal Vt estimation. The embodiments eliminate the time-consuming step of reserving networks for different distribution models and ensure high reliability for future NAND products with cell threshold voltage distributions having different PV levels.

[0147] Although the embodiments described in detail above have been provided for clarity and understanding, the invention is not limited to the details provided. Those skilled in the art will appreciate from the foregoing disclosure that many alternative ways of carrying out the invention exist. Therefore, the disclosed embodiments are illustrative and not restrictive. The invention is intended to include all modifications and substitutions falling within the scope of the claims. Furthermore, embodiments may be combined to form additional embodiments.

Claims

1. A memory system, comprising: A memory device comprising multiple units; as well as The controller includes a combined neural network, said combined neural network: Receive a first cumulative distribution function value, i.e., a first CDF value, and a second cumulative distribution function value, i.e., a second CDF value, each CDF value corresponding to a programming voltage level, i.e., a PV level, associated with a read operation on the unit; Based on the first CDF value, the second CDF value, and the first weight value, a first connection vector and a second connection vector are generated. and Based on the first connection vector, the second connection vector, and the second weight value, the optimal readout threshold voltage is estimated. The combined neural network includes: A first neural network receives the first CDF value and generates the first connection vector based on the first CDF value and the first weight value; The second neural network receives the second CDF value and generates the second connection vector based on the second CDF value and the first weight value; The third neural network receives the first connection vector and the second connection vector and generates the optimal readout threshold voltage based on the first connection vector, the second connection vector, and the second weight value.

2. The memory system of claim 1, wherein the controller further uses the optimal read threshold voltage to perform the next read operation on the cell.

3. The memory system of claim 1, wherein the combined neural network is trained based on a set dataset including CDF values, sampling voltages corresponding to the CDF values, and the optimal read threshold voltage.

4. The memory system of claim 3, wherein the combined neural network measures the error between the output of the combined neural network and the optimal read threshold voltage to determine a set loss function.

5. The memory system according to claim 4, wherein the first weight value and the second weight value are obtained by a stochastic gradient descent algorithm to minimize the loss function.

6. The memory system of claim 4, wherein each weight value comprises a plurality of matrices and a bias vector.

7. The memory system of claim 6, wherein the first neural network generates the first connection vector based on the first CDF value, the first weight value, and a set activation function; The second neural network generates the second connection vector based on the second CDF value, the first weight value, and the activation function; and The third neural network generates the optimal readout threshold voltage based on the first connection vector, the second connection vector, the second weight value, and the activation function.

8. The memory system of claim 4, wherein the error includes the mean square error between the output of the combined neural network and the optimal read threshold voltage.

9. A method of operating a memory system, the memory system comprising a memory device including a plurality of cells and a controller including a combined neural network, the method comprising: Receive a first cumulative distribution function value, i.e., a first CDF value, and a second cumulative distribution function value, i.e., a second CDF value, each CDF value corresponding to a programming voltage level, i.e., a PV level, associated with a read operation on the unit; Based on the first CDF value, the second CDF value, and the first weight value, a first connection vector and a second connection vector are generated; and Based on the first connection vector, the second connection vector, and the second weight value, the optimal readout threshold voltage is estimated. The combined neural network includes a first neural network, a second neural network, and a third neural network, and The estimation of the optimal reading threshold includes: The first CDF value is received through the first neural network, and the first connection vector is generated based on the first CDF value and the first weight value. The second CDF value is received through the second neural network, and the second connection vector is generated based on the second CDF value and the first weight value; and The third neural network receives the first connection vector and the second connection vector, and generates the optimal readout threshold voltage based on the first connection vector, the second connection vector, and the second weight value.

10. The method of claim 9, further comprising: The next read operation is performed on the cell using the optimal read threshold voltage.

11. The method of claim 9, further comprising: The combined neural network is trained based on a set dataset including CDF values, sampling voltages corresponding to the CDF values, and the optimal readout threshold voltage.

12. The method of claim 11, further comprising: The error between the output of the combined neural network and the optimal readout threshold voltage is measured using the combined neural network to determine the set loss function.

13. The method of claim 12, wherein the first weight value and the second weight value are obtained by a stochastic gradient descent algorithm to minimize the loss function.

14. The method of claim 12, wherein each weight value comprises a plurality of matrices and a bias vector.

15. The method of claim 14, wherein the first neural network generates the first connection vector based on the first CDF value, the first weight value, and a set activation function; The second neural network generates the second connection vector based on the second CDF value, the first weight value, and the activation function; and The third neural network generates the optimal readout threshold voltage based on the first connection vector, the second connection vector, the second weight value, and the activation function.

16. The method of claim 12, wherein the error includes the mean square error between the output of the combined neural network and the optimal readout threshold voltage.

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