Memory chip package structure, sdram circuit board, test method and storage medium

Abstract

The present disclosure provides a memory chip packaging structure, an SDRAM circuit board, a test method and a storage medium, and relates to the technical field of semiconductors. The memory chip packaging structure comprises a substrate provided with conductive pads; at least one wafer stacked on the substrate, the wafer being provided with first bonding pads, and the first bonding pads being electrically connected with corresponding conductive pads; an interposer provided on the at least one wafer, the interposer being provided with second bonding pads corresponding to the electrical connection and test points, and the second bonding pads also being electrically connected with corresponding first bonding pads; and a plastic encapsulation member injection-molded on the substrate, used for encapsulating the at least one wafer and the interposer, and the plastic encapsulation member being provided with a test hole at a position opposite to the test points on the upper surface of the plastic encapsulation member, so as to expose the test points. Through the technical scheme of the present disclosure, the influence of noise on test signals can be more accurately eliminated, and the test precision of the memory chip is thus improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a memory chip packaging structure, an SDRAM circuit board for testing, a memory chip testing method and a computer readable storage medium. BACKGROUND

[0002] In the related art, in order to test DDR4 (DDR SDRAM, Double Data Rate Synchronous Dynamic Random Access Memory) / LPDDR4 (Low Power Double Data Rate Synchronous Dynamic Random Access Memory), due to the high device layout density on the test mainboard, and due to the difficulty of directly reserving test points on the test mainboard, a signal test board is welded between the memory chip and the mainboard for testing, and test points are reserved on the signal test board, but the test scheme still has the following defects:

[0003] On the one hand, the high device layout density of the test mainboard also leads to high difficulty in welding the signal test board, and on the other hand, the insertion of the signal test board also introduces power loss, combined with the power loss introduced by the packaged memory chip which cannot be accurately measured, the deviation between the test signal and the actual signal can be reduced through de-embedding processing, but the test accuracy of the memory chip is still deviated.

[0004] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0005] The purpose of the present disclosure is to provide a memory chip packaging structure, an SDRAM circuit board, a testing method and a storage medium.

[0006] Other characteristics and advantages of the present disclosure will become apparent from the following detailed description, or will be learned by practice of the present disclosure.

[0007] According to one aspect of the present disclosure, a memory chip package structure is provided, comprising: a substrate provided with conductive pads; at least one wafer stacked on the substrate, the wafer being provided with first bonding pads, the first bonding pads being electrically connected with corresponding conductive pads; an interposer provided on the at least one wafer, the interposer being provided with second bonding pads and test points corresponding to the electrically connected second bonding pads, the second bonding pads being further electrically connected with corresponding first bonding pads; and a plastic encapsulation member injection-molded on the substrate for encapsulating the at least one wafer and the interposer, an upper surface of the plastic encapsulation member being provided with a test hole at a position opposite to the test points to expose the test points.

[0008] In one exemplary embodiment of the present disclosure, the semiconductor bonding wires are electrically connected between corresponding second bonding pads and first bonding pads.

[0009] In one exemplary embodiment of the present disclosure, the second bonding pads are arranged close to a board edge of the interposer opposite to the test points, wherein the length of the semiconductor bonding wires is greater than or equal to 340 um and less than or equal to 360 um.

[0010] In one exemplary embodiment of the present disclosure, the second bonding pads and the test points corresponding to the electrically connected second bonding pads are arranged on the same test pad.

[0011] In one exemplary embodiment of the present disclosure, the length of the test pad is greater than or equal to 140 um and less than or equal to 160 um.

[0012] In one exemplary embodiment of the present disclosure, the test points and corresponding second bonding pads are electrically connected by conductive traces.

[0013] In one exemplary embodiment of the present disclosure, the test points include signal test points and first ground test points, and power test points and second ground test points, wherein the signal test points and the first ground test points are arranged adjacent to each other, and the power test points and the second ground test points are arranged adjacent to each other.

[0014] In one exemplary embodiment of the present disclosure, the signal test points and the first ground test points are arranged at one end of the interposer, and the power test points and the second ground test points are arranged at the other end of the interposer.

[0015] In one exemplary embodiment of the present disclosure, an insulating adhesive layer is arranged between the at least one wafer and the substrate.

[0016] In one exemplary embodiment of the present disclosure, the Young's modulus of the insulating adhesive layer is greater than the Young's modulus of the plastic encapsulation member.

[0017] In an example embodiment of the present disclosure, the filler content of the plastic package is less than the filler content of the insulating adhesive layer.

[0018] In an example embodiment of the present disclosure, the insulating adhesive layer further comprises: a first insulating adhesive layer in contact with the substrate; and a second insulating adhesive layer on the first insulating adhesive layer and in contact with the wafer, wherein the first insulating adhesive layer has a thermal expansion coefficient less than that of the second insulating adhesive layer.

[0019] According to another aspect of the present disclosure, there is provided an SDRAM circuit board for testing, comprising: a test mainboard; and a memory chip package structure as described in any of the above embodiments, welded on the test mainboard.

[0020] According to still another aspect of the present disclosure, there is provided a testing method of a memory chip, comprising: covering an interposer board provided with test points on at least one wafer and establishing electrical connection with the wafer; injection molding the interposer board and the at least one wafer on a substrate by using a plastic package to form a memory chip package structure, wherein an upper surface of the plastic package is provided with a test hole at a position opposite to the test points to expose the test points; welding the memory chip package structure on a test mainboard; and contacting probes of a test fixture with the test points to perform a test operation.

[0021] According to still another aspect of the present disclosure, there is provided a computer readable medium having a computer program stored thereon, which, when executed by a processor, implements the testing method of a memory chip as described in the above embodiments.

[0022] The memory chip package structure and the SDRAM circuit board provided by the embodiments of the present disclosure have the following advantages. The interposer board is arranged on the upper layer of the wafer layer, and the second bonding pad and the test point are arranged on the interposer board and electrically connected, respectively. The second bonding pad is used to realize electrical connection with the first bonding pad on the wafer, and the conductive contact piece electrically connected with the first bonding pad is used to ensure reliable electrical property of the test point after the memory chip package structure is attached to the test mainboard. Further, the interposer board provided with the test point and the wafer are both encapsulated in the plastic package to form a chip particle, and the test point is arranged close to the wafer, so that the power supply noise of the memory chip can be directly detected, and the voltage of the measurement point can accurately reflect the internal voltage of the memory chip, so that the influence of the noise on the test signal can be more accurately eliminated, thereby facilitating improvement of the test precision of the memory chip.

[0023] In addition, the chip grain formed only needs to increase the height compared with the original SDRAM chip, and thus the reliable test of the SDRAM chip can be realized without increasing the soldering difficulty.

[0024] It should be understood that the general description above and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0025] The drawings incorporated in the specification and constituting a part of the specification illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0026] Figure 1 A schematic diagram of an SDRAM circuit board for testing in the related art is shown;

[0027] Figure 2 A schematic diagram of another SDRAM circuit board for testing in the related art is shown;

[0028] Figure 3 A schematic diagram of a memory chip packaging structure provided by an embodiment of the present disclosure is shown;

[0029] Figure 4 A schematic diagram of a memory chip packaging structure provided by another embodiment of the present disclosure is shown;

[0030] Figure 5 A schematic diagram of an interposer provided by an embodiment of the present disclosure is shown;

[0031] Figure 6 A schematic diagram of an interposer provided by another embodiment of the present disclosure is shown;

[0032] Figure 7 A schematic diagram of a memory chip packaging structure provided by another embodiment of the present disclosure is shown;

[0033] Figure 8 A top view schematic diagram of a memory chip packaging structure provided by an embodiment of the present disclosure is shown;

[0034] Figure 9 A schematic diagram of an SDRAM circuit board for testing provided by an embodiment of the present disclosure is shown;

[0035] Figure 10A schematic flow chart of a testing method of a memory chip is shown according to an embodiment of the present disclosure;

[0036] Figure 11 A structural schematic diagram of a computer system of an electronic device suitable for implementing the embodiments of the present disclosure is shown according to an embodiment of the present disclosure.

[0037] wherein, Figures 1 to 9 The reference signs in the drawings are explained as follows:

[0038] 102 test mainboard, 104 memory chip, 106 test point, 108 signal test board, 110 pad raising board, 112 other elements, 302 substrate, 304 conductive contact, 306 wafer, 308 first bonding pad, 310 interposer, 312 second bonding pad, 314 test point, 316 plastic package, 318 connecting line, 320 test pad, 322 conductive trace, 324A first insulating adhesive layer, 324B second insulating adhesive layer, 316A test hole, 326 solder ball, 40 test mainboard. DETAILED DESCRIPTION

[0039] Example implementations are now described with reference to the drawings; however, these implementations are merely examples of implementations and are not intended to limit example implementations in any way. In fact, example implementations described in this disclosure can be used in any number of ways, combinations, and sub-combinations. It is understood that one implication of the drawings is that elements of an implementation can be added, removed, modified, or supplemented. Additionally, it is understood that one implication of the drawings is that certain elements of an implementation can be combined, separated, or supplemented. It is further understood that one implication of the drawings is that certain elements of an implementation can be combined, separated, or supplemented with other elements of the same or different implementations.

[0040] In addition, the drawings are merely schematic and are not necessarily drawn to scale. Like reference numerals designate like elements throughout the drawings. Some of the blocks in the drawings represent functional entities that can be realized in software, or in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0041] The flow charts shown in the drawings are merely exemplary and do not necessarily include all of the content and steps, nor do they necessarily have to be performed in the order described. For example, some steps can be broken down, while some steps can be combined or partially combined, so the actual order of execution can be changed according to the actual situation. The terms "one", "a", and "the" are used to indicate the presence of one or more elements / components / etc. The terms "comprise", "include", and "have" are used to indicate an open-ended inclusion and refer to the presence of additional elements / components / etc. in addition to the listed elements / components / etc.

[0042] In some embodiments, in the scheme of testing the power supply and signals of the memory chip, as shown in FIG. 1, the memory chip 104 is surface-mounted on the test mainboard 102, and the test points 106 of the memory chip 104 are directly arranged, but it is difficult to measure the power supply from the test points reserved on the test mainboard 102 due to the layout of the mainboard. Figure 1

[0043] As shown in FIG. 2, a signal test board 108 is inserted between the test mainboard 102 and the memory chip 104 to arrange the test points 106 on the signal test board 108, and in order to insert the signal test board 108, a spacer board 110 is also inserted between the signal test board 108 and the test mainboard 102, in combination with other elements 112 on the test mainboard 102, the inserted test board introduces power loss, and it is also difficult to measure the power loss introduced by the package due to the test points outside the packaged memory chip 104. Figure 2

[0044] As shown in FIG. 3, the branch trace length of the test points 106 on the signal test board 108 is at most 10 mm, and if the channel frequency of the branch trace exceeds 2 GHz, a large frequency attenuation will be generated, which cannot meet the test requirements of the LPDDR4 memory chip with a basic frequency higher than 2 GHz. Figure 1

[0045] In addition, as shown in FIG. 4, due to the additional trace design on the signal test board, the test points also need to be arranged in the middle of the signal line, which shortens the branch trace length of the tested signal line to not more than 0.3 mm. Although this method can meet the test requirements, the trace difficulty and PCB processing difficulty are very large in some package types with a large BALL map density. Figure 2

[0046] In order to solve the defects in the above embodiments, with reference to FIG. 5, the embodiments of the present disclosure first provide a memory chip packaging structure, which comprises a substrate 302, at least one wafer 306, an interlayer board 310 and a plastic package 316, wherein, Figure 3 The substrate 302 is provided with a conductive contact 304.

[0047] The conductive contact plate is used to realize electrical connection with the wafer 306 and the interlayer board 310.

[0048] The at least one wafer 306 is stacked on the substrate 302, and the wafer 306 is provided with a first bonding pad 308, and the first bonding pad 308 and the corresponding conductive contact 304 are electrically connected.

[0049]

[0050] ​​​​​The interposer plate 310 is arranged on the at least one wafer 306, and the interposer plate 310 is provided with the second bonding pad 312 and the test point 314 corresponding to the electrical connection, and the second bonding pad 312 is also electrically connected with the corresponding first bonding pad 308.

[0051] The second bonding pad 312 on the interposer plate 310 is used for electrical connection with the first bonding pad 308, and the interposer plate 310 is also provided with the test point 314 in contact with the probe of the test fixture.

[0052] The plastic package 316 is injection molded on the substrate 302, and is used for plastic packaging of the at least one wafer 306 and the interposer plate 310, and a test hole is formed on the upper surface of the plastic package 316 at a position opposite to the test point 314, so as to expose the test point 314.

[0053] The first improvement of the plastic package 316 is that the height of the plastic package 316 needs to be increased because the interposer plate also needs to be plastic packaged inside, and the second improvement of the plastic package 316 is that a test hole is formed on the top of the plastic package 316 at a position corresponding to the test point 314, and the size of the test hole is determined to facilitate the probe of the test fixture to contact the test point 314.

[0054] In this embodiment, by arranging the interposer plate on the upper layer of the wafer, and arranging the electrically connected second bonding pad and test point on the interposer plate respectively, the second bonding pad is used to realize electrical connection with the first bonding pad on the wafer, and the conductive contact piece electrically connected with the first bonding pad is used to ensure the reliable electrical property of the test point after the memory chip packaging structure is pasted on the test mainboard, further, by packaging the interposer plate provided with the test point and the wafer in the inside of the plastic package, a chip particle is formed, the test point is arranged close to the wafer, the power supply noise of the memory chip can be directly detected, the voltage of the measurement point can accurately reflect the internal voltage of the memory chip, the influence of the noise on the test signal can be more accurately eliminated, thereby the test precision of the memory chip is improved.

[0055] In addition, compared with the operation of increasing the welding of the signal test board in the test scheme in the related art, because the chip particle only needs to increase the height compared with the original SDRAM chip, the reliable test of the SDRAM chip can be realized without increasing the welding difficulty, and compared with the scheme of increasing the signal test board, the wiring difficulty and processing difficulty of the circuit board are reduced.

[0056] As Figure 3As shown, the addition of an interposer introduces stub lines into the entire memory chip package structure, including the connection line 318 between the second bonding pad 312 and the first bonding pad 308, and the conductive trace between the second bonding pad 312 and the test point 314 (not shown in the figure). In this embodiment, by creating a cut-out layer on other circuit layers in the second bonding pad area of ​​the interposer, it is beneficial to improve impedance and reduce the impact of stub lines on the performance of the memory chip package structure.

[0057] like Figure 3 As shown, in an exemplary embodiment of this disclosure, the connection line 318 between the corresponding second bonding pad 312 and the first bonding pad 308 is a semiconductor bonding wire.

[0058] In this embodiment, by using semiconductor bonding wire as the stub wire to connect the two corresponding bonding pads, it has advantages such as high conductivity, strong electrical conductivity, strong bonding force with conductor materials, and stable chemical properties, which helps to further reduce the impact of the stub wire on the performance of the memory chip packaging structure.

[0059] In one exemplary embodiment of this disclosure, the second bonding pad 312 is disposed near the edge of the interposer 310 relative to the test point, wherein the length of the semiconductor bonding wire is greater than or equal to 340 μm and less than or equal to 360 μm.

[0060] Preferably, the length of the semiconductor bonding wire is controlled to be around 350 μm.

[0061] like Figure 4 As shown, the memory chip packaging structure disclosed herein includes wafer 306A and wafer 306B. A first bonding pad 308A is provided on wafer 306A, and a first bonding pad 308B is provided on wafer 306B. A second bonding pad 312A and a second bonding pad 312B are provided on an interposer 310. Conductive contacts 304A and 304B are provided on a substrate 302. The conductive contacts 304A, the first bonding pad 308A, and the second bonding pad 312A are connected by a connecting line 318A, and the conductive contacts 304B, the first bonding pad 308B, and the second bonding pad 312B are connected by a connecting line 318B.

[0062] In this embodiment, the impact of the stub line on the memory chip package structure performance is further reduced by setting the second bonding pad close to the edge of the interposer and by controlling the length of the semiconductor bonding wire.

[0063] like Figure 5As shown in the figure, in an example embodiment of the present disclosure, on the interposer 310, the second bonding pads 312 and the test points 314 corresponding to the electrical connection are arranged on the same test pads 320, i.e., the second bonding pad 312A and the test point 314A are arranged on the same test pad 320A, and the second bonding pad 312B and the test point 314B are arranged on the same test pad 320B.

[0064] In this embodiment, as the first connection mode of the second bonding pad and the test point, the second bonding pad and the test point are arranged on the same test pad, which is conducive to ensuring the reliability of the electrical connection between the two.

[0065] Specifically, as shown in the figure, Figure 4 312A is a test bonding pad, which can be a signal test bonding pad or a power test bonding pad, and 312B is a ground bonding pad. By arranging the ground bonding pad next to the test bonding pad, the loop inductance in the test path can be reduced.

[0066] In an example embodiment of the present disclosure, the length of the test pad is greater than or equal to 140um and less than or equal to 160um.

[0067] Preferably, the length of the test pad is 150um.

[0068] In this embodiment, by limiting the length of the test pad, the influence of the stub line on the test signal can be reduced while ensuring electrical reliability.

[0069] As shown in the figure, Figure 6 In an example embodiment of the present disclosure, on the interposer 310, the test point 314 and the corresponding second bonding pad 312 are electrically connected by the conductive trace 322.

[0070] In this embodiment, as the second connection mode of the second bonding pad and the test point, the electrical connection by the trace can also ensure the acquisition of the test signal based on the test point.

[0071] As shown in the figure, Figure 6 In an example embodiment of the present disclosure, the test point includes a signal test point 314C and a first ground test point 314D, and a power test point 314E and a second ground test point 314F, wherein the signal test point 314C and the first ground test point 314D are arranged adjacent to each other, and the power test point 314E and the second ground test point 314F are arranged adjacent to each other, so as to reduce the loop inductance in the test path.

[0072] Specifically, signal test point 314C is connected to the second bonding pad 312C via trace 322C, first ground test point 314D is connected to the second bonding pad 312D via trace 322D, power test point 314E is connected to the second bonding pad 312E via trace 322E, and second ground test point 314F is connected to the second bonding pad 312F via trace 322F.

[0073] like Figure 6 As shown, in an exemplary embodiment of this disclosure, signal test point 314C and first ground test point 314D are disposed at one end of the interposer plate; power test point 314E and second ground test point 314F are disposed at the other end of the interposer plate.

[0074] In one exemplary embodiment of this disclosure, an insulating adhesive layer is disposed between at least one wafer and a substrate.

[0075] In one exemplary embodiment of this disclosure, the Young's modulus of the insulating adhesive layer is greater than that of the molding compound.

[0076] In another exemplary embodiment of this disclosure, the filler content of the molding compound is less than the filler content of the insulating adhesive layer.

[0077] In this embodiment, since the insulating adhesive layer and the molding compound have different filler contents, by setting a larger filler content in the insulating adhesive layer, the Young's modulus of the insulating adhesive layer is made to be greater than that of the molding compound. This setting method is conducive to better elastic deformation of the insulating adhesive layer, so that the insulating layer can better support the wafer.

[0078] In addition, those skilled in the art will understand that when a wafer has multiple layers, an insulating adhesive layer is also provided between adjacent wafer layers.

[0079] like Figure 7 As shown, in an exemplary embodiment of this disclosure, the insulating adhesive layer further includes: a first insulating adhesive layer 324A, which is in contact with the substrate 302; and a second insulating adhesive layer 324B, which is located on the first insulating adhesive layer and is in contact with the wafer 306; wherein the coefficient of thermal expansion of the first insulating adhesive layer is smaller than the coefficient of thermal expansion of the second insulating adhesive layer.

[0080] Specifically, such as Figure 7 As shown, a second insulating adhesive layer 324B is also provided between adjacent wafers 306. By providing conductive contacts 304 on the substrate 302, a first bonding pad 308 on the wafer 306, and a second bonding pad 312 on the interposer, and connecting them sequentially with connecting lines 318, and further, connecting the second bonding pad 312 with the test point 314 with conductive traces, the function of testing the SDRAM chip based on the test point 314 is realized.

[0081] In this embodiment, for the insulating adhesive layer between the substrate and the wafer, a first insulating adhesive layer and a second insulating adhesive layer configuration can be further adopted. Since more heat is accumulated on the substrate, the first insulating adhesive layer with a smaller coefficient of thermal expansion is selected, so that the thermal expansion deformation of the first insulating adhesive layer is small, thereby making the deformation between the second insulating adhesive layer and the first insulating layer more matched, and further facilitating the improvement of the overall warping phenomenon of the wafer and the substrate.

[0082] As shown in the top view of the memory chip packaging structure according to one embodiment of the present disclosure, the test hole 316A is opened on the plastic package 316 to expose the test point 314 to the outside, thereby facilitating testing. Figure 8

[0083] As shown in the top view of the memory chip packaging structure according to one embodiment of the present disclosure, the test hole 316A is opened on the plastic package 316 to expose the test point 314 to the outside, thereby facilitating testing. Figure 9 Specifically, the memory chip packaging structure includes a substrate 302, a wafer 306, an interlayer board 310, and a plastic package 316 for packaging the above-mentioned devices.

[0084] In this embodiment, the interlayer board is arranged on the upper layer of the wafer layer, and the electrically connected second bonding pad and test point are arranged on the interlayer board, respectively. The second bonding pad is used to realize electrical connection with the first bonding pad on the wafer, and the conductive contact piece electrically connected with the first bonding pad is combined to ensure the reliable electrical property of the test point after the memory chip packaging structure is attached to the test mainboard. Further, by encapsulating the interlayer board and the wafer provided with the test point in the plastic package, a chip particle is formed, the test point is arranged close to the wafer, the power supply noise of the memory chip can be directly detected, the voltage of the measurement point can accurately reflect the internal voltage of the memory chip, the influence of the noise on the test signal can be more accurately eliminated, and thus the test precision of the memory chip is improved.

[0085] In addition, compared with the welding operation of the signal test board in the test scheme in the related art, since the chip particle only needs to increase the height compared with the original SDRAM chip, the reliable test of the SDRAM chip can be realized without increasing the welding difficulty, and compared with the scheme of increasing the signal test board, the wiring difficulty and processing difficulty of the circuit board are reduced.

[0086] As shown in the top view of the memory chip packaging structure according to one embodiment of the present disclosure, the test hole 316A is opened on the plastic package 316 to expose the test point 314 to the outside, thereby facilitating testing.

[0087] Figure 10 As shown in the top view of the memory chip packaging structure according to one embodiment of the present disclosure, the test hole 316A is opened on the plastic package 316 to expose the test point 314 to the outside, thereby facilitating testing. ​​

[0088] Step S1002, the interposer provided with the test points is covered on the at least one wafer, and the electrical connection between the interposer and the wafer is established.

[0089] Step S1004, the interposer and the at least one wafer are injection molded on the substrate by using the plastic package, and the test holes are formed on the upper surface of the plastic package opposite to the positions of the test points to expose the test points.

[0090] Step S1006, the memory chip package structure is welded on the test mainboard.

[0091] Step S1008, the probe of the test fixture is contacted with the test points to perform the test operation.

[0092] The test points include the signal test points and the first ground test points, and the power supply test points and the second ground test points, wherein the signal test points are used for testing the chip signals, the power supply test points are used for testing the power supply signals, the wafer is provided with the first bonding pads, the interposer is provided with the second bonding pads, and the first bonding pads and the second bonding pads are electrically connected by using the semiconductor bonding wires.

[0093] Specifically, first, an interposer is provided, the power supply test points and the ground test points are arranged on the interposer, and the second bonding pads for press welding are reserved, further, when the SDRAM is packaged, the interposer is packaged and solidified together with the wafer by using the plastic package to form the chip package structure, wherein the second bonding pads respectively connected with the power supply test points, the signal test points and the ground test points on the interposer are connected with the first bonding pads on the wafer by using the bonding wires, after the overall packaging and solidification are completed, the test holes are formed on the top of the plastic package to expose the test points to the outside.

[0094] Further, the chip package structure is welded on the test mainboard, the probe of the test fixture is contacted with the exposed test points to test the power supply and the signals.

[0095] Reference is made to the following description of the drawings. Figure 11 Fig. 1 shows a structural schematic diagram of a computer system 1100 of an electronic device suitable for implementing the embodiments of the present disclosure. Figure 11 The computer system 1100 of the electronic device shown is only an example, and should not bring any limitation to the functions and use range of the embodiments of the present disclosure.

[0096] As shown in Fig. 1, the computer system 1100 of the electronic device includes a processor 1102, a memory 1104, a storage 1106, a keyboard 1108, a mouse 1110, a display 1112, and other input / output devices 1114. Figure 11As shown, the computer system 1100 includes a central processing unit (CPU) 1101 which can execute various appropriate actions and processes according to programs stored in a read only memory (ROM) 1102 or loaded from a storage section 1108 into a random access memory (RAM) 1103. Various programs and data required for system operation are also stored in the RAM 1103. The CPU 1101, the ROM 1102, and the RAM 1103 are connected to each other through a bus 1104. An input / output (I / O) interface 1105 is also connected to the bus 1104.

[0097] The following components are connected to the I / O interface 1105: an input section 1106 including a keyboard, a mouse, etc.; an output section 1107 including a display such as a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 1108 including a hard disk, etc.; and a communication section 1109 including a network interface card such as a LAN card, a modem, etc. The communication section 1109 performs communication processing via a network such as the Internet. A drive 1110 is also connected to the I / O interface 1105 as necessary. A removable media 1111 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc. is attached to the drive 1110 as necessary, so that a computer program read therefrom is installed into the storage section 1108 as necessary.

[0098] As another aspect, the present application also provides a computer readable medium, which can be included in the electronic device described in the above embodiments; or can exist separately without being assembled into the electronic device. The above computer readable medium carries one or more programs, which when executed by the electronic device, cause the electronic device to implement the memory chip testing method as defined in the above embodiments.

[0099] In particular, according to embodiments of the present disclosure, the processes described above with reference to the flowcharts can be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a computer readable medium, the computer program comprising program code for executing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network by the communication section, and / or installed from a removable medium. When the computer program is executed by a central processing unit (CPU), the above functions defined in the system of the present application are executed.

[0100] It should be noted that the computer-readable medium shown in the present disclosure can be a computer-readable signal medium or a computer-readable storage medium or any combination of the two. The computer-readable storage medium may, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or apparatus, or any combination of the above. More specific examples of computer-readable storage media can include, but are not limited to, an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, the computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device or apparatus. In the present disclosure, the computer-readable signal medium can include a data signal carried in a baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals or any suitable combination thereof. The computer-readable signal medium can also be any computer-readable medium other than the computer-readable storage medium, which can send, propagate or transmit a program for use by or in conjunction with an instruction execution system, device or apparatus. The program code contained on the computer-readable medium can be transmitted by any suitable medium, including but not limited to wireless, wire, optical cable, RF, etc., or any suitable combination thereof.

[0101] In the present application, the terms "first", "second", "third" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance; the term "multiple" refers to two or more, unless otherwise explicitly limited. The terms "mounting", "connecting", "connecting", "fixing" and the like should be broadly understood, for example, "connecting" can be fixed connection, or detachable connection, or integral connection; "connecting" can be direct connection, or indirect connection through intermediate medium. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0102] In the description of the present application, it should be understood that the orientation or position relationship indicated by the terms "up", "down", "left", "right", "front", "back" and the like is based on the orientation or position relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or unit referred to must have a particular direction, be constructed and operated in a particular orientation, therefore, it cannot be understood as a limitation on the present application.

[0103] In the description of the application, the terms "one embodiment", "some embodiments", "certain embodiments", etc. do not necessarily refer to the same embodiment or example, but instead can refer to a different embodiment or example. Furthermore, the described

[0104] The preferred embodiments of the application are described above in detail. The application is not limited to the embodiments described above, but can vary and be modified in various ways without departing from the scope of the application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the application should be included in the scope of the application.

[0105] Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the present disclosure cover any and all variations of the application that come within the scope of the following claims and their equivalents. It is intended that the specification and examples be considered exemplary only, with the true scope and spirit of the application indicated by the following claims.

Claims

1. A memory chip packaging structure, characterized in that, include: The substrate is provided with conductive contacts; At least one wafer is stacked on the substrate, and the wafer is provided with a first bonding pad, and the first bonding pad and the corresponding conductive contact are electrically connected. An interposer is disposed on the at least one wafer layer, the interposer being provided with a second bonding pad and a test point for corresponding electrical connections, the second bonding pad being also electrically connected to a corresponding first bonding pad; A molding compound is injection molded onto the substrate to encapsulate at least one wafer and the interposer. A test hole is provided on the upper surface of the molding compound at a position opposite to the test point to expose the test point.

2. The memory chip packaging structure according to claim 1, characterized in that, The corresponding second bonding pad and the first bonding pad are electrically connected by semiconductor bonding alloy wire.

3. The memory chip packaging structure according to claim 2, characterized in that, The second bonding pad is positioned relative to the test point near the edge of the interposer plate. The length of the semiconductor bonding wire is greater than or equal to 340 μm and less than or equal to 360 μm.

4. The memory chip packaging structure according to claim 1, characterized in that, The second bonding pad corresponding to the electrical connection and the test point are set on the same test pad.

5. The memory chip packaging structure according to claim 4, characterized in that, The length of the test pad is greater than or equal to 140µm and less than or equal to 160µm.

6. The memory chip packaging structure according to claim 1, characterized in that, The test point and the corresponding second bonding pad are electrically connected by conductive traces.

7. The memory chip packaging structure according to claim 4 or 6, characterized in that, The test points include a signal test point and a first ground test point, as well as a power supply test point and a second ground test point, wherein... The signal test point and the first ground test point are arranged adjacent to each other, and the power supply test point and the second ground test point are arranged adjacent to each other.

8. The memory chip packaging structure according to claim 7, characterized in that, The signal test point and the first ground test point are located at one end of the interlayer plate; The power test point and the second ground test point are located at the other end of the interlayer plate.

9. The memory chip packaging structure according to any one of claims 1 to 8, characterized in that, An insulating adhesive layer is disposed between the at least one wafer and the substrate.

10. The memory chip packaging structure according to claim 9, characterized in that, The Young's modulus of the insulating adhesive layer is greater than that of the molding compound.

11. The memory chip packaging structure according to claim 9, characterized in that, The filler content of the molding compound is less than the filler content of the insulating adhesive layer.

12. The memory chip packaging structure according to claim 9, characterized in that, The insulating adhesive layer includes: The first insulating adhesive layer is in contact with the substrate; The second insulating adhesive layer is located on the first insulating adhesive layer and is in contact with the wafer; The coefficient of thermal expansion of the first insulating adhesive layer is smaller than that of the second insulating adhesive layer.

13. An SDRAM circuit board for testing, characterized in that, include: Test motherboard; The memory chip package structure as described in any one of claims 1 to 12 is soldered onto the test motherboard.

14. A testing method for a memory chip, characterized in that, include: An interlayer with test points is placed over at least one wafer and an electrical connection is established with the wafer. The intermediate layer and the at least one wafer are injection molded onto a substrate using a molding compound to form a memory chip package structure. Test holes are provided on the upper surface of the molding compound at positions opposite to the test points to expose the test points. The memory chip package structure is soldered onto the test motherboard; The probe of the test fixture is brought into contact with the test point to perform the test operation.

15. A computer-readable storage medium having a program stored thereon that, when executed by a processor, implements the testing method for the memory chip as described in claim 14.

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