Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same, wherein the structure includes: a substrate; a plurality of channel layers overlapping on the substrate and along the normal direction of the substrate surface; a gate structure on the substrate, the gate structure surrounding the channel layers; an outer wall on the sidewall surface of the gate structure, the sidewall of the outer wall being recessed relative to the end face of the channel layer; source / drain openings within fin structures on both sides of the gate structure; an isolation groove between adjacent channel layers; an inner wall within the isolation groove; a source / drain doped layer within the source / drain opening; and a dielectric layer on the isolation layer, the dielectric layer covering the plurality of channel layers and the gate structure. By thinning the initial outer wall, the formed outer wall can expose the other two surfaces of the sacrificial layer, thereby facilitating contact with the three surfaces of the sacrificial layer during subsequent etching of part of the sacrificial layer, reducing the difficulty of the etching process, reducing the residue of etching byproducts, and improving the morphology of the isolation groove.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are among the most important components in modern integrated circuits. The basic structure of a MOSFET includes: a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate, the gate structure including: a gate dielectric layer located on the surface of the semiconductor substrate and a gate electrode layer located on the surface of the gate dielectric layer; and source and drain doped regions located in the semiconductor substrate on both sides of the gate structure.

[0003] With the further development of semiconductor technology and the shrinking of gate size, traditional fin field-effect transistors (FETs) face limitations in pinch-off current and increasing operating current. Specifically, traditional FETs control the channel only through three gate sides, and the channel region is limited to the area near the top surface and sidewalls of the fin. This is detrimental to gate control of the channel and results in a small volume of the channel region within the fin, limiting the increase in operating current. Therefore, a gate-all-around (GAA) MOSFET structure has been proposed. This structure allows for omnidirectional channel control by the gate, further reducing off-state current, while also increasing the volume of the channel region, thereby increasing the operating current of the GAA MOSFET.

[0004] However, there are still many problems in the formation process of the existing GAA structure. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the final semiconductor structure.

[0006] To address the aforementioned problems, the present invention provides a semiconductor structure comprising: a substrate; a plurality of channel layers located on the substrate, the plurality of channel layers being stacked perpendicularly along the normal direction of the substrate surface and extending along a first direction parallel to the substrate surface; an isolation layer located on the substrate, the top surface of the isolation layer not exceeding the top surface of the bottom channel layer; an isolation recess located between the ends of adjacent channel layers; an inner wall located within the isolation recess, the inner wall perpendicularly isolating the channel layers in the normal direction of the substrate surface, such that adjacent channel layers are suspended; and a spaced space between the ends of the channel layers. A gate structure on the isolation layer, the gate structure surrounding a plurality of channel layers along a second direction perpendicular to the first direction and parallel to the substrate surface; an outer wall located on the sidewall surface of the gate structure, the sidewall of the outer wall being recessed relative to the end face of the channel layer in the first direction; source / drain doped layers located on both sides of the gate structure, the surface of the source / drain doped layers, the surface of the inner sidewall, and the end face of the channel layer being perpendicular and coplanar; a dielectric layer located on the isolation layer, the dielectric layer covering the gate structure and the plurality of channel layers, and the dielectric layer exposing the top surface of the gate structure.

[0007] Optionally, the isolation groove includes a first corner groove, a middle groove, and a second corner groove arranged along the second direction; the dimensions of the first corner groove and the second corner groove along the first direction are greater than the dimensions of the middle groove along the first direction.

[0008] Optionally, the inner wall includes a first corner layer located in the first corner groove, an intermediate layer located in the intermediate groove, and a second corner layer located in the second corner groove.

[0009] Optionally, the sidewall of the outer wall is recessed relative to the end face of the channel layer by a range of 1 nanometer to 5 nanometers.

[0010] Optionally, the material of the inner sidewall includes silicon nitride.

[0011] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a plurality of initial channel layers and a plurality of initial sacrificial layers on the substrate, wherein the plurality of initial channel layers and the plurality of initial sacrificial layers are stacked perpendicularly at intervals along the normal direction of the substrate surface, and the initial channel layers and the initial sacrificial layers extend along a first direction, the first direction being parallel to the substrate surface; forming an isolation layer on the substrate, wherein the top surface of the isolation layer is not higher than the top surface of the initial channel layer located at the bottom layer; forming a dummy gate structure and an initial outer wall located on the sidewall surface of the dummy gate structure on the substrate, wherein the dummy gate structure spans across the plurality of initial channel layers and the plurality of initial sacrificial layers along a second direction, the second direction being perpendicular to the first direction and parallel to the substrate surface; and using the dummy gate... The structure and the initial outer wall are formed by mask etching of several initial channel layers and several initial sacrificial layers to form source / drain openings, several channel layers, and several sacrificial layers; after forming the source / drain openings, the initial outer wall is thinned to form an outer wall, the dimension of the outer wall parallel to a first direction being smaller than the dimension of the initial outer wall parallel to the first direction; a portion of the sacrificial layer exposed by the source / drain openings is etched back to form an isolation groove between adjacent channel layers; an inner sidewall is formed within the isolation groove; a source / drain doped layer is formed within the source / drain openings, the surface of the source / drain doped layer, the surface of the inner sidewall, and the end face of the channel layer are perpendicular and coplanar; a dielectric layer is formed on the isolation layer, the dielectric layer covering the pseudo-gate structure, several channel layers, and several sacrificial layers, and the dielectric layer exposing the top surface of the pseudo-gate structure.

[0012] Optionally, the isolation groove includes a first corner groove, a middle groove, and a second corner groove arranged along the second direction; the dimensions of the first corner groove and the second corner groove along the first direction are greater than the dimensions of the middle groove along the first direction.

[0013] Optionally, the inner wall includes a first corner layer located in the first corner groove, an intermediate layer located in the intermediate groove, and a second corner layer located in the second corner groove.

[0014] Optionally, the dimension of the outer wall parallel to the first direction is smaller than the dimension of the initial outer wall parallel to the first direction by a range of 1 nanometer to 5 nanometers.

[0015] Optionally, the process for thinning the initial outer wall includes an isotropic etching process.

[0016] Optionally, the method for forming the inner sidewall includes: forming a first initial inner sidewall within the isolation groove, the sidewall and bottom surface of the source / drain opening, the sidewall of the outer sidewall, and the top surface of the dummy gate structure; etching back the first initial inner sidewall until the bottom surface of the source / drain opening and the top surface of the dummy gate structure are exposed, to form a second initial inner sidewall; and etching back the second initial inner sidewall until the outer sidewall and the sidewall of the channel layer are exposed, to form the inner sidewall.

[0017] Optionally, the process for forming the first initial inner wall includes physical vapor deposition, chemical vapor deposition, or atomic layer deposition.

[0018] Optionally, the material of the inner sidewall includes silicon nitride.

[0019] Optionally, after forming the dielectric layer, the method further includes: removing the dummy gate structure and forming a gate opening within the dielectric layer; removing the gate opening to expose the sacrificial layer and forming a gate trench between adjacent channel layers; and forming a gate structure within the gate opening and the gate trench, the gate structure surrounding the channel layer.

[0020] Optionally, the material of the sacrificial layer is different from the material of the channel layer.

[0021] Optionally, the material of the sacrificial layer includes silicon germanium; the material of the channel layer includes silicon.

[0022] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0023] The structure of the technical solution of the present invention includes: an outer wall located on the sidewall surface of the gate structure, wherein, in the first direction, the sidewall of the outer wall is recessed relative to the end face of the channel layer. By thinning the initial outer wall, the formed outer wall can expose the other two surfaces of the sacrificial layer, thereby making it easier for etching to contact the three surfaces of the sacrificial layer during the formation of the isolation groove, reducing the difficulty of the etching process, reducing the residue of etching by-products, and improving the morphology of the isolation groove.

[0024] In addition, since the sidewall of the outer wall is recessed relative to the end face of the channel layer, the outer wall can expose the other two surfaces of the channel layer, thereby increasing the contact area between the source / drain doped layer and the channel layer, which is beneficial to improving the operating current of the device.

[0025] Furthermore, the isolation groove includes a first corner groove, a middle groove, and a second corner groove arranged along the second direction; the dimensions of the first corner groove and the second corner groove along the first direction are larger than the dimension of the middle groove along the first direction; the inner sidewall includes a first corner layer located in the first corner groove, an intermediate layer located in the middle groove, and a second corner layer located in the second corner groove. Due to the reduced difficulty of the etching process, the dimensions of the first corner groove and the second corner groove of the final formed isolation groove are larger, which in turn makes the dimensions of the first corner layer and the second corner layer located in the first corner groove and the second corner groove of the inner sidewall larger, thereby improving the isolation effect of the inner sidewall and reducing the occurrence of leakage problems between the gate structure and the source / drain doped layers.

[0026] Furthermore, the recessed range of the sidewall of the outer wall relative to the end face of the channel layer is 1 nanometer to 5 nanometers. When the recessed range of the sidewall of the outer wall relative to the end face of the channel layer is less than 1 nanometer, the area of ​​the other two sides of the sacrificial layer exposed by the outer wall is small, resulting in defects in the morphology of the subsequently formed isolation groove. When the recessed range of the sidewall of the outer wall relative to the end face of the channel layer is greater than 5 nanometers, the thickness of the outer wall is small, which affects the isolation effect of the outer wall and easily leads to leakage current in adjacent gate structures.

[0027] In the method for forming the technical solution of the present invention, after forming the source / drain opening, the initial outer wall is thinned to form an outer wall, wherein the dimension of the outer wall parallel to the first direction is smaller than the dimension of the initial outer wall parallel to the first direction. By thinning the initial outer wall, the formed outer wall can expose the other two surfaces of the sacrificial layer, thereby making it easier for the etching process to contact the three surfaces of the sacrificial layer during subsequent etching of a portion of the sacrificial layer, reducing the difficulty of the etching process, reducing the residue of etching by-products, and improving the morphology of the isolation groove.

[0028] In addition, since the dimension of the outer wall parallel to the first direction is smaller than the dimension of the initial outer wall parallel to the first direction, the formed outer wall can also expose the other two surfaces of the channel layer, thereby ensuring that the contact area between the source / drain doped layer and the channel layer is increased, which is beneficial to improving the operating current of the device.

[0029] Furthermore, the isolation groove includes a first corner groove, a middle groove, and a second corner groove arranged along the second direction; the dimensions of the first corner groove and the second corner groove along the first direction are larger than the dimension of the middle groove along the first direction; the inner sidewall includes a first corner layer located in the first corner groove, an intermediate layer located in the middle groove, and a second corner layer located in the second corner groove. Due to the reduced difficulty of the etching process, the dimensions of the first corner groove and the second corner groove of the final formed isolation groove are larger, which in turn makes the dimensions of the first corner layer and the second corner layer located in the first corner groove and the second corner groove of the inner sidewall larger, improving the isolation effect of the inner sidewall and reducing the occurrence of leakage problems between the subsequent gate structure and the source / drain doped layers.

[0030] Furthermore, the dimension of the outer wall parallel to the first direction is smaller than the dimension of the channel layer parallel to the first direction by a range of 1 nanometer to 5 nanometers. When the dimension of the outer wall parallel to the first direction is less than 1 nanometer smaller than the initial dimension of the outer wall parallel to the first direction, the area of ​​the other two sides of the sacrificial layer exposed by the outer wall is small, resulting in defects in the morphology of the subsequently formed isolation groove. When the dimension of the outer wall parallel to the first direction is greater than 5 nanometers smaller than the initial dimension of the outer wall parallel to the first direction, the thickness of the outer wall is small, which affects the isolation effect of the outer wall and easily leads to leakage current in adjacent gate structures. Attached Figure Description

[0031] Figure 1 and Figure 2 This is a schematic diagram of a semiconductor structure.

[0032] Figures 3 to 17 This is a schematic diagram of the steps in an embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0033] As described in the background section, the existing GAA structure still has many problems in its formation process. These will be explained in detail below with reference to the accompanying drawings.

[0034] Please refer to Figure 1A substrate 100 is provided; the substrate 100 has a plurality of initial sacrificial layers overlapping along the normal direction of the surface of the substrate 100, and an initial channel layer (not shown) located between two adjacent initial sacrificial layers, wherein the initial sacrificial layers and the initial channel layers extend along a first direction X; a pseudo-gate structure 103 is formed on the substrate 100, the pseudo-gate structure 103 spans the plurality of initial sacrificial layers and the plurality of initial channel layers along a second direction Y, wherein the second direction Y is perpendicular to the first direction X; an outer wall 104 is formed on the sidewall of the pseudo-gate structure 103; the plurality of initial sacrificial layers and the plurality of initial channel layers are etched using the pseudo-gate structure 103 and the outer wall 104 as a mask to form source / drain openings 105, and a plurality of sacrificial layers 101 and a plurality of channel layers 102.

[0035] Please refer to Figure 2 The portion of the sacrificial layer 101 exposed by the source / drain opening 105 is etched to form an isolation groove (not shown) between adjacent channel layers 102; an inner sidewall 106 is formed within the isolation groove.

[0036] In this embodiment, after etching several initial sacrificial layers and several initial channel layers using the dummy gate structure 103 and the outer wall 104 as masks, only one side of the sacrificial layer 101 is exposed. During the etching of the portion of the sacrificial layer 101 exposed by the source / drain opening 105, the etching solution can only contact one side of the sacrificial layer 101, making the etching process more difficult and prone to leaving etching byproducts. Furthermore, the morphology of the resulting isolation groove is also poor. Specifically, the corner areas of the isolation groove are shallow, which prevents the inner wall 106 located in the corner areas from providing adequate isolation, easily leading to leakage between the gate structure and the source / drain doped layers.

[0037] Based on this, the present invention provides a semiconductor structure and a method for forming the same. By performing a back-etching process on the initial outer wall, the formed outer wall can expose the other two sides of the sacrificial layer. This makes it easier for the etching process to contact the three sides of the sacrificial layer during subsequent etching of the sacrificial layer, thereby reducing the difficulty of etching the sacrificial layer.

[0038] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0039] Figures 3 to 17 This is a schematic diagram of the formation process of a semiconductor structure according to an embodiment of the present invention.

[0040] Please refer to Figure 3 Substrate 200 is provided.

[0041] In this embodiment, the substrate 200 is made of silicon.

[0042] Please refer to Figure 4 A plurality of initial channel layers 201 and a plurality of initial sacrificial layers 101 are formed on the substrate 200. The plurality of initial channel layers 201 and the plurality of initial sacrificial layers 202 are stacked perpendicularly at intervals along the normal direction of the surface of the substrate 200, and the initial channel layers 201 and the initial sacrificial layers 202 extend along a first direction X, which is parallel to the surface of the substrate 200.

[0043] In this embodiment, the method for forming a plurality of initial channel layers 201 and a plurality of initial sacrificial layers 101 on the substrate 200 includes: forming a plurality of channel material films overlapping along the normal direction of the surface of the substrate 200 and a sacrificial material film located in two adjacent channel material films on the substrate 200; forming a patterned layer (not shown) on the fin material film; and etching the plurality of channel material films and the plurality of sacrificial material films using the patterned layer as a mask to form a plurality of initial channel layers 201 and a plurality of initial sacrificial layers 101.

[0044] The initial sacrificial layer 202 is made of a different material than the initial channel layer 201. This is because the sacrificial layer needs to be removed during the subsequent formation of the gate structure. Therefore, by using different materials, the initial sacrificial layer 202 and the initial channel layer 201 have a larger etch selectivity, reducing damage to the channel layer during the removal of the sacrificial layer.

[0045] In this embodiment, the initial sacrificial layer 202 is made of silicon-germanium; the initial channel layer 201 is made of silicon. In other embodiments, the initial sacrificial layer may also be made of germanium; the initial channel layer may be made of silicon-germanium.

[0046] Please refer to Figure 5 An isolation layer 203 is formed on the substrate 200, wherein the top surface of the isolation layer 202 is not higher than the top surface of the initial channel layer 201 located at the bottom layer.

[0047] In this embodiment, the method for forming the isolation layer 203 includes: forming an isolation material layer (not shown) on the substrate 200, the isolation material layer covering the sidewalls of a plurality of the initial channel layers 201 and a plurality of the initial sacrificial layers 101; and etching back the isolation material layer to form the isolation layer 203.

[0048] The material of the isolation layer 203 includes silicon oxide or silicon nitride. In this embodiment, the material of the isolation layer 203 is silicon nitride.

[0049] Please refer to Figure 6 After the isolation layer 203 is formed, a pseudo gate structure 204 and an initial outer wall 205 located on the sidewall surface of the pseudo gate structure 204 are formed on the substrate 200. The pseudo gate structure 204 spans a plurality of the initial channel layers and a plurality of the initial sacrificial layers along a second direction Y. The second direction Y is perpendicular to the first direction X and parallel to the surface of the substrate 200.

[0050] In this embodiment, the pseudo-gate structure 204 includes: a gate dielectric layer, a pseudo-gate layer located on the gate dielectric layer, and a protective layer (not shown) located on the pseudo-gate layer.

[0051] In this embodiment, the dummy gate layer is made of polycrystalline silicon; in other embodiments, the dummy gate layer may also be made of amorphous silicon.

[0052] In this embodiment, the protective layer is made of silicon nitride; in other embodiments, the protective layer may also be made of silicon oxide.

[0053] In this embodiment, the method for forming the initial outer wall 205 includes: forming an outer wall material layer (not shown) on the sidewall and top surface of the pseudo-gate structure 204 and the top surface of the isolation layer 203; and etching the outer wall material layer back until the top surfaces of the pseudo-gate structure 204 and the isolation layer 203 are exposed, thereby forming the initial outer wall 205.

[0054] In this embodiment, the outer wall material layer is formed using atomic layer deposition (ALD).

[0055] Please refer to Figure 7 Using the pseudo-gate structure 204 and the initial outer wall 205 as a mask, a number of initial channel layers 201 and a number of initial sacrificial layers 202 are etched to form source / drain openings 206, as well as a number of channel layers 213 and a number of sacrificial layers 214.

[0056] In this embodiment, the source / drain opening 206 serves to provide space for the subsequently formed source / drain doped layer.

[0057] Please refer to Figure 8 and Figure 9 , Figure 8 It is a 3D diagram of a semiconductor structure. Figure 9 yes Figure 8 A schematic diagram of the cross-section along line AA shows that after the source / drain opening 206 is formed, the initial outer wall 205 is thinned to form an outer wall 207. The dimension of the outer wall 207 parallel to the first direction X is smaller than the dimension of the initial outer wall 205 parallel to the first direction X.

[0058] In this embodiment, by thinning the initial outer wall 205, the formed outer wall 207 can expose the other two surfaces of the sacrificial layer 214. This makes it easier for the etching process to contact the three surfaces of the sacrificial layer 214 during subsequent etching of the sacrificial layer 214, reducing the difficulty of the etching process, reducing the residue of etching by-products, and improving the morphology of the subsequently formed isolation groove.

[0059] In this embodiment, the dimension of the outer wall 207 parallel to the first direction X is smaller than the dimension of the initial outer wall 205 parallel to the first direction X by a range of 1 nanometer to 5 nanometers.

[0060] When the dimension of the outer wall 207 parallel to the first direction X is less than 1 nanometer smaller than the dimension of the initial outer wall 205 parallel to the first direction X, the area of ​​the other two sides of the sacrificial layer 214 exposed by the outer wall 207 is small, resulting in defects in the morphology of the subsequently formed isolation groove. When the dimension of the outer wall 207 parallel to the first direction X is greater than 5 nanometers smaller than the dimension of the initial outer wall 205 parallel to the first direction X, the thickness of the outer wall 207 is small, which affects the isolation effect of the outer wall 207 and easily leads to leakage problems in adjacent gate structures.

[0061] In this embodiment, the process of thinning the initial outer wall 205 is an isotropic etching process.

[0062] Please refer to Figures 10 to 12 , Figure 10 It is a 3D diagram of a semiconductor structure. Figure 11 yes Figure 10 Schematic diagram of the cross section along line BB. Figure 12 yes Figure 11 A top view of part A shows the portion of the sacrificial layer 214 exposed by the source / drain opening 206 being etched back, forming an isolation groove 208 between adjacent channel layers 213.

[0063] Since the outer wall 207 formed can expose the other two sides of the sacrificial layer 214, when the portion of the sacrificial layer 214 exposed by the source / drain opening 206 is etched back, the sacrificial layer 214 in the corner region will come into contact with more etching solution, thereby making the sacrificial layer 214 in the corner region etched faster.

[0064] Therefore, the final isolation groove 208 includes a first corner groove 208a, a middle groove 208b, and a second corner groove 208c arranged along the second direction Y; the dimensions of the first corner groove 208a and the second corner groove 208c along the first direction X are larger than the dimensions of the middle groove 208b along the first direction X.

[0065] In this embodiment, the isolation groove 208 serves to provide space for the subsequently formed inner sidewalls. These inner sidewalls ensure electrical isolation between the subsequently formed gate structure and the source / drain doped layers.

[0066] Please refer to Figure 13 and Figure 14 , Figure 13 and Figure 11 The view orientation is consistent. Figure 14 yes Figure 13 The top view of part B shows an inner wall 209 formed within the isolation groove 208.

[0067] In this embodiment, the method for forming the inner sidewall 209 includes: forming a first initial inner sidewall (not shown) within the isolation groove 208, the sidewall and bottom surface of the source / drain opening 206, the sidewall of the outer sidewall 207, and the top surface of the pseudo-gate structure 204; etching back the first initial inner sidewall until the bottom surface of the source / drain opening 206 and the top surface of the pseudo-gate structure 204 are exposed, forming a second initial inner sidewall (not shown); etching back the second initial inner sidewall until the sidewall of the outer sidewall 207 and the sidewall of the channel layer 213 are exposed, forming the inner sidewall 209.

[0068] The process for forming the first initial inner wall includes physical vapor deposition, chemical vapor deposition, or atomic layer deposition. In this embodiment, atomic layer deposition is used to form the first initial inner wall.

[0069] Since the inner wall 209 is used to fill the isolation groove 208, the morphology of the final inner wall 209 is consistent with the morphology of the isolation groove 208.

[0070] The inner wall 209 is located in the first corner layer 209a in the first corner groove 208a, the middle layer 209b in the middle groove 208b, and the second corner layer 209c in the second corner groove 208c.

[0071] Since the first corner layer 209a and the second corner layer 209c located in the first corner groove 208a and the second corner groove 208c in the inner wall 209 are relatively large, the isolation effect of the inner wall 209 can be effectively improved, and the occurrence of leakage problems between the subsequent gate structure and the source / drain doped layer can be reduced.

[0072] In this embodiment, the inner wall 209 is made of silicon nitride.

[0073] Please refer to Figure 15 After the inner sidewall 209 is formed, a source / drain doped layer 210 is formed in the source / drain opening 206. The source / drain doped layer 210 contains source / drain ions, and the surface of the source / drain doped layer 210, the surface of the inner sidewall 209, and the end face of the channel layer 213 are perpendicular and coplanar.

[0074] In this embodiment, since the initial outer wall 205 is thinned, the formed outer wall 207 can also expose the other two surfaces of the channel layer 213, thereby ensuring that the contact area between the source / drain doped layer 210 and the channel layer 213 is increased, which is beneficial to improving the operating current of the device.

[0075] In this embodiment, the formation process of the source / drain doped layer 210 includes an epitaxial growth process; the process of doping the source / drain ions in the source / drain doped layer 210 includes an in-situ doping process.

[0076] When the semiconductor structure is a P-type device, the material of the source / drain doped layer 210 includes silicon, germanium, or silicon-germanium; the source / drain ions are P-type ions, including boron ions and BF ions. 2- The source / drain doped layer 210 is made of silicon, gallium arsenide, or indium gallium arsenide when the semiconductor structure is an N-type device; the source / drain ions are N-type ions, including phosphorus ions or arsenic ions.

[0077] In this embodiment, the semiconductor structure is an N-type device, the source / drain doped layer 210 is made of silicon, and the source / drain ions are phosphorus ions.

[0078] Please refer to Figure 16 After the source / drain doped layer 210 is formed, a dielectric layer 211 is formed on the isolation layer 203. The dielectric layer 211 covers the pseudo gate structure 204, a plurality of channel layers 213 and a plurality of sacrificial layers 214, and the dielectric layer 211 exposes the top surface of the pseudo gate structure 204.

[0079] In this embodiment, the method for forming the dielectric layer 211 includes: forming an initial dielectric layer (not shown) on the source / drain doped layer 210 and the dummy gate structure 204, the initial dielectric layer covering the top surface and sidewall surface of the dummy gate structure 204; planarizing the initial dielectric layer until the protective layer surface on top of the dummy gate structure 204 is exposed, thereby forming the dielectric layer 211.

[0080] In this embodiment, the dielectric layer 211 is made of silicon oxide.

[0081] Please refer to Figure 17 After forming the dielectric layer 211, the dummy gate structure 204 is removed, and a gate opening (not shown) is formed in the dielectric layer 211; the gate opening is removed to expose the sacrificial layer 214, and a gate trench is formed between adjacent channel layers 213; a gate structure 212 is formed in the gate opening and the gate trench, and the gate structure 212 surrounds the channel layer 213.

[0082] In this embodiment, the gate structure 212 includes a gate layer.

[0083] The gate layer is made of metal, including one or more combinations of copper, tungsten, nickel, chromium, titanium, tantalum, and aluminum. In this embodiment, the gate layer 218 is made of tungsten.

[0084] Accordingly, an embodiment of the present invention also provides a semiconductor structure, please refer to [link / reference needed]. Figure 17The system includes: a substrate 200; a plurality of channel layers 213 on the substrate 200, wherein the plurality of channel layers 213 are stacked perpendicularly along the normal direction of the surface of the substrate 200 and the channel layers 213 extend along a first direction X, the first direction X being parallel to the surface of the substrate 200; an isolation layer 203 on the substrate 200, wherein the top surface of the isolation layer 203 is not higher than the top surface of the bottom channel layer 213; an isolation recess 208 between the ends of adjacent channel layers 213; an inner wall 209 within the isolation recess 208, wherein the inner wall 209 perpendicularly isolates the channel layers 213 in the normal direction of the surface of the substrate 200, such that adjacent channel layers 213 are suspended; and a gate structure 21 on the isolation layer 203. 2. The gate structure 212 surrounds a plurality of the channel layers 213 along a second direction Y, the second direction Y being perpendicular to the first direction X and parallel to the surface of the substrate 200; an outer wall 207 located on the sidewall surface of the gate structure 212, the sidewall of the outer wall 207 being recessed relative to the end face of the channel layer 213 in the first direction X; source and drain doped layers 210 located on both sides of the gate structure 212, the surface of the source and drain doped layers 210, the surface of the inner sidewall 209, and the end face of the channel layer 213 being perpendicular and coplanar; a dielectric layer 211 located on the isolation layer 203, the dielectric layer 211 covering the gate structure 212 and the plurality of the channel layers 213, and the dielectric layer 211 exposing the top surface of the gate structure 212.

[0085] In this embodiment, an outer wall 207 is included, located on the sidewall surface of the gate structure 212. In the first direction X, the sidewall of the outer wall 207 is recessed relative to the end face of the channel layer 213. By thinning the initial outer wall, the formed outer wall 207 can expose the other two surfaces of the sacrificial layer 214. This makes it easier for etching to contact the three surfaces of the sacrificial layer 214 during the formation of the isolation groove 208, reducing the difficulty of the etching process, reducing the residue of etching byproducts, and improving the morphology of the isolation groove 208.

[0086] In addition, since the sidewall of the outer wall 207 is recessed relative to the end face of the channel layer 213, the outer wall 207 can expose the other two surfaces of the channel layer 213, thereby ensuring that the contact area between the source / drain doped layer 210 and the channel layer 213 is increased, which is beneficial to improving the operating current of the device.

[0087] In this embodiment, the isolation groove 208 includes a first corner groove 208a, a middle groove 208b, and a second corner groove 208c arranged along the second direction Y; the dimensions of the first corner groove 208a and the second corner groove 208c along the first direction X are greater than the dimensions of the middle groove 208b along the first direction X.

[0088] In this embodiment, the inner sidewall 209 comprises a first corner layer 209a within the first corner groove 208a, an intermediate layer 209b within the intermediate groove 208b, and a second corner layer 209c within the second corner groove 208c. Because the first corner layer 209a and the second corner layer 209c within the first corner groove 208a and the second corner groove 208c of the inner sidewall 209 are relatively large, the isolation effect of the inner sidewall 209 can be effectively improved, reducing the occurrence of leakage current between the gate structure 212 and the source / drain doped layer 210.

[0089] In this embodiment, the sidewall of the outer wall 207 is recessed relative to the end face of the channel layer 213 by a range of 1 nanometer to 5 nanometers.

[0090] When the recessed area of ​​the sidewall of the outer wall 207 relative to the end face of the channel layer 213 is less than 1 nanometer, the area of ​​the other two sides of the sacrificial layer 213 exposed by the outer wall 207 is small, resulting in defects in the morphology of the subsequently formed isolation groove. When the recessed area of ​​the sidewall of the outer wall 207 relative to the end face of the channel layer 213 is greater than 5 nanometers, the thickness of the outer wall 207 is small, which affects the isolation effect of the outer wall 207 and easily leads to leakage problems in adjacent gate structures.

[0091] In this embodiment, the material of the inner wall 209 includes silicon nitride.

[0092] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A plurality of initial channel layers and a plurality of initial sacrificial layers are formed on the substrate. The plurality of initial channel layers and the plurality of initial sacrificial layers are stacked perpendicularly at intervals along the normal direction of the substrate surface, and the initial channel layers and the initial sacrificial layers extend along a first direction, which is parallel to the substrate surface. An isolation layer is formed on the substrate, wherein the top surface of the isolation layer is not higher than the top surface of the initial trench layer located at the bottom layer; A pseudo-gate structure and an initial outer wall located on the sidewall surface of the pseudo-gate structure are formed on the substrate. The pseudo-gate structure spans a plurality of initial channel layers and a plurality of initial sacrificial layers along a second direction, which is perpendicular to the first direction and parallel to the substrate surface. Using the pseudo-gate structure and the initial outer wall as a mask, a number of initial channel layers and a number of initial sacrificial layers are etched to form source / drain openings, as well as a number of channel layers and a number of sacrificial layers; After the source-drain opening is formed, the initial outer wall is thinned to form an outer wall, the dimension of which parallel to the first direction is smaller than the dimension of which parallel to the first direction of the initial outer wall; The sacrificial layer exposed by the source / drain opening is etched back to form an isolation groove between adjacent channel layers; An inner wall is formed within the isolation groove; A source / drain doped layer is formed inside the source / drain opening, and the surface of the source / drain doped layer, the surface of the inner sidewall, and the end face of the channel layer are perpendicular and coplanar. A dielectric layer is formed on the isolation layer, the dielectric layer covering the pseudo-gate structure, the plurality of the channel layers and the plurality of the sacrificial layers, and the dielectric layer exposing the top surface of the pseudo-gate structure.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The isolation groove includes a first corner groove, a middle groove, and a second corner groove arranged along the second direction; the dimensions of the first corner groove and the second corner groove along the first direction are greater than the dimensions of the middle groove along the first direction.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The inner wall includes a first corner layer located in the first corner groove, an intermediate layer located in the intermediate groove, and a second corner layer located in the second corner groove.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The dimension of the outer wall parallel to the first direction is smaller than the dimension of the initial outer wall parallel to the first direction by a range of 1 nanometer to 5 nanometers.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for thinning the initial outer wall includes an isotropic etching process.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the inner sidewall includes: forming a first initial inner sidewall within the isolation groove, the sidewall and bottom surface of the source / drain opening, the sidewall of the outer sidewall, and the top surface of the dummy gate structure; etching back the first initial inner sidewall until the bottom surface of the source / drain opening and the top surface of the dummy gate structure are exposed, forming a second initial inner sidewall; and etching back the second initial inner sidewall until the outer sidewall and the sidewall of the channel layer are exposed, forming the inner sidewall.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The process for forming the first initial inner wall includes physical vapor deposition, chemical vapor deposition, or atomic layer deposition.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the inner wall includes silicon nitride.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, After forming the dielectric layer, the method further includes: removing the dummy gate structure and forming a gate opening within the dielectric layer; removing the gate opening to expose the sacrificial layer and forming a gate trench between adjacent channel layers; and forming a gate structure within the gate opening and the gate trench, the gate structure surrounding the channel layer.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the sacrificial layer is different from the material of the channel layer.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The material of the sacrificial layer includes silicon and germanium; the material of the channel layer includes silicon.

12. A semiconductor structure formed using the method of any one of claims 1 to 11, characterized in that, include: Substrate; A plurality of channel layers are located on the substrate, the plurality of channel layers are stacked perpendicularly along the normal direction of the substrate surface, and the channel layers extend along a first direction, the first direction being parallel to the substrate surface; An isolation layer located on the substrate, wherein the top surface of the isolation layer is not higher than the top surface of the trench layer located at the bottom layer; An isolation groove located between the ends of adjacent channel layers; An inner wall located within the isolation groove perpendicularly isolates the channel layer in the direction normal to the substrate surface, thereby suspending adjacent channel layers. A gate structure located on the isolation layer, the gate structure surrounding a plurality of the channel layers along a second direction, the second direction being perpendicular to the first direction and parallel to the substrate surface; The outer wall located on the sidewall surface of the gate structure is recessed relative to the end face of the channel layer in the first direction. The source and drain doped layers located on both sides of the gate structure are perpendicularly coplanar, with the surface of the source and drain doped layers, the surface of the inner sidewalls, and the end face of the channel layer. A dielectric layer is located on the isolation layer, the dielectric layer covers a plurality of the channel layers and the gate structure, and the dielectric layer exposes the top surface of the gate structure.

13. The semiconductor structure as described in claim 12, characterized in that, The isolation groove includes a first corner groove, a middle groove, and a second corner groove arranged along the second direction; the dimensions of the first corner groove and the second corner groove along the first direction are greater than the dimensions of the middle groove along the first direction.

14. The semiconductor structure as described in claim 13, characterized in that, The inner wall includes a first corner layer located in the first corner groove, an intermediate layer located in the intermediate groove, and a second corner layer located in the second corner groove.

15. The semiconductor structure as described in claim 12, characterized in that, The indentation range of the sidewall of the outer wall relative to the end face of the channel layer is 1 nanometer to 5 nanometers.

16. The semiconductor structure as described in claim 12, characterized in that, The material of the inner wall includes silicon nitride.

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