Super-beta triode and method of making same

Abstract

The application provides a super-beta transistor and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a substrate, forming an isolated buried layer of a first conductive type and a doped layer of the first conductive type based on the substrate, forming a base region of a second conductive type in the doped layer, forming a doped island of the second conductive type on the side of the base region, the doping concentration of the doped island being greater than that of the base region, forming a collector region of the first conductive type in the substrate, the collector region being arranged apart from the base region, and forming an emitter region of the first conductive type in the base region. The super-beta transistor of the application can effectively reduce the longitudinal electric field of the base region, reduce the transverse leakage of the device, and achieve better balance of preventing the base region from being penetrated and improving the current amplification factor.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device design and manufacturing, and in particular relates to a super-β transistor and its fabrication method. Background Technology

[0002] A transistor has two N-type regions surrounding a P-type region. One of the N-type regions is the collector, the P-type region is the base, and the second N-type region is the emitter. Depending on the voltage bias, the transistor will have different operating modes. When both the emitter-base junction and the collector-base junction are reverse biased, the transistor operates in cutoff mode. When both the emitter-base junction and the collector-base junction are forward biased, the transistor operates in active mode, and when both are forward biased, the transistor operates in saturation mode. Active mode is used when the transistor is used as an amplifier, and cutoff and saturation modes are used when the transistor is used as a switch. One parameter of a transistor is the common-emitter current gain, often referred to as β or HFE. In active mode, the common-emitter current gain is the ratio of the collector current to the base current.

[0003] To reduce base recombination and ensure sufficient base transport coefficient, existing transistor structures typically have very shallow base regions with low doping concentrations. Therefore, existing transistor structures have a significant risk of base punch-through. Furthermore, the uniform, low-concentration base region results in a large lateral NPN leakage current, leading to low emitter junction injection efficiency, high leakage current, and low current gain. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a super β transistor and its fabrication method, so as to solve the problem of the large base region punch-through risk in the existing transistor structure.

[0005] To achieve the above and other related objectives, the present invention provides a method for fabricating a super-β transistor. The method includes: providing a substrate; forming an isolation buried layer of a first conductivity type and a doped layer of the same first conductivity type on the substrate, wherein the isolation buried layer is located at the bottom of the doped layer; forming a base region of a second conductivity type in the doped layer; forming doped islands of the second conductivity type around the base region, wherein the doping concentration of the doped islands is greater than the doping concentration of the base region; forming a collector region of the first conductivity type in the substrate, wherein the collector region is spaced apart from the base region; and forming an emitter region of the first conductivity type in the base region.

[0006] Optionally, the doping concentration of the base region ranges from 5e17cm. -3~8e17cm -3 The doping concentration of the doped islands is greater than or equal to 5e18cm. -3 .

[0007] Optionally, the doping concentration of the collector region is greater than the doping concentration of the doped layer, and the doping concentration of the isolation buried layer is greater than the doping concentration of the doped layer.

[0008] Optionally, the implantation junction depth of the base region is less than or equal to the implantation junction depth of the doped island.

[0009] Optionally, the method further includes the steps of forming a contact region of a second conductivity type in the base region and forming a contact region of a first conductivity type in the collector region, wherein the doping concentration of the contact region of the second conductivity type is greater than the doping concentration of the doped island, and the doping concentration of the contact region of the first conductivity type is greater than the doping concentration of the collector region.

[0010] Optionally, the bottom of the current collector region is connected to at least a portion of the buried isolation layer, and the bottom of the doped island is connected to at least a portion of the buried isolation layer.

[0011] Optionally, forming an isolation buried layer of a first conductivity type and a doped layer of a first conductivity type in the substrate, wherein the isolation buried layer is located at the bottom of the doped layer, includes: forming the isolation buried layer inside the substrate by ion implantation; forming the doped layer on the surface of the substrate by ion implantation; or: forming the isolation buried layer on the surface of the substrate by ion implantation; forming the doped layer on the substrate by epitaxial process.

[0012] The present invention also provides a super-β transistor, comprising: a substrate, wherein a first conductivity type isolation buried layer is formed therein; a first conductivity type doped layer is formed on the surface of the substrate or on the substrate, the isolation buried layer being located at the bottom of the doped layer; a second conductivity type base region is formed in the doped layer; a second conductivity type doped island is formed around the base region, the doping concentration of the doped island being greater than the doping concentration of the base region; a first conductivity type collector region is formed in the substrate, the collector region being spaced apart from the base region; and a first conductivity type emitter region is formed in the base region.

[0013] Optionally, the doping concentration of the base region ranges from 5e17cm. -3 ~8e17cm -3 The doping concentration of the doped islands is greater than or equal to 5e18cm. -3 .

[0014] Optionally, the doping concentration of the buried isolation layer ranges from 1e17cm. -3 ~3e17cm -3The doping concentration range of the doped layer is 1e16cm. -3 ~4e16cm -3 The doping concentration range of the collector region is 1e17cm. -3 ~5e17cm -3 The doping concentration range of the emitter region is 1e17cm. -3 ~5e17cm -3 .

[0015] Optionally, a second conductivity type contact region is further formed in the base region, the doping concentration of the second conductivity type contact region being greater than the doping concentration of the doped island, and a first conductivity type contact region is further formed in the collector region, the doping concentration of the first conductivity type contact region being greater than the doping concentration of the collector region.

[0016] Optionally, the bottom of the current collector region is connected to at least a portion of the buried isolation layer, and the bottom of the doped island is connected to at least a portion of the buried isolation layer.

[0017] Optionally, the doping concentration of the collector region is greater than the doping concentration of the doped layer, and the doping concentration of the isolation buried layer is greater than the doping concentration of the doped layer.

[0018] Optionally, the implantation junction depth of the base region is less than or equal to the implantation junction depth of the doped island.

[0019] Optionally, the base region is formed on the upper surface of the doped layer, and the enclosing structure composed of the doped island and the isolation buried layer surrounds the base region.

[0020] As described above, the super-β transistor and its fabrication method of the present invention have the following beneficial effects:

[0021] This invention forms doped islands around the base region by high-concentration ion implantation. These doped islands have a concentration gradient with the base region. The doped islands not only assist in the bottom lateral depletion and the rapid pinch-off of the bottom of the base region to prevent base region punch-through, but also, due to the presence of the doped islands, the P-type concentration in the non-working base region is high, which greatly reduces the leakage current of the lateral NPN, thereby enabling the device to generate a high current gain.

[0022] The super-β transistor of the present invention can effectively reduce the longitudinal electric field in the base region and reduce the lateral leakage current of the device, thereby achieving a better balance between preventing base region punch-through and improving the current amplification factor. Attached Figure Description

[0023] Figures 1 to 7 The diagram shows the structural schematics of each step in the fabrication method of the super-β transistor according to an embodiment of the present invention. Figure 7The diagram shown is a schematic diagram of the structure of the superβ transistor according to an embodiment of the present invention.

[0024] Component designation explanation

[0025] 101 substrate

[0026] 102 Isolation Buried Layer

[0027] 103 doped layer

[0028] 104 base areas

[0029] 105 Doped Island

[0030] 106 power collection area

[0031] 107 Second type of contact area

[0032] Launch Area 108

[0033] 109 Contact area of ​​the first conductivity type Detailed Implementation

[0034] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0035] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0036] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0037] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0038] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0039] To reduce base recombination and ensure sufficient base transport coefficient, existing bipolar junction transistor (BJT) structures typically have very shallow base regions with low doping concentrations. Therefore, these structures have a significant risk of base punch-through. Furthermore, the uniformly low-concentration base region results in a large lateral NPN leakage current, leading to low emitter junction implantation efficiency, high leakage current, and low current gain. This invention addresses this by forming doped islands 105 around the base region through high-concentration ion implantation. These islands 105 have a concentration gradient with the base region. They not only assist in bottom lateral depletion and rapid base region pinch-off to prevent punch-through, but also, due to their presence, result in a higher P-type concentration in the non-working base region, significantly reducing lateral NPN leakage current and enabling the device to generate higher current gain.

[0040] To solve the above problems, such as Figures 1 to 7 As shown, this embodiment provides a method for fabricating a super-β transistor, the method comprising the following steps:

[0041] like Figure 1 As shown, step 1) is performed first, a substrate 101 is provided, and an isolation buried layer 102 of a first conductivity type is formed in the substrate 101.

[0042] As an example, the substrate can be a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, SOI (silicon-on-insulator), or GOI (germanium-on-insulator). In other embodiments, the semiconductor substrate can also be a substrate comprising other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, and can also be a stacked structure, such as Si / SiGe, or other epitaxial structures, such as SGOI (germanium-silicon-on-insulator). In this embodiment, the substrate is a Si substrate.

[0043] As an example, a first conductivity type isolation buried layer 102 can be formed in the substrate using ion implantation and annealing processes. In this embodiment, the doping concentration of the isolation buried layer 102 ranges from 1e17cm⁻¹. -3 ~3e17cm -3 .

[0044] like Figure 2As shown, then step 2) is performed to form a doped layer 103 of a first conductivity type on the substrate 101, and the isolation buried layer 102 is located at the bottom of the doped layer.

[0045] As an example, a first conductivity type doped layer 103 can be formed on the substrate 101 using a vapor phase epitaxy process. Preferably, the material of the doped layer 103 is the same as that of the substrate 101. In this embodiment, the material of the doped layer 103 is Si.

[0046] The doping concentration range of the doped layer 103 can be 1e16cm. -3 ~4e16cm -3 In one specific implementation, the doping concentration of the doped layer 103 is 2e16cm. -3 By adjusting the doping concentration of the doped layer 103, the on-resistance and breakdown voltage of the device can be effectively adjusted to meet different device performance requirements.

[0047] In another embodiment, the isolation buried layer 102 can be first formed inside the substrate by ion implantation, and then the doped layer 103 can be formed on the surface of the substrate by ion implantation. By controlling the depth of the isolation buried layer 102, the isolation buried layer 102 can be located at the bottom of the doped layer 103.

[0048] like Figure 3 As shown, step 3) is then performed to form a base region 104 of a second conductivity type in the doped layer 103.

[0049] For example, a base region 104 of a second conductivity type can be formed in the doped layer 103 by photolithography, ion implantation, and annealing processes. The doping concentration of the base region 104 can be in the range of 5e17cm. -3 ~8e17cm -3 In one specific implementation, the doping concentration of the base region 104 is 6e17cm. -3 In this embodiment, the base region 104 doping concentration is low, which can effectively reduce base region 104 recombination and ensure sufficient base region 104 transport coefficient.

[0050] like Figure 4 As shown, step 4) is then performed, in which a doped island 105 of a second conductivity type is formed around the base region 104, the doping concentration of the doped island 105 being greater than the doping concentration of the base region 104. The bottom of the doped island 105 is connected to at least a portion of the buried isolation layer 102.

[0051] In this embodiment, the implantation junction depth of the base region 104 is less than or equal to the implantation junction depth of the doped island 105. The base region 104 is formed on the upper surface of the doped layer 103, and the enclosing structure composed of the doped island 105 and the isolation buried layer 102 surrounds the base region 104.

[0052] For example, doped islands 105 of a second conductivity type can be formed around the base region 104 using photolithography, ion implantation, and annealing processes. The doping concentration of the doped islands 105 is greater than that of the base region 104. In this embodiment, the doping concentration of the doped islands 105 is greater than or equal to 5e18cm. -3 For example, it can be 8e18cm -3 ~9e18cm -3 The present invention forms doped islands 105 around the base region 104 by high-concentration ion implantation. The doped islands 105 have a concentration gradient with the base region 104. The doped islands 105 not only assist in bottom lateral depletion and rapid pinch-off of the bottom of the base region 104 to prevent the base region 104 from punching through, but also, due to the presence of the doped islands 105, the P-type concentration of the non-working base region 104 is high, which greatly reduces the leakage current of the lateral NPN, thereby enabling the device to generate a high current gain.

[0053] like Figure 5 As shown, step 5) is then performed, in which a collector region 106 of a first conductivity type is formed in the substrate 101, the collector region 106 being spaced apart from the base region 104.

[0054] For example, a collector region 106 of a first conductivity type can be formed in the substrate 101 using photolithography, ion implantation, and annealing processes. The collector region 106 is spaced apart from the base region 104, and the bottom of the collector region 106 is at least partially connected to the buried isolation layer 102. As an example, the doping concentration of the collector region 106 is in the range of 1e17cm. -3 ~5e17cm -3 In one specific implementation, the doping concentration of the collector region 106 is 3e17cm. -3 .

[0055] like Figure 6 As shown, step 6) is then performed, in which a second conductivity type contact region 107 is formed in the base region 104. The doping concentration of the second conductivity type contact region 107 is greater than the doping concentration of the doped island 105, so as to reduce the contact resistance of the base region 104.

[0056] like Figure 7 As shown, step 6) is performed last to form an emitter region 108 of the first conductivity type in the base region 104.

[0057] For example, an emitter region 108 of a first conductivity type can be formed in the base region 104 by photolithography, ion implantation, and annealing processes, wherein the doping concentration of the emitter region 108 is in the range of 1e17cm. -3 ~5e17cm -3 In one specific implementation, the doping concentration of the emitter region 108 is 5e17cm. -3 This step also includes forming a contact region 109 of a first conductivity type in the collector region 106, wherein the doping concentration of the first conductivity type contact region 109 is greater than the doping concentration of the collector region 106. As an example, the emitter region 108 of the first conductivity type and the contact region 109 of the first conductivity type can be formed in the same doping step, i.e., the emitter region 108 and the contact region 109 of the first conductivity type can be formed simultaneously through a photolithography process, an ion implantation process, and an annealing process, thereby reducing process costs and improving process efficiency. In other embodiments, the collector region 106, the base region 107, and the emitter region 108 are all led out to the substrate surface, and the leading-out methods include, but are not limited to, implanted contact regions, doped region leading-out, and vias.

[0058] In this embodiment, the first conductivity type is N-type conductivity, and the second conductivity type is P-type conductivity. Of course, in other embodiments, the first conductivity type can also be P-type conductivity, and the second conductivity type can also be N-type conductivity.

[0059] like Figure 7 As shown, this embodiment also provides a super-β transistor, comprising: a substrate 101, wherein a first conductivity type isolation buried layer 102 is formed in the substrate 101; a first conductivity type doped layer 103 is formed on the surface of the substrate 101 or on the substrate 101, and the isolation buried layer 102 is located at the bottom of the doped layer 103; a second conductivity type base region 104 is formed in the doped layer 103; a second conductivity type doped island 105 is formed around the base region 104, wherein the doping concentration of the doped island 105 is greater than the doping concentration of the base region 104; a first conductivity type collector region 106 is formed in the substrate 101, wherein the collector region 106 is spaced apart from the base region 104; and a first conductivity type emitter region 108 is formed in the base region 104.

[0060] As an example, the substrate 101 can be a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, SOI (silicon-on-insulator), or GOI (germanium-on-insulator). In other embodiments, the semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, and can also be a stacked structure, such as Si / SiGe, or other epitaxial structures, such as SGOI (germanium-silicon-on-insulator). In this embodiment, the substrate is a Si substrate.

[0061] As an example, the doping concentration range of the doped layer 103 can be 1e16cm. -3 ~4e16cm -3 In one specific implementation, the doping concentration of the doped layer 103 is 2e16cm. -3 By adjusting the doping concentration of the doped layer 103, the on-resistance and breakdown voltage of the device can be effectively adjusted to meet different device performance requirements.

[0062] As an example, the doping concentration range of the base region 104 can be 5e17cm. -3 ~8e17cm -3 In one specific implementation, the doping concentration of the base region 104 is 6e17cm. -3 In this embodiment, the base region 104 has a low doping concentration, which effectively reduces base region 104 recombination and ensures a sufficient base region 104 transport coefficient. In this embodiment, the doping concentration of the doped island 105 is greater than or equal to 5e18cm. -3 For example, it can be 8e18cm -3 ~9e18cm -3 The present invention forms doped islands 105 around the base region 104 by high-concentration ion implantation. The doped islands 105 have a concentration gradient with the base region 104. The doped islands 105 not only assist in bottom lateral depletion and rapid pinch-off of the bottom of the base region 104 to prevent the base region 104 from punching through, but also, due to the presence of the doped islands 105, the P-type concentration of the non-working base region 104 is high, which greatly reduces the leakage current of the lateral NPN, thereby enabling the device to generate a high current gain.

[0063] In this embodiment, the implantation junction depth of the base region 104 is less than or equal to the implantation junction depth of the doped island 105. The base region 104 is formed on the upper surface of the doped layer 103, and the enclosing structure composed of the doped island 105 and the isolation buried layer 102 surrounds the base region 104.

[0064] As an example, the doping concentration range of the buried isolation layer 102 is 1e17cm. -3 ~3e17cm-3 The doping concentration range of the collector region 106 is 1e17cm. -3 ~5e17cm -3 In one specific implementation, the doping concentration of the collector region 106 is 3e17cm. -3 The doping concentration range of the emitter region 108 is 1e17cm. -3 ~5e17cm -3 In one specific implementation, the doping concentration of the emitter region 108 is 5e17cm. -3 .

[0065] In this embodiment, a second conductivity type contact region 107 is also formed in the base region 104, and the doping concentration of the second conductivity type contact region 107 is greater than the doping concentration of the doped island 105. A first conductivity type contact region 109 is also formed in the collector region 106, and the doping concentration of the first conductivity type contact region 109 is greater than the doping concentration of the collector region 106.

[0066] In this embodiment, the bottom of the current collector region 106 is connected to at least a portion of the isolation buried layer 102, and the bottom of the doped island 105 is connected to at least a portion of the isolation buried layer 102.

[0067] In this embodiment, the first conductivity type is N-type conductivity, and the second conductivity type is P-type conductivity. Of course, in other embodiments, the first conductivity type can also be P-type conductivity, and the second conductivity type can also be N-type conductivity.

[0068] As described above, the super-β transistor and its fabrication method of the present invention have the following beneficial effects:

[0069] This invention forms doped islands 105 around the base region 104 by high-concentration ion implantation. The doped islands 105 have a concentration gradient with the base region 104. The doped islands 105 not only assist in bottom lateral depletion and help the bottom of the base region 104 to quickly pinch off and prevent the base region 104 from punching through, but also, due to the presence of the doped islands 105, the P-type concentration of the non-working base region 104 is high, which greatly reduces the leakage current of the lateral NPN, thereby enabling the device to generate a high current gain.

[0070] The super-β transistor of the present invention can effectively reduce the longitudinal electric field of the base region 104 and reduce the lateral leakage current of the device, thus achieving a better balance between preventing the base region 104 from punching through and improving the current amplification factor.

[0071] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0072] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a super-β transistor, characterized in that, The manufacturing method includes: A substrate is provided, and an isolation buried layer of a first conductivity type and a doped layer of a first conductivity type are formed on the substrate, wherein the isolation buried layer is located at the bottom of the doped layer; A base region of a second conductivity type is formed in the doped layer; A doped island of a second conductivity type is formed on the periphery of the base region. The doping concentration of the doped island is greater than that of the base region. The bottom of the doped island is connected to at least a portion of the buried isolation layer. A collector region of a first conductivity type is formed in the substrate, and the collector region is spaced apart from the base region; An emitter region of a first conductivity type is formed in the base region.

2. The method for fabricating a super-β transistor according to claim 1, characterized in that: The doping concentration range of the base region is 5e17cm. -3 ~8e17cm -3 The doping concentration of the doped islands is greater than or equal to 5e18cm. -3 .

3. The method for fabricating a super-β transistor according to claim 1, characterized in that: The doping concentration of the current collector region is greater than that of the doped layer, and the doping concentration of the isolation buried layer is greater than that of the doped layer.

4. The method for fabricating a super-β transistor according to claim 1, characterized in that: The implantation junction depth of the base region is less than or equal to the implantation junction depth of the doped island.

5. The method for fabricating a super-β transistor according to claim 1, characterized in that: It also includes the steps of forming a contact region of a second conductivity type in the base region and forming a contact region of a first conductivity type in the collector region, wherein the doping concentration of the contact region of the second conductivity type is greater than the doping concentration of the doped island, and the doping concentration of the contact region of the first conductivity type is greater than the doping concentration of the collector region.

6. The method for fabricating a super-β transistor according to claim 1, characterized in that: The bottom of the current collection area is connected to at least a portion of the isolation layer.

7. The method for fabricating a super-β transistor according to claim 1, characterized in that: An isolation buried layer of a first conductivity type and a doped layer of the first conductivity type are formed on the substrate, wherein the isolation buried layer is located at the bottom of the doped layer and includes: An isolation buried layer is formed inside the substrate by ion implantation. A doped layer is formed on the surface of the substrate by ion implantation. or: An isolation buried layer is formed on the surface of the substrate by ion implantation. A doped layer is formed on the substrate using an epitaxial process.

8. A super-β transistor, characterized in that, include: Substrate, wherein an isolation buried layer of a first conductivity type is formed therein; A doped layer of a first conductivity type is formed on the surface of the substrate or on the substrate, and the isolation buried layer is located at the bottom of the doped layer; A base region of the second conductivity type is formed in the doped layer; A second type of conductive doped island is formed on the periphery of the base region. The doping concentration of the doped island is greater than that of the base region. The bottom of the doped island is connected to at least a portion of the buried isolation layer. A collector region of a first conductivity type is formed in the substrate, and the collector region is disposed at a distance from the base region; An emitter region of the first conductivity type is formed in the base region.

9. The super-β transistor according to claim 8, characterized in that: The doping concentration range of the base region is 5e17cm. -3 ~8e17cm -3 The doping concentration of the doped islands is greater than or equal to 5e18cm. -3 .

10. The super-β transistor according to claim 8, characterized in that: The doping concentration range of the buried isolation layer is 1e17cm. -3 ~3e17cm -3 The doping concentration range of the doped layer is 1e16cm. -3 ~4e16cm -3 The doping concentration range of the collector region is 1e17cm. -3 ~5e17cm -3 The doping concentration range of the emitter region is 1e17cm. -3 ~5e17cm -3 .

11. The super-β transistor according to claim 8, characterized in that: The base region also contains a contact region of a second conductivity type, the doping concentration of which is greater than that of the doped island. The collector region also contains a contact region of a first conductivity type, the doping concentration of which is greater than that of the collector region.

12. The super-β transistor according to claim 8, characterized in that: The bottom of the current collection area is connected to at least a portion of the isolation layer.

13. The super-β transistor according to claim 8, characterized in that: The doping concentration of the current collector region is greater than that of the doped layer, and the doping concentration of the isolation buried layer is greater than that of the doped layer.

14. The super-β transistor according to claim 8, characterized in that: The implantation junction depth of the base region is less than or equal to the implantation junction depth of the doped island.

15. The super-β transistor according to claim 8, characterized in that: The base region is formed on the upper surface of the doped layer, and the enclosing structure composed of the doped island and the isolation buried layer surrounds the base region.

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