A novel TOPCON battery and its manufacturing method

Abstract

This invention relates to the field of photovoltaic device manufacturing, and in particular to a novel TOPCON cell and its fabrication method. The method involves sequentially depositing silicon oxide and polycrystalline silicon layers on the front and back sides of a grooved n-type substrate silicon to obtain a silicon wafer to be doped, followed by double-sided doping. The polycrystalline silicon layer and silicon oxide layer in the non-SE region of the front side of the doped silicon wafer are then removed to obtain a cell pre-mount. The pre-mount is cleaned to remove glass transition silicon. An aluminum oxide passivation layer is deposited on the front side of the pre-mount after glass transition silicon removal. A front-side silicon nitride layer is deposited on the surface of the aluminum oxide passivation layer, and a back-side silicon nitride layer is deposited on the surface of the polycrystalline silicon on the back side to obtain a photovoltaic silicon wafer. The photovoltaic silicon wafer is then surface-metallized to obtain the novel TOPCON cell. This invention increases the contact area between the front-side silicon oxide layer and the front-side polycrystalline silicon layer and the n-type substrate silicon, thereby improving the short-circuit current and fill factor of the cell.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic device manufacturing, and in particular to a novel TOPCON cell and its manufacturing method. Background Technology

[0002] In the field of photovoltaic power generation, traditional PERC cells generate a large number of minority carrier recombination centers due to the direct contact between the metal electrodes and the silicon substrate, which negatively impacts efficiency. The emerging TOPCon cells, however, improve power generation efficiency by fabricating an ultrathin tunneling oxide layer and a highly doped polycrystalline silicon film in the metal electrode contact area, forming a passivated contact structure.

[0003] However, since most TOPCon cells on the market have fully passivated contacts on the back, the silver electrode on the front still directly contacts the boron diffusion electrode, resulting in high metal recombination and no passivated contact. This prevents the open-circuit voltage and fill factor of the solar cell from being further improved.

[0004] Therefore, how to improve the contact performance of the front electrode of the current TOPCON solar cell is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a novel TOPCON battery and its manufacturing method to solve the problem of poor contact performance of the front electrode in existing TOPCON solar cells.

[0006] To solve the above-mentioned technical problems, the present invention provides a novel method for manufacturing a TOPCON battery, comprising:

[0007] Grooves are formed in the SE region of n-type substrate silicon to obtain grooves;

[0008] A silicon oxide layer and a polycrystalline silicon layer are deposited sequentially on both sides of the grooved n-type substrate silicon to obtain the silicon wafer to be doped.

[0009] The front side of the silicon wafer to be doped is boron-doped, and the back side is phosphorus-doped.

[0010] Remove the polycrystalline silicon layer and silicon oxide layer from the non-SE region on the front side of the doped silicon wafer to obtain the battery front-end material;

[0011] Clean the battery pre-pack to remove the glassy silicon.

[0012] An aluminum oxide passivation layer is provided on the front side of the battery front element after removing the silicon glass;

[0013] A front silicon nitride layer is formed on the surface of the alumina passivation layer, and a back silicon nitride layer is formed on the surface of the back polycrystalline silicon layer to obtain a photovoltaic silicon wafer;

[0014] The photovoltaic silicon wafer is surface-metallized to obtain the novel TOPCON cell.

[0015] Optionally, in the method for fabricating the novel TOPCON battery, the step of removing the polycrystalline silicon layer and silicon oxide layer from the non-SE region of the front side of the doped silicon wafer to obtain the battery preform includes:

[0016] A mask layer is placed in the SE region of the doped silicon wafer;

[0017] The front side of the silicon wafer with the mask layer is acid-washed to remove the polycrystalline silicon layer and silicon oxide layer in the non-SE area on the front side, thus obtaining the battery front panel.

[0018] Optionally, in the method for manufacturing the novel TOPCON battery, before cleaning the battery pre-substrate and removing the glassy silicon, the method further includes:

[0019] Boron redoping was performed on the SE region on the front side of the n-type substrate silicon using laser redoping.

[0020] Optionally, in the method for manufacturing the novel TOPCON battery, the power range of the laser redoping is 25 watts to 35 watts, including the endpoint value.

[0021] Optionally, in the method for manufacturing the novel TOPCON battery, before forming a groove in the SE region of the n-type substrate silicon, the method further includes:

[0022] The n-type substrate silicon is placed in a potassium hydroxide solution for surface texturing; the concentration of the potassium hydroxide solution is in the range of 0.5% to 2%, including the endpoint value, and the temperature of the potassium hydroxide solution is in the range of 40 degrees Celsius to 60 degrees Celsius, including the endpoint value.

[0023] Optionally, in the method for manufacturing the novel TOPCON cell, after surface metallization of the photovoltaic silicon wafer, the method further includes:

[0024] The photovoltaic silicon wafer is subjected to photo-injection hydrogen passivation to obtain the novel TOPCON cell; the temperature range of the photo-injection hydrogen passivation is 300 degrees Celsius to 500 degrees Celsius, including the endpoint value.

[0025] A novel TOPCON battery includes an n-type substrate silicon. The front side of the n-type substrate silicon includes a groove disposed in the SE region. The groove includes, from the inside to the outside, a front silicon oxide layer and a front boron-doped polycrystalline silicon layer. The front side of the n-type substrate silicon includes an aluminum oxide passivation layer that is disposed on the entire surface and covers the front boron-doped polycrystalline silicon layer, a front silicon nitride layer disposed on the outer surface of the aluminum oxide passivation layer, and a front electrode that penetrates the front silicon nitride layer and the aluminum oxide passivation layer and contacts the front boron-doped polycrystalline silicon layer.

[0026] From the back side of the n-type substrate silicon outwards, it includes a back silicon oxide layer, a back phosphorus-doped polycrystalline silicon layer, a back silicon nitride layer, and a back electrode that penetrates the back silicon nitride layer and contacts the back phosphorus-doped polycrystalline silicon layer.

[0027] Optionally, in the novel TOPCON battery, the sheet resistance of the front boron-doped polycrystalline silicon layer ranges from 100 ohms to 120 ohms, including the endpoint values.

[0028] Optionally, in the novel TOPCON battery, the sheet resistance of the phosphorus-doped polycrystalline silicon layer on the back side ranges from 36 ohms to 48 ohms, including the endpoint values.

[0029] Optionally, in the novel TOPCON battery, the thickness of the front silicon nitride layer and / or the back silicon nitride layer ranges from 70 nanometers to 80 nanometers, including endpoint values.

[0030] The present invention provides a method for fabricating a novel TOPCON battery, which involves creating a groove in the SE region of an n-type substrate silicon to obtain a groove; sequentially depositing a silicon oxide layer and a polycrystalline silicon layer on both sides of the grooved n-type substrate silicon to obtain a silicon wafer to be doped; performing boron doping on the front side and phosphorus doping on the back side of the silicon wafer to be doped; removing the polycrystalline silicon layer and silicon oxide layer in the non-SE region of the front side of the doped silicon wafer to obtain a battery pre-mount; cleaning the battery pre-mount to remove glass transition silicon; depositing an aluminum oxide passivation layer on the front side of the battery pre-mount after removing glass transition silicon; depositing a front silicon nitride layer on the surface of the aluminum oxide passivation layer and a back silicon nitride layer on the surface of the back polycrystalline silicon layer to obtain a photovoltaic silicon wafer; and performing surface metallization on the photovoltaic silicon wafer to obtain the novel TOPCON battery.

[0031] This invention selectively passivates contacts only in the front metal region of the battery, meaning the silicon oxide layer and the polycrystalline silicon layer are only disposed in the front metal region. This reduces the absorption of free carriers on the front of the battery, decreases metal recombination between the metal and non-metal regions, and improves the open-circuit voltage and fill factor of the battery cell. Simultaneously, the grooves in the front metal region significantly increase the contact area between the front silicon oxide layer and the front polycrystalline silicon layer and the n-type substrate silicon, reducing the internal resistance of the battery cell and further improving the short-circuit current and fill factor. This invention also provides a novel TOPCON battery with the aforementioned beneficial effects. Attached Figure Description

[0032] To more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 A flowchart illustrating a specific embodiment of the manufacturing method of the novel TOPCON battery provided by the present invention;

[0034] Figure 2 A flowchart illustrating another specific embodiment of the manufacturing method of the novel TOPCON battery provided by the present invention;

[0035] Figure 3 This is a schematic diagram of a specific embodiment of the novel TOPCON battery provided by the present invention. Detailed Implementation

[0036] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] The core of this invention is to provide a novel method for manufacturing a TOPCON battery, and a flowchart of one specific embodiment is shown below. Figure 1 As shown, this is referred to as Specific Implementation Method One, which includes:

[0038] S101: Grooves are cut in the SE region of n-type substrate silicon to obtain grooves.

[0039] Prior to this step, the following may also be included:

[0040] The n-type substrate silicon is placed in a potassium hydroxide solution for surface texturing; the concentration of the potassium hydroxide solution is in the range of 0.5% to 2%, including the endpoint value, and the temperature of the potassium hydroxide solution is in the range of 40 degrees Celsius to 60 degrees Celsius, including the endpoint value.

[0041] The n-type substrate silicon will form a pyramidal appearance in the above environment; during the surface texturing process, the weight reduction is controlled at 0.25g-0.35g, and the reflectivity is 9.5%-10.5%.

[0042] Before surface texturing, the process may further include removing the damaged layer on the silicon wafer surface using an 8%-12% KOH solution at a temperature of 40-60°C.

[0043] After the surface texturing is completed, the back surface of the n-star substrate silicon can be further polished. Specifically, in a chain equipment, an 8%-12% KOH solution is used to etch and polish the back surface and edges of the textured silicon wafer; the weight is reduced by 0.2mg-0.3mg, the back surface reflectivity is 37%-40%, and the tower base size is 5μm-12μm.

[0044] The grooves can be obtained through physical etching or chemical etching. For example, the front side of a polished silicon wafer can be etched according to the pattern of the laser SE zone at a power of 60W-70W to form holes, which facilitates the deposition of silicon dioxide and polycrystalline silicon within the holes.

[0045] S102: A silicon oxide layer and a polycrystalline silicon layer are deposited sequentially on both sides of the grooved n-type substrate silicon to obtain the silicon wafer to be doped.

[0046] Of course, the front silicon oxide layer can be set at the same time as the back silicon oxide layer, and the polycrystalline silicon layer on the front can be set at the same time as the polycrystalline silicon layer on the back.

[0047] Specifically, the double-sided silicon oxide layer is uniformly deposited on both sides under the conditions of temperature 580℃-630℃, oxygen flow rate 18000sccm-19000sccm, oxidation pressure 700mbar-900mbar, and oxidation time 10min-20min, with a thickness range of 1.5nm-1.7nm.

[0048] Specifically, amorphous silicon with a uniform thickness of about 100 nm is deposited on both sides of the double-sided polycrystalline silicon layer at a temperature of 580℃-630℃, a SiH4 flow rate of 800sccm-1200sccm, a pressure of 280mbar-320mbar, and a time of 30min-50min, and then crystallized at a temperature of 800℃-850℃ to form polycrystalline silicon.

[0049] S103: The front side of the silicon wafer to be doped is boron doped and the back side is phosphorus doped.

[0050] The boron doping conditions include: front-side doping at a temperature of 850℃-1050℃, an oxygen flow rate of 480 sccm, a BCl3 flow rate of 100 sccm-300 sccm, a pressure of 250 mbar-300 mbar, and a time of 40 min-60 min, with a target sheet resistance of 100 Ω-120 Ω.

[0051] The phosphorus doping conditions include: back-side doping at a temperature of 800℃-870℃, an oxygen flow rate of 2,100,000 sccm, a POCl3 flow rate of 10,500,000 sccm, a pressure of 200 mbar-400 mbar, and a time of 20 min-35 min, with a target sheet resistance of 36 Ω-48 Ω.

[0052] S104: Remove the polycrystalline silicon layer and silicon oxide layer from the non-SE region on the front side of the doped silicon wafer to obtain the battery pre-face material.

[0053] In this step, HF solution can be used in a chain-type device to etch the front and edges. The silicon dioxide and polysilicon outside the groove are washed away together, leaving the silicon dioxide layer and polysilicon layer inside the hole.

[0054] As a specific implementation method, the method for selectively removing the epitaxial layer includes:

[0055] A1: A mask layer is placed in the SE region of the doped silicon wafer.

[0056] A2: The front side of the silicon wafer with the mask layer is acid-washed to remove the polycrystalline silicon layer and silicon oxide layer in the non-SE area on the front side, thus obtaining the battery pre-face material.

[0057] The mask layer is an acid-resistant mask.

[0058] S105: Clean the battery pre-pack to remove the glassy silicon.

[0059] The glass-tight silicon may include BSG, PSG and BPSG. Specifically, the front BSG can be removed with a 35%-45% HF solution and the back PSG can be removed with an 8%-12% HF solution.

[0060] S106: An aluminum oxide passivation layer is provided on the front side of the battery front element after removing the glass silicon.

[0061] S107: A front silicon nitride layer is formed on the surface of the alumina passivation layer, and a back silicon nitride layer is formed on the surface of the back polycrystalline silicon layer to obtain a photovoltaic silicon wafer.

[0062] S108: Surface metallization is performed on the photovoltaic silicon wafer to obtain the novel TOPCON cell.

[0063] The surface metallization refers to the provision of a front metal electrode and a back metal electrode on both sides of the battery, specifically, it may include:

[0064] Metal grid lines are printed within the laser SE area pattern and sintered at a temperature of 770℃-800℃.

[0065] In a preferred embodiment, after surface metallization, the method further includes:

[0066] The photovoltaic silicon wafer is subjected to photo-injection hydrogen passivation to obtain the novel TOPCON cell; the photo-injection hydrogen passivation temperature range is 300 degrees Celsius to 500 degrees Celsius, including endpoint values ​​such as any one of 300.0 degrees Celsius, 463.2 degrees Celsius, or 500.0 degrees Celsius. The light intensity of the injected light is 10 sun.

[0067] The present invention provides a method for fabricating a novel TOPCON battery, which involves creating a groove in the SE region of an n-type substrate silicon to obtain a groove; sequentially depositing a silicon oxide layer and a polycrystalline silicon layer on both sides of the grooved n-type substrate silicon to obtain a silicon wafer to be doped; performing boron doping on the front side and phosphorus doping on the back side of the silicon wafer to be doped; removing the polycrystalline silicon layer and silicon oxide layer in the non-SE region of the front side of the doped silicon wafer to obtain a battery pre-mount; cleaning the battery pre-mount to remove glass transition silicon; depositing an aluminum oxide passivation layer on the front side of the battery pre-mount after removing glass transition silicon; depositing a front silicon nitride layer on the surface of the aluminum oxide passivation layer and a back silicon nitride layer on the surface of the back polycrystalline silicon layer to obtain a photovoltaic silicon wafer; and performing surface metallization on the photovoltaic silicon wafer to obtain the novel TOPCON battery. This invention selectively passivates contacts only in the front metal region of the battery, that is, the silicon oxide layer and the polycrystalline silicon layer are only provided in the front metal region. This reduces the absorption of free carriers on the front of the battery, reduces metal recombination between the metal and non-metal regions, and improves the open-circuit voltage and fill factor of the battery cell. At the same time, since the groove is provided in the front metal region, the contact area between the silicon oxide layer and the polycrystalline silicon layer on the front and the n-type substrate silicon is greatly increased, reducing the internal resistance of the battery cell and further improving the short-circuit current and fill factor of the battery cell.

[0068] Based on Implementation Method 1, the front side of the battery cell is further graphicized to obtain Implementation Method 2, the flowchart of which is shown below. Figure 2 As shown, it includes:

[0069] S201: Grooves are cut in the SE region of n-type substrate silicon to obtain grooves.

[0070] S202: A silicon oxide layer and a polycrystalline silicon layer are deposited sequentially on both sides of the grooved n-type substrate silicon to obtain the silicon wafer to be doped.

[0071] S203: The front side of the silicon wafer to be doped is boron doped and the back side is phosphorus doped.

[0072] S204: Remove the polycrystalline silicon layer and silicon oxide layer from the non-SE region on the front side of the doped silicon wafer to obtain the battery pre-face material.

[0073] S205: Boron redoping is performed on the SE region on the front side of the n-type substrate silicon using laser redoping.

[0074] Specifically, the power range of the laser redoping is 25 watts to 35 watts, including endpoint values ​​such as any one of 25.0 watts, 31.8 watts, or 35.0 watts.

[0075] S206: Clean the battery pre-pack to remove the glassy silicon.

[0076] S207: An aluminum oxide passivation layer is provided on the front side of the battery front element after removing the glass silicon.

[0077] S208: A front silicon nitride layer is formed on the surface of the alumina passivation layer, and a back silicon nitride layer is formed on the surface of the back polycrystalline silicon layer to obtain a photovoltaic silicon wafer.

[0078] S209: Surface metallization is performed on the photovoltaic silicon wafer to obtain the novel TOPCON cell.

[0079] The difference between this specific embodiment and the aforementioned specific embodiment is that, in this specific embodiment, laser redoping is further performed before removing the glassy silicon. The remaining steps are the same as those in the aforementioned specific embodiment, and will not be elaborated here.

[0080] In this specific embodiment, after double-sided doping, the glass transition silicon byproduct generated by the reaction is not removed immediately. Instead, the glass transition silicon is used to re-dope the front SE region of the battery by laser re-doping, which burns off the BSG in the front SE region and drives some of the boron in the BSG into the corresponding front polycrystalline silicon layer, thereby achieving re-doping. At the same time, organic compounds or organic complexes that are impurities can be burned off.

[0081] This invention also provides a novel TOPCON battery, the structural schematic diagram of one specific embodiment of which is shown below. Figure 3 As shown, referred to as Specific Embodiment Three, it includes an n-type substrate silicon 10. The front side of the n-type substrate silicon 10 includes a groove disposed in the SE region. The groove includes, from the inside to the outside, a front silicon oxide layer 20 and a front boron-doped polysilicon layer 30. The front side of the n-type substrate silicon 10 includes an aluminum oxide passivation layer 40 that is disposed on the entire surface and covers the front boron-doped polysilicon layer 30, a front silicon nitride layer 50 disposed on the outer surface of the aluminum oxide passivation layer 40, and a front electrode 91 that penetrates the front silicon nitride layer 50 and the aluminum oxide passivation layer 40 and contacts the front boron-doped polysilicon layer 30.

[0082] From the back side of the n-type substrate silicon 10 outwards, it includes a back silicon oxide layer 60, a back phosphorus-doped polycrystalline silicon layer 70, a back silicon nitride layer 80, and a back electrode 92 that penetrates the back silicon nitride layer 80 and contacts the back phosphorus-doped polycrystalline silicon layer 70.

[0083] In a preferred embodiment, the sheet resistance of the front boron-doped polysilicon layer 30 ranges from 100 ohms to 120 ohms, including endpoint values ​​such as any one of 100.0 ohms, 115.3 ohms, or 120.0 ohms.

[0084] Additionally, the sheet resistance of the back phosphorus-doped polysilicon layer 70 ranges from 36 ohms to 48 ohms, including endpoint values ​​such as any one of 36.0 ohms, 40.1 ohms, or 48.0 ohms.

[0085] Furthermore, the thickness of the front silicon nitride layer 50 and / or the back silicon nitride layer 80 ranges from 70 nanometers to 80 nanometers, including endpoint values ​​such as any one of 70.0 nanometers, 72.3 nanometers, or 80.0 nanometers.

[0086] The novel TOPCON battery in this specific embodiment corresponds to the manufacturing method of the novel TOPCON battery described above. For specific technical details and beneficial effects, please refer to the previous text, which will not be elaborated here.

[0087] The novel TOPCON battery provided by this invention includes an n-type substrate silicon 10. The front side of the n-type substrate silicon 10 includes a groove disposed in the SE region. From the inside to the outside, the groove includes a front silicon oxide layer 20 and a front boron-doped polycrystalline silicon layer 30. The front side of the n-type substrate silicon 10 includes an aluminum oxide passivation layer 40 that is disposed on the entire surface and covers the front boron-doped polycrystalline silicon layer 30, a front silicon nitride layer 50 disposed on the outer surface of the aluminum oxide passivation layer 40, and a front electrode 91 that penetrates the front silicon nitride layer 50 and the aluminum oxide passivation layer 40 and contacts the front boron-doped polycrystalline silicon layer 30. From the back side of the n-type substrate silicon 10 outward, it includes a back silicon oxide layer 60, a back phosphorus-doped polycrystalline silicon layer 70, a back silicon nitride layer 80, and a back electrode 92 that penetrates the back silicon nitride layer 80 and contacts the back phosphorus-doped polycrystalline silicon layer 70. This invention selectively passivates contacts only in the front metal region of the battery, that is, the front silicon oxide layer 20 and the front polycrystalline silicon layer are only provided in the front metal region. This reduces the absorption of free carriers on the front of the battery, reduces metal recombination between the metal and non-metal regions, and improves the open-circuit voltage and fill factor of the battery cell. At the same time, since the groove is provided in the front metal region, the contact area between the front silicon oxide layer 20 and the front polycrystalline silicon layer and the n-type substrate silicon 10 is greatly increased, reducing the internal resistance of the battery cell and further improving the short-circuit current and fill factor of the battery cell.

[0088] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0089] It should be noted that in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0090] The novel TOPCON battery and its manufacturing method provided by this invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this invention. It should be noted that those skilled in the art can make several improvements and modifications to this invention without departing from the principles of this invention, and these improvements and modifications also fall within the protection scope of the claims of this invention.

Claims

1. A method for manufacturing a novel TOPCON cell, characterized by, The method comprises the following steps: Grooving the SE region of the n-type base silicon to form a groove; Depositing a silicon oxide layer and a polysilicon layer on the front and back surfaces of the grooved n-type base silicon in sequence to obtain a to-be-doped silicon wafer; Boron-doping the front surface and phosphorus-doping the back surface of the to-be-doped silicon wafer; Removing the polysilicon layer and the silicon oxide layer of the non-SE region on the front surface of the doped silicon wafer to obtain a cell precursor; Cleaning the cell precursor to remove glassified silicon; Setting an aluminum oxide passivation layer on the front surface of the cell precursor from which the glassified silicon is removed; Setting a front surface silicon nitride layer on the surface of the aluminum oxide passivation layer and a back surface silicon nitride layer on the surface of the polysilicon layer on the back surface to obtain a photovoltaic silicon wafer; Surface metallization of the photovoltaic silicon wafer to obtain the new TOPCON cell.

2. The method of claim 1, wherein the method is a method of manufacturing a novel TOPCON cell, characterized by, The step of removing the polysilicon layer and the silicon oxide layer of the non-SE region on the front surface of the doped silicon wafer to obtain a cell precursor comprises: Setting a mask layer on the SE region of the doped silicon wafer; Acid washing the front surface of the silicon wafer on which the mask layer is set to remove the polysilicon layer and the silicon oxide layer of the non-SE region on the front surface to obtain a cell precursor.

3. The method of claim 1, wherein the method is a method of manufacturing a novel TOPCON cell, characterized by, Before the step of cleaning the cell precursor to remove glassified silicon, the method further comprises: Boron re-doping the SE region on the front surface of the n-type base silicon by using laser re-doping.

4. The method of claim 3, wherein the method is a method of manufacturing a novel TOPCON cell, characterized by, The power range of the laser re-doping is 25-35 W, inclusive.

5. The method of claim 1, wherein the novel TOPCON cell is fabricated by the steps of: Before the step of setting a groove on the SE region of the n-type base silicon, the method further comprises: Placing the n-type base silicon in a potassium hydroxide solution for surface texturing; the concentration of the potassium hydroxide solution ranges from 0.5% to 2%, inclusive, and the temperature of the potassium hydroxide solution ranges from 40°C to 60°C, inclusive.

6. The method of claim 1, wherein the novel TOPCON cell is fabricated by the steps of: After the step of surface metallization of the photovoltaic silicon wafer, the method further comprises: Light injection hydrogen passivation of the photovoltaic silicon wafer to obtain the new TOPCON cell; the temperature range of the light injection hydrogen passivation is 300-500°C, inclusive.

7. A novel TOPCON cell comprising n-type bulk silicon, characterized in that, The front surface of the n-type base silicon comprises a groove set in the SE region, and the groove comprises, from inside to outside, a front surface silicon oxide layer and a front surface boron-doped polysilicon layer; the front surface of the n-type base silicon comprises an aluminum oxide passivation layer set on the entire surface and covering the front surface boron-doped polysilicon layer, a front surface silicon nitride layer set on the outer surface of the aluminum oxide passivation layer, and a front surface electrode penetrating through the front surface silicon nitride layer and the aluminum oxide passivation layer and in contact with the front surface boron-doped polysilicon layer; The back surface of the n-type base silicon comprises, from outside to inside, a back surface silicon oxide layer, a back surface phosphorus-doped polysilicon layer, a back surface silicon nitride layer, and a back surface electrode penetrating through the back surface silicon nitride layer and in contact with the back surface phosphorus-doped polysilicon layer.

8. The novel TOPCON cell of claim 7, wherein, The sheet resistance of the front surface boron-doped polysilicon layer ranges from 100 to 120 ohms, inclusive.

9. The novel TOPCON cell as claimed in claim 7, wherein, The sheet resistance of the back surface phosphorus-doped polysilicon layer ranges from 36 to 48 ohms, inclusive.

10. The novel TOPCON cell as claimed in claim 7, wherein, The thickness of the front surface silicon nitride layer and / or the back surface silicon nitride layer ranges from 70 to 80 nm, inclusive.

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