A three wire common mode filter

Abstract

The application provides a three-wire common-mode filter, which comprises a first layer of thick copper, a second layer of thick copper, a third layer of thick copper and a fourth layer of thick copper; a first via hole is arranged between the first layer of thick copper and the second layer of thick copper; a second via hole is arranged between the second layer of thick copper and the third layer of thick copper; a third via hole is arranged between the third layer of thick copper and the fourth layer of thick copper; the second layer of thick copper, the third layer of thick copper and the fourth layer of thick copper are all provided with a capacitor pole plate for adjusting return loss. The three-wire common-mode filter with high performance and small size is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of filters, in particular to a three-wire common-mode filter. BACKGROUND

[0002] The three-wire common-mode filter is currently mainly applied to MIPI C-PHY. The MIPI protocol mainly solves the data transmission between the screen / camera module and the application IC. At present, the protocol mainly used in mobile terminals is MIPI D-PHY, but in the application scene such as mobile phones which needs miniaturization, C-PHY which can be higher speed and reduce the number of lines is becoming a trend. SUMMARY

[0003] In view of the above problems, the present application is proposed in order to provide a three-wire common-mode filter which overcomes the above problems or at least partially solves the above problems.

[0004] According to one aspect of the present application, a three-wire common-mode filter is provided, the common-mode filter comprising: a first layer of thick copper, a second layer of thick copper, a third layer of thick copper and a fourth layer of thick copper;

[0005] A first via hole is arranged between the second layer of thick copper and the first layer of thick copper;

[0006] A second via hole is arranged between the third layer of thick copper and the second layer of thick copper;

[0007] A third via hole is arranged between the fourth layer of thick copper and the third layer of thick copper;

[0008] The second layer of thick copper, the third layer of thick copper and the fourth layer of thick copper are all provided with a capacitor plate for adjusting return loss.

[0009] Optionally, the common-mode filter further comprises: a bottom thick copper layer and a bottom pad;

[0010] The bottom thick copper layer is arranged on the bottom pad for leading out a signal line.

[0011] Optionally, the bottom pad is an SMD package.

[0012] Optionally, the common-mode filter further comprises: a TGV hole layer arranged on the bottom thick copper layer.

[0013] Optionally, the signal lines of the third layer of thick copper and the second layer of thick copper are single-layer wiring.

[0014] Optionally, the signal lines of the first layer of thick copper and the fourth layer of thick copper are connected through the via hole between the layers to realize the effect of parallel common walking.

[0015] Optionally, the filter further comprises a top pad disposed on the fourth thick copper layer.

[0016] The application provides a three-wire common-mode filter, which comprises a first thick copper layer, a second thick copper layer, a third thick copper layer and a fourth thick copper layer; a first via hole is arranged between the second thick copper layer and the first thick copper layer; a second via hole is arranged between the third thick copper layer and the second thick copper layer; a third via hole is arranged between the fourth thick copper layer and the third thick copper layer; the second thick copper layer, the third thick copper layer and the fourth thick copper layer are all provided with a capacitor pole plate for adjusting return loss. The three-wire common-mode filter with high performance and small size is realized.

[0017] The above description is only a summary of the technical scheme of the application. In order to more clearly understand the technical means of the application, the application can be implemented according to the content of the specification, and in order to make the above and other purposes, characteristics and advantages of the application more obvious and easy to understand, the following specific embodiments of the application are described. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical scheme of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the application, and those skilled in the art can also obtain other drawings according to these drawings without creating any creative labor.

[0019] Figure 1 The TGV process schematic diagram of the four-layer thick copper SMD package provided by the embodiment of the application;

[0020] Figure 2 The WB / FC package provided by the embodiment of the application does not need TGV and bottom thick copper, and the process schematic diagram is shown in the figure;

[0021] Figure 3 The pad adopts SMD package for the bottom thick copper layer and the TGV hole layer provided by the embodiment of the application;

[0022] Figure 4 The via hole schematic diagram of the thick copper 1 and the via hole from the thick copper 1 to the thick copper 2 provided by the embodiment of the application;

[0023] Figure 5 The via hole schematic diagram of the thick copper 2 and the via hole from the thick copper 2 to the thick copper 3 provided by the embodiment of the application;

[0024] Figure 6 The via hole schematic diagram of the thick copper 3 and the via hole from the thick copper 3 to the thick copper 4 provided by the embodiment of the application;

[0025] Figure 7 The thick copper 4 schematic diagram provided by the embodiment of the application;

[0026] Figure 8 The schematic diagram of the principle provided for the embodiment of the present application;

[0027] Figure 9 The simulation S parameter performance schematic provided for the embodiment of the present application. DETAILED DESCRIPTION

[0028] Exemplary embodiments of the present disclosure will be described in greater detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it is understood that the present disclosure can be embodied in various forms without being limited by the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure can be thoroughly understood, and the scope of the present disclosure can be accurately conveyed to those skilled in the art.

[0029] The terms "include" and "have" and any variations thereof in the specification, claims and drawings of the present application are intended to cover the non-exclusive inclusion, for example, the inclusion of a series of steps or units.

[0030] The technical solutions of the present application will be described in further detail below in combination with the drawings and embodiments.

[0031] The present application takes the four-layer thick copper TGV (Through-Glass Vias) process of penetrating the glass substrate as an example. The integrated passive device IPD process can be divided into high-resistance silicon / gallium arsenide and glass processes according to different substrates, and the present application is not limited to any of these processes.

[0032] As shown in Figure 1 , according to the packaging form, it can be divided into wire bonding WB (Wire bonding), flip chip FC (Flip chip) and the surface mount device SMD shown in the present patent, and it is also not limited to any of these packaging forms.

[0033] The bottom thick copper and TGV are not necessary processes of the present application, and are only used for signal lead-out function. The core is the four-layer thick copper, and the WB / FC packaging does not need TGV and bottom thick copper, and the process schematic diagram is shown in Figure 2 .

[0034] As shown in Figure 3 , it is the bottom thick copper layer and the TGV hole layer, and the pad adopts SMD packaging, which is used for signal line lead-out function.

[0035] As shown in Figure 4 , it is the thick copper 1 and the via hole from the thick copper 1 to the thick copper 2.

[0036] As shown in Figure 5 , it is the thick copper 2 and the via hole from the thick copper 2 to the thick copper 3, and the present application adds a capacitor plate for adjusting return loss.

[0037] As Figure 6 The thick copper 3 and the via hole from the thick copper 3 to the thick copper 4, the capacitor plate for adjusting the return loss is added in the application.

[0038] As Figure 7 The thick copper 4, the capacitor plate for adjusting the return loss is added in the application.

[0039] As Figure 8 The schematic diagram of the above example is shown, the thick copper 1 and the thick copper 4 signal lines are connected through the via hole between the layers, achieving the effect of parallel common walk, in the example, the walk line layer used for signal a.

[0040] The thick copper 2 and the thick copper 3 signal lines are single-layer walk lines, respectively, the walk line layer used for signal b and signal c. The structure is approximately symmetrical between signal b and a and signal c and a, and the coupling strength is improved.

[0041] The symmetrical structure can increase the isolation degree between the differential mode and the common mode signal, and the parallel walk line can also reduce the walk DC resistance of the signal line a.

[0042] In the example, the capacitor plate for adjusting the return loss is added between the first signal b and signal c, and the occupied layer is the thick copper 2 / 3 / 4 layer. In the application, according to the actual layout and process, the corresponding size of the capacitor can be reasonably added between the three signal lines for performance adjustment, or the capacitor can be removed, depending on the situation.

[0043] As Figure 9 The simulation S parameter performance diagram of the above example is shown:

[0044] Performance advantage: under the feasible process parameters, the chip size is 850umx650um (including cutting channel) and SMD surface mounting is performed. The SDD21 differential mode-3dB cutoff frequency is more than 10GHz; the SCC21 common mode suppression bandwidth can be about 2 to 5GHz; the isolation degree between the differential mode and the common mode of the SCD21 is less than-30dB within 6GHz; the reflection of all signal ports within-15dB can be close to 6GHz.

[0045] Beneficial effect: a high-performance small-size three-wire common mode filter is realized, achieving the effects of high performance and miniaturization.

[0046] The above specific embodiments further illustrate the purpose, technical solutions and beneficial effects of the application. It should be understood that the above is only a specific embodiment of the application and is not used to limit the protection scope of the application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the application shall be included in the protection scope of the application.

Claims

1. A three-wire common-mode filter, characterized in that, The common-mode filter includes: a first layer of thick copper, a second layer of thick copper, a third layer of thick copper, and a fourth layer of thick copper; A first via is provided between the second thick copper layer and the first thick copper layer; A second via is provided between the third thick copper layer and the second thick copper layer; A third via is provided between the fourth thick copper layer and the third thick copper layer; The second, third, and fourth thick copper layers are all equipped with capacitor plates to adjust return loss. The signal lines of the third thick copper layer and the second thick copper layer are single-layer traces; The signal lines of the first thick copper layer and the fourth thick copper layer are connected through interlayer vias to achieve parallel operation.

2. A three-wire common-mode filter according to claim 1, characterized in that, The common-mode filter further includes: a bottom thick copper layer and a bottom pad; The thick copper layer at the bottom is disposed on the bottom pad and is used to lead out signal lines.

3. A three-wire common-mode filter according to claim 2, characterized in that, The bottom pad is an SMD package.

4. A three-line common-mode filter according to claim 2, characterized in that, The common-mode filter further includes a TGV via layer disposed on the bottom thick copper layer.

5. A three-wire common-mode filter according to claim 1, characterized in that, The filter also includes a top pad disposed on the fourth layer of thick copper.

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