Global mismatch calibration method and circuit for array-level dynamic comparators

Abstract

The application discloses a global misadjustment calibration method and circuit of an array-level dynamic comparator and belongs to the technical field of integrated circuits.The application uses a set of high-precision calibration signal generation circuits in common, and the comparator only needs to increase calibration logic circuits and calibration and storage circuits, so that the contradiction between calibration precision and area overhead is effectively balanced, high-precision calibration signals are obtained, and the area overhead of the calibration circuit of each comparator is greatly reduced.The use of the same calibration signal source is favorable to the matching between the comparators in the array, reduces the mismatch between the comparators caused by the traditional independent calibration circuit, improves the array-level matching, improves the misadjustment calibration precision, and can be applied to the global calibration of the array-level dynamic comparator.

Description

TECHNICAL FIELD

[0001] The present application relates to a global offset calibration method and circuit of an array-level dynamic comparator, and belongs to the technical field of integrated circuits. BACKGROUND

[0002] In the field of image sensors, integrated computing and calculating chips, etc., with the decrease of device size and the expansion of array size, the analog signal processing circuit is limited by the array width, and the area needs to be reduced as much as possible. In the mainstream column-level signal processing circuit, an analog-to-digital converter (ADC) is needed for each column, and the area of the ADC accounts for a large proportion of the overall circuit, so it is necessary to improve the conversion accuracy in a smaller area. Among them, the dynamic comparator circuit is an important module for converting analog signals to digital signals, and needs to have high comparison accuracy. However, with the fluctuation of process parameters, an equivalent input offset is generated at the output end of the dynamic comparator, and the offset voltage can reach tens of millivolts, which greatly affects the comparison accuracy. The offset voltage of the comparator will reduce the dynamic input range of the ADC and also reduce the conversion accuracy.

[0003] For a two-stage dynamic comparator, the offset voltage is composed of a pre-amplification stage offset and a latching stage offset, and the comparator offset voltage can be expressed as:

[0004]

[0005] Among them, V OS is the comparator offset voltage, V OS,PREAMP and V OS,LATCH are the equivalent input offset voltages of the pre-amplification stage and the latching stage respectively, and A is the gain of the pre-amplification stage. As can be seen from the above formula, the offset is mainly generated by the pre-amplification stage, and the current calibration scheme mainly calibrates the offset of the pre-amplification stage under the condition of maintaining a high gain of the pre-amplification stage.

[0006] The pre-amplification stage offset is mainly caused by the mismatch of the input tube threshold voltage (V TH ), the width-length ratio (W / L) and the load (R):

[0007]

[0008]

[0009] Among them, ΔV TH is the threshold voltage offset of the input tube, A VT is a process-related parameter, and ΔW / L and ΔR are the mismatches of the width-length ratio and the load respectively.

[0010] The common calibration methods at present mainly include the offset voltage storage method represented by automatic zero setting and correlated double sampling and the analog trimming method using digital assistance. The offset voltage storage method needs to add an additional calibration period in the comparator timing, and the offset voltage is stored on the capacitor before each comparison and is subtracted during the comparison, so as to eliminate the influence of the offset voltage. This method introduces a large capacitive load in the circuit, which affects the speed and bandwidth of the circuit, and is not suitable for calibration of high-speed dynamic comparators. The analog trimming method using digital assistance is the mainstream technology for high-speed dynamic comparators. The calibration circuit applies a calibration voltage controlled by a digital circuit to one of the signal paths of the comparator to change the delay, current or load on the corresponding path, so as to offset the offset, including: offset calibration method based on body voltage trimming (CN113765519A), calibration method based on current compensation (CN106059583A), calibration method based on adjustable charge pump (CN110460335A) and the like. This kind of method only needs to add a few devices to the comparator, and has little effect on the speed of the circuit, but the calibration accuracy is limited by the calibration range and step size. High-precision calibration generally needs to cover as much as possible the offset voltage values that may occur under each process corner, and at the same time, the calibration step size should be as small as possible, which leads to problems such as too long calibration period and too large calibration voltage generation circuit area.

[0011] The array-level dynamic comparator refers to a dynamic comparator used in a large-scale array signal processing circuit. Although the above calibration methods can achieve good calibration effect, they all have the problem of huge area consumption when applied to the array-level dynamic comparator, and the scheme of calibrating each comparator respectively will cause the comparators at different positions in the array to still have mismatch after calibration, and the calibration accuracy is poor. Therefore, a global calibration method for the array-level dynamic comparator is needed. SUMMARY

[0012] In order to solve the problems of large area consumption and poor calibration accuracy when the current offset calibration circuit and method are applied to the array-level dynamic comparator, the present application provides an array-level dynamic comparator global offset calibration method and circuit, and the technical solution is as follows:

[0013] The first object of the present application is to provide a global offset calibration circuit for an array-level dynamic comparator, which comprises a calibration voltage generation circuit, a calibration logic circuit and a calibration and storage circuit.

[0014] The calibration voltage generation circuit is used to generate calibration voltage for all array calibration circuits;

[0015] The calibration logic circuit generates a calibration signal according to the output of the comparator to control the global offset calibration circuit to perform reset, start calibration and end calibration operations.

[0016] The calibration and storage circuit is used for offsetting the influence of the offset by changing the calibration parameter during the calibration process, sampling the calibration voltage and storing it in the corresponding energy storage element or energy storage module, and keeping the calibration voltage at the end of the calibration process to eliminate the influence of the offset during the normal operation of the subsequent comparator;

[0017] The calibration parameter includes voltage, current and delay parameter.

[0018] Optionally, the calibration voltage generation circuit includes an N bit counter and an N bit digital-to-analog converter.

[0019] The counter is triggered by the clock signal to realize the operation of outputting one more than the previous one in each clock cycle; the output of the counter is used as the input signal of the digital-to-analog converter, and the step voltage signal output by the digital-to-analog converter is used as the calibration voltage signal.

[0020] Optionally, the calibration logic circuit includes a calibration state conversion logic circuit and a calibration switch conversion logic circuit.

[0021] The calibration state conversion logic circuit includes flip-flops DFF1-DFF4, or gates OR1-OR2, an inverter INV1 and an AND gate AND1; wherein the data input end D of the flip-flops DFF1 and DFF3 is connected to GND, and the clock input end CLK is connected to the comparator output COMP_P; the data input end D of the flip-flops DFF2 and DFF4 is connected to GND, and the clock input end CLK is connected to the comparator output COMP_N; the set signal input end of the flip-flops DFF1 and DFF2 is connected to the calibration reset signal PRE.

[0022] The output of the flip-flops DFF1 and DFF2 generates a local first calibration period signal ZN1 through the or gate OR1, generates a local second calibration period signal ZN2 through the inverter INV1, and the local second calibration period signal ZN2 is used as the set signal of the flip-flops DFF3 and DFF4; the output of the flip-flops DFF3 and DFF4 generates a local second calibration period enable signal EN2 through the or gate OR2; and the local second calibration period enable signal EN2 and the global calibration enable signal EN generate an input shorting switch signal OC through the AND gate AND1.

[0023] The calibration switch conversion logic circuit comprises flip-flops DFF5-DFF11, AND gates AND2-AND3; wherein the local first calibration period signal ZN1 and the calibration reset signal PRE are connected to the reset signal input terminals of flip-flops DFF5 and DFF6 through the AND gate AND2; the data input terminals D of flip-flops DFF5 and DFF6 are connected to the power supply VDD; the clock input terminal CLK of flip-flop DFF5 is connected to the comparator output COMP_N, and the clock input terminal CLK of flip-flop DFF6 is connected to the comparator output COMP_P; the positive output terminal Q of flip-flop DFF5 is the P-side switch signal SCP of the first calibration period and is connected to the clock input terminal of flip-flop DFF7; the negative output terminal of flip-flop DFF5 is connected to the clock input terminal of flip-flop DFF8; the positive output terminal Q of flip-flop DFF6 is the N-side switch signal SCN of the first calibration period and is connected to the clock input terminal of flip-flop DFF9; the negative output terminal of flip-flop DFF6 is connected to the clock input terminal of flip-flop DFF10; the data input terminals D of flip-flops DFF7 and DFF9 are connected to GND, and the set signals are connected to the calibration reset signal PRE; the data input terminals D of flip-flops DFF8 and DFF10 are connected to the outputs COMP_N and COMP_P of the comparator respectively, and the set signals are connected to the local second calibration period signal ZN2; the output of flip-flop DFF7 is the P-side switch signal SCP_GND of the first calibration period, the output of flip-flop DFF8 is the N-side switch signal SFN of the second calibration period, the output of flip-flop DFF9 is the N-side switch signal SCN_GND of the first calibration period, and the output of flip-flop DFF10 is the P-side switch signal SFP of the second calibration period. The local second calibration period signal ZN2, the local second calibration period enable signal EN2 and the global second calibration period signal ENF generate the local second calibration period switch signal SF through the AND gate AND3 and serve as the clock signal of flip-flop DFF11; the data input terminal of flip-flop DFF11 is connected to GND, the set signal is connected to the calibration reset signal PRE, and the output signal is the local second calibration period switch signal SF_GND.

[0024] Optionally, the calibration and storage circuit comprises a calibration module and a storage module.

[0025] The storage module is responsible for storing the calibration voltage signal, maintaining the voltage signal and connecting the voltage signal to the calibration module; the calibration module changes the calibration parameter according to the voltage signal of the storage module to offset the influence of the offset.

[0026] Optionally, the calibration and storage circuit comprises a current compensation and storage circuit and a delay adjustable and storage circuit.

[0027] The current compensation and storage circuit comprises an auxiliary discharge NMOS tube, a first storage capacitor and a first gating switch; the first gating switch connects the gate of the auxiliary discharge NMOS tube and the upper plate of the first storage capacitor to the low voltage GND or a first calibration voltage signal VOC1 according to the control signal of the calibration logic circuit; the auxiliary discharge NMOS tube changes the passing current I according to the first calibration voltage signal VOC1 applied to the gate, so as to offset the influence of the offset D ; and the first storage capacitor is responsible for storing and keeping the calibration voltage.

[0028] Optionally, the delay adjustable circuit and storage circuit comprises PMOS tubes PM7 and PM8, NMOS tubes NM9 and NM10, a second storage capacitor C F and a second gating switch.

[0029] The second gating switch connects the gate of the PMOS tube PM7 and the upper plate of the second storage capacitor C F to the low voltage GND or a second calibration voltage signal VOC2 according to the control signal of the calibration logic circuit; the PMOS tube PM8 and the NMOS tube NM9 constitute an inverter, the drain of the NMOS tube NM10 is connected with the source of the NMOS tube NM9, and the source is connected with GND; the PMOS tube PM7 serves as a delay MOS tube, the source is connected with VDD, the drain is connected with the source of the PMOS tube PM8, and the PMOS tube PM7 changes the rising edge delay between CLK_N and CLKD according to the second calibration voltage signal VOC2 applied to the gate; and the second storage capacitor C F is responsible for storing and keeping the calibration voltage.

[0030] Optionally, the energy storage element comprises a capacitor.

[0031] The second object of the present application is to provide a global offset calibration method of an array-level dynamic comparator, which is realized based on the above-mentioned global offset calibration circuit of the array-level dynamic comparator, and comprises the following steps:

[0032] Step one: a calibration voltage signal with step change is generated by the calibration voltage generation circuit and is output to the calibration logic circuit, the calibration and storage circuit of all comparators;

[0033] Step two: at the beginning of the calibration period, the comparator outputs a first group of comparison results according to the clock signal; the calibration logic circuit judges the calibration side according to the comparison results and outputs a control signal to connect the calibration and storage circuit to the calibration voltage generation circuit;

[0034] Step three: the calibration voltage changes step by step until the polarity of the comparator output is reversed; the calibration logic circuit detects the polarity reversal, outputs a control signal to float the storage circuit, and keeps the calibration voltage in the storage circuit; and ends the calibration period of the comparator.

[0035] Step four: the calibration voltage continues to change in steps until the output voltage reaches full scale, at which time the calibration voltage generation circuit stops changing, all comparators in the array should end calibration, the calibration voltage of each comparator is maintained, and the comparator mismatch calibration ends.

[0036] A third object of the present application is to provide a memory-compute integrated chip comprising the above-mentioned array-level dynamic comparator global mismatch calibration circuit.

[0037] A fourth object of the present application is to provide an image sensor comprising the above-mentioned array-level dynamic comparator global mismatch calibration circuit.

[0038] The present application has the following beneficial effects:

[0039] The array-level dynamic comparator global mismatch calibration method and circuit of the present application uses a set of high-precision calibration signal generation circuit globally, and only needs to add calibration logic circuit and calibration and storage circuit to the comparator, thereby solving the contradiction between calibration accuracy and area overhead, achieving higher calibration accuracy with small area increase. Meanwhile, the method can be extended to two-step calibration, solving the contradiction between calibration accuracy and time. And because the same calibration signal generation circuit is used, the mismatch between comparators caused by traditional independent calibration circuits is reduced, improving the array-level matching. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0041] Figure 1 is the overall structure diagram of the array-level dynamic comparator global mismatch calibration of the present application.

[0042] Figure 2 is the two-step calibration logic circuit diagram provided by the second embodiment of the present application, wherein (a) is the calibration state transition logic circuit diagram, and (b) is the calibration switch transition logic circuit diagram.

[0043] Figure 3 is the calibration and storage circuit diagram provided by the third embodiment of the present application, wherein (a) is the current compensation and storage circuit diagram, and (b) is the delay adjustable and storage circuit diagram.

[0044] Figure 4is the input signal range and the calibratable offset voltage range of the calibration voltage generation circuit provided by the third embodiment of the present application, wherein (a) the first calibration voltage and the calibratable offset voltage range, (b) the second calibration voltage and the calibratable offset voltage range.

[0045] Figure 5 is the dynamic comparator and calibration circuit diagram provided by the third embodiment of the present application.

[0046] Figure 6 is the calibration timing diagram provided by the third embodiment of the present application.

[0047] Figure 7 is the offset voltage normal distribution curve diagram before calibration of the third embodiment of the present application.

[0048] Figure 8 is the offset voltage normal distribution curve diagram after calibration of the third embodiment of the present application. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solutions and advantages of the present application more clear, the following will combine the drawings to make further detailed description of the embodiments of the present application.

[0050] Embodiment One:

[0051] The present embodiment provides a global offset calibration circuit of array-level dynamic comparator, referring to Figure 1 , comprising: a calibration signal generation circuit, a calibration logic circuit and a calibration and storage circuit.

[0052] A global offset calibration circuit of array-level dynamic comparator, characterized in that the global offset calibration circuit comprises: a calibration signal voltage generation circuit, a calibration logic circuit and a calibration signal and storage circuit.

[0053] The calibration signal voltage generation circuit is used to generate calibration signals for all array calibration circuits in the whole chip.

[0054] The calibration logic circuit controls the global offset calibration circuit to implement reset, start calibration and end calibration operations according to the calibration signal.

[0055] The calibration signal and storage circuit is used to offset the influence of offset by changing parameters such as voltage, current and delay during calibration, sample the calibration signal and store it in the corresponding energy storage element (such as capacitor) or energy storage circuit, and keep the calibration signal at the end of calibration to eliminate the influence of offset during subsequent comparator normal operation.

[0056] Embodiment Two:

[0057] The calibration logic circuit of the present embodiment is as shown in Figure 2As shown, it is a two-step calibration logic circuit, including calibration state transition logic circuit and calibration switch transition logic circuit.

[0058] The calibration state transition logic circuit includes flip-flops DFF1-DFF4, OR gates OR1-OR2, an inverter INV1, and an AND gate AND1. The data input terminals D of DFF1 and DFF3 are connected to GND, and the clock input terminals CLK are connected to the comparator output COMP_P. The data input terminals D of DFF2 and DFF4 are connected to GND, and the clock input terminals CLK are connected to the comparator output COMP_N. The set signal input terminals of DFF1 and DFF2 are connected to the calibration reset signal PRE. The outputs of DFF1 and DFF2 are input to the OR gate OR1 to generate a local first calibration period signal ZN1, and the output of the OR gate OR1 is input to the inverter INV1 to generate a local second calibration period signal ZN2, which is used as the set signal of DFF3 and DFF4. The outputs of DFF3 and DFF4 are input to the OR gate OR2 to generate a local second calibration period enable signal EN2. The EN2 and the global calibration enable signal EN are input to the AND gate AND1 to generate an input shorting switch signal OC.

[0059] The calibration switch conversion logic circuit comprises flip-flops DFF5-DFF11 and AND gates AND2-AND3. The local first calibration period signal ZN1 and the calibration reset signal PRE are connected to the reset signal input terminals of DFF5 and DFF6 through the AND gate AND2. The data input terminals D of DFF5 and DFF6 are connected to VDD. The clock input terminal CLK of DFF5 is connected to the comparator output COMP_N, and the clock input terminal CLK of DFF6 is connected to the comparator output COMP_P. The positive output terminal Q of DFF5 is the first calibration period P-side switch signal SCP and is connected to the clock input terminal of DFF7; the negative output terminal of DFF5 is connected to the clock input terminal of DFF8. The positive output terminal Q of DFF6 is the first calibration period N-side switch signal SCN and is connected to the clock input terminal of DFF9; the negative output terminal of DFF6 is connected to the clock input terminal of DFF10. The data input terminals D of DFF7 and DFF9 are connected to GND, and the set signals are connected to the calibration reset signal PRE. The data input terminals D of DFF8 and DFF10 are connected to the comparator outputs COMP_N and COMP_P respectively, and the set signals are connected to the local second calibration period signal ZN2. The output of DFF7 is the first calibration period P-side switch signal SCP_GND, the output of DFF8 is the second calibration period N-side switch signal SFN, the output of DFF9 is the first calibration period N-side switch signal SCN_GND, and the output of DFF10 is the second calibration period P-side switch signal SFP. The local second calibration period signal ZN2, the local second calibration period enable signal EN2 and the global second calibration period signal ENF are connected to the local second calibration period switch signal SF through the AND gate AND3, and the local second calibration period switch signal SF is the clock signal of DFF11. The data input terminal of DFF11 is connected to GND, the set signal is connected to the calibration reset signal PRE, and the output signal is the local second calibration period switch signal SF_GND.

[0060] Before calibration, the low level is generated by the calibration reset signal PRE firstly, and the calibration logic circuit is reset. After the calibration reset signal becomes high level, the global calibration enable signal EN becomes high level, and the input shorting switch signal OC is high level, which connects the comparator input to the common mode level. The calibration logic circuit receives the comparator output signals COMP P and COMP N, and at this time, one of the two signals must be low level and the other one jumps from low level to high level. The rising edge triggers DFF1 and DFF6 (or DFF2 and DFF5), so that SCN (or SCP) becomes high level, and the N-side (or P-side) calibration circuit is disconnected from GND and connected to the first calibration voltage generating circuit. Before the end of the first calibration period, the comparator output polarity is reversed, i.e. the output which keeps low level changes from low level to high level, and the other one changes to low level. At this time, DFF2 (or DFF1) is triggered, so that the local first calibration period signal ZN1 becomes low level, and the first calibration period ends. The local second calibration period signal ZN2 becomes high level, and the flip-flop DFF4 (or DFF3) is triggered by the corresponding output signal of the comparator. At this time, the local second calibration period enable signal EN2 keeps high level. The local first calibration period signal ZN1 becomes low level, and DFF5 and DFF6 are reset, so that the negative output of DFF5 (or DFF6) changes from low level to high level, and DFF8 (or DFF10) outputs high level, which connects the corresponding side of the comparator to the second calibration circuit. When the global second calibration period signal ENF becomes high level, the second calibration period starts. Before the end of the second calibration period, the comparator output polarity is reversed, and at this time, DFF3 (or DFF4) is triggered, so that the local second calibration period enable signal EN2 becomes low level, and the local second calibration period ends.

[0061] Embodiment three:

[0062] The embodiment provides a global two-step offset calibration circuit of an array-level dynamic comparator, which adopts the calibration logic circuit described in embodiment two.

[0063] The calibration signal generating circuit of the embodiment includes a 6-bit counter and a digital-to-analog converter (DAC) as the first calibration voltage generating circuit, and a 10-bit counter and a DAC as the second calibration voltage generating circuit. The counter is triggered by a clock signal, and the operation of increasing the output of the counter by one is realized every clock cycle. The output of the counter is used as the input signal of the DAC, and a stepped voltage signal is output by the DAC as the calibration voltage signal.

[0064] The first calibration voltage generating circuit can calibrate the voltage range that needs to cover the possible offset voltage value. According to the Monte-Carlo simulation of the uncalibrated comparator, the offset voltage range is calculated to be ±19.73mV at the confidence level of 99.9% (3.3σ). Thus it is determined that the range that the first calibration period needs to cover is at least ±20mV. The first calibration voltage corresponding to the calibratable offset voltage is shown in Figure 4 (a). The first calibration voltage can achieve the calibration range of ±20mV in the range of 550-750mV. The calibration time is preferred, thus a 6-bit counter and a DAC are selected as the first calibration voltage generating circuit.

[0065] The second calibration voltage generating circuit can calibrate the voltage range that needs to cover the maximum calibration step of the first calibration period, i.e. 7mV, thus it is determined that the second calibration voltage range is 0-650mV, as shown in Figure 4 (b). The calibration accuracy is preferred, thus a 10-bit counter and a DAC are selected as the second calibration voltage generating circuit.

[0066] The calibration and storage circuit of the embodiment is shown in Figure 3 , which comprises:

[0067] The current compensation and storage circuit, the delay adjustable and storage circuit.

[0068] The current compensation and storage circuit comprises auxiliary discharge NMOS tubes NM3 (NM4), a capacitor C CP (C CN ) and a gating switch. The gating switch connects the gate of NM3 (NM4) and the upper plate of capacitor C CP (C CN ) to the low level GND or the calibration voltage signal VOC1 according to the control signal SCP (SCN), SCP (SCN)_GND of the calibration logic circuit; the auxiliary discharge NMOS tube NM3 (NM4) changes the passing current I D according to the calibration voltage signal VOC1 applied to the gate, so as to offset the influence of the offset; the capacitor C CP (C CN ) is responsible for storing and maintaining the calibration voltage.

[0069] The delay adjustable circuit comprises PMOS tubes PM7, PM8, NMOS tubes NM9, NM10, a capacitor C F and a gating switch. The gating switch connects the gate of PM7 and the upper plate of capacitor C FThe upper plate is connected to low level GND or calibration voltage signal VOC2; PM8 and NM9 form an inverter, the drain of NM10 is connected to the source of NM9, and the source is connected to GND; PM7 is a delay MOS, the source is connected to VDD, the drain is connected to the source of PM8, and PM7 changes the rising edge delay between CLK_N and CLKD according to the calibration voltage signal VOC2 applied to the gate; capacitor C F is responsible for storing and maintaining the calibration voltage.

[0070] The dynamic comparator and calibration circuit of the embodiment are as shown in Figure 3 , Figure 5 .

[0071] calibration state conversion logic circuit and calibration switch conversion logic circuit; the calibration state conversion logic circuit includes flip-flops DFF1-DFF4, or gates OR1-OR2, an inverter INV1, and an AND gate AND1. The data input end D of DFF1 and DFF3 is connected to GND, and the clock input end CLK is connected to the comparator output COMP_P; the data input end D of DFF2 and DFF4 is connected to GND, and the clock input end CLK is connected to the comparator output COMP_N; the set signal input end of DFF1 and DFF2 is connected to the calibration reset signal PRE. The output of DFF1 and DFF2 generates a local first calibration period signal ZN1 through or gate OR1, generates a local second calibration period signal ZN2 through inverter INV1, and ZN2 is used as the set signal of DFF3 and DFF4; the output of DFF3 and DFF4 generates a local second calibration period enable signal EN2 through or gate OR2; EN2 and the global calibration enable signal EN generate an input shorting switch signal OC through AND gate AND1.

[0072] The calibration switch conversion logic circuit comprises flip-flops DFF5-DFF11 and AND gates AND2-AND3. The local first calibration period signal ZN1 and the calibration reset signal PRE are connected to the reset signal input terminals of DFF5 and DFF6 through the AND gate AND2. The data input terminals D of DFF5 and DFF6 are connected to VDD. The clock input terminal CLK of DFF5 is connected to the output of the comparator COMP_N, and the clock input terminal CLK of DFF6 is connected to the output of the comparator COMP_P. The positive output terminal Q of DFF5 is the first calibration period P-side switch signal SCP and is connected to the clock input terminal of DFF7; the negative output terminal of DFF5 is connected to the clock input terminal of DFF8. The positive output terminal Q of DFF6 is the first calibration period N-side switch signal SCN and is connected to the clock input terminal of DFF9; the negative output terminal of DFF6 is connected to the clock input terminal of DFF10. The data input terminals D of DFF7 and DFF9 are connected to GND, and the set signals are connected to the calibration reset signal PRE. The data input terminals D of DFF8 and DFF10 are connected to the outputs of the comparators COMP_N and COMP_P respectively, and the set signals are connected to the local second calibration period signal ZN2. The output of DFF7 is the first calibration period P-side switch signal SCP_GND, the output of DFF8 is the second calibration period N-side switch signal SFN, the output of DFF9 is the first calibration period N-side switch signal SCN_GND, and the output of DFF10 is the second calibration period P-side switch signal SFP. The local second calibration period signal ZN2, the local second calibration period enable signal EN2 and the global second calibration period signal ENF are connected to the local second calibration period switch signal SF through the AND gate AND3, and the local second calibration period switch signal SF is the clock signal of DFF11. The data input terminal of DFF11 is connected to GND, the set signal is connected to the calibration reset signal PRE, and the output signal is the local second calibration period switch signal SF_GND.

[0073] The misadjustment calibration process is as follows: Figure 6 The calibration timing diagram is as follows:

[0074] There is a positive misadjustment voltage V on the P side OS For example, the following single-throw switches are all turned on at high level and turned off at low level. CLK_N is the opposite signal of CLK, and CLKD is the time-adjustable signal relative to CLK.

[0075] Calibration reset phase: the PRE signal is at low level, the calibration logic circuit of the comparator in the array is reset, the calibration capacitor is discharged to GND, and the calibration voltage of the last period is emptied.

[0076] The first calibration period: the global calibration enable signal EN is high, and EN_N is its opposite signal, i.e., low. The differential input ends VIP and VIN are disconnected from the input signal and are shorted to the common-mode voltage V CM . The comparator compares at the high level of the clock signal CLK, and the first comparator output COMP_P = 1 and COMP_N = 0, which can be regarded as the existence of a positive equivalent input offset voltage at the P input end. The calibration logic circuit judges to set the SCN signal on the N side to 1, and the first calibration voltage acts on the auxiliary input MOS tube NM2 and is stored in the capacitor C CN . With the gradual increase of the first calibration voltage, the equivalent input offset voltage gradually decreases and becomes negative in the first calibration period, until the polarity of the comparator output changes, the calibration logic circuit controls SCN to be 0, and the connection with the first calibration voltage is disconnected, and the current voltage is kept by the capacitor.

[0077] The second calibration period: when the polarity change is detected in the first calibration period, the calibration logic circuit sets the switch SW2N on the side with the output high to low according to the comparison result, and connects to the delay adjustable circuit output end CLKD; the SF signal becomes high, and the delay adjustable circuit is connected to the output end of DAC2. When the global second calibration period signal ENF becomes high, the counter controls DAC2 to generate a second calibration voltage signal with a step increase, which is applied to the PM8 gate, thereby gradually increasing the delay of the rising edge of the CLKD signal relative to the CLK signal. With the calibration, the equivalent input offset voltage gradually decreases until the polarity of the comparator output signal changes, and the SF signal becomes low, and the second calibration voltage is saved in the capacitor C F . At the same time, the OC signal becomes low, and the differential input end is disconnected from the common-mode voltage V CM .

[0078] The calibration end stage: the global calibration enable signal EN and the global second calibration period signal ENF become low, and the calibration ends. The first and second calibration voltages are respectively kept in the corresponding capacitors, and the differential input ends are respectively connected to the input signal, and the normal comparison operation can be performed. Because of the existence of the leakage current in the circuit, the calibration voltage saved in the capacitor will decrease with time, thereby affecting the calibration accuracy, and therefore, the calibration needs to be performed regularly, and the calibration period interval is affected by the capacitor size and the circuit leakage.

[0079] After Monte-carlo simulation verification, the comparator offset voltage is reduced from 5.89 mV (as shown in Figure 7 ) to 0.28 mV (as shown in Figure 8). Compared with literature 1, 2, the offset voltage is much lower than 1.29mV of literature 1 (Okazawa T, Akita I, Ishida M. A digitally calibrated dynamic comparator using time-domain offset detection [J]. Analog Integrated Circuits & Signal Processing, 2014, 81(03): 561-570.) and 0.53mV of literature 2 (Chi-Hang Chan, Yan Zhu, U-Fat Chio, et al. A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS [C] / / Solid State Circuits Conference. Jeju, Korea. 2011: 233-236.). At the same time, because of the global shared calibration voltage generation circuit, the area overhead of high-precision DAC is very small. After layout design, the area of comparator and calibration circuit is 697μm 2 , much smaller than 46800μm 2 of literature 1 and 1089μm 2 of literature 2.

[0080] Example Four

[0081] The embodiment provides a global offset calibration method for an array-level dynamic comparator, which is realized by using the global offset calibration circuit for the array-level dynamic comparator provided in the first or third embodiment, and comprises the following steps.

[0082] Step 1: a calibration voltage signal with step change is generated by the calibration voltage generation circuit and is output to the calibration logic circuit, the calibration and storage circuit of all comparators.

[0083] Step 2: at the beginning of the calibration period, the comparator outputs a first set of comparison results according to the clock signal; the calibration logic circuit judges the calibration side according to the comparison results and outputs a control signal to connect the calibration and storage circuit to the calibration voltage generation circuit.

[0084] Step 3: the calibration voltage changes step by step until the polarity of the comparator output is reversed; the calibration logic circuit detects the polarity reversal and outputs a control signal to float the storage circuit, and the calibration voltage is kept in the storage circuit; and the calibration period of the comparator is ended.

[0085] Step four: the calibration voltage continues to change in steps until the output voltage reaches full scale, at which time the calibration voltage generation circuit stops changing, all comparators in the array should end calibration, the calibration voltage of each comparator is maintained, and the comparator offset calibration ends.

[0086] Part of the steps in the embodiments of the present application can be implemented by software, and the corresponding software program can be stored in a readable storage medium, such as an optical disc or a hard disk.

[0087] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A global mismatch calibration circuit for an array stage dynamic comparator, the circuit comprising: The global offset calibration circuit comprises a calibration voltage generation circuit, a calibration logic circuit and a calibration and storage circuit; The calibration voltage generation circuit is configured to generate a calibration voltage for all array calibration circuits; The calibration logic circuit is configured to generate a calibration signal according to the output of the comparator to control the global offset calibration circuit to implement reset, start calibration and end calibration operations; The calibration and storage circuit is configured to offset the influence of the offset by changing a calibration parameter during the calibration process, sample the calibration voltage and store it in a corresponding energy storage element or energy storage module, and maintain the calibration voltage at the end of the calibration to eliminate the influence of the offset during normal operation of the subsequent comparator; The calibration parameter comprises a voltage, a current and a delay parameter; The calibration voltage generation circuit comprises an N-bit counter and an N-bit digital-to-analog converter; The counter is triggered by a clock signal to output an increment operation in each clock cycle; the output of the counter is used as an input signal of the digital-to-analog converter, and a stepped voltage signal output by the digital-to-analog converter is used as a calibration voltage signal; The calibration and storage circuit comprises a current compensation and storage circuit and a delay adjustable and storage circuit; The current compensation and storage circuit comprises an auxiliary discharge NMOS tube, a first storage capacitor and a first gating switch; the first gating switch connects the gate of the auxiliary discharge NMOS tube and the upper plate of the first storage capacitor to a low voltage GND or a first calibration voltage signal VOC1 according to a control signal of the calibration logic circuit; the auxiliary discharge NMOS tube changes the passing current I according to the first calibration voltage signal VOC1 applied to the gate, so as to offset the influence of the offset D ; and the first storage capacitor is responsible for storing and maintaining the calibration voltage; The delay adjustable circuit and storage circuit comprises PMOS tubes PM7 and PM8, NMOS tubes NM9 and NM10, a second storage capacitor C F and a second gating switch; The second gate switch connects the gate of PMOS PM7, the upper plate of the second storage capacitor C F to low level GND or the second calibration voltage signal VOC2; PMOS PM8 and NM9 form an inverter, the drain of NMOS NM10 is connected to the source of NMOS NM9, and the source is connected to GND; PMOS PM7 is a delay MOS, the source is connected to VDD, the drain is connected to the source of PMOS PM8, and PMOS PM7 changes the rising edge delay between CLK_N and CLKD according to the second calibration voltage signal VOC2 applied to the gate; the second storage capacitor C F is responsible for storing and maintaining the calibration voltage.

2. The global mismatch calibration circuit for array-level dynamic comparators of claim 1, wherein, The calibration logic circuit comprises a calibration state conversion logic circuit and a calibration switch conversion logic circuit; The calibration state conversion logic circuit comprises flip-flops DFF1-DFF4, OR gates OR1-OR2, an inverter INV1 and an AND gate AND1; a data input end D of the flip-flops DFF1 and DFF3 is connected to GND, and a clock input end CLK is connected to the output COMP_P of the comparator; a data input end D of the flip-flops DFF2 and DFF4 is connected to GND, and a clock input end CLK is connected to the output COMP_N of the comparator; a set signal input end of the flip-flops DFF1 and DFF2 is connected to a calibration reset signal PRE; The outputs of the flip-flops DFF1 and DFF2 generate a local first calibration period signal ZN1 through the OR gate OR1, generate a local second calibration period signal ZN2 through the inverter INV1, and the local second calibration period signal ZN2 is used as a set signal of the flip-flops DFF3 and DFF4; the outputs of the flip-flops DFF3 and DFF4 generate a local second calibration period enable signal EN2 through the OR gate OR2; and the local second calibration period enable signal EN2 and a global calibration enable signal EN generate an input shorting switch signal OC through the AND gate AND1. The calibration switch conversion logic circuit comprises flip-flops DFF5-DFF11 and AND gates AND2-AND3; wherein the local first calibration period signal ZN1 and the calibration reset signal PRE are connected to the reset signal input terminals of flip-flops DFF5 and DFF6 through the AND gate AND2; the data input terminals D of flip-flops DFF5 and DFF6 are connected to the power supply VDD; the clock input terminal CLK of flip-flop DFF5 is connected to the comparator output COMP_N, and the clock input terminal CLK of flip-flop DFF6 is connected to the comparator output COMP_P; the positive output terminal Q of flip-flop DFF5 serves as the P-side switch signal SCP of the first calibration period and is connected to the clock input terminal of flip-flop DFF7; the negative output terminal of flip-flop DFF5 is connected to the clock input terminal of flip-flop DFF8; the positive output terminal Q of flip-flop DFF6 serves as the N-side switch signal SCN of the first calibration period and is connected to the clock input terminal of flip-flop DFF9; the negative output terminal of flip-flop DFF6 is connected to the clock input terminal of flip-flop DFF10; the data input terminals D of flip-flops DFF7 and DFF9 are connected to GND, and the set signals are connected to the calibration reset signal PRE; the data input terminals D of flip-flops DFF8 and DFF10 are connected to the outputs COMP_N and COMP_P of the comparator respectively, and the set signals are connected to the local second calibration period signal ZN2; the output of flip-flop DFF7 serves as the P-side switch signal SCP_GND of the first calibration period, the output of flip-flop DFF8 serves as the N-side switch signal SFN of the second calibration period, the output of flip-flop DFF9 serves as the N-side switch signal SCN_GND of the first calibration period, and the output of flip-flop DFF10 serves as the P-side switch signal SFP of the second calibration period; the local second calibration period signal ZN2, the local second calibration period enable signal EN2 and the global second calibration period signal ENF generate the local second calibration period switch signal SF through the AND gate AND3, and the local second calibration period switch signal SF serves as the clock signal of flip-flop DFF11; the data input terminal of flip-flop DFF11 is connected to GND, the set signal is connected to the calibration reset signal PRE, and the output signal serves as the local second calibration period switch signal SF_GND.

3. The global offset calibration circuit for array-level dynamic comparators of claim 1, wherein, The calibration and storage circuit comprises a calibration module and a storage module. The storage module is responsible for storing the calibration voltage signal, maintaining the voltage signal and connecting the voltage signal to the calibration module; the calibration module changes the calibration parameter according to the voltage signal of the storage module to offset the influence of the offset.

4. The global offset calibration circuit for array-level dynamic comparators of claim 1, wherein, The energy storage element comprises a capacitor.

5. A memory computing integrated chip, comprising: The in-memory computing chip comprises the global offset calibration circuit of the array-level dynamic comparator according to any one of claims 1-4.

6. An image sensor, characterized by, The image sensor comprises the global offset calibration circuit of the array-level dynamic comparator according to any one of claims 1-4.

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