An AD chip synchronization correction method and device based on FPGA

Abstract

In an embodiment of the present invention, a method and device for synchronous calibration of an AD chip based on an FPGA are provided. In this method, after the FPGA obtains the synchronization matrix corresponding to the AD chip to be synchronously calibrated, it performs an increasing delay training on the test code of the AD chip to obtain the corresponding training matrix. By determining whether the number of different bits between the synchronization matrix and the training matrix exceeds a set value, it is determined whether to send a SYNC signal to the AD chip. If it does not exceed the set value, the synchronous calibration is completed. Therefore, in the present invention, by pre-generating the synchronization matrix, after each power-on, it only takes dozens of microseconds for the increasing delay training to traverse all delays. Thus, even if the SYNC signal is sent multiple times to achieve synchronization between AD chips, the time spent will still not exceed 1 second. At the same time, the implementation of the above functions in the present invention does not occupy a high amount of logical resources of the FPGA and can support the expansion of more AD chips.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and particularly relates to a method and device for synchronously correcting an AD chip based on an FPGA. Background Art

[0002] The multi-AD chip synchronization technology is widely used in fields such as modulation and demodulation in communication, quantum measurement and control, and radar. However, with the development of technology, the rates of AD / DA are getting higher and higher, and the number of channels to be synchronized is also increasing. For example, in the field of quantum measurement and control, the number of channels for synchronous acquisition and transmission increases with the increase in the number of quantum bits. These technological changes have brought new difficulties to the stable synchronization technology of AD / DA.

[0003] Chinese invention patent ZL201810522695.8 discloses a self-correction method for multi-device data synchronization. In this method, under the ADC test mode, the delay of the BUFR reset signal is adjusted inside the FPGA, and the consistency of the multiple paths of data output by the multi-core ADC is judged. The statistical analysis of the results obtains an optimal delay setting value, thereby ensuring the synchronization between the multi-core data of the ADC. On this basis, the delay of the ADC reset signal is continuously adjusted, and the relationship between the ADC reset signal and the sampling clock SCLK is judged by the change of the optimal delay value of the BUFR synchronous reset signal, and finally the optimal delay value of the ADC reset signal is obtained to ensure the stability of the ADC reset. Finally, by judging the sampled data of each ADC in the test mode, the value of the ADC synchronization register is adjusted to ensure the synchronization between multiple ADCs, thereby realizing the stable stitching of data between multiple ADCs and improving the sampling rate of the acquisition system. However, since the above solution corrects the SYNC and BUFR reset signals of the ADC every time it is powered on to achieve stable synchronization, when the number of ADCs increases, the correction time will increase exponentially, and it will also occupy more logic resources of the FPGA.

[0004] Therefore, it is necessary to design a synchronization correction scheme for multi-AD chips with less correction time and less occupation of FPGA logic resources. Summary of the Invention

[0005] In view of the above-mentioned deficiencies of the prior art, the purpose of the present invention is to provide a method for synchronously correcting an AD chip based on an FPGA, which not only has low occupation of logic resources, but also only takes dozens of microseconds to traverse all delays. Thus, even if the SYNC signal is sent multiple times to achieve synchronization between AD chips, the time spent will still not exceed 1 second.

[0006] In the first aspect of the present invention, a method for synchronously correcting an AD chip based on an FPGA is provided, which includes:

[0007] S1: Enable the FPGA to obtain the synchronization matrix corresponding to the AD chip to be synchronously corrected;

[0008] S2: Configure the AD chip to be synchronously corrected into the test code mode and continuously send the test code to the FPGA;

[0009] S3: The FPGA performs incremental delay training on the test code continuously sent by the AD chip and reads the test code in each delay state with the data clock of the reference chip corresponding to the AD chip; wherein, the maximum number of incremental times of the incremental delay training is determined by the minimum delay step and the maximum delay provided by the FPGA;

[0010] S4: The FPGA detects whether the test code in each delay state it reads is the correct test codeword, and generates a training matrix corresponding to the AD chip to be synchronously corrected according to the detection result; wherein, the synchronization matrix is the training matrix generated when the AD chip and its reference chip are in the synchronous state;

[0011] S5: The FPGA detects the number of different bits between the training matrix of the AD chip to be synchronously corrected and the synchronization matrix, and determines whether the number of different bits exceeds the set value; wherein, if the number of different bits exceeds the set value, the FPGA sends a SYNC signal to the AD chip and re-enters step S2; otherwise, the synchronous correction is completed.

[0012] In some possible embodiments, both the synchronization matrix and the training matrix are 1×N one-dimensional matrices; wherein, if the test code in the corresponding delay state read is the correct test codeword, the value at the corresponding position of the one-dimensional matrix is set to 1, otherwise it is set to 0.

[0013] In some possible embodiments, the method for detecting the number of different bits between the training matrix of the AD chip to be synchronously corrected and the synchronization matrix is: performing an exclusive OR logic operation on the training matrix and the synchronization matrix to obtain a difference matrix; counting the number of 1s in the difference matrix is the number of different bits.

[0014] In some possible embodiments, the reference chip of each AD chip is set to the same AD chip.

[0015] In the second aspect of the present invention, there is provided an AD chip synchronous correction device based on an FPGA, which includes:

[0016] An FPGA, which is configured to include: a plurality of IDELAY units, a plurality of ISERDES units, a PLL unit, an SPI unit, and a SYNC signal generation unit; wherein,

[0017] Among them, each of the IDELAY units is respectively connected to one of the ISERDES units to form a transmission channel for transmitting test codes of the AD chip to be synchronously corrected; the PLL unit is used to distribute the data clock of the reference chip received by it to the ISERDES units in different transmission channels; the SPI unit is used to configure the AD chip to be synchronously corrected into a test code mode;

[0018] The SYNC signal generating unit is used to, after obtaining the synchronization matrix corresponding to the AD chip to be synchronously corrected, control the IDELAY unit to perform incremental delay training on the test codes continuously sent by the AD chip to be synchronously corrected, and control the ISERDES unit to read the test codes in each delay state with the data clock of the reference chip corresponding to the AD chip; and, detect whether the test codes in each delay state read by it are correct test code words, and generate a training matrix corresponding to the AD chip to be synchronously corrected according to the detection result; and, detect the number of different bits between the training matrix of the AD chip to be synchronously corrected and the synchronization matrix, and determine whether the number of different bits exceeds a set value; wherein, if the number of different bits exceeds the set value, the FPGA sends a SYNC signal to the AD chip, otherwise, the synchronous correction is completed;

[0019] Among them, the synchronization matrix is a training matrix generated when the AD chip and its reference chip are in a synchronous state, and the maximum number of incremental times of the incremental delay training is determined by the minimum delay step and the maximum delay provided by the FPGA.

[0020] In some possible embodiments, the SYNC signal generating unit is configured to perform an exclusive OR logical operation on the training matrix and the synchronization matrix to obtain a difference matrix, and count the number of 1s in the difference matrix to obtain the number of different bits.

[0021] Compared with the prior art, the beneficial effects of the present invention are:

[0022] In the AD chip synchronous correction method based on FPGA of the present invention, after the FPGA obtains the synchronization matrix corresponding to the AD chip to be synchronously corrected, it performs incremental delay training on the test codes of the AD chip to obtain a corresponding training matrix, and determines whether it is necessary to send a SYNC signal to the AD chip by judging whether the number of different bits between the synchronization matrix and the training matrix exceeds a set value. If it does not exceed the set value, the synchronous correction is completed. Therefore, in the present invention, by pre-generating the synchronization matrix, after each power-on, it only takes dozens of microseconds for the incremental delay training to traverse all delays. Thus, even if the SYNC signal is sent multiple times to achieve the synchronization between AD chips, the time spent will still not exceed 1 second; at the same time, the present invention does not occupy a high logical resource of the FPGA to implement the above functions and can support the expansion of more AD chips. Description of the Drawings

[0023] Figure 1 It is a schematic flowchart of the AD chip synchronization correction method based on FPGA provided in the embodiment of the present invention;

[0024] Figure 2 It is a schematic structural diagram of the AD chip synchronization correction device based on FPGA provided in the embodiment of the present invention;

[0025] Figure 3 It is a timing comparison diagram of two AD chips in the synchronous and asynchronous cases. Specific Embodiments

[0026] The present invention will be further described in detail below in conjunction with the drawings and specific embodiments. However, this should not be construed as limiting the scope of the above-mentioned subject matter of the present invention to the following embodiments. Any technology implemented based on the content of the present invention belongs to the scope of the present invention.

[0027] In an embodiment of the present invention, there is provided a method for synchronizing and correcting an AD chip based on FPGA as shown in Figure 1 The method includes:

[0028] S1: Enable the FPGA to obtain the synchronization matrix corresponding to the AD chip to be synchronously corrected;

[0029] S2: Configure the AD chip to be synchronously corrected into the test code mode and continuously send the test code to the FPGA;

[0030] S3: The FPGA performs incremental delay training on the test code continuously sent by the AD chip and reads the test code in each delay state with the data clock of the reference chip corresponding to the AD chip; wherein, the maximum number of incremental times of the incremental delay training is determined by the minimum delay step and the maximum delay provided by the FPGA;

[0031] Specifically, configure Delay_Num as the count value of the number of incremental times of the incremental delay training. The initial value of Delay_Num is 0. After the FPGA maintains the current delay state for the set time, it increments a delay step on the current delay, and at this time Delay_Num + 1; assume the delay step is Δt, then the delay time for the FPGA to delay the test code continuously sent by the AD chip can be expressed as: T = Delay_Num * Δt; at the same time, the maximum number of incremental times of the incremental delay training is determined by the minimum delay step and the maximum delay provided by the FPGA. In other words, if the maximum delay provided by the FPGA is selected as the maximum delay of the incremental delay training and the minimum step of the internal delay of the FPGA is selected as the delay step of the incremental delay training, the maximum number of incremental times that the FPGA can perform the incremental delay training can be obtained.

[0032] S4: The FPGA detects whether the test code in each delay state it reads is a correct test codeword, and generates a training matrix corresponding to the AD chip to be synchronously corrected according to the detection result; wherein, the synchronization matrix is a training matrix generated when the AD chip and its reference chip are in a synchronous state;

[0033] Specifically, both the synchronization matrix and the training matrix are 1×N one-dimensional matrices; wherein, if the test code in the corresponding delay state read is a correct test codeword, the value at the corresponding position of the one-dimensional matrix is set to 1, otherwise it is set to 0. At the same time, if Delay_Num reaches the maximum value, a training matrix corresponding to the AD chip to be synchronously corrected is generated.

[0034] S5: The FPGA detects the number of different bits Diff_Num between the training matrix of the AD chip to be synchronously corrected and the synchronization matrix, and determines whether the number of different bits exceeds a set value; wherein, if the number of different bits exceeds the set value M, the FPGA sends a SYNC signal to the AD chip and re-enters step S2; otherwise, the synchronous correction is completed.

[0035] In some possible embodiments, the method for detecting the number of different bits between the training matrix of the AD chip to be synchronously corrected and the synchronization matrix is: performing an exclusive OR logic operation on the training matrix and the synchronization matrix to obtain a difference matrix; counting the number of 1s in the difference matrix is the number of different bits.

[0036] In some possible embodiments, in order to reduce the wiring complexity inside the FPGA and the occupation of hardware resources, the reference chip of each AD chip is set to the same AD chip.

[0037] In an embodiment of the present invention, there is provided an Figure 3 AD chip synchronous correction device based on FPGA as shown in

[0038] FPGA, which is configured to include: 2 IDELAY units, 2 ISERDES units, a PLL unit, an SPI unit, and a SYNC signal generation unit; wherein,

[0039] wherein, each IDELAY unit is respectively connected to an ISERDES unit to form a transmission channel for transmitting test codes for the AD chip to be synchronously corrected; the PLL unit is used to distribute the data clock of the reference chip it receives to the ISERDES units in different transmission channels; the SPI unit is used to configure the AD chip to be synchronously corrected into a test code mode;

[0040] The SYNC signal generation unit is used to, after obtaining the synchronization matrix corresponding to the AD chip to be synchronously corrected, configure the AD chip to be synchronously corrected into the test code mode through the SPI unit, control the IDELAY unit to perform incremental delay training on the test codes continuously sent by the AD chip to be synchronously corrected, and then control the ISERDES unit to read the test codes in each delay state with the data clock of the reference chip corresponding to the AD chip; and, detect whether the test codes read in each delay state are correct test code words, and generate a training matrix corresponding to the AD chip to be synchronously corrected according to the detection result; and, detect the number of different bits between the training matrix of the AD chip to be synchronously corrected and the synchronization matrix, and determine whether the number of different bits exceeds a set value; wherein, if the number of different bits exceeds the set value, the FPGA sends a SYNC signal to the AD chip, otherwise, the synchronous correction is completed;

[0041] Wherein, the synchronization matrix is the training matrix generated when the AD chip and its reference chip are in a synchronous state, and the maximum number of incremental times of the incremental delay training is determined by the minimum delay step and the maximum delay provided by the FPGA.

[0042] In some possible embodiments, the SYNC signal generation unit is configured to perform an exclusive OR logic operation on the training matrix and the synchronization matrix to obtain a difference matrix, and count the number of 1s in the difference matrix to obtain the number of different bits.

[0043] Specifically, the number of test code transmission channels provided by the FPGA depends on its internal hardware resources. The richer the hardware resources of the FPGA, the more ADCs can be supported for expansion. Taking the Xilinx 7 series FPGA as an example, since the internal hardware resources of the Xilinx 7 series FPGA include: a PLL unit, a dedicated delay unit DELAY2, and an ISERDES unit; among them, the PLL unit is one of the most basic IP cores in the FPGA, the delay unit DELAY2 can provide 31 levels of delay steps, and the function of the ISERDES unit is to realize the serial-to-parallel conversion of high-speed source synchronous input data; moreover, the Xilinx 7 series FPGA also supports the SPI interface protocol, and the control of the test code mode of the AD chip can be realized through simple configuration.

[0044] To further illustrate the synchronous correction principle of the AD chip, in combination with Figure 2 the connection structure of two ADCs of a single FPGA shown in Figure 3The timing comparison between the two cases of synchronous and asynchronous operation of the two ADCs shown. Taking the AD190 chip as an example for the ADC, the synchronization principle of the AD190 is to align the internal sampling clocks (InternalSampling) of multiple AD190s through the SYNC pulse to achieve synchronization. Moreover, the data clock (XDR) and data (X0…X9) of a single-chip ADC always maintain a fixed phase relationship with the internal sampling clock. Since the internal sampling clock is obtained by dividing the device clock (CLK) by 2, the SYNC pulse reset will cause the internal sampling clocks of multiple chips to output two phases. Case 1, that is, CASE1: The SYNC signal aligns the internal sampling clocks of the two ADCs. At this time, the internal sampling clocks of the two ADs maintain the same phase. Even if the moments of sampling the SYNC by the device clock are different, since the internal sampling clocks have the same phase, the moments of the sampling signals of the two ADs remain the same. Due to the different moments of collecting the SYNC, the times of outputting valid samples are inconsistent. And Case 2, that is, CASE2: The SYNC signal does not align the internal sampling clocks of the two ADCs. Due to the SYNC signal, the internal sampling clocks of the two ADs differ by one device clock, that is, 400 ps. The phases of the sampling signals of the two AD chips always differ by 400 ps, corresponding to Figure 3 points N and K in

[0045] and the two AD chips do not maintain synchronization. Under ideal conditions, regardless of whether the two AD chips are synchronized or not, the data clock (XDR) of the reference chip is aligned with the center of its own data signal (X0-X9). When another AD chip is synchronized with the reference chip, the data clock of the reference chip is aligned with the center position of the data of this AD chip. When another AD chip is not synchronized with the reference chip, the data clock of the reference chip is aligned with the data edge of this AD chip. Therefore, in the present invention, after configuring the AD chip to be synchronously corrected into the test code mode, the data clock of the reference chip is used to read the transmitted data of this AD chip. If it is synchronized, the test code can be received accurately without error, otherwise incorrect or empty data will be received.

[0046] The AD chip synchronization correction method based on FPGA of the present invention is applicable to the situation of synchronously correcting the AD chip after each power-on. By pre-generating a synchronization matrix, it only takes dozens of microseconds to traverse all delays in the incremental delay test after each power-on. Thus, even if the SYNC signal is sent multiple times to achieve the synchronization between AD chips, the time spent will still not exceed 1 second. Moreover, the implementation of the above functions by the present invention does not occupy much logical resources of the FPGA and can support the expansion of more AD chips.

[0047] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. An AD chip synchronization correction method based on FPGA, characterized in that Including: S1: Enable the FPGA to obtain the synchronization matrix corresponding to the AD chip to be synchronously corrected; S2: Configure the AD chip to be synchronously corrected into the test code mode and continuously send the test code to the FPGA; S3: The FPGA performs incremental delay training on the test code continuously sent by the AD chip and reads the test code in each delay state with the data clock of the reference chip corresponding to the AD chip; wherein, the maximum increment times N of the incremental delay training are determined by the minimum delay step and the maximum delay provided by the FPGA; S4: The FPGA detects whether the test code in each delay state it reads is a correct test codeword, and generates a training matrix corresponding to the AD chip to be synchronously corrected according to the detection result; wherein, the synchronization matrix is the training matrix generated when the AD chip and its reference chip are in the synchronous state; S5: The FPGA detects the number of different bits between the training matrix of the AD chip to be synchronously corrected and the synchronization matrix, and determines whether the number of different bits exceeds the set value; wherein, if the number of different bits exceeds the set value, the FPGA sends a SYNC signal to the AD chip and re-enters step S2; otherwise, the synchronous correction is completed.

2. The AD chip synchronization correction method based on FPGA according to claim 1, characterized in that, Both the synchronization matrix and the training matrix are 1×N one-dimensional matrices; wherein, if the test code in the corresponding delay state read is a correct test codeword, the value of the corresponding position of the one-dimensional matrix is set to 1, otherwise it is set to 0.

3. The method for synchronously correcting an AD chip based on FPGA according to claim 2, wherein, The method for detecting the number of different bits between the training matrix of the AD chip to be synchronously corrected and the synchronization matrix is: perform an exclusive OR logic operation on the training matrix and the synchronization matrix to obtain a difference matrix; count the number of 1s in the difference matrix, which is the number of different bits.

4. The FPGA-based AD chip synchronization correction method according to any one of claims 1 to 3, characterized in that Set the reference chip of each AD chip to the same AD chip.

5. An AD chip synchronization correction device based on FPGA, characterized in that, Including: FPGA, which is configured to include: a plurality of IDELAY units, a plurality of ISERDES units, a PLL unit, an SPI unit, and a SYNC signal generation unit; Wherein, each of the IDELAY units is respectively connected to one of the ISERDES units to form a transmission channel for transmitting the test code for the AD chip to be synchronously corrected; the PLL unit is used to distribute the data clock of the reference chip it receives to the ISERDES units in different transmission channels; the SPI unit is used to configure the AD chip to be synchronously corrected into the test code mode; The SYNC signal generation unit is configured to, after obtaining the synchronization matrix corresponding to the AD chip to be synchronously corrected, control the IDELAY unit to perform incremental delay training on the test codes continuously transmitted by the AD chip to be synchronously corrected, and control the ISERDES unit to read the test codes in each delay state using the data clock of the reference chip corresponding to the AD chip; and, detect whether the test codes read in each delay state are correct test codewords, and generate a training matrix corresponding to the AD chip to be synchronously corrected according to the detection result; and, detect the number of different bits between the training matrix of the AD chip to be synchronously corrected and the synchronization matrix, and determine whether the number of different bits exceeds a set value; wherein, if the number of different bits exceeds the set value, the FPGA sends a SYNC signal to the AD chip, otherwise, the synchronous correction is completed; Wherein, the synchronization matrix is the training matrix generated when the AD chip and its reference chip are in a synchronous state, and the maximum number of increments for the incremental delay training is determined by the minimum delay step and the maximum delay provided by the FPGA.

6. The FPGA-based AD chip synchronization correction device according to claim 5, wherein, The SYNC signal generation unit is configured to perform an exclusive OR logic operation on the training matrix and the synchronization matrix to obtain a difference matrix, and count the number of 1s in the difference matrix to obtain the number of different bits.

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