Digital-to-analog converter circuits and current-guided digital-to-analog converters

Abstract

The digital-to-analog converter circuit includes an input circuit and a switched capacitor circuit. The input circuit selectively draws a first current from a first node or a second current from a second node based on a first bit and a second bit, wherein the first and second bits have opposite logic values. The switched capacitor circuit selectively compensates for the capacitance value of one of the first and second nodes based on the first and second bits.

Description

Technical Field

[0001] This invention relates to digital-to-analog converter circuits, and more particularly to digital-to-analog converter circuits that improve linearity by compensating for capacitor values ​​and current-guided digital-to-analog converters. Background Technology

[0002] For current-steering digital-to-analog converters (DADCs) in high-speed applications, the switching impedance determines the linearity of the DADC. In existing technologies, the switching impedance of the DADC is increased by directly increasing the equivalent impedance of the transistor. However, in practical applications, the switching impedance is affected by parasitic elements in the transistor or circuitry, resulting in poor matching of the transistor's equivalent impedance at high frequencies, thus reducing the linearity of the current-steering DADC. Summary of the Invention

[0003] In some embodiments, the digital-to-analog converter circuit includes an input circuit, an impedance adjustment circuit, and a switched capacitor circuit. The input circuit is configured to selectively draw a first current from a first node or a second current from a second node based on a first bit and a second bit, wherein the first bit and the second bit have opposite logic values. The switched capacitor circuit is configured to selectively compensate the capacitance value of one of the first node and the second node based on the first bit and the second bit.

[0004] In some embodiments, the current-directed digital-to-analog converter includes a load circuit and a plurality of digital-to-analog converter circuits. The load circuit is used to convert a first current into a first output signal and a second current into a second output signal. The plurality of digital-to-analog converter circuits are used to draw the first current and the second current according to a plurality of bits. One of these digital-to-analog converter circuits includes an input circuit and a switched capacitor circuit. The input circuit is used to draw a signal component of the first current from a first node or a signal component of the second current from a second node according to a first bit and a second bit, wherein the first bit is the most significant bit among the bits, and the first bit and the second bit have opposite logic values. The switched capacitor circuit is used to selectively compensate the capacitance value of one of the first node and the second node according to the first bit and the second bit.

[0005] The features, implementation, and effects of the present invention are described in detail below with reference to the accompanying drawings, using preferred embodiments. Attached Figure Description

[0006] Figure 1A A schematic diagram of a digital-to-analog converter circuit according to some embodiments of the present invention;

[0007] Figure 1B Drawings for some embodiments of the present invention Figure 1A A schematic diagram of the input circuit, impedance adjustment circuit, and related parasitic capacitances;

[0008] Figure 2 A schematic diagram of a digital-to-analog converter circuit according to some embodiments of the present invention;

[0009] Figure 3A A schematic diagram of a current-guided digital-to-analog converter according to some embodiments of the present invention;

[0010] Figure 3B A schematic diagram of a current-guided digital-to-analog converter according to some embodiments of the present invention;

[0011] Figure 4A A schematic diagram of a current-guided digital-to-analog converter according to some embodiments of the present invention; and

[0012] Figure 4B This is a schematic diagram of a current-guided digital-to-analog converter according to some embodiments of the present invention. Detailed Implementation

[0013] All terms used herein have their ordinary meanings. The definitions of the terms above in commonly used dictionaries, and any examples of the use of any term discussed herein within the scope of this invention, are merely illustrative and should not limit the scope or meaning of the invention. Similarly, the invention is not limited to the various embodiments shown in this specification.

[0014] As used herein, “coupled” or “connected” can refer to two or more components making direct physical or electrical contact with each other, or indirectly making direct physical or electrical contact with each other, or to two or more components operating or acting on each other. As used herein, the term “circuit” can be a device consisting of at least one transistor and / or at least one active or passive component connected in a certain manner to process signals.

[0015] As used herein, the term "and / or" includes any combination of one or more of the listed related items. The terms first, second, third, etc., are used herein to describe and identify individual elements. Therefore, a first element herein may also be referred to as a second element without departing from the spirit of the invention. For ease of understanding, similar elements in the various figures will be designated with the same reference numerals.

[0016] Figure 1A This is a schematic diagram of a digital-to-analog converter circuit 100 according to some embodiments of the present invention. In some embodiments, the digital-to-analog converter circuit 100 may be a digital-to-analog converter (e.g., a... Figure 3A The digital-to-analog converter 300A is used to convert a set of corresponding bits of circuit cells.

[0017] The digital-to-analog converter circuit 100 includes an input circuit 120, an impedance adjustment circuit 140, and a switched capacitor circuit 160. The input circuit 120 selectively draws current I1 from node N1 or current I2 from node N2 based on bit D and bit DB. Bit D and bit DB have opposite logic values. For example, if bit D is logic 1, then bit DB is logic 0. Or, if bit D is logic 0, then bit DB is logic 1.

[0018] The input circuit 120 includes multiple transistors M0 to M2. The first terminal (e.g., drain) of transistor M1 is coupled to node N1, and the second terminal (e.g., source) of transistor M1 is coupled to the first terminal of transistor M0. The control terminal (e.g., gate) of transistor M1 receives bit D. The first terminal of transistor M2 is coupled to node N2, and the second terminal of transistor M2 is coupled to the first terminal of transistor M0. The control terminal of transistor M2 receives bit DB. The second terminal of transistor M0 is coupled to ground, and the control terminal of transistor M0 receives voltage VB1.

[0019] In this example, transistor M0 can operate as a current source circuit, which is used to generate current based on voltage VB1 (e.g., for...). Figure 3A 2 shown n ×I or 2 0 ×I), to bias transistors M1 and M2. Transistors M1 and M2 are operable as a differential input pair. Transistor M1 is selectively turned on according to bit D, and transistor M2 is selectively turned on according to bit DB. When transistor M1 is on, transistor M2 is not on. Under this condition, transistor M1 can draw current I1 from node N1. Similarly, when transistor M2 is on, transistor M1 is not on. Under this condition, transistor M2 can draw current I2 from node N2.

[0020] Impedance adjustment circuit 140 is used to transfer current I1 from output terminal O+ to node N1, or current I2 from output terminal O- to node N2, and to increase the output impedance Z+ of output terminal O+ and the output impedance Z- of output terminal O-. Output impedances Z- and Z+ define the switching resistance of digital-to-analog converter circuit 100. Circuit analysis and simulation show that the larger this switching resistance, the smaller the harmonic distortion of digital-to-analog converter circuit 100, and therefore the better the linearity of digital-to-analog converter circuit 100. Circuit analysis and simulation show that to increase the aforementioned switching resistance, output impedances Z- and Z+ can be increased, or they can be matched (i.e., made the same). In some embodiments, impedance adjustment circuit 140 can be used to increase output impedances Z+ and Z-, and switching capacitor circuit 160 can be used to match output impedances Z+ and Z- as closely as possible.

[0021] In detail, the impedance adjustment circuit 140 includes transistors M3 and M4, current source circuit 141, and current source circuit 142. The first terminal of transistor M3 is coupled to the output terminal O+, the second terminal of transistor M3 is coupled to node N1, and the control terminal of transistor M3 receives voltage VB2. The first terminal of transistor M4 is coupled to the output terminal O-, the second terminal of transistor M4 is coupled to node N2, and the control terminal of transistor M4 receives voltage VB2. (The rest of the text is missing.) Figure 1A As shown, transistors M3 and M1 are cascode connected, and transistors M4 and M2 are also cascode connected. This improves both the output impedance Z+ and the output impedance Z-.

[0022] Current source circuit 141 is coupled to node N1 and provides current to bias transistor M3 to maintain the operating region of transistor M3. Similarly, current source circuit 142 is coupled to node N2 and provides current to bias transistor M4 to maintain the operating region of transistor M4. In some embodiments, to save power consumption, the current generated by each of current source circuits 141 and 142 may be less than the current generated by transistor M0, but the invention is not limited thereto. As previously described, when one of transistors M1 and M2 is turned on, the other of transistors M1 and M2 is not turned on. When transistor M1 is turned on and transistor M2 is not turned on, current source circuit 142 can continuously bias transistor M4 to keep transistor M4 operable in a preset operating region (e.g., saturation region). In this way, the output impedance Z- is ensured to be close to the output impedance Z+, thereby improving overall linearity. Similarly, when transistor M2 is turned on and transistor M1 is not turned on, the current source circuit 141 can continuously bias transistor M3 to keep transistor M3 operable in a preset operating region (e.g., the saturation region). In this way, it can be ensured that the output impedance Z+ is close to the output impedance Z-.

[0023] A switching capacitor circuit 160 is used to selectively compensate the capacitance values ​​of nodes N1 and N2 according to bit D and bit DB. Specifically, the switching capacitor circuit 160 can increase the capacitance value of node N1 according to bit DB and increase the capacitance value of node N2 according to bit D. In this example, the switching capacitor circuit 160 is used to selectively couple a capacitor (e.g., capacitor C1) to node N1 according to bit DB and selectively couple a capacitor (e.g., capacitor C2) to node N2 according to bit D. In detail, the switching capacitor circuit 160 includes capacitor C1, capacitor C2, switch SW1, and switch SW2. One end of capacitor C1 is coupled to node N1, and the other end of capacitor C1 is coupled to ground via switch SW1. Switch SW1 is selectively turned on according to bit DB. When switch SW1 is turned on, node N1 can be coupled to ground via capacitor C1. Similarly, one end of capacitor C2 is coupled to node N2, and the other end of capacitor C2 is coupled to ground via switch SW2. Switch SW2 is selectively turned on according to bit D. When switch SW2 is turned on, node N2 can be coupled to ground via capacitor C2.

[0024] With the above configuration, the switching capacitor circuit 160 can increase the capacitance value of node N1 when transistor M1 is off, and increase the capacitance value of node N2 when transistor M2 is off. For example, when transistor M1 is off according to bit D, switch SW1 can be turned on according to bit DB to couple node N1 to ground via capacitor C1. Thus, the capacitance value of node N1 can be increased. Similarly, when transistor M2 is off according to bit DB, switch SW2 can be turned on according to bit D to couple node N2 to ground via capacitor C2. Thus, the capacitance value of node N2 can be increased. This allows for a better match between the aforementioned output impedance Z+ and output impedance Z-, thereby improving linearity. The configuration of the switching capacitor circuit 160 will be explained by referring to... Figure 1B Further explanation.

[0025] Figure 1B Drawings for some embodiments of the present invention Figure 1A A schematic diagram of the input circuit 120, impedance adjustment circuit 140, and related parasitic capacitances is shown. For ease of explanation, Figure 1B The example is assumed to be 160 without the use of a switching capacitor circuit.

[0026] In practical applications, due to the parasitic capacitance of the transistor and the influence of the transistor's operating region, the output impedance Z+ and output impedance Z- may be mismatched, resulting in reduced linearity. For example, the capacitance of node N1 (hereinafter referred to as capacitance C) A The main component is the parasitic capacitance C of transistor M3. GS3 and the parasitic capacitance C of transistor M1 GD1 Decision (i.e., C) A =C GS3 +C GD1 The capacitance of node N2 (hereinafter referred to as capacitance C) B The main component is the parasitic capacitance C of transistor M4. GS4 And the parasitic capacitance C of transistor M2 GD2 Decision (i.e., C) B =C GS4 +C GD2 Referring to existing technologies and analyses of parasitic capacitance in transistors (e.g., metal-oxide-semiconductor field-effect transistors; MOSFETs), the parasitic capacitance between the gate and drain (e.g., parasitic capacitance C) can be determined. GD1 Or C GD2 The capacitance value is related to the operating region of the transistor. In this example, assuming transistor M1 is on and transistor M2 is off, transistor M1 operates in the saturation region (or linear region) and transistor M2 operates in the cutoff region. Therefore, the parasitic capacitance C... GD1 The capacitance value will be equal to (or greater than) the parasitic capacitance C. GD2 The capacitance value.

[0027] Similarly, referring to existing analyses of parasitic capacitance in transistors, the parasitic capacitance between the gate and source (e.g., parasitic capacitance C) can be determined. GS3 Or C GS4 The capacitance value of transistor M4 is related to the gate-source voltage. As mentioned earlier, the current generated by current source circuit 142 (or current source circuit 141) can be set to be less than the current generated by transistor M3. When transistor M2 is not conducting, the current flowing through transistor M4 (current provided only by current source circuit 142) will be less than the current flowing through transistor M3 (current provided by both current source circuit 141 and transistor M1). Under this condition, it can be deduced that the gate-source voltage of transistor M3 is greater than the gate-source voltage of transistor M4. Therefore, it can be concluded that the parasitic capacitance C... GS3 The capacitance value will be greater than the parasitic capacitance C. GS4 The capacitance value.

[0028] Therefore, under the conditions that transistor M1 is turned on, transistor M2 is not turned on, and the switching capacitor circuit 160 is not used, it can be deduced that the capacitance C A Higher than capacitance C B .like Figure 1B As shown, the output impedance Z+ includes the capacitor C. A And the output impedance Z- includes the capacitor C B And capacitor C A impedance and capacitance C B The impedance changes with frequency. In other words, the output impedance Z+ and output impedance Z- are frequency-dependent impedances. In this example, due to the capacitance C... A Greater than the capacitance C B ,when Figure 1B When the circuit operates at high frequencies, capacitor C A The impedance will be different from the capacitance C. B The impedance is different. As a result, the output impedance Z+ will be different from the output impedance Z-, which reduces the linearity.

[0029] To improve the above problems, Figure 1A The switching capacitor circuit 160 can provide capacitor C2 to node N2 when transistor M2 is off, thereby increasing the capacitance value of node N2 (i.e., increasing capacitance C). B (The capacitance value). Through the above operations, the capacitance C B The capacitance value can be corrected to be close to (or the same as) the capacitance C. A The capacitance value. Therefore, when Figure 1AWhen the digital-to-analog converter circuit 100 operates at high frequencies, the output impedance Z- should be matched as closely as possible to improve the linearity of the digital-to-analog converter circuit 100. Similarly, when transistor M1 is off, the switching capacitor circuit 160 can provide capacitor C1 to node N1 to increase the capacitance value of node N1 (i.e., increase capacitance C). A (capacitance value).

[0030] Figure 2 This is a schematic diagram of a digital-to-analog converter circuit 200 according to some embodiments of the present invention. Compared to Figure 1A ,exist Figure 2 In the example, the switching capacitor circuit 160 can couple capacitors (e.g., capacitor CC) from bit D to bit DB to one of the corresponding nodes N1 and N2.

[0031] In detail, the switching capacitor circuit 160 includes a capacitor CC, a switch SW21, and a switch SW22. One end of the capacitor CC is coupled to switches SW21 and SW22, and the other end of the capacitor CC is coupled to ground. Switch SW21 is used to selectively turn on according to bit DB to couple capacitor CC to node N1. Switch SW22 is used to selectively turn on according to bit D to couple capacitor CC to node N2.

[0032] The above Figure 1A and / or Figure 2 The configuration of the switching capacitor circuit 160 described herein is for illustrative purposes only and is not intended to limit the invention. Various configuration methods for compensating capacitance values ​​are within the scope of this invention.

[0033] Figure 3A This is a schematic diagram of a current-steering digital-to-analog converter 300A according to some embodiments of the present invention. In this example, the current-steering digital-to-analog converter 300A includes a load circuit 320 and a plurality of digital-to-analog converter circuits 340[0] to 340[n].

[0034] The load circuit 320 is coupled to the output terminals O+ and O-, and is used to convert the current IO+ into the output signal VO+, and the current IO- into the output signal VO-. For example, the load circuit 320 includes resistors R1 and R2. One end of resistor R1 receives the voltage VDD, and the other end of resistor R1 is used to generate the output signal VO-. One end of resistor R2 receives the voltage VDD, and the other end of resistor R2 is used to generate the output signal VO+.

[0035] Multiple digital-to-analog converter circuits 340[0] to 340[n] generate currents IO+ and IO- based on multiple bits D[0] to D[n] and multiple bits DB[0] to DB[n]. In this example, each of the multiple digital-to-analog converter circuits 340[0] to 340[n] can be generated by... Figure 1A The digital-to-analog converter circuit 100 is implemented. For ease of explanation, Figure 3A This only shows the corresponding setup of a portion of the circuits in the digital-to-analog converter circuit 100. For detailed setup methods and operations, please refer to [reference needed]. Figure 1A Therefore, I will not repeat the details.

[0036] Taking the digital-to-analog converter circuit 340[n] as an example, in the digital-to-analog converter circuit 340[n], transistor M1 receives bit D[n] and transistor M2 receives bit DB[n], where bit D[n] and bit DB[n] have opposite logic values. Transistor M1 is selectively turned on according to bit D[n] to generate a signal component of current IO+ (e.g., for...). Figure 1A The current I1), and transistor M2 is selectively turned on according to bit DB[n] to generate a signal component of current IO- (e.g., for the ...). Figure 1A The current I2). According to the binary weight corresponding to bit D[n] (i.e., the value n, where n can be an integer greater than or equal to 0), transistor M0 is used to provide current I2. n ×I (where I is the unit current). Correspondingly, in the digital-to-analog converter circuit 340[n], the capacitance value of each of capacitors C1 and C2 is 2. n ×C (C is the unit capacitance), switch SW1 is selectively turned on according to bit DB[n], and switch SW2 is selectively turned on according to bit D[n]. Similarly, in the digital-to-analog converter circuit 340[0], transistor M1 is selectively turned on according to bit D[0] to generate another signal component of current IO+ (e.g., for…). Figure 1A The current I1), and transistor M2 is selectively turned on according to bit DB[0] to generate another signal component of current IO- (e.g., for the ...). Figure 1A The current I2), where bit D[0] and bit DB[0] have opposite logic values. According to the binary weight corresponding to bit D[0], transistor M0 is used to provide current 2. 0 ×I. Correspondingly, in the digital-to-analog converter circuit 340[0], the capacitance value of each of capacitors C1 and C2 is 2. 0 ×C, switch SW1 is selectively turned on according to bit DB[0], and switch SW2 is selectively turned on according to bit D[0]. It should be understood that the current provided by transistor M0 and the capacitance value of capacitor C1 (and capacitor C2) are proportional to the weight corresponding to the received bit D[n].

[0037] Figure 3B This is a schematic diagram of a current-guided digital-to-analog converter 300B according to some embodiments of the present invention. Compared to Figure 3A In this example, at least one of the multiple digital-to-analog converter circuits 340[0] to 340[n] corresponding to a high-weight bit (e.g., the most significant bit D[n]) can be generated by... Figure 1A The digital-to-analog converter circuit 100 is implemented.

[0038] For example, the digital-to-analog converter circuit 340[n] used to process the most significant bit D[n] can be derived from... Figure 1A The digital-to-analog converter circuit 100 is implemented, and the detailed configuration is similar to... Figure 1A and Figure 3A Therefore, it will not be repeated here. The remaining circuits in the multiple digital-to-analog converter circuits 340[0] to 340[n] may not use the switching capacitor circuit 160. For example, the digital-to-analog converter circuit 340[0] can operate without the switching capacitor circuit 160. By improving the switching impedance of the digital-to-analog converter circuit 340[n] that processes the high-weight bits, the linearity of the current-guided digital-to-analog converter 300B can also be effectively improved.

[0039] Figure 4A This is a schematic diagram of a current-driven digital-to-analog converter 400A according to some embodiments of the present invention. In this example, the current-driven digital-to-analog converter 400A includes a load circuit 320 and a plurality of digital-to-analog converter circuits 340[0] to 340[n].

[0040] Compared to Figure 3A In this example, each of the multiple digital-to-analog converter circuits 340[0] to 340[n] can be generated by... Figure 2 The digital-to-analog converter circuit 200 is implemented. For ease of explanation, Figure 4A This only shows the corresponding setup of a portion of the circuits in the digital-to-analog converter circuit 200. For detailed setup methods and operations, please refer to [reference needed]. Figure 2 Therefore, I will not repeat the details.

[0041] Taking the digital-to-analog converter circuit 340[n] as an example, in the digital-to-analog converter circuit 340[n], transistor M1 receives bit D[n], and transistor M2 receives bit DB[n]. Transistor M1 is selectively turned on according to bit D[n] to generate a signal component of current IO+ (e.g., for...). Figure 2 The current I1), and transistor M2 is selectively turned on according to bit DB[n] to generate a signal component of current IO- (e.g., for the ...). Figure 2 The current I2). According to the binary weight corresponding to bit D[n], transistor M0 is used to provide current 2.n ×I. Correspondingly, in the digital-to-analog converter circuit 340[n], the capacitance value of capacitor CC is 2. n ×C (C is the unit capacitance), switch SW21 is selectively turned on according to bit DB[n], and switch SW22 is selectively turned on according to bit D[n]. Similarly, in the digital-to-analog converter circuit 340[0], M1 is selectively turned on according to bit D[0] to generate another signal component of the current IO+ (e.g., for…). Figure 2 The current I1), and transistor M2 is selectively turned on according to bit DB[0] to generate another signal component of current IO- (e.g., for the ...). Figure 2 The current I2). According to the binary weight corresponding to bit D[0], transistor M0 is used to provide current 2). 0 ×I. Correspondingly, in the digital-to-analog converter circuit 340[0], the capacitance value of capacitor CC is 2. 0 ×C, switch SW21 is selectively turned on according to bit DB[0], and switch SW22 is selectively turned on according to bit D[0]. It should be understood that the current provided by transistor M0 and the capacitance value of capacitor CC are proportional to the weight corresponding to the received bit D[n].

[0042] Figure 4B This is a schematic diagram of a current-guided digital-to-analog converter 400B according to some embodiments of the present invention. Compared to Figure 4A In this example, at least one of the multiple digital-to-analog converter circuits 340[0] to 340[n] corresponding to a high-weight bit (e.g., the most significant bit D[n]) can be generated by... Figure 2 The digital-to-analog converter circuit 200 is implemented.

[0043] For example, the digital-to-analog converter circuit 340[n] used to process the most significant bit D[n] can be derived from... Figure 2 The digital-to-analog converter circuit 200 is implemented, and its circuit configuration is similar to... Figure 2 and Figure 4A Therefore, it will not be repeated here. The remaining circuits in the multiple digital-to-analog converter circuits 340[0] to 340[n] may not use the switching capacitor circuit 160. For example, the digital-to-analog converter circuit 340[0] can operate without the switching capacitor circuit 160. By improving the switching impedance of the digital-to-analog converter circuit 340[n] that processes the high-weight bits, the linearity of the current-guided digital-to-analog converter 400B can also be effectively improved.

[0044] In other words, in different embodiments, a portion of the multiple digital-to-analog converter circuits 340[0] to 340[n] (e.g., the portion for processing the most significant bit) can be provided by Figure 1A Digital-to-analog converter circuit 100 or Figure 2 The digital-to-analog converter circuit 200 is implemented, and the remaining circuits in the plurality of digital-to-analog converter circuits 340[0] to 340[n] can be implemented by the digital-to-analog converter circuit that does not use the switching capacitor circuit 160.

[0045] Figures 3A to 4B The examples are only illustrated using a binary weighted encoding method, but the invention is not limited thereto. In other embodiments, the digital-to-analog converter in the foregoing examples may be implemented using other encoding methods (e.g., thermometer code or thermometer code-binary segmented encoding, etc.).

[0046] In other embodiments, Figure 1A Digital converter circuit 100 or Figure 2 The digital converter circuit 200 can operate without the impedance adjustment circuit 140. In these embodiments, the output terminal O+ can be directly connected to node N1, the output terminal O- can be directly connected to node N2, and the switched capacitor circuit 160 can be used to reduce the parasitic capacitance (e.g., parasitic capacitance C) of transistors M1 and M2. GD1 And C GD2 The impact of ).

[0047] The correspondences between the number of circuits, the number of bits, and the high-weight bits in the examples above are merely illustrative and are not intended to limit the invention. The correspondences between the number of circuits, the number of bits, and the high-weight bits in each example can be adjusted according to actual application requirements.

[0048] In some embodiments, the plurality of transistors or switches described above may be N-type transistors. In some embodiments, each of the transistors or switches described above may be implemented by a metal-oxide-semiconductor field-effect transistor, but the present invention is not limited thereto. Various conductivity types (P-type or N-type) or various types of transistors that can perform similar operations are all within the scope of the present invention.

[0049] In summary, the digital-to-analog converter circuit and digital-to-analog converter in some embodiments of the present invention can improve the switching resistance of the digital-to-analog converter circuit to enhance the linearity of the digital-to-analog converter.

[0050] While the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention. Those skilled in the art can make changes to the technical features of the present invention based on the express or implied content of the present invention, and all such changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined by the claims of this specification.

[0051] Explanation of reference numerals in the attached figures:

[0052] 100, 200: Digital-to-analog converter circuit

[0053] 120: Input Circuit

[0054] 140: Impedance Adjustment Circuit

[0055] 141, 142: Current source circuits

[0056] 2 n ×C,2 0 ×C: Capacitance value

[0057] 2 n ×I,2 0 ×I,I1,I2,IO+,IO-: Current

[0058] 300A, 300B, 400A, 400B: Digital-to-Analog Converters

[0059] 320: Load circuit

[0060] 340[0]~340[n]: Digital-to-analog converter circuit

[0061] CC, C1, C2: Capacitors

[0062] C GD1 C GD2 C GS3 C GS4 Parasitic capacitance

[0063] D,DB,D[0]~D[n],DB[0]~DB[n]: bit

[0064] M0~M4: Transistors

[0065] N1, N2: Nodes

[0066] O+, O-: Output terminals

[0067] R1, R2: Resistors

[0068] SW1, SW2, SW21, SW22: Switches

[0069] VB1, VB2, VDD: Voltage

[0070] VO+, VO-: Output signals

[0071] Z+, Z-: Output impedance

Claims

1. A digital-to-analog converter circuit, comprising: Input circuitry for selectively drawing a first current from a first node or a second current from a second node based on a first bit and a second bit, wherein the first bit and the second bit have opposite logic values; and A switching capacitor circuit is used to selectively compensate the capacitance value of one of the first node and the second node based on the first bit and the second bit; The capacitance value is proportional to the weight corresponding to the first bit.

2. The digital-to-analog converter circuit of claim 1, wherein the switching capacitor circuit is used to increase the capacitance value of the first node according to the second bit, and to increase the capacitance value of the second node according to the first bit.

3. The digital-to-analog converter circuit of claim 1, wherein the switching capacitor circuit is used to selectively couple a first capacitor to the first node according to the second bit, and to selectively couple a second capacitor to the second node according to the first bit.

4. The digital-to-analog converter circuit of claim 1, wherein the switching capacitor circuit is used to couple capacitors to one of the first node and the second node according to the first bit and the second bit.

5. The digital-to-analog converter circuit of claim 1, wherein the switching capacitor circuit comprises: The first capacitor is coupled to the first node; The second capacitor is coupled to the second node; A first switch is selectively turned on according to the second bit to couple the first node to ground via the first capacitor; as well as A second switch is used to selectively turn on according to the first bit to couple the second node to ground via the second capacitor.

6. The digital-to-analog converter circuit of claim 1, wherein the switching capacitor circuit comprises: capacitance; A first switch is configured to selectively conduct according to the second bit to couple the capacitor to the first node; as well as A second switch is used to selectively turn on according to the first bit to couple the capacitor to the second node.

7. The digital-to-analog converter circuit of claim 1, wherein the input circuit comprises: A first transistor, coupled to the first node, and configured to be selectively turned on according to the first bit; and A second transistor is coupled to the second node and is used to selectively turn on according to the second bit. The switching capacitor circuit is used to increase the capacitance value of the first node when the first transistor is off, and to increase the capacitance value of the second node when the second transistor is off.

8. The digital-to-analog converter circuit as claimed in claim 1, further comprising: An impedance adjustment circuit is used to transmit the first current from the first output terminal to the first node or the second current from the second output terminal to the second node, and to increase the output impedance of each of the first output terminal and the second output terminal.

9. A current-driven digital-to-analog converter, comprising: A load circuit for converting a first current into a first output signal and a second current into a second output signal; and Multiple digital-to-analog converter circuits are configured to draw the first current and the second current according to multiple bits, wherein one of these digital-to-analog converter circuits includes: An input circuit is configured to draw a signal component of the first current from a first node or a signal component of the second current from a second node based on the first and second bits of these bits, wherein the first bit is the most significant bit of these bits, and the first bit and the second bit have opposite logic values; and A switching capacitor circuit is used to selectively compensate the capacitance value of one of the first node and the second node according to the first bit and the second bit; The capacitance value is proportional to the weight corresponding to the first bit.

10. The current-guided digital-to-analog converter of claim 9, wherein the switching capacitor circuit is configured to couple capacitors to one of the first node and the second node according to the first bit and the second bit.

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