Transceiver circuitry and associated radio frequency circuitry

Abstract

Transceiver circuitry and related radio frequency circuitry is provided. The RF circuitry is coupled to the transceiver circuitry, which is configured to produce an envelope tracking (ET) target voltage. The RF circuitry includes a tracker circuit and a power amplifier circuit. The tracker circuit can have an intrinsic frequency dependent impedance that can interact with a load current of the amplifier circuit to cause a reduction in the ET modulation voltage, which can result in spectral distortion in the RF offset spectrum. As such, a voltage compensation circuit is provided in the transceiver circuitry, and the voltage compensation circuit is configured to add a voltage compensation term in the ET target voltage. By adding the voltage compensation term in the ET target voltage, the reduction in the ET modulation voltage can be compensated for, thereby helping to reduce spectral distortion in the RF offset spectrum and improve linearity and efficiency of the amplifier circuit.

Description

[0001] This application is a divisional application of application No. 201910145870.0, filed on February 27, 2019, entitled "Transceiver Circuit and Related Radio Frequency Circuit".

[0002] Related applications

[0003] This application claims the benefit of provisional patent application serial number 62 / 638,652, filed on March 5, 2018, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0004] The technology disclosed herein generally relates to radio frequency (RF) transceivers and front-end circuitry. Background Technology

[0005] Mobile communication devices have become increasingly prevalent in modern society, providing wireless communication services. This widespread use is partly driven by the many features now enabled on these devices. Increased processing power means that mobile communication devices have evolved from mere communication tools into sophisticated mobile multimedia hubs, thereby enabling enhanced user experiences.

[0006] The redefined user experience requires higher data rates provided by wireless communication technologies such as 5G-NR and Wi-Fi, which typically operates in higher spectrum. To achieve higher data rates with enhanced robustness in higher spectrum, sophisticated power amplifiers (PAs) can be employed to increase the output power of the radio frequency (RF) signal before transmission (e.g., to maintain sufficient energy per bit).

[0007] Envelope tracking (ET) is a power management technique designed to improve the efficiency of a power amplifier (PA) to help reduce power consumption in mobile communication devices. As the name suggests, an ET circuit is configured to generate a modulation voltage that tracks the target voltage envelope and provides this modulation voltage to the PA to amplify the RF signal. However, ET circuits have an inherent output impedance that can interact with the PA's inherent load, especially at higher modulation bandwidths (e.g., >100MHz). Therefore, the modulation voltage may decrease, resulting in distortion outside the modulation bandwidth. Thus, it may be necessary to control the output impedance of the ET circuit to help reduce the distortion associated with higher modulation bandwidths. Summary of the Invention

[0008] Embodiments of this disclosure relate to transceiver circuitry and associated radio frequency (RF) circuitry. In the example discussed herein, RF circuitry is coupled to transceiver circuitry configured to generate an envelope tracking (ET) target voltage. The RF circuitry includes a tracker circuit and a power amplifier circuit. The tracker circuit generates an ET modulated voltage based on the ET target voltage with a wide modulation bandwidth (e.g., up to 160 MHz), and the power amplifier circuit is configured to amplify the RF signal based on the ET modulated voltage. Notably, the tracker circuit may have an inherent frequency-dependent impedance that can interact with the load current of the amplifier circuitry to cause a reduction in the ET modulated voltage, which can further lead to spectral distortion in the RF offset spectrum. Thus, a voltage compensation circuit is provided in the transceiver circuitry, and this voltage compensation circuit is configured to add a voltage compensation term (e.g., based on an estimated load current) to the ET target voltage. By adding the voltage compensation term to the ET target voltage, the reduction in the ET modulated voltage can be compensated, thereby helping to reduce spectral distortion in the RF offset spectrum and improve the linearity and efficiency of the amplifier circuitry.

[0009] In one aspect, a transceiver circuit is provided. The transceiver circuit includes an output node coupled to an RF circuit. The transceiver circuit also includes a voltage generation circuit coupled to the output node. The voltage generation circuit is configured to receive multiple digital amplitudes. The voltage generation circuit is further configured to generate a digital target voltage based on the multiple digital amplitudes. The transceiver circuit also includes a voltage compensation circuit connected in parallel with the voltage generation circuit. The voltage compensation circuit is configured to generate a voltage compensation term based on the multiple digital amplitudes. The digital target voltage is combined with the voltage compensation term before converting it into an ET target voltage at the output node.

[0010] In another aspect, an apparatus is provided. The apparatus includes a transceiver circuit. The transceiver circuit includes an output node coupled to an RF circuit. The transceiver circuit also includes a voltage generation circuit coupled to the output node. The voltage generation circuit is configured to receive a plurality of digital amplitudes. The voltage generation circuit is further configured to generate a digital target voltage based on the plurality of digital amplitudes. The transceiver circuit also includes a voltage compensation circuit arranged in parallel with the voltage generation circuit. The voltage compensation circuit is configured to generate a voltage compensation term based on the plurality of digital amplitudes. The digital target voltage is combined with the voltage compensation term before converting the digital target voltage to an ET target voltage at the output node. The apparatus also includes an RF circuit coupled to the output node. The RF circuit is configured to receive the ET target voltage.

[0011] In another aspect, an RF circuit is provided. The RF circuit includes a power amplifier circuit configured to amplify an RF signal based on an ET modulation voltage. The ET modulation voltage includes a first voltage term and a second voltage term. The RF circuit also includes a tracker circuit. The tracker circuit is configured to generate the ET modulation voltage based on an ET target voltage. The tracker circuit is further configured to generate a voltage correction term to compensate for voltage distortion associated with the first voltage term of the ET modulation voltage.

[0012] After reading the following detailed description of preferred embodiments in conjunction with the accompanying drawings, those skilled in the art will understand the scope of this disclosure and implement other aspects thereof. Attached Figure Description

[0013] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0014] Figure 1A This is a schematic diagram of an exemplary radio frequency (RF) circuit, in which an amplifier circuit is configured to amplify an RF signal based on a modulation voltage generated by a tracker circuit.

[0015] Figure 1B It provides Figure 1A An exemplary illustration of the characteristic curves of an amplifier circuit is shown in the graph.

[0016] Figure 1C It provides Figure 1A A schematic diagram of an exemplary illustration of the output stage of a tracker circuit in an RF circuit;

[0017] Figure 1D It is shown Figure 1A A schematic diagram showing how the output impedance of a tracker circuit can be modeled using output inductance and output resistance;

[0018] Figure 1E This is a schematic diagram providing an exemplary illustration of a time-division duplex (TDD) RF spectrum and adjacent RF offset spectra;

[0019] Figure 2 It is configured according to embodiments of the present disclosure to digitally incorporate voltage compensation terms into the digital target voltage to help reduce Figure 1E A schematic diagram of an exemplary transceiver circuit for spectral distortion in the RF offset spectrum;

[0020] Figure 3 It is incorporated according to an embodiment of this disclosure. Figure 2 transceiver circuit and Figure 1A A schematic diagram of an exemplary device for an RF circuit; and

[0021] Figure 4This is a schematic diagram of an exemplary device configured according to another embodiment of the present disclosure. Detailed Implementation

[0022] The embodiments described below illustrate the necessary information to enable those skilled in the art to practice the embodiments and demonstrate the best mode for practicing the embodiments. By reading the following description in conjunction with the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and will recognize the application of these concepts, which are not specifically set forth herein. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

[0023] It should be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0024] It should be understood that when a component, such as a layer, region, or substrate, is referred to as being "on" or extending "to" another component, it can be directly on or directly extended to the other component, or intermediate components may be present. Conversely, when a component is referred to as being "directly on" another component or "directly" extending "to" another component, no intermediate components are present. Similarly, it should be understood that when a component, such as a layer, region, or substrate, is referred to as extending "above" another component or "above" another component, it can be directly above or directly above the other component, or intermediate components may be present. Conversely, when a component is referred to as extending "directly above" another component or directly above another component, no intermediate components are present. It should also be understood that when a component is referred to as being "connected" or "coupled" to another component, it can be directly connected or coupled to the other component, or intermediate components may be present. Conversely, when a component is referred to as being "directly connected" or "directly coupled" to another component, no intermediate components are present.

[0025] This document may use relative terms such as “below” or “above” or “up” or “down” or “horizontal” or “vertical” to describe the relationship between one element, layer, or region and another element, layer, or region as shown in the figure. It should be understood that, in addition to the orientation shown in the figure, these terms and those discussed above are intended to include different orientations of the device.

[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and / or “including” as used herein specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0027] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that the terms used herein shall be interpreted as having the meaning consistent with their meaning in the context of this specification and the relevant field, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0028] Embodiments of this disclosure relate to transceiver circuitry and associated radio frequency (RF) circuitry. In the example discussed herein, RF circuitry is coupled to transceiver circuitry configured to generate an envelope tracking (ET) target voltage. The RF circuitry includes a tracker circuit and a power amplifier circuit. The tracker circuit generates an ET modulated voltage based on the ET target voltage with a wide modulation bandwidth (e.g., up to 160 MHz), and the power amplifier circuit is configured to amplify the RF signal based on the ET modulated voltage. Notably, the tracker circuit may have an inherent frequency-dependent impedance that can interact with the load current of the amplifier circuitry to cause a reduction in the ET modulated voltage, which can further lead to spectral distortion in the RF offset spectrum. Thus, a voltage compensation circuit is provided in the transceiver circuitry, and this voltage compensation circuit is configured to add a voltage compensation term (e.g., based on an estimated load current) to the ET target voltage. By adding the voltage compensation term to the ET target voltage, the reduction in the ET modulated voltage can be compensated, thereby helping to reduce spectral distortion in the RF offset spectrum and improve the linearity and efficiency of the amplifier circuitry.

[0029] Before discussing the transceiver circuitry and related RF circuitry of this disclosure, please first refer to... Figure 1A-1E This section provides a brief overview of RF circuitry to help understand common issues related to supporting wideband modulation in RF circuits. References are provided below. Figure 2 We will begin by discussing specific exemplary aspects of transceiver circuitry and related RF circuitry, which can be configured to overcome common problems in RF circuitry.

[0030] in this regard, Figure 1AThis is a schematic diagram of an exemplary RF circuit 10, in which the power amplifier circuit 12 is configured based on the ET modulation voltage V generated by the tracker circuit 16. CC RF signal 14 is transferred from input power P IN Amplified to output power P OUT The power amplifier circuit 12 can be configured to operate as a linear or nonlinear device based on the power amplifier (PA) characteristic curve 18, as will be described below. Figure 1B Let's have a discussion.

[0031] refer to Figure 1B PA characteristic curve 18 includes theoretical response curve 20 and actual response curve 22. The theoretical response curve 20 represents the output power P. OUT and input power P IN The theoretical relationship between them, and the actual response curve 22 represents the output power P. OUT and input power P IN The actual relationship between them. For example... Figure 1B As shown, the power amplifier circuit 12 can be configured to operate in either the linear region 24 or the compression region 26. When the power amplifier circuit 12 operates in the linear region 24, the output power P OUT Will be related to input power P IN The power gain (G) of power amplifier circuit 12 is linearly related, as shown in theoretical response curve 20. In contrast, when power amplifier circuit 12 operates in compression region 26, the output power P... OUT No longer responding to input power P IN The increase in voltage V can be achieved by modulating voltage V through ET. CC Controlling output power P OUT Typically, the power amplifier circuit 12 can operate in the nonlinear region 28 between the linear region 24 and the compression region 26. In this respect, the output power P OUT Based on the actual response curve 22 in the nonlinear region 28, nonlinearly related to the input power P IN Related.

[0032] Return to reference Figure 1A The tracker circuit 16 includes an inherent source impedance Z. SOURCE In the non-restrictive example, the source impedance Z SOURCE This represents the combined impedance seen by the power amplifier circuit 12 when viewed from the coupling point 30 towards the tracker circuit 16.

[0033] In a non-limiting example, the power amplifier circuit 12 can be modeled as a current source. In this respect, the source impedance Z... SOURCE and ET modulation voltage V CC A load current I can be generated in the power amplifier circuit 12. CCAs previously in Figure 1B As discussed herein, the power amplifier circuit 12 can operate in the linear region 24, the nonlinear region 28, or the compression region 26. When the power amplifier circuit 12 operates in the linear region 24, the load current I... CC With ET modulation voltage V CC Disproportionate (hereinafter referred to as "non-proportional load current I") CC_NP In this regard, the load current I CC It can be determined by the non-proportional load current I CC_NP Dominated. In contrast, when the power amplifier circuit 12 operates in the compression region 26, the load current I... CC With ET modulation voltage V CC Proportional (hereinafter referred to as "proportional load current I") CC_P In this regard, the load current I CC It can be determined by the proportional load current I CC_P Dominated. Furthermore, when the power amplifier circuit 12 operates in the nonlinear region 28, the load current I... CC This can include the proportional load current I CC_P Non-proportional load current I CC_NP Both.

[0034] Tracker circuit 16 may include charge pump circuit 32 and amplifier 34. Charge pump circuit 32 is coupled to battery voltage V. BAT And it is configured to generate load current I CC It can include both direct current and alternating current. Amplifier 34 receives power supply voltage V. BATAMP It can be derived from the battery voltage V BAT Export. Amplifier 34 can receive the target voltage V ET. TARGET And based on the ET target voltage V TARGET Generate ET modulation voltage V CC .

[0035] It is worth noting that the RF signal 14 can be modulated to follow the time-varying power envelope, which can occasionally generate higher peak power. Therefore, the tracker circuit 16 needs to provide the ET modulation voltage V at a sufficient level. CC and current I CC This allows the power amplifier circuit 12 to amplify the RF signal 14 to an output power P that corresponds to a higher peak power of the time-varying power envelope. OUT For example, RF signal 14 may have a peak power exceeding 28.5 dBm, and power amplifier circuit 12 needs to amplify RF signal 14 to a Class 2 output power exceeding 26 dBm. If power amplifier circuit 12 has a power amplifier efficiency (PAE) of 45% and the ET modulation voltage V... CCIf the voltage is 5V, then the current I generated by tracker circuit 16 is... CC This will require approximately 314.6mA. Therefore, amplifier 34 needs to employ a sufficiently large output stage to generate the required current I. CC .

[0036] Figure 1C It provides Figure 1A This is a schematic diagram of an exemplary output stage 36 of amplifier 34 in RF circuit 10. Output stage 36 includes a first transistor 38 and a second transistor 40 arranged in series. The first transistor 38 may be a p-type field-effect transistor (pFET), and the second transistor 40 may be an n-type field-effect transistor (nFET). When the supply voltage V... BATAMP When applied to output stage 36, the first transistor 38 and the second transistor 40 can generate parasitic capacitance. Thus, a pair of balancing capacitors C1 and C2 can be provided in output stage 36 to help balance the parasitic capacitance.

[0037] As mentioned above, output stage 36 needs to generate a sufficiently large current I. CC , making Figure 1A The power amplifier circuit 12 can amplify the RF signal 14 to an output power P that corresponds to a higher peak power of the time-varying power envelope. OUT In this respect, the first transistor 38 and the second transistor 40 need to be large enough, which in turn can generate larger parasitic capacitances during operation. As a result, the balancing capacitors C1 and C2 need to be larger in order to provide higher balancing capacitance to offset the increased parasitic capacitance. The increased size of the first transistor 38, the second transistor 40, and the balancing capacitors C1 and C2 can lead to a larger footprint and more power consumption in the output stage 36. Furthermore, the higher balancing capacitance introduced by the balancing capacitors C1 and C2 can reduce the slew rate of the amplifier 34, thereby reducing the voltage modulation bandwidth of the amplifier 34.

[0038] Return to reference Figure 1A Source impedance Z SOURCE It can be modeled as being mainly composed of the output inductance L ZOUT and output resistance R ZOUT Confirmed, such as Figure 1D As shown. Figure 1D It is shown Figure 1A The source impedance Z of tracker circuit 16 SOURCE It can be achieved through the output inductor L ZOUT and output resistance R ZOUT A schematic diagram of the modeling. Figure 1A-1D Common elements between them are shown in this document as having common element numbers, and will not be described again here.

[0039] Source impedance Z SOURCEET modulation output voltage V CC The effect can be expressed by the following equation (Equation 1).

[0040] V CC =V TARGET -L ZOUT ·dI CC / dt–R ZOUT .I CC (Equation 1)

[0041] As shown in equation (Equation 1) above, the source impedance Z SOURCE This can cause the target voltage V to be ET. TARGET and ET modulation voltage V CC The voltage deviation between them can be exacerbated when the RF signal 14 is modulated with a wider modulation bandwidth (e.g., up to 160 MHz). Furthermore, the source impedance Z... SOURCE This can increase the power consumption in RF circuit 10. Furthermore, when the capacitance of the balancing capacitors C1 and C2 in the output stage 36 of tracker circuit 16 increases, the source impedance Z... SOURCE It can also be increased, thus reducing the switching rate of tracker circuit 16 and causing the ET modulation voltage V. CC Further deviations.

[0042] Power amplifier circuit 12 can be configured to amplify RF signal 14 for transmission in time-division duplex (TDD) RF spectrum 42, such as Figure 1E As shown. The TDD RF spectrum 42 is adjacent to the RF offset spectrum 44. The RF offset spectrum 44 may be above or below the TDD RF spectrum 42, but does not overlap with the TDD RF spectrum 42.

[0043] The RF offset spectrum 44 may include a lower offset spectrum 46L and an upper offset spectrum 46U. The lower offset spectrum 46L and the upper offset spectrum 46U may correspond to the same or different bandwidths. For example, if the TDD RF spectrum 42 has a 100MHz bandwidth, the RF offset spectrum 44 may have a 200MHz bandwidth that is equally or unequally divided between the lower offset spectrum 46L and the upper offset spectrum 46U.

[0044] Return to reference Figure 1A The power amplifier circuit 12 can act as a current source for the tracker circuit 16. It is worth noting that the current I... CC It can have a wide current spectrum, which can be compared with the source impedance Z. SOURCE Interaction to reduce ET modulation voltage V CC Furthermore, a significant energy content is generated in the RF offset spectrum 44 due to spectral regeneration. Additionally, when the RF signal 14 is modulated with a wider modulation bandwidth, the source impedance Z... SOURCEThe voltage tends to increase, thereby further reducing the ET modulation voltage V. CC This also worsens the distortion in the RF offset spectrum 44. Therefore, it may be necessary to control the source impedance Z. SOURCE This helps reduce distortion (e.g., noise and ripple) in the RF offset spectrum 44.

[0045] in this regard, Figure 2 It is configured according to embodiments of the present disclosure to digitally introduce the voltage compensation term Δv into the digital target voltage V. TARGET_D Help reduce Figure 1E A schematic diagram of an exemplary transceiver circuit 48 exhibiting spectral distortion of the RF offset spectrum 44. The transceiver circuit 48 includes a voltage generation circuit 50 configured to receive a plurality of digital amplitudes 52 and generate a digital target voltage V based on the digital amplitudes 52. TARGET_D The transceiver circuit 48 also includes a voltage compensation circuit 54 connected in parallel with the voltage generation circuit 50. The voltage compensation circuit 54 is configured to generate a voltage compensation term Δv based on the digital amplitude 52. At the digital target voltage V... TARGET_D Converted to ET target voltage V TARGET Before outputting at output node 56, the voltage compensation term Δv and the digital target voltage V TARGET_D combination.

[0046] As discussed in detail below, this can be based on the estimated load current I. CC_E (For example, Figure 1A Load current I in CC The estimated voltage (Δv) is used to generate a voltage compensation term Δv to help compensate for the target voltage V of ET. TARGET The reduction. Therefore, the RF circuit coupled to output node 56 can be corrected based on the target voltage VET. TARGET The generated ET modulation voltage V CC The associated potential distortion. As a result, it can be reduced. Figure 1E Spectral distortion in the RF offset spectrum 44.

[0047] The voltage generation circuit 50 includes a target voltage lookup table (LUT) 58, which may be, for example, an application-specific integrated circuit (ASIC). The target voltage LUT 58 may include storage elements (e.g., registers) for storing a predetermined digital target voltage associated with a digital amplitude 52. The target voltage LUT 58 may also include processing elements (e.g., a microprocessor) to generate a digital target voltage V based on the digital amplitude 52. TARGET_D .

[0048] The voltage compensation circuit 54 includes a load current LUT 60, which may be, for example, an ASIC. The load current LUT 60 may include an estimated load current I associated with the digital amplitude 52. CC_EThe load current LUT 60 may also include a processing element (e.g., a microprocessor) to generate an estimated load current I based on a digital amplitude 52. CC_E The voltage compensation circuit 54 also includes a filter circuit 62, which is configured to adjust based on the estimated load current I. CC_E This generates a voltage compensation term Δv.

[0049] Transceiver circuit 48 may include voltage combiner 64, which is configured to combine digital target voltage V TARGET_D Combined with the voltage compensation term Δv to generate a compensated digital target voltage V' TARGET_D The transceiver circuit 48 includes a digital-to-analog converter (DAC) 66, which is configured to compensate for the digital target voltage V'. TARGET_D Converted to ET target voltage V TARGET and the target voltage V of ET TARGET Provided to output node 56. DAC 66 can be configured to generate the target voltage V ET. TARGET As a differential target voltage, transceiver circuit 48 may also include delay circuit 68 coupled between voltage combiner 64 and DAC 66.

[0050] Transceiver circuit 48 includes signal processing circuitry 70 configured to generate RF signal 72 based on digital signal 74. In a non-limiting example, digital signal 74 (which may be a digital baseband signal) includes a digital in-phase (I) signal 76I and a digital quadrature (Q) signal 76Q. The digital in-phase signal 76I and the digital quadrature signal 76Q correspond to in-phase amplitude I and quadrature amplitude Q, respectively. The in-phase amplitude I and the quadrature amplitude Q together define multiple digital amplitudes. Transceiver circuit 48 may include combiner 78, which combines digital amplitudes And digital reference signal 80 to generate digital amplitude 52.

[0051] Signal processing circuitry 70 may include a memory digital predistortion (mDPD) circuitry 82 configured to perform mDPD on the digital in-phase signal 76I and the digital quadrature signal 76Q. Signal processing circuitry 70 includes an in-phase DAC 84I and a quadrature DAC 84Q, which convert the digital in-phase signal 76I and the digital quadrature signal 76Q into analog in-phase signals 86I and 86Q, respectively. Signal processing circuitry 70 may include an in-phase filter 88I and a quadrature filter 88Q for passing the analog in-phase signal 86I and the analog quadrature signal 86Q in desired frequency bands, respectively. Signal processing circuitry 70 may include an in-phase multiplexer 90I and a quadrature mixer 90Q configured to convert the analog in-phase signal 86I and the analog quadrature signal 86Q to an appropriate frequency (e.g., carrier frequency or intermediate frequency). In-phase multiplexer 90I and quadrature mixer 90Q may be configured to operate based on a reference frequency provided by oscillator 92. Signal processing circuit 70 includes a signal combiner 94 configured to combine an analog in-phase signal 86I and an analog quadrature signal 86Q to generate an RF signal 72.

[0052] Transceiver circuitry 48 can be provided in a device (e.g., a smartphone) to help reduce... Figure 1E This reduces spectral distortion in the RF offset spectrum 44 and improves the linearity and efficiency of the amplifier circuitry in the device. Figure 3 It is incorporated according to an embodiment of this disclosure. Figure 2 transceiver circuit 48 and Figure 1A A schematic diagram of an exemplary device 96 of the RF circuit 10. Figure 1A , Figure 2 and Figure 3 Common elements between them are shown in this document as having common element numbers, and will not be described again here.

[0053] Tracker circuit 16 is coupled to output node 56 to receive ET target V TARGET And based on the ET target voltage V TARGET Generate ET modulation voltage V CC The power amplifier circuit 12, which can be a single-stage or multi-stage power amplifier circuit, is coupled to the transceiver circuit 48 to receive the RF signal 72. The power amplifier circuit 12 is also coupled to the tracker circuit 16 to receive the ET modulation voltage V. CC And based on the ET modulation voltage V CC Amplify the RF signal 72.

[0054] As previously Figure 1A-1E The tracker circuit 16 discussed herein includes a source impedance Z. SOURCE It can be modeled as being mainly composed of the output inductance L ZOUT and output resistance R ZOUTThis can be determined and can affect the ET modulation output voltage V. CC As shown in the equation above (Equation 1). Further according to... Figure 1A-1E In the previous discussion, the source impedance Z SOURCE This can cause the target voltage V to be ET. TARGET and ET modulation voltage V CC The voltage deviation between them can be exacerbated when the RF signal 72 is modulated with a wider modulation bandwidth (e.g., up to 160 MHz).

[0055] On the other hand, the power amplifier circuit 12 can be modeled as a current source of the tracker circuit 16. In this respect, the source impedance Z... SOURCE and ET modulation voltage V CC This can cause a load current I in the power amplifier circuit 12. CC As mentioned earlier... Figure 1B As discussed herein, the power amplifier circuit 12 can operate in the linear region 24, the nonlinear region 28, or the compression region 26.

[0056] Depending on the PA characteristics of power amplifier circuit 12 (e.g.) Figure 1B As shown), the load current I CC This can include non-proportional load current I CC_NP and / or proportional load current I CC_P In this respect, the load current LUT 60 can be configured to generate an estimated current I. CC_E To include the estimated non-proportional load current I CC_NP and the estimated proportional load current I CC_P Both.

[0057] Therefore, the filter circuit 62 can be configured based on the estimated load current I. CC_E And a set of estimated source impedance impulse responses Z SOURCE The convolution of (t) is used to generate the voltage compensation term Δv (Δv = I). CC_E (t)**Z SOURCE (t)). More specifically, the filter circuit 62 can be based on the estimated load current I. CC_E and the estimated impedance impulse response Z corresponding to RF circuit 10 SOURCE (t) Perform a convolution function to generate the voltage compensation term Δv. The estimated impedance impulse response Z SOURCE (t) can be determined based on the design / characteristics of the power amplifier circuit 12. For example, it can be based on the high-pass filter and the source impedance Z. SOURCE The convolution is used to determine the estimated impedance impulse response Z. SOURCE (t), source impedance Z SOURCE It is known based on the design / characteristics of RF circuit 10.

[0058] The power amplifier circuit 12 can be considered as a 2-input circuit, where the 2 inputs correspond to the ET modulation voltage V respectively. CC and load current I CC Load current I CC This can include the proportional load current I CC_P and / or non-proportional load current I CC_NP In this respect, the ET modulation voltage V CC It can be represented by the following equation (Equation 2).

[0059] V CC =H(s)*V TARGET -I CC_P *Z SOURCE -I CC_NP *Z SOURCE (Equation 2)

[0060] In the above equation (Equation 2), H(s) represents the voltage transfer function associated with tracker circuit 16. As shown in Equation (Equation 2), the ET modulation voltage V CC It can be considered to include the proportional load current I CC_P The first voltage term V TERM1 and corresponding to the non-proportional load current I CC_NP The second voltage term V TERM2 Therefore, equation (Equation 2) can be replaced by the following equations (Equations 2.1, 2.2 and 2.3).

[0061] V CC =V TERM1 +V TERM2 (Equation 2.1)

[0062] V TERM1 =H(s)*V TARGET -I CC_P *Z SOURCE (Equation 2.2)

[0063] V TERM2 =-I CC_NP *Z SOURCE (Equation 2.3)

[0064] In this respect, the load current LUT 60 can be configured to generate an estimated load current I. CC_E It includes the proportional load current I CC_P Estimation and for non-proportional load current I CC_NP The estimates of both. Therefore, filter circuit 62 can generate a voltage compensation term Δv to compensate for the difference between the first voltage term V and the second voltage term V. TERM1 Second voltage term VTERM2 Voltage distortion in the ET modulated voltage associated with both.

[0065] Assume the first voltage term V as shown in equation (Equation 2.2) above. TERM1 Only with proportional load current I CC_P The relevant equation can be expressed in the following equation (Equation 3) as the ET modulation voltage V. CC .

[0066] V CC =H(s)*V TARGET / (1+Z SOURCE / R ICC (Equation 3)

[0067] In equation (Equation 3), R ICC Presents the equivalent resistance (R) of power amplifier circuit 12 ICC =V CC / I CC_P In this way, an output equal to 1 / (1+Z) can be generated in tracker circuit 16. SOURCE / R ICC The voltage correction term is used to compensate for the voltage difference with the first voltage term V. TERM1 The associated voltage distortion, while still based on the voltage compensation term Δv compensation and the second voltage term V TERM2 Associated voltage distortion. In this respect, Figure 4 This is a schematic diagram of an exemplary device 96A configured according to another embodiment of the present disclosure. Figure 1A , Figure 2 , Figure 3 and Figure 4 Common elements between them are shown in this document as having common element numbers, and will not be described again here.

[0068] Device 96A includes RF circuitry 10A, which includes power amplifier circuitry 12 and tracker circuitry 16A. Tracker circuitry 16A may include an equalizer (e.g., a frequency equalizer) 98, which may be configured to generate a voltage correction term to compensate for a first voltage term V. TERM1 Associated voltage distortion.

[0069] Device 96A includes transceiver circuitry 48A, which includes voltage compensation circuitry 54A. Voltage compensation circuitry 54A includes a subtractor 100 coupled between load current LUT 60 and filter circuitry 62. Subtractor 100 is configured to subtract from estimated load current I... CC_E Subtract the proportional load current I CC_P To generate a load that includes only the non-proportional load current I CC_NP Modified estimated load current I' CC_ETherefore, filter circuit 62 is configured to generate a voltage compensation term Δv to compensate for the voltage difference with the second voltage term V. TERM2 Associated voltage distortion.

[0070] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of this disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the subsequent claims.

Claims

1. A transceiver circuit, comprising: an output node coupled to a radio frequency (RF) circuit configured for producing an envelope tracking (ET) modulation voltage based on an ET target voltage to amplify a radio frequency (RF) signal; a voltage producing circuit coupled to the output node and configured to: receive a plurality of digital amplitudes; and produce a digital target voltage based on the plurality of digital amplitudes; and a voltage combiner configured to combine the digital target voltage with a voltage compensation term before the digital target voltage is converted to the ET target voltage at the output node.

2. The transceiver circuit of claim 1, further comprising a voltage compensation circuit disposed in parallel with the voltage producing circuit and configured to produce the voltage compensation term based on the plurality of digital amplitudes.

3. The transceiver circuit of claim 2, wherein the voltage compensation circuit comprises: a load current lookup table (LUT) configured to produce an estimated load current based on the plurality of digital amplitudes; and a filter circuit configured to produce the voltage compensation term based on the estimated load current.

4. The transceiver circuit of claim 3, wherein the filter circuit is further configured to: receive the estimated load current from the load current LUT; and perform a convolution function based on the estimated load current and a set of estimated source impedance impulse responses corresponding to the RF circuit to produce the voltage compensation term.

5. The transceiver circuit of claim 3, wherein the estimated load current comprises a proportional load current and a non-proportional load current, the proportional load current having a proportional relationship to an ET modulation voltage and the non-proportional load current having a non-proportional relationship to an ET modulation voltage.

6. The transceiver circuit of claim 5, wherein the voltage compensation circuit is further configured to subtract the proportional load current from the estimated load current before producing the voltage compensation term.

7. The transceiver circuit of claim 3, wherein: the voltage producing circuit comprises a target voltage LUT configured to produce the digital target voltage based on the plurality of digital amplitudes; and the voltage combiner is further configured to combine the digital target voltage with the voltage compensation term to produce a compensated digital target voltage.

8. The transceiver circuit of claim 7, further comprising a digital-to-analog converter (DAC) configured to: convert the compensated digital target voltage to the ET target voltage; and provide the ET target voltage to the output node.

9. A wireless device, comprising: a transceiver circuit, comprising: an output node; a voltage producing circuit coupled to the output node and configured to: receive a plurality of digital amplitudes; and produce a digital target voltage based on the plurality of digital amplitudes; and a voltage combiner configured to combine the digital target voltage with a voltage compensation term before the digital target voltage is converted to an envelope tracking (ET) target voltage at the output node; and ​ ​ ​ ​ Radio frequency (RF) circuitry coupled to the output node and configured to produce an envelope tracking (ET) modulation voltage based on an ET target voltage to amplify a radio frequency (RF) signal.

10. The wireless device of claim 9, wherein the transceiver circuitry additionally includes a voltage compensation circuit configured to produce the voltage compensation term based on the plurality of digital amplitudes in parallel with the voltage production circuit.

11. The wireless device of claim 10, wherein the RF circuitry includes: a tracker circuit coupled to the output node and configured to produce an ET modulation voltage based on the ET target voltage; and a power amplifier circuit configured to amplify an RF signal based on the ET modulation voltage.

12. The wireless device of claim 11, wherein the voltage compensation circuit includes: a load current lookup table (LUT) configured to produce an estimated load current based on the plurality of digital amplitudes; and a filter circuit configured to produce the voltage compensation term based on the estimated load current.

13. The wireless device of claim 12, wherein the filter circuit is additionally configured to: receive the estimated load current from the load current LUT; and perform a convolution function based on the estimated load current and a set of estimated source impedance impulse responses corresponding to the RF circuit to produce the voltage compensation term.

14. The wireless device of claim 12, wherein: the voltage production circuit includes a target voltage LUT configured to produce the digital target voltage based on the plurality of digital amplitudes; and the voltage combiner is additionally configured to combine the digital target voltage with the voltage compensation term to produce a compensated digital target voltage.

15. The wireless device of claim 14, wherein the transceiver circuitry additionally includes a digital-to-analog converter (DAC) configured to: convert the compensated digital target voltage to the ET target voltage; and provide the ET target voltage to the output node.

16. The wireless device of claim 12, wherein the estimated load current corresponds to a load current in the power amplifier circuit caused by the ET modulation voltage and a source impedance coupled to the power amplifier circuit.

17. The wireless device of claim 16, wherein the estimated load current includes a proportional load current having a proportional relationship to ET modulation voltage and a non-proportional load current having a non-proportional relationship to ET modulation voltage.

18. The wireless device of claim 17, wherein the ET modulation voltage includes: a first voltage term corresponding to the proportional load current; and a second voltage term corresponding to the non-proportional load current.

19. The wireless device of claim 18, wherein the voltage compensation circuit is additionally configured to generate the voltage compensation term to compensate for voltage distortion associated with the first voltage term and the second voltage term of the ET modulated voltage.

20. The wireless device of claim 18, wherein the voltage compensation circuit is additionally configured to subtract the proportional load current from the estimated load current prior to generating the voltage compensation term.

21. The wireless device of claim 20, wherein the voltage compensation circuit is additionally configured to generate the voltage compensation term to compensate for voltage distortion associated with the second voltage term of the ET modulated voltage.

22. The wireless device of claim 21, wherein the tracker circuit comprises a frequency equalizer configured to generate a voltage correction term to compensate for the voltage distortion associated with the first voltage term of the ET modulated voltage.

Images